FILE
trans.c
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linux-6.19.14/drivers/net/wireless/intel/iwlwifi/pcie/gen1_2/trans.c
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2/* 3 * Copyright (C) 2007-2015, 2018-2024 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7#include <linux/pci.h> 8#include <linux/interrupt.h> 9#include <linux/debugfs.h> 10#include <linux/sched.h> 11#include <linux/bitops.h> 12#include <linux/gfp.h> 13#include <linux/vmalloc.h> 14#include <linux/module.h> 15#include <linux/wait.h> 16#include <linux/seq_file.h> 17 18#include "iwl-drv.h" 19#include "iwl-trans.h" 20#include "iwl-csr.h" 21#include "iwl-prph.h" 22#include "iwl-scd.h" 23#include "iwl-agn-hw.h" 24#include "fw/error-dump.h" 25#include "fw/dbg.h" 26#include "fw/api/tx.h" 27#include "fw/acpi.h" 28#include "mei/iwl-mei.h" 29#include "internal.h" 30#include "iwl-fh.h" 31#include "pcie/iwl-context-info-v2.h" 32#include "pcie/utils.h" 33 34#define IWL_HOST_MON_BLOCK_PEMON 0x00 35#define IWL_HOST_MON_BLOCK_HIPM 0x22 36 37#define IWL_HOST_MON_BLOCK_PEMON_VEC0 0x00 38#define IWL_HOST_MON_BLOCK_PEMON_VEC1 0x01 39#define IWL_HOST_MON_BLOCK_PEMON_WFPM 0x06 40 41static void iwl_dump_host_monitor_block(struct iwl_trans *trans, 42 u32 block, u32 vec, u32 iter) 43{ 44 int i; 45 46 IWL_ERR(trans, "Host monitor block 0x%x vector 0x%x\n", block, vec); 47 iwl_write32(trans, CSR_MONITOR_CFG_REG, (block << 8) | vec); 48 for (i = 0; i < iter; i++) 49 IWL_ERR(trans, " value [iter %d]: 0x%08x\n", 50 i, iwl_read32(trans, CSR_MONITOR_STATUS_REG)); 51} 52 53static void iwl_pcie_dump_host_monitor(struct iwl_trans *trans) 54{ 55 switch (trans->mac_cfg->device_family) { 56 case IWL_DEVICE_FAMILY_22000: 57 case IWL_DEVICE_FAMILY_AX210: 58 IWL_ERR(trans, "CSR_RESET = 0x%x\n", 59 iwl_read32(trans, CSR_RESET)); 60 iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_PEMON, 61 IWL_HOST_MON_BLOCK_PEMON_VEC0, 15); 62 iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_PEMON, 63 IWL_HOST_MON_BLOCK_PEMON_VEC1, 15); 64 iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_PEMON, 65 IWL_HOST_MON_BLOCK_PEMON_WFPM, 15); 66 iwl_dump_host_monitor_block(trans, IWL_HOST_MON_BLOCK_HIPM, 67 IWL_HOST_MON_BLOCK_PEMON_VEC0, 1); 68 break; 69 default: 70 return; 71 } 72} 73 74/* extended range in FW SRAM */ 75#define IWL_FW_MEM_EXTENDED_START 0x40000 76#define IWL_FW_MEM_EXTENDED_END 0x57FFF 77 78int iwl_trans_pcie_sw_reset(struct iwl_trans *trans, bool retake_ownership) 79{ 80 /* Reset entire device - do controller reset (results in SHRD_HW_RST) */ 81 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 82 iwl_set_bit(trans, CSR_GP_CNTRL, 83 CSR_GP_CNTRL_REG_FLAG_SW_RESET); 84 usleep_range(10000, 20000); 85 } else { 86 iwl_set_bit(trans, CSR_RESET, 87 CSR_RESET_REG_FLAG_SW_RESET); 88 usleep_range(5000, 6000); 89 } 90 91 if (retake_ownership) 92 return iwl_pcie_prepare_card_hw(trans); 93 94 return 0; 95} 96 97static void iwl_pcie_free_fw_monitor(struct iwl_trans *trans) 98{ 99 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 100 101 if (!fw_mon->size) 102 return; 103 104 dma_free_coherent(trans->dev, fw_mon->size, fw_mon->block, 105 fw_mon->physical); 106 107 fw_mon->block = NULL; 108 fw_mon->physical = 0; 109 fw_mon->size = 0; 110} 111 112static void iwl_pcie_alloc_fw_monitor_block(struct iwl_trans *trans, 113 u8 max_power) 114{ 115 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 116 void *block = NULL; 117 dma_addr_t physical = 0; 118 u32 size = 0; 119 u8 power; 120 121 if (fw_mon->size) { 122 memset(fw_mon->block, 0, fw_mon->size); 123 return; 124 } 125 126 /* need at least 2 KiB, so stop at 11 */ 127 for (power = max_power; power >= 11; power--) { 128 size = BIT(power); 129 block = dma_alloc_coherent(trans->dev, size, &physical, 130 GFP_KERNEL | __GFP_NOWARN); 131 if (!block) 132 continue; 133 134 IWL_INFO(trans, 135 "Allocated 0x%08x bytes for firmware monitor.\n", 136 size); 137 break; 138 } 139 140 if (WARN_ON_ONCE(!block)) 141 return; 142 143 if (power != max_power) 144 IWL_ERR(trans, 145 "Sorry - debug buffer is only %luK while you requested %luK\n", 146 (unsigned long)BIT(power - 10), 147 (unsigned long)BIT(max_power - 10)); 148 149 fw_mon->block = block; 150 fw_mon->physical = physical; 151 fw_mon->size = size; 152} 153 154void iwl_pcie_alloc_fw_monitor(struct iwl_trans *trans, u8 max_power) 155{ 156 if (!max_power) { 157 /* default max_power is maximum */ 158 max_power = 26; 159 } else { 160 max_power += 11; 161 } 162 163 if (WARN(max_power > 26, 164 "External buffer size for monitor is too big %d, check the FW TLV\n", 165 max_power)) 166 return; 167 168 iwl_pcie_alloc_fw_monitor_block(trans, max_power); 169} 170 171static u32 iwl_trans_pcie_read_shr(struct iwl_trans *trans, u32 reg) 172{ 173 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 174 ((reg & 0x0000ffff) | (2 << 28))); 175 return iwl_read32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG); 176} 177 178static void iwl_trans_pcie_write_shr(struct iwl_trans *trans, u32 reg, u32 val) 179{ 180 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_DATA_REG, val); 181 iwl_write32(trans, HEEP_CTRL_WRD_PCIEX_CTRL_REG, 182 ((reg & 0x0000ffff) | (3 << 28))); 183} 184 185static void iwl_pcie_set_pwr(struct iwl_trans *trans, bool vaux) 186{ 187 if (trans->mac_cfg->base->apmg_not_supported) 188 return; 189 190 if (vaux && pci_pme_capable(to_pci_dev(trans->dev), PCI_D3cold)) 191 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 192 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 193 ~APMG_PS_CTRL_MSK_PWR_SRC); 194 else 195 iwl_set_bits_mask_prph(trans, APMG_PS_CTRL_REG, 196 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 197 ~APMG_PS_CTRL_MSK_PWR_SRC); 198} 199 200/* PCI registers */ 201#define PCI_CFG_RETRY_TIMEOUT 0x041 202 203void iwl_pcie_apm_config(struct iwl_trans *trans) 204{ 205 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 206 u16 lctl; 207 u16 cap; 208 209 /* 210 * L0S states have been found to be unstable with our devices 211 * and in newer hardware they are not officially supported at 212 * all, so we must always set the L0S_DISABLED bit. 213 */ 214 iwl_set_bit(trans, CSR_GIO_REG, CSR_GIO_REG_VAL_L0S_DISABLED); 215 216 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_LNKCTL, &lctl); 217 trans_pcie->pm_support = !(lctl & PCI_EXP_LNKCTL_ASPM_L0S); 218 219 pcie_capability_read_word(trans_pcie->pci_dev, PCI_EXP_DEVCTL2, &cap); 220 trans_pcie->ltr_enabled = cap & PCI_EXP_DEVCTL2_LTR_EN; 221 IWL_DEBUG_POWER(trans, "L1 %sabled - LTR %sabled\n", 222 (lctl & PCI_EXP_LNKCTL_ASPM_L1) ? "En" : "Dis", 223 trans_pcie->ltr_enabled ? "En" : "Dis"); 224} 225 226/* 227 * Start up NIC's basic functionality after it has been reset 228 * (e.g. after platform boot, or shutdown via iwl_pcie_apm_stop()) 229 * NOTE: This does not load uCode nor start the embedded processor 230 */ 231static int iwl_pcie_apm_init(struct iwl_trans *trans) 232{ 233 int ret; 234 235 IWL_DEBUG_INFO(trans, "Init card's basic functions\n"); 236 237 /* 238 * Use "set_bit" below rather than "write", to preserve any hardware 239 * bits already set by default after reset. 240 */ 241 242 /* Disable L0S exit timer (platform NMI Work/Around) */ 243 if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_8000) 244 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 245 CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER); 246 247 /* 248 * Disable L0s without affecting L1; 249 * don't wait for ICH L0s (ICH bug W/A) 250 */ 251 iwl_set_bit(trans, CSR_GIO_CHICKEN_BITS, 252 CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX); 253 254 /* Set FH wait threshold to maximum (HW error during stress W/A) */ 255 iwl_set_bit(trans, CSR_DBG_HPET_MEM_REG, CSR_DBG_HPET_MEM_REG_VAL); 256 257 /* 258 * Enable HAP INTA (interrupt from management bus) to 259 * wake device's PCI Express link L1a -> L0s 260 */ 261 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 262 CSR_HW_IF_CONFIG_REG_HAP_WAKE); 263 264 iwl_pcie_apm_config(trans); 265 266 /* Configure analog phase-lock-loop before activating to D0A */ 267 if (trans->mac_cfg->base->pll_cfg) 268 iwl_set_bit(trans, CSR_ANA_PLL_CFG, CSR50_ANA_PLL_CFG_VAL); 269 270 ret = iwl_trans_activate_nic(trans); 271 if (ret) 272 return ret; 273 274 if (trans->cfg->host_interrupt_operation_mode) { 275 /* 276 * This is a bit of an abuse - This is needed for 7260 / 3160 277 * only check host_interrupt_operation_mode even if this is 278 * not related to host_interrupt_operation_mode. 279 * 280 * Enable the oscillator to count wake up time for L1 exit. This 281 * consumes slightly more power (100uA) - but allows to be sure 282 * that we wake up from L1 on time. 283 * 284 * This looks weird: read twice the same register, discard the 285 * value, set a bit, and yet again, read that same register 286 * just to discard the value. But that's the way the hardware 287 * seems to like it. 288 */ 289 iwl_read_prph(trans, OSC_CLK); 290 iwl_read_prph(trans, OSC_CLK); 291 iwl_set_bits_prph(trans, OSC_CLK, OSC_CLK_FORCE_CONTROL); 292 iwl_read_prph(trans, OSC_CLK); 293 iwl_read_prph(trans, OSC_CLK); 294 } 295 296 /* 297 * Enable DMA clock and wait for it to stabilize. 298 * 299 * Write to "CLK_EN_REG"; "1" bits enable clocks, while "0" 300 * bits do not disable clocks. This preserves any hardware 301 * bits already set by default in "CLK_CTRL_REG" after reset. 302 */ 303 if (!trans->mac_cfg->base->apmg_not_supported) { 304 iwl_write_prph(trans, APMG_CLK_EN_REG, 305 APMG_CLK_VAL_DMA_CLK_RQT); 306 udelay(20); 307 308 /* Disable L1-Active */ 309 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 310 APMG_PCIDEV_STT_VAL_L1_ACT_DIS); 311 312 /* Clear the interrupt in APMG if the NIC is in RFKILL */ 313 iwl_write_prph(trans, APMG_RTC_INT_STT_REG, 314 APMG_RTC_INT_STT_RFKILL); 315 } 316 317 set_bit(STATUS_DEVICE_ENABLED, &trans->status); 318 319 return 0; 320} 321 322/* 323 * Enable LP XTAL to avoid HW bug where device may consume much power if 324 * FW is not loaded after device reset. LP XTAL is disabled by default 325 * after device HW reset. Do it only if XTAL is fed by internal source. 326 * Configure device's "persistence" mode to avoid resetting XTAL again when 327 * SHRD_HW_RST occurs in S3. 328 */ 329static void iwl_pcie_apm_lp_xtal_enable(struct iwl_trans *trans) 330{ 331 int ret; 332 u32 apmg_gp1_reg; 333 u32 apmg_xtal_cfg_reg; 334 u32 dl_cfg_reg; 335 336 /* Force XTAL ON */ 337 iwl_trans_set_bit(trans, CSR_GP_CNTRL, 338 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 339 340 ret = iwl_trans_pcie_sw_reset(trans, true); 341 342 if (!ret) 343 ret = iwl_trans_activate_nic(trans); 344 345 if (WARN_ON(ret)) { 346 /* Release XTAL ON request */ 347 iwl_trans_clear_bit(trans, CSR_GP_CNTRL, 348 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 349 return; 350 } 351 352 /* 353 * Clear "disable persistence" to avoid LP XTAL resetting when 354 * SHRD_HW_RST is applied in S3. 355 */ 356 iwl_clear_bits_prph(trans, APMG_PCIDEV_STT_REG, 357 APMG_PCIDEV_STT_VAL_PERSIST_DIS); 358 359 /* 360 * Force APMG XTAL to be active to prevent its disabling by HW 361 * caused by APMG idle state. 362 */ 363 apmg_xtal_cfg_reg = iwl_trans_pcie_read_shr(trans, 364 SHR_APMG_XTAL_CFG_REG); 365 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 366 apmg_xtal_cfg_reg | 367 SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 368 369 ret = iwl_trans_pcie_sw_reset(trans, true); 370 if (ret) 371 IWL_ERR(trans, 372 "iwl_pcie_apm_lp_xtal_enable: failed to retake NIC ownership\n"); 373 374 /* Enable LP XTAL by indirect access through CSR */ 375 apmg_gp1_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_GP1_REG); 376 iwl_trans_pcie_write_shr(trans, SHR_APMG_GP1_REG, apmg_gp1_reg | 377 SHR_APMG_GP1_WF_XTAL_LP_EN | 378 SHR_APMG_GP1_CHICKEN_BIT_SELECT); 379 380 /* Clear delay line clock power up */ 381 dl_cfg_reg = iwl_trans_pcie_read_shr(trans, SHR_APMG_DL_CFG_REG); 382 iwl_trans_pcie_write_shr(trans, SHR_APMG_DL_CFG_REG, dl_cfg_reg & 383 ~SHR_APMG_DL_CFG_DL_CLOCK_POWER_UP); 384 385 /* 386 * Enable persistence mode to avoid LP XTAL resetting when 387 * SHRD_HW_RST is applied in S3. 388 */ 389 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 390 CSR_HW_IF_CONFIG_REG_PERSISTENCE); 391 392 /* 393 * Clear "initialization complete" bit to move adapter from 394 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 395 */ 396 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 397 398 /* Activates XTAL resources monitor */ 399 iwl_trans_set_bit(trans, CSR_MONITOR_CFG_REG, 400 CSR_MONITOR_XTAL_RESOURCES); 401 402 /* Release XTAL ON request */ 403 iwl_trans_clear_bit(trans, CSR_GP_CNTRL, 404 CSR_GP_CNTRL_REG_FLAG_XTAL_ON); 405 udelay(10); 406 407 /* Release APMG XTAL */ 408 iwl_trans_pcie_write_shr(trans, SHR_APMG_XTAL_CFG_REG, 409 apmg_xtal_cfg_reg & 410 ~SHR_APMG_XTAL_CFG_XTAL_ON_REQ); 411} 412 413void iwl_pcie_apm_stop_master(struct iwl_trans *trans) 414{ 415 int ret; 416 417 /* stop device's busmaster DMA activity */ 418 419 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 420 iwl_set_bit(trans, CSR_GP_CNTRL, 421 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ); 422 423 ret = iwl_poll_bits(trans, CSR_GP_CNTRL, 424 CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS, 425 100); 426 usleep_range(10000, 20000); 427 } else { 428 iwl_set_bit(trans, CSR_RESET, CSR_RESET_REG_FLAG_STOP_MASTER); 429 430 ret = iwl_poll_bits(trans, CSR_RESET, 431 CSR_RESET_REG_FLAG_MASTER_DISABLED, 100); 432 } 433 434 if (ret) 435 IWL_WARN(trans, "Master Disable Timed Out, 100 usec\n"); 436 437 IWL_DEBUG_INFO(trans, "stop master\n"); 438} 439 440static void iwl_pcie_apm_stop(struct iwl_trans *trans, bool op_mode_leave) 441{ 442 IWL_DEBUG_INFO(trans, "Stop card, put in low power state\n"); 443 444 if (op_mode_leave) { 445 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 446 iwl_pcie_apm_init(trans); 447 448 /* inform ME that we are leaving */ 449 if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_7000) 450 iwl_set_bits_prph(trans, APMG_PCIDEV_STT_REG, 451 APMG_PCIDEV_STT_VAL_WAKE_ME); 452 else if (trans->mac_cfg->device_family >= 453 IWL_DEVICE_FAMILY_8000) { 454 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 455 CSR_RESET_LINK_PWR_MGMT_DISABLED); 456 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 457 CSR_HW_IF_CONFIG_REG_WAKE_ME | 458 CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN); 459 mdelay(1); 460 iwl_clear_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 461 CSR_RESET_LINK_PWR_MGMT_DISABLED); 462 } 463 mdelay(5); 464 } 465 466 clear_bit(STATUS_DEVICE_ENABLED, &trans->status); 467 468 /* Stop device's DMA activity */ 469 iwl_pcie_apm_stop_master(trans); 470 471 if (trans->cfg->lp_xtal_workaround) { 472 iwl_pcie_apm_lp_xtal_enable(trans); 473 return; 474 } 475 476 iwl_trans_pcie_sw_reset(trans, false); 477 478 /* 479 * Clear "initialization complete" bit to move adapter from 480 * D0A* (powered-up Active) --> D0U* (Uninitialized) state. 481 */ 482 iwl_clear_bit(trans, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 483} 484 485static int iwl_pcie_nic_init(struct iwl_trans *trans) 486{ 487 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 488 int ret; 489 490 /* nic_init */ 491 spin_lock_bh(&trans_pcie->irq_lock); 492 ret = iwl_pcie_apm_init(trans); 493 spin_unlock_bh(&trans_pcie->irq_lock); 494 495 if (ret) 496 return ret; 497 498 iwl_pcie_set_pwr(trans, false); 499 500 iwl_op_mode_nic_config(trans->op_mode); 501 502 /* Allocate the RX queue, or reset if it is already allocated */ 503 ret = iwl_pcie_rx_init(trans); 504 if (ret) 505 return ret; 506 507 /* Allocate or reset and init all Tx and Command queues */ 508 if (iwl_pcie_tx_init(trans)) { 509 iwl_pcie_rx_free(trans); 510 return -ENOMEM; 511 } 512 513 if (trans->mac_cfg->base->shadow_reg_enable) { 514 /* enable shadow regs in HW */ 515 iwl_set_bit(trans, CSR_MAC_SHADOW_REG_CTRL, 0x800FFFFF); 516 IWL_DEBUG_INFO(trans, "Enabling shadow registers in device\n"); 517 } 518 519 return 0; 520} 521 522#define HW_READY_TIMEOUT (50) 523 524/* Note: returns poll_bit return value, which is >= 0 if success */ 525static int iwl_pcie_set_hw_ready(struct iwl_trans *trans) 526{ 527 int ret; 528 529 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 530 CSR_HW_IF_CONFIG_REG_PCI_OWN_SET); 531 532 /* See if we got it */ 533 ret = iwl_poll_bits(trans, CSR_HW_IF_CONFIG_REG, 534 CSR_HW_IF_CONFIG_REG_PCI_OWN_SET, 535 HW_READY_TIMEOUT); 536 537 if (!ret) 538 iwl_set_bit(trans, CSR_MBOX_SET_REG, CSR_MBOX_SET_REG_OS_ALIVE); 539 540 IWL_DEBUG_INFO(trans, "hardware%s ready\n", ret ? " not" : ""); 541 return ret; 542} 543 544/* Note: returns standard 0/-ERROR code */ 545int iwl_pcie_prepare_card_hw(struct iwl_trans *trans) 546{ 547 int ret; 548 int iter; 549 550 IWL_DEBUG_INFO(trans, "iwl_trans_prepare_card_hw enter\n"); 551 552 ret = iwl_pcie_set_hw_ready(trans); 553 /* If the card is ready, exit 0 */ 554 if (!ret) { 555 trans->csme_own = false; 556 return 0; 557 } 558 559 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 560 CSR_RESET_LINK_PWR_MGMT_DISABLED); 561 usleep_range(1000, 2000); 562 563 for (iter = 0; iter < 10; iter++) { 564 int t = 0; 565 566 /* If HW is not ready, prepare the conditions to check again */ 567 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 568 CSR_HW_IF_CONFIG_REG_WAKE_ME); 569 570 do { 571 ret = iwl_pcie_set_hw_ready(trans); 572 if (!ret) { 573 trans->csme_own = false; 574 return 0; 575 } 576 577 if (iwl_mei_is_connected()) { 578 IWL_DEBUG_INFO(trans, 579 "Couldn't prepare the card but SAP is connected\n"); 580 trans->csme_own = true; 581 if (trans->mac_cfg->device_family != 582 IWL_DEVICE_FAMILY_9000) 583 IWL_ERR(trans, 584 "SAP not supported for this NIC family\n"); 585 586 return -EBUSY; 587 } 588 589 usleep_range(200, 1000); 590 t += 200; 591 } while (t < 150000); 592 msleep(25); 593 } 594 595 IWL_ERR(trans, "Couldn't prepare the card\n"); 596 597 return ret; 598} 599 600/* 601 * ucode 602 */ 603static void iwl_pcie_load_firmware_chunk_fh(struct iwl_trans *trans, 604 u32 dst_addr, dma_addr_t phy_addr, 605 u32 byte_cnt) 606{ 607 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 608 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_PAUSE); 609 610 iwl_write32(trans, FH_SRVC_CHNL_SRAM_ADDR_REG(FH_SRVC_CHNL), 611 dst_addr); 612 613 iwl_write32(trans, FH_TFDIB_CTRL0_REG(FH_SRVC_CHNL), 614 phy_addr & FH_MEM_TFDIB_DRAM_ADDR_LSB_MSK); 615 616 iwl_write32(trans, FH_TFDIB_CTRL1_REG(FH_SRVC_CHNL), 617 (iwl_get_dma_hi_addr(phy_addr) 618 << FH_MEM_TFDIB_REG1_ADDR_BITSHIFT) | byte_cnt); 619 620 iwl_write32(trans, FH_TCSR_CHNL_TX_BUF_STS_REG(FH_SRVC_CHNL), 621 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_NUM) | 622 BIT(FH_TCSR_CHNL_TX_BUF_STS_REG_POS_TB_IDX) | 623 FH_TCSR_CHNL_TX_BUF_STS_REG_VAL_TFDB_VALID); 624 625 iwl_write32(trans, FH_TCSR_CHNL_TX_CONFIG_REG(FH_SRVC_CHNL), 626 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 627 FH_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_DISABLE | 628 FH_TCSR_TX_CONFIG_REG_VAL_CIRQ_HOST_ENDTFD); 629} 630 631static int iwl_pcie_load_firmware_chunk(struct iwl_trans *trans, 632 u32 dst_addr, dma_addr_t phy_addr, 633 u32 byte_cnt) 634{ 635 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 636 int ret; 637 638 trans_pcie->ucode_write_complete = false; 639 640 if (!iwl_trans_grab_nic_access(trans)) 641 return -EIO; 642 643 iwl_pcie_load_firmware_chunk_fh(trans, dst_addr, phy_addr, 644 byte_cnt); 645 iwl_trans_release_nic_access(trans); 646 647 ret = wait_event_timeout(trans_pcie->ucode_write_waitq, 648 trans_pcie->ucode_write_complete, 5 * HZ); 649 if (!ret) { 650 IWL_ERR(trans, "Failed to load firmware chunk!\n"); 651 iwl_trans_pcie_dump_regs(trans, trans_pcie->pci_dev); 652 return -ETIMEDOUT; 653 } 654 655 return 0; 656} 657 658static int iwl_pcie_load_section(struct iwl_trans *trans, u8 section_num, 659 const struct fw_desc *section) 660{ 661 u8 *v_addr; 662 dma_addr_t p_addr; 663 u32 offset, chunk_sz = min_t(u32, FH_MEM_TB_MAX_LENGTH, section->len); 664 int ret = 0; 665 666 IWL_DEBUG_FW(trans, "[%d] uCode section being loaded...\n", 667 section_num); 668 669 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, &p_addr, 670 GFP_KERNEL | __GFP_NOWARN); 671 if (!v_addr) { 672 IWL_DEBUG_INFO(trans, "Falling back to small chunks of DMA\n"); 673 chunk_sz = PAGE_SIZE; 674 v_addr = dma_alloc_coherent(trans->dev, chunk_sz, 675 &p_addr, GFP_KERNEL); 676 if (!v_addr) 677 return -ENOMEM; 678 } 679 680 for (offset = 0; offset < section->len; offset += chunk_sz) { 681 u32 copy_size, dst_addr; 682 bool extended_addr = false; 683 684 copy_size = min_t(u32, chunk_sz, section->len - offset); 685 dst_addr = section->offset + offset; 686 687 if (dst_addr >= IWL_FW_MEM_EXTENDED_START && 688 dst_addr <= IWL_FW_MEM_EXTENDED_END) 689 extended_addr = true; 690 691 if (extended_addr) 692 iwl_set_bits_prph(trans, LMPM_CHICK, 693 LMPM_CHICK_EXTENDED_ADDR_SPACE); 694 695 memcpy(v_addr, (const u8 *)section->data + offset, copy_size); 696 ret = iwl_pcie_load_firmware_chunk(trans, dst_addr, p_addr, 697 copy_size); 698 699 if (extended_addr) 700 iwl_clear_bits_prph(trans, LMPM_CHICK, 701 LMPM_CHICK_EXTENDED_ADDR_SPACE); 702 703 if (ret) { 704 IWL_ERR(trans, 705 "Could not load the [%d] uCode section\n", 706 section_num); 707 break; 708 } 709 } 710 711 dma_free_coherent(trans->dev, chunk_sz, v_addr, p_addr); 712 return ret; 713} 714 715static int iwl_pcie_load_cpu_sections_8000(struct iwl_trans *trans, 716 const struct fw_img *image, 717 int cpu, 718 int *first_ucode_section) 719{ 720 int shift_param; 721 int i, ret = 0, sec_num = 0x1; 722 u32 val, last_read_idx = 0; 723 724 if (cpu == 1) { 725 shift_param = 0; 726 *first_ucode_section = 0; 727 } else { 728 shift_param = 16; 729 (*first_ucode_section)++; 730 } 731 732 for (i = *first_ucode_section; i < image->num_sec; i++) { 733 last_read_idx = i; 734 735 /* 736 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 737 * CPU1 to CPU2. 738 * PAGING_SEPARATOR_SECTION delimiter - separate between 739 * CPU2 non paged to CPU2 paging sec. 740 */ 741 if (!image->sec[i].data || 742 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 743 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 744 IWL_DEBUG_FW(trans, 745 "Break since Data not valid or Empty section, sec = %d\n", 746 i); 747 break; 748 } 749 750 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 751 if (ret) 752 return ret; 753 754 /* Notify ucode of loaded section number and status */ 755 val = iwl_read_direct32(trans, FH_UCODE_LOAD_STATUS); 756 val = val | (sec_num << shift_param); 757 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, val); 758 759 sec_num = (sec_num << 1) | 0x1; 760 } 761 762 *first_ucode_section = last_read_idx; 763 764 iwl_enable_interrupts(trans); 765 766 if (trans->mac_cfg->gen2) { 767 if (cpu == 1) 768 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 769 0xFFFF); 770 else 771 iwl_write_prph(trans, UREG_UCODE_LOAD_STATUS, 772 0xFFFFFFFF); 773 } else { 774 if (cpu == 1) 775 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 776 0xFFFF); 777 else 778 iwl_write_direct32(trans, FH_UCODE_LOAD_STATUS, 779 0xFFFFFFFF); 780 } 781 782 return 0; 783} 784 785static int iwl_pcie_load_cpu_sections(struct iwl_trans *trans, 786 const struct fw_img *image, 787 int cpu, 788 int *first_ucode_section) 789{ 790 int i, ret = 0; 791 u32 last_read_idx = 0; 792 793 if (cpu == 1) 794 *first_ucode_section = 0; 795 else 796 (*first_ucode_section)++; 797 798 for (i = *first_ucode_section; i < image->num_sec; i++) { 799 last_read_idx = i; 800 801 /* 802 * CPU1_CPU2_SEPARATOR_SECTION delimiter - separate between 803 * CPU1 to CPU2. 804 * PAGING_SEPARATOR_SECTION delimiter - separate between 805 * CPU2 non paged to CPU2 paging sec. 806 */ 807 if (!image->sec[i].data || 808 image->sec[i].offset == CPU1_CPU2_SEPARATOR_SECTION || 809 image->sec[i].offset == PAGING_SEPARATOR_SECTION) { 810 IWL_DEBUG_FW(trans, 811 "Break since Data not valid or Empty section, sec = %d\n", 812 i); 813 break; 814 } 815 816 ret = iwl_pcie_load_section(trans, i, &image->sec[i]); 817 if (ret) 818 return ret; 819 } 820 821 *first_ucode_section = last_read_idx; 822 823 return 0; 824} 825 826static void iwl_pcie_apply_destination_ini(struct iwl_trans *trans) 827{ 828 enum iwl_fw_ini_allocation_id alloc_id = IWL_FW_INI_ALLOCATION_ID_DBGC1; 829 struct iwl_fw_ini_allocation_tlv *fw_mon_cfg = 830 &trans->dbg.fw_mon_cfg[alloc_id]; 831 struct iwl_dram_data *frag; 832 833 if (!iwl_trans_dbg_ini_valid(trans)) 834 return; 835 836 if (le32_to_cpu(fw_mon_cfg->buf_location) == 837 IWL_FW_INI_LOCATION_SRAM_PATH) { 838 IWL_DEBUG_FW(trans, "WRT: Applying SMEM buffer destination\n"); 839 /* set sram monitor by enabling bit 7 */ 840 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 841 CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM); 842 843 return; 844 } 845 846 if (le32_to_cpu(fw_mon_cfg->buf_location) != 847 IWL_FW_INI_LOCATION_DRAM_PATH || 848 !trans->dbg.fw_mon_ini[alloc_id].num_frags) 849 return; 850 851 frag = &trans->dbg.fw_mon_ini[alloc_id].frags[0]; 852 853 IWL_DEBUG_FW(trans, "WRT: Applying DRAM destination (alloc_id=%u)\n", 854 alloc_id); 855 856 iwl_write_umac_prph(trans, MON_BUFF_BASE_ADDR_VER2, 857 frag->physical >> MON_BUFF_SHIFT_VER2); 858 iwl_write_umac_prph(trans, MON_BUFF_END_ADDR_VER2, 859 (frag->physical + frag->size - 256) >> 860 MON_BUFF_SHIFT_VER2); 861} 862 863void iwl_pcie_apply_destination(struct iwl_trans *trans) 864{ 865 const struct iwl_fw_dbg_dest_tlv_v1 *dest = trans->dbg.dest_tlv; 866 const struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 867 int i; 868 869 if (iwl_trans_dbg_ini_valid(trans)) { 870 iwl_pcie_apply_destination_ini(trans); 871 return; 872 } 873 874 IWL_INFO(trans, "Applying debug destination %s\n", 875 get_fw_dbg_mode_string(dest->monitor_mode)); 876 877 if (dest->monitor_mode == EXTERNAL_MODE) 878 iwl_pcie_alloc_fw_monitor(trans, dest->size_power); 879 else 880 IWL_WARN(trans, "PCI should have external buffer debug\n"); 881 882 for (i = 0; i < trans->dbg.n_dest_reg; i++) { 883 u32 addr = le32_to_cpu(dest->reg_ops[i].addr); 884 u32 val = le32_to_cpu(dest->reg_ops[i].val); 885 886 switch (dest->reg_ops[i].op) { 887 case CSR_ASSIGN: 888 iwl_write32(trans, addr, val); 889 break; 890 case CSR_SETBIT: 891 iwl_set_bit(trans, addr, BIT(val)); 892 break; 893 case CSR_CLEARBIT: 894 iwl_clear_bit(trans, addr, BIT(val)); 895 break; 896 case PRPH_ASSIGN: 897 iwl_write_prph(trans, addr, val); 898 break; 899 case PRPH_SETBIT: 900 iwl_set_bits_prph(trans, addr, BIT(val)); 901 break; 902 case PRPH_CLEARBIT: 903 iwl_clear_bits_prph(trans, addr, BIT(val)); 904 break; 905 case PRPH_BLOCKBIT: 906 if (iwl_read_prph(trans, addr) & BIT(val)) { 907 IWL_ERR(trans, 908 "BIT(%u) in address 0x%x is 1, stopping FW configuration\n", 909 val, addr); 910 goto monitor; 911 } 912 break; 913 default: 914 IWL_ERR(trans, "FW debug - unknown OP %d\n", 915 dest->reg_ops[i].op); 916 break; 917 } 918 } 919 920monitor: 921 if (dest->monitor_mode == EXTERNAL_MODE && fw_mon->size) { 922 iwl_write_prph(trans, le32_to_cpu(dest->base_reg), 923 fw_mon->physical >> dest->base_shift); 924 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 925 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 926 (fw_mon->physical + fw_mon->size - 927 256) >> dest->end_shift); 928 else 929 iwl_write_prph(trans, le32_to_cpu(dest->end_reg), 930 (fw_mon->physical + fw_mon->size) >> 931 dest->end_shift); 932 } 933} 934 935static int iwl_pcie_load_given_ucode(struct iwl_trans *trans, 936 const struct fw_img *image) 937{ 938 int ret = 0; 939 int first_ucode_section; 940 941 IWL_DEBUG_FW(trans, "working with %s CPU\n", 942 image->is_dual_cpus ? "Dual" : "Single"); 943 944 /* load to FW the binary non secured sections of CPU1 */ 945 ret = iwl_pcie_load_cpu_sections(trans, image, 1, &first_ucode_section); 946 if (ret) 947 return ret; 948 949 if (image->is_dual_cpus) { 950 /* set CPU2 header address */ 951 iwl_write_prph(trans, 952 LMPM_SECURE_UCODE_LOAD_CPU2_HDR_ADDR, 953 LMPM_SECURE_CPU2_HDR_MEM_SPACE); 954 955 /* load to FW the binary sections of CPU2 */ 956 ret = iwl_pcie_load_cpu_sections(trans, image, 2, 957 &first_ucode_section); 958 if (ret) 959 return ret; 960 } 961 962 if (iwl_pcie_dbg_on(trans)) 963 iwl_pcie_apply_destination(trans); 964 965 iwl_enable_interrupts(trans); 966 967 /* release CPU reset */ 968 iwl_write32(trans, CSR_RESET, 0); 969 970 return 0; 971} 972 973static int iwl_pcie_load_given_ucode_8000(struct iwl_trans *trans, 974 const struct fw_img *image) 975{ 976 int ret = 0; 977 int first_ucode_section; 978 979 IWL_DEBUG_FW(trans, "working with %s CPU\n", 980 image->is_dual_cpus ? "Dual" : "Single"); 981 982 if (iwl_pcie_dbg_on(trans)) 983 iwl_pcie_apply_destination(trans); 984 985 IWL_DEBUG_POWER(trans, "Original WFPM value = 0x%08X\n", 986 iwl_read_prph(trans, WFPM_GP2)); 987 988 /* 989 * Set default value. On resume reading the values that were 990 * zeored can provide debug data on the resume flow. 991 * This is for debugging only and has no functional impact. 992 */ 993 iwl_write_prph(trans, WFPM_GP2, 0x01010101); 994 995 /* configure the ucode to be ready to get the secured image */ 996 /* release CPU reset */ 997 iwl_write_prph(trans, RELEASE_CPU_RESET, RELEASE_CPU_RESET_BIT); 998 999 /* load to FW the binary Secured sections of CPU1 */ 1000 ret = iwl_pcie_load_cpu_sections_8000(trans, image, 1, 1001 &first_ucode_section); 1002 if (ret) 1003 return ret; 1004 1005 /* load to FW the binary sections of CPU2 */ 1006 return iwl_pcie_load_cpu_sections_8000(trans, image, 2, 1007 &first_ucode_section); 1008} 1009 1010bool iwl_pcie_check_hw_rf_kill(struct iwl_trans *trans) 1011{ 1012 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1013 bool hw_rfkill = iwl_is_rfkill_set(trans); 1014 bool prev = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1015 bool report; 1016 1017 if (hw_rfkill) { 1018 set_bit(STATUS_RFKILL_HW, &trans->status); 1019 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1020 } else { 1021 clear_bit(STATUS_RFKILL_HW, &trans->status); 1022 if (trans_pcie->opmode_down) 1023 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1024 } 1025 1026 report = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1027 1028 if (prev != report) 1029 iwl_trans_pcie_rf_kill(trans, report, false); 1030 1031 return hw_rfkill; 1032} 1033 1034struct iwl_causes_list { 1035 u16 mask_reg; 1036 u8 bit; 1037 u8 addr; 1038}; 1039 1040#define IWL_CAUSE(reg, mask) \ 1041 { \ 1042 .mask_reg = reg, \ 1043 .bit = ilog2(mask), \ 1044 .addr = ilog2(mask) + \ 1045 ((reg) == CSR_MSIX_FH_INT_MASK_AD ? -16 : \ 1046 (reg) == CSR_MSIX_HW_INT_MASK_AD ? 16 : \ 1047 0xffff), /* causes overflow warning */ \ 1048 } 1049 1050static const struct iwl_causes_list causes_list_common[] = { 1051 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH0_NUM), 1052 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_D2S_CH1_NUM), 1053 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_S2D), 1054 IWL_CAUSE(CSR_MSIX_FH_INT_MASK_AD, MSIX_FH_INT_CAUSES_FH_ERR), 1055 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_ALIVE), 1056 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_WAKEUP), 1057 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RESET_DONE), 1058 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_TOP_FATAL_ERR), 1059 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_CT_KILL), 1060 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_RF_KILL), 1061 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_PERIODIC), 1062 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SCD), 1063 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_FH_TX), 1064 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HW_ERR), 1065 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_HAP), 1066}; 1067 1068static const struct iwl_causes_list causes_list_pre_bz[] = { 1069 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR), 1070}; 1071 1072static const struct iwl_causes_list causes_list_bz[] = { 1073 IWL_CAUSE(CSR_MSIX_HW_INT_MASK_AD, MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ), 1074}; 1075 1076static void iwl_pcie_map_list(struct iwl_trans *trans, 1077 const struct iwl_causes_list *causes, 1078 int arr_size, int val) 1079{ 1080 int i; 1081 1082 for (i = 0; i < arr_size; i++) { 1083 iwl_write8(trans, CSR_MSIX_IVAR(causes[i].addr), val); 1084 iwl_clear_bit(trans, causes[i].mask_reg, 1085 BIT(causes[i].bit)); 1086 } 1087} 1088 1089static void iwl_pcie_map_non_rx_causes(struct iwl_trans *trans) 1090{ 1091 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1092 int val = trans_pcie->def_irq | MSIX_NON_AUTO_CLEAR_CAUSE; 1093 /* 1094 * Access all non RX causes and map them to the default irq. 1095 * In case we are missing at least one interrupt vector, 1096 * the first interrupt vector will serve non-RX and FBQ causes. 1097 */ 1098 iwl_pcie_map_list(trans, causes_list_common, 1099 ARRAY_SIZE(causes_list_common), val); 1100 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1101 iwl_pcie_map_list(trans, causes_list_bz, 1102 ARRAY_SIZE(causes_list_bz), val); 1103 else 1104 iwl_pcie_map_list(trans, causes_list_pre_bz, 1105 ARRAY_SIZE(causes_list_pre_bz), val); 1106} 1107 1108static void iwl_pcie_map_rx_causes(struct iwl_trans *trans) 1109{ 1110 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1111 u32 offset = 1112 trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 1 : 0; 1113 u32 val, idx; 1114 1115 /* 1116 * The first RX queue - fallback queue, which is designated for 1117 * management frame, command responses etc, is always mapped to the 1118 * first interrupt vector. The other RX queues are mapped to 1119 * the other (N - 2) interrupt vectors. 1120 */ 1121 val = BIT(MSIX_FH_INT_CAUSES_Q(0)); 1122 for (idx = 1; idx < trans->info.num_rxqs; idx++) { 1123 iwl_write8(trans, CSR_MSIX_RX_IVAR(idx), 1124 MSIX_FH_INT_CAUSES_Q(idx - offset)); 1125 val |= BIT(MSIX_FH_INT_CAUSES_Q(idx)); 1126 } 1127 iwl_write32(trans, CSR_MSIX_FH_INT_MASK_AD, ~val); 1128 1129 val = MSIX_FH_INT_CAUSES_Q(0); 1130 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_NON_RX) 1131 val |= MSIX_NON_AUTO_CLEAR_CAUSE; 1132 iwl_write8(trans, CSR_MSIX_RX_IVAR(0), val); 1133 1134 if (trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS) 1135 iwl_write8(trans, CSR_MSIX_RX_IVAR(1), val); 1136} 1137 1138void iwl_pcie_conf_msix_hw(struct iwl_trans_pcie *trans_pcie) 1139{ 1140 struct iwl_trans *trans = trans_pcie->trans; 1141 1142 if (!trans_pcie->msix_enabled) { 1143 if (trans->mac_cfg->mq_rx_supported && 1144 test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1145 iwl_write_umac_prph(trans, UREG_CHICK, 1146 UREG_CHICK_MSI_ENABLE); 1147 return; 1148 } 1149 /* 1150 * The IVAR table needs to be configured again after reset, 1151 * but if the device is disabled, we can't write to 1152 * prph. 1153 */ 1154 if (test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 1155 iwl_write_umac_prph(trans, UREG_CHICK, UREG_CHICK_MSIX_ENABLE); 1156 1157 /* 1158 * Each cause from the causes list above and the RX causes is 1159 * represented as a byte in the IVAR table. The first nibble 1160 * represents the bound interrupt vector of the cause, the second 1161 * represents no auto clear for this cause. This will be set if its 1162 * interrupt vector is bound to serve other causes. 1163 */ 1164 iwl_pcie_map_rx_causes(trans); 1165 1166 iwl_pcie_map_non_rx_causes(trans); 1167} 1168 1169static void iwl_pcie_init_msix(struct iwl_trans_pcie *trans_pcie) 1170{ 1171 struct iwl_trans *trans = trans_pcie->trans; 1172 1173 iwl_pcie_conf_msix_hw(trans_pcie); 1174 1175 if (!trans_pcie->msix_enabled) 1176 return; 1177 1178 trans_pcie->fh_init_mask = ~iwl_read32(trans, CSR_MSIX_FH_INT_MASK_AD); 1179 trans_pcie->fh_mask = trans_pcie->fh_init_mask; 1180 trans_pcie->hw_init_mask = ~iwl_read32(trans, CSR_MSIX_HW_INT_MASK_AD); 1181 trans_pcie->hw_mask = trans_pcie->hw_init_mask; 1182} 1183 1184static void _iwl_trans_pcie_stop_device(struct iwl_trans *trans, bool from_irq) 1185{ 1186 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1187 1188 lockdep_assert_held(&trans_pcie->mutex); 1189 1190 if (trans_pcie->is_down) 1191 return; 1192 1193 trans_pcie->is_down = true; 1194 1195 /* tell the device to stop sending interrupts */ 1196 iwl_disable_interrupts(trans); 1197 1198 /* device going down, Stop using ICT table */ 1199 iwl_pcie_disable_ict(trans); 1200 1201 /* 1202 * If a HW restart happens during firmware loading, 1203 * then the firmware loading might call this function 1204 * and later it might be called again due to the 1205 * restart. So don't process again if the device is 1206 * already dead. 1207 */ 1208 if (test_and_clear_bit(STATUS_DEVICE_ENABLED, &trans->status)) { 1209 IWL_DEBUG_INFO(trans, 1210 "DEVICE_ENABLED bit was set and is now cleared\n"); 1211 if (!from_irq) 1212 iwl_pcie_synchronize_irqs(trans); 1213 iwl_pcie_rx_napi_sync(trans); 1214 iwl_pcie_tx_stop(trans); 1215 iwl_pcie_rx_stop(trans); 1216 1217 /* Power-down device's busmaster DMA clocks */ 1218 if (!trans->mac_cfg->base->apmg_not_supported) { 1219 iwl_write_prph(trans, APMG_CLK_DIS_REG, 1220 APMG_CLK_VAL_DMA_CLK_RQT); 1221 udelay(5); 1222 } 1223 } 1224 1225 /* Make sure (redundant) we've released our request to stay awake */ 1226 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1227 iwl_clear_bit(trans, CSR_GP_CNTRL, 1228 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 1229 else 1230 iwl_clear_bit(trans, CSR_GP_CNTRL, 1231 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1232 1233 /* Stop the device, and put it in low power state */ 1234 iwl_pcie_apm_stop(trans, false); 1235 1236 /* re-take ownership to prevent other users from stealing the device */ 1237 iwl_trans_pcie_sw_reset(trans, true); 1238 1239 /* 1240 * Upon stop, the IVAR table gets erased, so msi-x won't 1241 * work. This causes a bug in RF-KILL flows, since the interrupt 1242 * that enables radio won't fire on the correct irq, and the 1243 * driver won't be able to handle the interrupt. 1244 * Configure the IVAR table again after reset. 1245 */ 1246 iwl_pcie_conf_msix_hw(trans_pcie); 1247 1248 /* 1249 * Upon stop, the APM issues an interrupt if HW RF kill is set. 1250 * This is a bug in certain verions of the hardware. 1251 * Certain devices also keep sending HW RF kill interrupt all 1252 * the time, unless the interrupt is ACKed even if the interrupt 1253 * should be masked. Re-ACK all the interrupts here. 1254 */ 1255 iwl_disable_interrupts(trans); 1256 1257 /* clear all status bits */ 1258 clear_bit(STATUS_SYNC_HCMD_ACTIVE, &trans->status); 1259 clear_bit(STATUS_INT_ENABLED, &trans->status); 1260 clear_bit(STATUS_TPOWER_PMI, &trans->status); 1261 1262 /* 1263 * Even if we stop the HW, we still want the RF kill 1264 * interrupt 1265 */ 1266 iwl_enable_rfkill_int(trans); 1267} 1268 1269void iwl_pcie_synchronize_irqs(struct iwl_trans *trans) 1270{ 1271 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1272 1273 if (trans_pcie->msix_enabled) { 1274 int i; 1275 1276 for (i = 0; i < trans_pcie->alloc_vecs; i++) 1277 synchronize_irq(trans_pcie->msix_entries[i].vector); 1278 } else { 1279 synchronize_irq(trans_pcie->pci_dev->irq); 1280 } 1281} 1282 1283int iwl_trans_pcie_start_fw(struct iwl_trans *trans, 1284 const struct iwl_fw *fw, 1285 const struct fw_img *img, 1286 bool run_in_rfkill) 1287{ 1288 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1289 bool hw_rfkill; 1290 int ret; 1291 1292 /* This may fail if AMT took ownership of the device */ 1293 if (iwl_pcie_prepare_card_hw(trans)) { 1294 IWL_WARN(trans, "Exit HW not ready\n"); 1295 return -EIO; 1296 } 1297 1298 iwl_enable_rfkill_int(trans); 1299 1300 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1301 1302 /* 1303 * We enabled the RF-Kill interrupt and the handler may very 1304 * well be running. Disable the interrupts to make sure no other 1305 * interrupt can be fired. 1306 */ 1307 iwl_disable_interrupts(trans); 1308 1309 /* Make sure it finished running */ 1310 iwl_pcie_synchronize_irqs(trans); 1311 1312 mutex_lock(&trans_pcie->mutex); 1313 1314 /* If platform's RF_KILL switch is NOT set to KILL */ 1315 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1316 if (hw_rfkill && !run_in_rfkill) { 1317 ret = -ERFKILL; 1318 goto out; 1319 } 1320 1321 /* Someone called stop_device, don't try to start_fw */ 1322 if (trans_pcie->is_down) { 1323 IWL_WARN(trans, 1324 "Can't start_fw since the HW hasn't been started\n"); 1325 ret = -EIO; 1326 goto out; 1327 } 1328 1329 /* make sure rfkill handshake bits are cleared */ 1330 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1331 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, 1332 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 1333 1334 /* clear (again), then enable host interrupts */ 1335 iwl_write32(trans, CSR_INT, 0xFFFFFFFF); 1336 1337 ret = iwl_pcie_nic_init(trans); 1338 if (ret) { 1339 IWL_ERR(trans, "Unable to init nic\n"); 1340 goto out; 1341 } 1342 1343 /* 1344 * Now, we load the firmware and don't want to be interrupted, even 1345 * by the RF-Kill interrupt (hence mask all the interrupt besides the 1346 * FH_TX interrupt which is needed to load the firmware). If the 1347 * RF-Kill switch is toggled, we will find out after having loaded 1348 * the firmware and return the proper value to the caller. 1349 */ 1350 iwl_enable_fw_load_int(trans); 1351 1352 /* really make sure rfkill handshake bits are cleared */ 1353 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1354 iwl_write32(trans, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 1355 1356 /* Load the given image to the HW */ 1357 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 1358 ret = iwl_pcie_load_given_ucode_8000(trans, img); 1359 else 1360 ret = iwl_pcie_load_given_ucode(trans, img); 1361 1362 /* re-check RF-Kill state since we may have missed the interrupt */ 1363 hw_rfkill = iwl_pcie_check_hw_rf_kill(trans); 1364 if (hw_rfkill && !run_in_rfkill) 1365 ret = -ERFKILL; 1366 1367out: 1368 mutex_unlock(&trans_pcie->mutex); 1369 return ret; 1370} 1371 1372void iwl_trans_pcie_fw_alive(struct iwl_trans *trans) 1373{ 1374 iwl_pcie_reset_ict(trans); 1375 iwl_pcie_tx_start(trans); 1376} 1377 1378void iwl_trans_pcie_handle_stop_rfkill(struct iwl_trans *trans, 1379 bool was_in_rfkill) 1380{ 1381 bool hw_rfkill; 1382 1383 /* 1384 * Check again since the RF kill state may have changed while 1385 * all the interrupts were disabled, in this case we couldn't 1386 * receive the RF kill interrupt and update the state in the 1387 * op_mode. 1388 * Don't call the op_mode if the rkfill state hasn't changed. 1389 * This allows the op_mode to call stop_device from the rfkill 1390 * notification without endless recursion. Under very rare 1391 * circumstances, we might have a small recursion if the rfkill 1392 * state changed exactly now while we were called from stop_device. 1393 * This is very unlikely but can happen and is supported. 1394 */ 1395 hw_rfkill = iwl_is_rfkill_set(trans); 1396 if (hw_rfkill) { 1397 set_bit(STATUS_RFKILL_HW, &trans->status); 1398 set_bit(STATUS_RFKILL_OPMODE, &trans->status); 1399 } else { 1400 clear_bit(STATUS_RFKILL_HW, &trans->status); 1401 clear_bit(STATUS_RFKILL_OPMODE, &trans->status); 1402 } 1403 if (hw_rfkill != was_in_rfkill) 1404 iwl_trans_pcie_rf_kill(trans, hw_rfkill, false); 1405} 1406 1407void iwl_trans_pcie_stop_device(struct iwl_trans *trans) 1408{ 1409 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1410 bool was_in_rfkill; 1411 1412 iwl_op_mode_time_point(trans->op_mode, 1413 IWL_FW_INI_TIME_POINT_HOST_DEVICE_DISABLE, 1414 NULL); 1415 1416 mutex_lock(&trans_pcie->mutex); 1417 trans_pcie->opmode_down = true; 1418 was_in_rfkill = test_bit(STATUS_RFKILL_OPMODE, &trans->status); 1419 _iwl_trans_pcie_stop_device(trans, false); 1420 iwl_trans_pcie_handle_stop_rfkill(trans, was_in_rfkill); 1421 mutex_unlock(&trans_pcie->mutex); 1422} 1423 1424void iwl_trans_pcie_rf_kill(struct iwl_trans *trans, bool state, bool from_irq) 1425{ 1426 struct iwl_trans_pcie __maybe_unused *trans_pcie = 1427 IWL_TRANS_GET_PCIE_TRANS(trans); 1428 1429 lockdep_assert_held(&trans_pcie->mutex); 1430 1431 IWL_WARN(trans, "reporting RF_KILL (radio %s)\n", 1432 state ? "disabled" : "enabled"); 1433 if (iwl_op_mode_hw_rf_kill(trans->op_mode, state) && 1434 !WARN_ON(trans->mac_cfg->gen2)) 1435 _iwl_trans_pcie_stop_device(trans, from_irq); 1436} 1437 1438static void iwl_pcie_d3_complete_suspend(struct iwl_trans *trans, 1439 bool reset) 1440{ 1441 iwl_disable_interrupts(trans); 1442 1443 iwl_pcie_disable_ict(trans); 1444 1445 iwl_pcie_synchronize_irqs(trans); 1446 1447 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 1448 iwl_clear_bit(trans, CSR_GP_CNTRL, 1449 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 1450 iwl_clear_bit(trans, CSR_GP_CNTRL, 1451 CSR_GP_CNTRL_REG_FLAG_MAC_INIT); 1452 } else { 1453 iwl_clear_bit(trans, CSR_GP_CNTRL, 1454 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1455 iwl_clear_bit(trans, CSR_GP_CNTRL, 1456 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 1457 } 1458 1459 if (reset) { 1460 /* 1461 * reset TX queues -- some of their registers reset during S3 1462 * so if we don't reset everything here the D3 image would try 1463 * to execute some invalid memory upon resume 1464 */ 1465 iwl_trans_pcie_tx_reset(trans); 1466 } 1467 1468 iwl_pcie_set_pwr(trans, true); 1469} 1470 1471static int iwl_pcie_d3_handshake(struct iwl_trans *trans, bool suspend) 1472{ 1473 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1474 int ret; 1475 1476 if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 1477 return 0; 1478 1479 trans_pcie->sx_state = IWL_SX_WAITING; 1480 1481 if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_AX210) 1482 iwl_write_umac_prph(trans, UREG_DOORBELL_TO_ISR6, 1483 suspend ? UREG_DOORBELL_TO_ISR6_SUSPEND : 1484 UREG_DOORBELL_TO_ISR6_RESUME); 1485 else 1486 iwl_write32(trans, CSR_IPC_SLEEP_CONTROL, 1487 suspend ? CSR_IPC_SLEEP_CONTROL_SUSPEND : 1488 CSR_IPC_SLEEP_CONTROL_RESUME); 1489 1490 ret = wait_event_timeout(trans_pcie->sx_waitq, 1491 trans_pcie->sx_state != IWL_SX_WAITING, 1492 2 * HZ); 1493 if (!ret) { 1494 IWL_ERR(trans, "Timeout %s D3\n", 1495 suspend ? "entering" : "exiting"); 1496 ret = -ETIMEDOUT; 1497 } else { 1498 ret = 0; 1499 } 1500 1501 if (trans_pcie->sx_state == IWL_SX_ERROR) { 1502 IWL_ERR(trans, "FW error while %s D3\n", 1503 suspend ? "entering" : "exiting"); 1504 ret = -EIO; 1505 } 1506 1507 /* Invalidate it toward next suspend or resume */ 1508 trans_pcie->sx_state = IWL_SX_INVALID; 1509 1510 return ret; 1511} 1512 1513int iwl_trans_pcie_d3_suspend(struct iwl_trans *trans, bool reset) 1514{ 1515 int ret; 1516 1517 if (!reset) 1518 /* Enable persistence mode to avoid reset */ 1519 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 1520 CSR_HW_IF_CONFIG_REG_PERSISTENCE); 1521 1522 ret = iwl_pcie_d3_handshake(trans, true); 1523 if (ret) 1524 return ret; 1525 1526 iwl_pcie_d3_complete_suspend(trans, reset); 1527 1528 return 0; 1529} 1530 1531int iwl_trans_pcie_d3_resume(struct iwl_trans *trans, 1532 bool reset) 1533{ 1534 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1535 u32 val; 1536 int ret; 1537 1538 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 1539 iwl_set_bit(trans, CSR_GP_CNTRL, 1540 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 1541 else 1542 iwl_set_bit(trans, CSR_GP_CNTRL, 1543 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1544 1545 ret = iwl_trans_activate_nic(trans); 1546 if (ret) { 1547 IWL_ERR(trans, "Failed to init nic upon resume. err = %d\n", 1548 ret); 1549 return ret; 1550 } 1551 1552 /* 1553 * Reconfigure IVAR table in case of MSIX or reset ict table in 1554 * MSI mode since HW reset erased it. 1555 * Also enables interrupts - none will happen as 1556 * the device doesn't know we're waking it up, only when 1557 * the opmode actually tells it after this call. 1558 */ 1559 iwl_pcie_conf_msix_hw(trans_pcie); 1560 if (!trans_pcie->msix_enabled) 1561 iwl_pcie_reset_ict(trans); 1562 iwl_enable_interrupts(trans); 1563 1564 iwl_pcie_set_pwr(trans, false); 1565 1566 if (!reset) { 1567 iwl_clear_bit(trans, CSR_GP_CNTRL, 1568 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 1569 } else { 1570 iwl_trans_pcie_tx_reset(trans); 1571 1572 ret = iwl_pcie_rx_init(trans); 1573 if (ret) { 1574 IWL_ERR(trans, 1575 "Failed to resume the device (RX reset)\n"); 1576 return ret; 1577 } 1578 } 1579 1580 IWL_DEBUG_POWER(trans, "WFPM value upon resume = 0x%08X\n", 1581 iwl_read_umac_prph(trans, WFPM_GP2)); 1582 1583 val = iwl_read32(trans, CSR_RESET); 1584 if (val & CSR_RESET_REG_FLAG_NEVO_RESET) { 1585 IWL_INFO(trans, "Device was reset during suspend\n"); 1586 trans->state = IWL_TRANS_NO_FW; 1587 return -ENOENT; 1588 } 1589 1590 return iwl_pcie_d3_handshake(trans, false); 1591} 1592 1593static void 1594iwl_pcie_set_interrupt_capa(struct pci_dev *pdev, 1595 struct iwl_trans *trans, 1596 const struct iwl_mac_cfg *mac_cfg, 1597 struct iwl_trans_info *info) 1598{ 1599 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1600 int max_irqs, num_irqs, i, ret; 1601 u16 pci_cmd; 1602 u32 max_rx_queues = IWL_MAX_RX_HW_QUEUES; 1603 1604 if (!mac_cfg->mq_rx_supported) 1605 goto enable_msi; 1606 1607 if (mac_cfg->device_family <= IWL_DEVICE_FAMILY_9000) 1608 max_rx_queues = IWL_9000_MAX_RX_HW_QUEUES; 1609 1610 max_irqs = min_t(u32, num_online_cpus() + 2, max_rx_queues); 1611 for (i = 0; i < max_irqs; i++) 1612 trans_pcie->msix_entries[i].entry = i; 1613 1614 num_irqs = pci_enable_msix_range(pdev, trans_pcie->msix_entries, 1615 MSIX_MIN_INTERRUPT_VECTORS, 1616 max_irqs); 1617 if (num_irqs < 0) { 1618 IWL_DEBUG_INFO(trans, 1619 "Failed to enable msi-x mode (ret %d). Moving to msi mode.\n", 1620 num_irqs); 1621 goto enable_msi; 1622 } 1623 trans_pcie->def_irq = (num_irqs == max_irqs) ? num_irqs - 1 : 0; 1624 1625 IWL_DEBUG_INFO(trans, 1626 "MSI-X enabled. %d interrupt vectors were allocated\n", 1627 num_irqs); 1628 1629 /* 1630 * In case the OS provides fewer interrupts than requested, different 1631 * causes will share the same interrupt vector as follows: 1632 * One interrupt less: non rx causes shared with FBQ. 1633 * Two interrupts less: non rx causes shared with FBQ and RSS. 1634 * More than two interrupts: we will use fewer RSS queues. 1635 */ 1636 if (num_irqs <= max_irqs - 2) { 1637 info->num_rxqs = num_irqs + 1; 1638 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX | 1639 IWL_SHARED_IRQ_FIRST_RSS; 1640 } else if (num_irqs == max_irqs - 1) { 1641 info->num_rxqs = num_irqs; 1642 trans_pcie->shared_vec_mask = IWL_SHARED_IRQ_NON_RX; 1643 } else { 1644 info->num_rxqs = num_irqs - 1; 1645 } 1646 1647 IWL_DEBUG_INFO(trans, 1648 "MSI-X enabled with rx queues %d, vec mask 0x%x\n", 1649 info->num_rxqs, trans_pcie->shared_vec_mask); 1650 1651 WARN_ON(info->num_rxqs > IWL_MAX_RX_HW_QUEUES); 1652 1653 trans_pcie->alloc_vecs = num_irqs; 1654 trans_pcie->msix_enabled = true; 1655 return; 1656 1657enable_msi: 1658 info->num_rxqs = 1; 1659 ret = pci_enable_msi(pdev); 1660 if (ret) { 1661 dev_err(&pdev->dev, "pci_enable_msi failed - %d\n", ret); 1662 /* enable rfkill interrupt: hw bug w/a */ 1663 pci_read_config_word(pdev, PCI_COMMAND, &pci_cmd); 1664 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 1665 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 1666 pci_write_config_word(pdev, PCI_COMMAND, pci_cmd); 1667 } 1668 } 1669} 1670 1671static void iwl_pcie_irq_set_affinity(struct iwl_trans *trans, 1672 struct iwl_trans_info *info) 1673{ 1674#if defined(CONFIG_SMP) 1675 int iter_rx_q, i, ret, cpu, offset; 1676 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1677 1678 i = trans_pcie->shared_vec_mask & IWL_SHARED_IRQ_FIRST_RSS ? 0 : 1; 1679 iter_rx_q = info->num_rxqs - 1 + i; 1680 offset = 1 + i; 1681 for (; i < iter_rx_q ; i++) { 1682 /* 1683 * Get the cpu prior to the place to search 1684 * (i.e. return will be > i - 1). 1685 */ 1686 cpu = cpumask_next(i - offset, cpu_online_mask); 1687 cpumask_set_cpu(cpu, &trans_pcie->affinity_mask[i]); 1688 ret = irq_set_affinity_hint(trans_pcie->msix_entries[i].vector, 1689 &trans_pcie->affinity_mask[i]); 1690 if (ret) 1691 IWL_ERR(trans_pcie->trans, 1692 "Failed to set affinity mask for IRQ %d\n", 1693 trans_pcie->msix_entries[i].vector); 1694 } 1695#endif 1696} 1697 1698static int iwl_pcie_init_msix_handler(struct pci_dev *pdev, 1699 struct iwl_trans_pcie *trans_pcie, 1700 struct iwl_trans_info *info) 1701{ 1702 int i; 1703 1704 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1705 int ret; 1706 struct msix_entry *msix_entry; 1707 const char *qname = queue_name(&pdev->dev, trans_pcie, i); 1708 1709 if (!qname) 1710 return -ENOMEM; 1711 1712 msix_entry = &trans_pcie->msix_entries[i]; 1713 ret = devm_request_threaded_irq(&pdev->dev, 1714 msix_entry->vector, 1715 iwl_pcie_msix_isr, 1716 (i == trans_pcie->def_irq) ? 1717 iwl_pcie_irq_msix_handler : 1718 iwl_pcie_irq_rx_msix_handler, 1719 IRQF_SHARED, 1720 qname, 1721 msix_entry); 1722 if (ret) { 1723 IWL_ERR(trans_pcie->trans, 1724 "Error allocating IRQ %d\n", i); 1725 1726 return ret; 1727 } 1728 } 1729 iwl_pcie_irq_set_affinity(trans_pcie->trans, info); 1730 1731 return 0; 1732} 1733 1734static int iwl_trans_pcie_clear_persistence_bit(struct iwl_trans *trans) 1735{ 1736 u32 hpm, wprot; 1737 1738 switch (trans->mac_cfg->device_family) { 1739 case IWL_DEVICE_FAMILY_9000: 1740 wprot = PREG_PRPH_WPROT_9000; 1741 break; 1742 case IWL_DEVICE_FAMILY_22000: 1743 wprot = PREG_PRPH_WPROT_22000; 1744 break; 1745 default: 1746 return 0; 1747 } 1748 1749 hpm = iwl_read_umac_prph_no_grab(trans, HPM_DEBUG); 1750 if (!iwl_trans_is_hw_error_value(hpm) && (hpm & PERSISTENCE_BIT)) { 1751 u32 wprot_val = iwl_read_umac_prph_no_grab(trans, wprot); 1752 1753 if (wprot_val & PREG_WFPM_ACCESS) { 1754 IWL_ERR(trans, 1755 "Error, can not clear persistence bit\n"); 1756 return -EPERM; 1757 } 1758 iwl_write_umac_prph_no_grab(trans, HPM_DEBUG, 1759 hpm & ~PERSISTENCE_BIT); 1760 } 1761 1762 return 0; 1763} 1764 1765static int iwl_pcie_gen2_force_power_gating(struct iwl_trans *trans) 1766{ 1767 int ret; 1768 1769 ret = iwl_trans_activate_nic(trans); 1770 if (ret < 0) 1771 return ret; 1772 1773 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 1774 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 1775 udelay(20); 1776 iwl_set_bits_prph(trans, HPM_HIPM_GEN_CFG, 1777 HPM_HIPM_GEN_CFG_CR_PG_EN | 1778 HPM_HIPM_GEN_CFG_CR_SLP_EN); 1779 udelay(20); 1780 iwl_clear_bits_prph(trans, HPM_HIPM_GEN_CFG, 1781 HPM_HIPM_GEN_CFG_CR_FORCE_ACTIVE); 1782 1783 return iwl_trans_pcie_sw_reset(trans, true); 1784} 1785 1786int _iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1787{ 1788 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1789 int err; 1790 1791 lockdep_assert_held(&trans_pcie->mutex); 1792 1793 err = iwl_pcie_prepare_card_hw(trans); 1794 if (err) { 1795 IWL_ERR(trans, "Error while preparing HW: %d\n", err); 1796 return err; 1797 } 1798 1799 err = iwl_trans_pcie_clear_persistence_bit(trans); 1800 if (err) 1801 return err; 1802 1803 err = iwl_trans_pcie_sw_reset(trans, true); 1804 if (err) 1805 return err; 1806 1807 if (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_22000 && 1808 trans->mac_cfg->integrated) { 1809 err = iwl_pcie_gen2_force_power_gating(trans); 1810 if (err) 1811 return err; 1812 } 1813 1814 err = iwl_pcie_apm_init(trans); 1815 if (err) 1816 return err; 1817 1818 iwl_pcie_init_msix(trans_pcie); 1819 1820 /* From now on, the op_mode will be kept updated about RF kill state */ 1821 iwl_enable_rfkill_int(trans); 1822 1823 trans_pcie->opmode_down = false; 1824 1825 /* Set is_down to false here so that...*/ 1826 trans_pcie->is_down = false; 1827 1828 /* ...rfkill can call stop_device and set it false if needed */ 1829 iwl_pcie_check_hw_rf_kill(trans); 1830 1831 return 0; 1832} 1833 1834int iwl_trans_pcie_start_hw(struct iwl_trans *trans) 1835{ 1836 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1837 int ret; 1838 1839 mutex_lock(&trans_pcie->mutex); 1840 ret = _iwl_trans_pcie_start_hw(trans); 1841 mutex_unlock(&trans_pcie->mutex); 1842 1843 return ret; 1844} 1845 1846void iwl_trans_pcie_op_mode_leave(struct iwl_trans *trans) 1847{ 1848 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1849 1850 mutex_lock(&trans_pcie->mutex); 1851 1852 /* disable interrupts - don't enable HW RF kill interrupt */ 1853 iwl_disable_interrupts(trans); 1854 1855 iwl_pcie_apm_stop(trans, true); 1856 1857 iwl_disable_interrupts(trans); 1858 1859 iwl_pcie_disable_ict(trans); 1860 1861 mutex_unlock(&trans_pcie->mutex); 1862 1863 iwl_pcie_synchronize_irqs(trans); 1864} 1865 1866void iwl_trans_pcie_write8(struct iwl_trans *trans, u32 ofs, u8 val) 1867{ 1868 writeb(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1869} 1870 1871void iwl_trans_pcie_write32(struct iwl_trans *trans, u32 ofs, u32 val) 1872{ 1873 writel(val, IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1874} 1875 1876u32 iwl_trans_pcie_read32(struct iwl_trans *trans, u32 ofs) 1877{ 1878 return readl(IWL_TRANS_GET_PCIE_TRANS(trans)->hw_base + ofs); 1879} 1880 1881static u32 iwl_trans_pcie_prph_msk(struct iwl_trans *trans) 1882{ 1883 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1884 return 0x00FFFFFF; 1885 else 1886 return 0x000FFFFF; 1887} 1888 1889u32 iwl_trans_pcie_read_prph(struct iwl_trans *trans, u32 reg) 1890{ 1891 u32 mask = iwl_trans_pcie_prph_msk(trans); 1892 1893 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_RADDR, 1894 ((reg & mask) | (3 << 24))); 1895 return iwl_trans_pcie_read32(trans, HBUS_TARG_PRPH_RDAT); 1896} 1897 1898void iwl_trans_pcie_write_prph(struct iwl_trans *trans, u32 addr, u32 val) 1899{ 1900 u32 mask = iwl_trans_pcie_prph_msk(trans); 1901 1902 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WADDR, 1903 ((addr & mask) | (3 << 24))); 1904 iwl_trans_pcie_write32(trans, HBUS_TARG_PRPH_WDAT, val); 1905} 1906 1907void iwl_pcie_gen1_2_op_mode_enter(struct iwl_trans *trans) 1908{ 1909 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1910 1911 /* free all first - we might be reconfigured for a different size */ 1912 iwl_pcie_free_rbs_pool(trans); 1913 1914 trans_pcie->rx_page_order = 1915 iwl_trans_get_rb_size_order(trans->conf.rx_buf_size); 1916 trans_pcie->rx_buf_bytes = 1917 iwl_trans_get_rb_size(trans->conf.rx_buf_size); 1918} 1919 1920void iwl_trans_pcie_free_pnvm_dram_regions(struct iwl_dram_regions *dram_regions, 1921 struct device *dev) 1922{ 1923 u8 i; 1924 struct iwl_dram_data *desc_dram = &dram_regions->prph_scratch_mem_desc; 1925 1926 /* free DRAM payloads */ 1927 for (i = 0; i < dram_regions->n_regions; i++) { 1928 dma_free_coherent(dev, dram_regions->drams[i].size, 1929 dram_regions->drams[i].block, 1930 dram_regions->drams[i].physical); 1931 } 1932 dram_regions->n_regions = 0; 1933 1934 /* free DRAM addresses array */ 1935 if (desc_dram->block) { 1936 dma_free_coherent(dev, desc_dram->size, 1937 desc_dram->block, 1938 desc_dram->physical); 1939 } 1940 memset(desc_dram, 0, sizeof(*desc_dram)); 1941} 1942 1943static void iwl_pcie_free_invalid_tx_cmd(struct iwl_trans *trans) 1944{ 1945 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1946 1947 iwl_pcie_free_dma_ptr(trans, &trans_pcie->invalid_tx_cmd); 1948} 1949 1950static int iwl_pcie_alloc_invalid_tx_cmd(struct iwl_trans *trans) 1951{ 1952 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1953 struct iwl_cmd_header_wide bad_cmd = { 1954 .cmd = INVALID_WR_PTR_CMD, 1955 .group_id = DEBUG_GROUP, 1956 .sequence = cpu_to_le16(0xffff), 1957 .length = cpu_to_le16(0), 1958 .version = 0, 1959 }; 1960 int ret; 1961 1962 ret = iwl_pcie_alloc_dma_ptr(trans, &trans_pcie->invalid_tx_cmd, 1963 sizeof(bad_cmd)); 1964 if (ret) 1965 return ret; 1966 memcpy(trans_pcie->invalid_tx_cmd.addr, &bad_cmd, sizeof(bad_cmd)); 1967 return 0; 1968} 1969 1970void iwl_trans_pcie_free(struct iwl_trans *trans) 1971{ 1972 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 1973 int i; 1974 1975 iwl_pcie_synchronize_irqs(trans); 1976 1977 if (trans->mac_cfg->gen2) 1978 iwl_txq_gen2_tx_free(trans); 1979 else 1980 iwl_pcie_tx_free(trans); 1981 iwl_pcie_rx_free(trans); 1982 1983 if (trans_pcie->rba.alloc_wq) { 1984 destroy_workqueue(trans_pcie->rba.alloc_wq); 1985 trans_pcie->rba.alloc_wq = NULL; 1986 } 1987 1988 if (trans_pcie->msix_enabled) { 1989 for (i = 0; i < trans_pcie->alloc_vecs; i++) { 1990 irq_set_affinity_hint( 1991 trans_pcie->msix_entries[i].vector, 1992 NULL); 1993 } 1994 1995 trans_pcie->msix_enabled = false; 1996 } else { 1997 iwl_pcie_free_ict(trans); 1998 } 1999 2000 free_netdev(trans_pcie->napi_dev); 2001 2002 iwl_pcie_free_invalid_tx_cmd(trans); 2003 2004 iwl_pcie_free_fw_monitor(trans); 2005 2006 iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->pnvm_data, 2007 trans->dev); 2008 iwl_trans_pcie_free_pnvm_dram_regions(&trans_pcie->reduced_tables_data, 2009 trans->dev); 2010 2011 mutex_destroy(&trans_pcie->mutex); 2012 2013 if (trans_pcie->txqs.tso_hdr_page) { 2014 for_each_possible_cpu(i) { 2015 struct iwl_tso_hdr_page *p = 2016 per_cpu_ptr(trans_pcie->txqs.tso_hdr_page, i); 2017 2018 if (p && p->page) 2019 __free_page(p->page); 2020 } 2021 2022 free_percpu(trans_pcie->txqs.tso_hdr_page); 2023 } 2024 2025 kmem_cache_destroy(trans_pcie->dev_cmd_pool); 2026 iwl_trans_free(trans); 2027} 2028 2029static union acpi_object * 2030iwl_trans_pcie_call_prod_reset_dsm(struct pci_dev *pdev, u16 cmd, u16 value) 2031{ 2032#ifdef CONFIG_ACPI 2033 struct iwl_dsm_internal_product_reset_cmd pldr_arg = { 2034 .cmd = cmd, 2035 .value = value, 2036 }; 2037 union acpi_object arg = { 2038 .buffer.type = ACPI_TYPE_BUFFER, 2039 .buffer.length = sizeof(pldr_arg), 2040 .buffer.pointer = (void *)&pldr_arg, 2041 }; 2042 static const guid_t dsm_guid = GUID_INIT(0x7266172C, 0x220B, 0x4B29, 2043 0x81, 0x4F, 0x75, 0xE4, 2044 0xDD, 0x26, 0xB5, 0xFD); 2045 2046 if (!acpi_check_dsm(ACPI_HANDLE(&pdev->dev), &dsm_guid, ACPI_DSM_REV, 2047 DSM_INTERNAL_FUNC_PRODUCT_RESET)) 2048 return ERR_PTR(-ENODEV); 2049 2050 return iwl_acpi_get_dsm_object(&pdev->dev, ACPI_DSM_REV, 2051 DSM_INTERNAL_FUNC_PRODUCT_RESET, 2052 &arg, &dsm_guid); 2053#else 2054 return ERR_PTR(-EOPNOTSUPP); 2055#endif 2056} 2057 2058void iwl_trans_pcie_check_product_reset_mode(struct pci_dev *pdev) 2059{ 2060 union acpi_object *res; 2061 2062 res = iwl_trans_pcie_call_prod_reset_dsm(pdev, 2063 DSM_INTERNAL_PLDR_CMD_GET_MODE, 2064 0); 2065 if (IS_ERR(res)) 2066 return; 2067 2068 if (res->type != ACPI_TYPE_INTEGER) 2069 IWL_ERR_DEV(&pdev->dev, 2070 "unexpected return type from product reset DSM\n"); 2071 else 2072 IWL_DEBUG_DEV_POWER(&pdev->dev, 2073 "product reset mode is 0x%llx\n", 2074 res->integer.value); 2075 2076 ACPI_FREE(res); 2077} 2078 2079static void iwl_trans_pcie_set_product_reset(struct pci_dev *pdev, bool enable, 2080 bool integrated) 2081{ 2082 union acpi_object *res; 2083 u16 mode = enable ? DSM_INTERNAL_PLDR_MODE_EN_PROD_RESET : 0; 2084 2085 if (!integrated) 2086 mode |= DSM_INTERNAL_PLDR_MODE_EN_WIFI_FLR | 2087 DSM_INTERNAL_PLDR_MODE_EN_BT_OFF_ON; 2088 2089 res = iwl_trans_pcie_call_prod_reset_dsm(pdev, 2090 DSM_INTERNAL_PLDR_CMD_SET_MODE, 2091 mode); 2092 if (IS_ERR(res)) { 2093 if (enable) 2094 IWL_ERR_DEV(&pdev->dev, 2095 "ACPI _DSM not available (%d), cannot do product reset\n", 2096 (int)PTR_ERR(res)); 2097 return; 2098 } 2099 2100 ACPI_FREE(res); 2101 IWL_DEBUG_DEV_POWER(&pdev->dev, "%sabled product reset via DSM\n", 2102 enable ? "En" : "Dis"); 2103 iwl_trans_pcie_check_product_reset_mode(pdev); 2104} 2105 2106void iwl_trans_pcie_check_product_reset_status(struct pci_dev *pdev) 2107{ 2108 union acpi_object *res; 2109 2110 res = iwl_trans_pcie_call_prod_reset_dsm(pdev, 2111 DSM_INTERNAL_PLDR_CMD_GET_STATUS, 2112 0); 2113 if (IS_ERR(res)) 2114 return; 2115 2116 if (res->type != ACPI_TYPE_INTEGER) 2117 IWL_ERR_DEV(&pdev->dev, 2118 "unexpected return type from product reset DSM\n"); 2119 else 2120 IWL_DEBUG_DEV_POWER(&pdev->dev, 2121 "product reset status is 0x%llx\n", 2122 res->integer.value); 2123 2124 ACPI_FREE(res); 2125} 2126 2127static void iwl_trans_pcie_call_reset(struct pci_dev *pdev) 2128{ 2129#ifdef CONFIG_ACPI 2130 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 2131 union acpi_object *p, *ref; 2132 acpi_status status; 2133 int ret = -EINVAL; 2134 2135 status = acpi_evaluate_object(ACPI_HANDLE(&pdev->dev), 2136 "_PRR", NULL, &buffer); 2137 if (ACPI_FAILURE(status)) { 2138 IWL_DEBUG_DEV_POWER(&pdev->dev, "No _PRR method found\n"); 2139 goto out; 2140 } 2141 p = buffer.pointer; 2142 2143 if (p->type != ACPI_TYPE_PACKAGE || p->package.count != 1) { 2144 pci_err(pdev, "Bad _PRR return type\n"); 2145 goto out; 2146 } 2147 2148 ref = &p->package.elements[0]; 2149 if (ref->type != ACPI_TYPE_LOCAL_REFERENCE) { 2150 pci_err(pdev, "_PRR wasn't a reference\n"); 2151 goto out; 2152 } 2153 2154 status = acpi_evaluate_object(ref->reference.handle, 2155 "_RST", NULL, NULL); 2156 if (ACPI_FAILURE(status)) { 2157 pci_err(pdev, 2158 "Failed to call _RST on object returned by _PRR (%d)\n", 2159 status); 2160 goto out; 2161 } 2162 ret = 0; 2163out: 2164 kfree(buffer.pointer); 2165 if (!ret) { 2166 IWL_DEBUG_DEV_POWER(&pdev->dev, "called _RST on _PRR object\n"); 2167 return; 2168 } 2169 IWL_DEBUG_DEV_POWER(&pdev->dev, 2170 "No BIOS support, using pci_reset_function()\n"); 2171#endif 2172 pci_reset_function(pdev); 2173} 2174 2175struct iwl_trans_pcie_removal { 2176 struct pci_dev *pdev; 2177 struct work_struct work; 2178 enum iwl_reset_mode mode; 2179 bool integrated; 2180}; 2181 2182static void iwl_trans_pcie_removal_wk(struct work_struct *wk) 2183{ 2184 struct iwl_trans_pcie_removal *removal = 2185 container_of(wk, struct iwl_trans_pcie_removal, work); 2186 struct pci_dev *pdev = removal->pdev; 2187 static char *prop[] = {"EVENT=INACCESSIBLE", NULL}; 2188 struct pci_bus *bus; 2189 2190 pci_lock_rescan_remove(); 2191 2192 bus = pdev->bus; 2193 /* in this case, something else already removed the device */ 2194 if (!bus) 2195 goto out; 2196 2197 kobject_uevent_env(&pdev->dev.kobj, KOBJ_CHANGE, prop); 2198 2199 if (removal->mode == IWL_RESET_MODE_PROD_RESET) { 2200 struct pci_dev *bt = NULL; 2201 2202 if (!removal->integrated) { 2203 /* discrete devices have WiFi/BT at function 0/1 */ 2204 int slot = PCI_SLOT(pdev->devfn); 2205 int func = PCI_FUNC(pdev->devfn); 2206 2207 if (func == 0) 2208 bt = pci_get_slot(bus, PCI_DEVFN(slot, 1)); 2209 else 2210 pci_info(pdev, "Unexpected function %d\n", 2211 func); 2212 } else { 2213 /* on integrated we have to look up by ID (same bus) */ 2214 static const struct pci_device_id bt_device_ids[] = { 2215#define BT_DEV(_id) { PCI_DEVICE(PCI_VENDOR_ID_INTEL, _id) } 2216 BT_DEV(0xA876), /* LNL */ 2217 BT_DEV(0xE476), /* PTL-P */ 2218 BT_DEV(0xE376), /* PTL-H */ 2219 BT_DEV(0xD346), /* NVL-H */ 2220 BT_DEV(0x6E74), /* NVL-S */ 2221 BT_DEV(0x4D76), /* WCL */ 2222 BT_DEV(0xD246), /* RZL-H */ 2223 BT_DEV(0x6C46), /* RZL-M */ 2224 {} 2225 }; 2226 struct pci_dev *tmp = NULL; 2227 2228 for_each_pci_dev(tmp) { 2229 if (tmp->bus != bus) 2230 continue; 2231 2232 if (pci_match_id(bt_device_ids, tmp)) { 2233 bt = tmp; 2234 break; 2235 } 2236 } 2237 } 2238 2239 if (bt) { 2240 pci_info(bt, "Removal by WiFi due to product reset\n"); 2241 pci_stop_and_remove_bus_device(bt); 2242 pci_dev_put(bt); 2243 } 2244 } 2245 2246 iwl_trans_pcie_set_product_reset(pdev, 2247 removal->mode == 2248 IWL_RESET_MODE_PROD_RESET, 2249 removal->integrated); 2250 if (removal->mode >= IWL_RESET_MODE_FUNC_RESET) 2251 iwl_trans_pcie_call_reset(pdev); 2252 2253 pci_stop_and_remove_bus_device(pdev); 2254 pci_dev_put(pdev); 2255 2256 if (removal->mode >= IWL_RESET_MODE_RESCAN) { 2257 if (bus->parent) 2258 bus = bus->parent; 2259 pci_rescan_bus(bus); 2260 } 2261 2262out: 2263 pci_unlock_rescan_remove(); 2264 2265 kfree(removal); 2266 module_put(THIS_MODULE); 2267} 2268 2269void iwl_trans_pcie_reset(struct iwl_trans *trans, enum iwl_reset_mode mode) 2270{ 2271 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2272 struct iwl_trans_pcie_removal *removal; 2273 char _msg = 0, *msg = &_msg; 2274 2275 if (WARN_ON(mode < IWL_RESET_MODE_REMOVE_ONLY || 2276 mode == IWL_RESET_MODE_BACKOFF)) 2277 return; 2278 2279 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2280 return; 2281 2282 if (trans_pcie->me_present && mode == IWL_RESET_MODE_PROD_RESET) { 2283 mode = IWL_RESET_MODE_FUNC_RESET; 2284 if (trans_pcie->me_present < 0) 2285 msg = " instead of product reset as ME may be present"; 2286 else 2287 msg = " instead of product reset as ME is present"; 2288 } 2289 2290 IWL_INFO(trans, "scheduling reset (mode=%d%s)\n", mode, msg); 2291 2292 iwl_pcie_dump_csr(trans); 2293 2294 /* 2295 * get a module reference to avoid doing this 2296 * while unloading anyway and to avoid 2297 * scheduling a work with code that's being 2298 * removed. 2299 */ 2300 if (!try_module_get(THIS_MODULE)) { 2301 IWL_ERR(trans, 2302 "Module is being unloaded - abort\n"); 2303 return; 2304 } 2305 2306 removal = kzalloc(sizeof(*removal), GFP_ATOMIC); 2307 if (!removal) { 2308 module_put(THIS_MODULE); 2309 return; 2310 } 2311 /* 2312 * we don't need to clear this flag, because 2313 * the trans will be freed and reallocated. 2314 */ 2315 set_bit(STATUS_TRANS_DEAD, &trans->status); 2316 2317 removal->pdev = to_pci_dev(trans->dev); 2318 removal->mode = mode; 2319 removal->integrated = trans->mac_cfg->integrated; 2320 INIT_WORK(&removal->work, iwl_trans_pcie_removal_wk); 2321 pci_dev_get(removal->pdev); 2322 schedule_work(&removal->work); 2323} 2324EXPORT_SYMBOL(iwl_trans_pcie_reset); 2325 2326/* 2327 * This version doesn't disable BHs but rather assumes they're 2328 * already disabled. 2329 */ 2330bool __iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans, bool silent) 2331{ 2332 int ret; 2333 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2334 u32 write = CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ; 2335 u32 mask = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY | 2336 CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP; 2337 u32 poll = CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN; 2338 2339 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2340 return false; 2341 2342 spin_lock(&trans_pcie->reg_lock); 2343 2344 if (trans_pcie->cmd_hold_nic_awake) 2345 goto out; 2346 2347 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 2348 write = CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ; 2349 mask = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 2350 poll = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 2351 } 2352 2353 /* this bit wakes up the NIC */ 2354 iwl_trans_set_bit(trans, CSR_GP_CNTRL, write); 2355 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 2356 udelay(2); 2357 2358 /* 2359 * These bits say the device is running, and should keep running for 2360 * at least a short while (at least as long as MAC_ACCESS_REQ stays 1), 2361 * but they do not indicate that embedded SRAM is restored yet; 2362 * HW with volatile SRAM must save/restore contents to/from 2363 * host DRAM when sleeping/waking for power-saving. 2364 * Each direction takes approximately 1/4 millisecond; with this 2365 * overhead, it's a good idea to grab and hold MAC_ACCESS_REQUEST if a 2366 * series of register accesses are expected (e.g. reading Event Log), 2367 * to keep device from sleeping. 2368 * 2369 * CSR_UCODE_DRV_GP1 register bit MAC_SLEEP == 0 indicates that 2370 * SRAM is okay/restored. We don't check that here because this call 2371 * is just for hardware register access; but GP1 MAC_SLEEP 2372 * check is a good idea before accessing the SRAM of HW with 2373 * volatile SRAM (e.g. reading Event Log). 2374 * 2375 * 5000 series and later (including 1000 series) have non-volatile SRAM, 2376 * and do not save/restore SRAM when power cycling. 2377 */ 2378 ret = iwl_poll_bits_mask(trans, CSR_GP_CNTRL, poll, mask, 15000); 2379 if (unlikely(ret)) { 2380 u32 cntrl = iwl_read32(trans, CSR_GP_CNTRL); 2381 2382 if (silent) { 2383 spin_unlock(&trans_pcie->reg_lock); 2384 return false; 2385 } 2386 2387 WARN_ONCE(1, 2388 "Timeout waiting for hardware access (CSR_GP_CNTRL 0x%08x)\n", 2389 cntrl); 2390 2391 iwl_trans_pcie_dump_regs(trans, trans_pcie->pci_dev); 2392 2393 if (iwlwifi_mod_params.remove_when_gone && cntrl == ~0U) 2394 iwl_trans_pcie_reset(trans, 2395 IWL_RESET_MODE_REMOVE_ONLY); 2396 else 2397 iwl_write32(trans, CSR_RESET, 2398 CSR_RESET_REG_FLAG_FORCE_NMI); 2399 2400 spin_unlock(&trans_pcie->reg_lock); 2401 return false; 2402 } 2403 2404out: 2405 /* 2406 * Fool sparse by faking we release the lock - sparse will 2407 * track nic_access anyway. 2408 */ 2409 __release(&trans_pcie->reg_lock); 2410 return true; 2411} 2412 2413bool iwl_trans_pcie_grab_nic_access(struct iwl_trans *trans) 2414{ 2415 bool ret; 2416 2417 local_bh_disable(); 2418 ret = __iwl_trans_pcie_grab_nic_access(trans, false); 2419 if (ret) { 2420 /* keep BHs disabled until iwl_trans_pcie_release_nic_access */ 2421 return ret; 2422 } 2423 local_bh_enable(); 2424 return false; 2425} 2426 2427void __releases(nic_access_nobh) 2428iwl_trans_pcie_release_nic_access(struct iwl_trans *trans) 2429{ 2430 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2431 2432 lockdep_assert_held(&trans_pcie->reg_lock); 2433 2434 /* 2435 * Fool sparse by faking we acquiring the lock - sparse will 2436 * track nic_access anyway. 2437 */ 2438 __acquire(&trans_pcie->reg_lock); 2439 2440 if (trans_pcie->cmd_hold_nic_awake) 2441 goto out; 2442 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 2443 iwl_trans_clear_bit(trans, CSR_GP_CNTRL, 2444 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ); 2445 else 2446 iwl_trans_clear_bit(trans, CSR_GP_CNTRL, 2447 CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 2448 /* 2449 * Above we read the CSR_GP_CNTRL register, which will flush 2450 * any previous writes, but we need the write that clears the 2451 * MAC_ACCESS_REQ bit to be performed before any other writes 2452 * scheduled on different CPUs (after we drop reg_lock). 2453 */ 2454out: 2455 __release(nic_access_nobh); 2456 spin_unlock_bh(&trans_pcie->reg_lock); 2457} 2458 2459int iwl_trans_pcie_read_mem(struct iwl_trans *trans, u32 addr, 2460 void *buf, int dwords) 2461{ 2462#define IWL_MAX_HW_ERRS 5 2463 unsigned int num_consec_hw_errors = 0; 2464 int offs = 0; 2465 u32 *vals = buf; 2466 2467 while (offs < dwords) { 2468 /* limit the time we spin here under lock to 1/2s */ 2469 unsigned long end = jiffies + HZ / 2; 2470 bool resched = false; 2471 2472 if (iwl_trans_grab_nic_access(trans)) { 2473 iwl_write32(trans, HBUS_TARG_MEM_RADDR, 2474 addr + 4 * offs); 2475 2476 while (offs < dwords) { 2477 vals[offs] = iwl_read32(trans, 2478 HBUS_TARG_MEM_RDAT); 2479 2480 if (iwl_trans_is_hw_error_value(vals[offs])) 2481 num_consec_hw_errors++; 2482 else 2483 num_consec_hw_errors = 0; 2484 2485 if (num_consec_hw_errors >= IWL_MAX_HW_ERRS) { 2486 iwl_trans_release_nic_access(trans); 2487 return -EIO; 2488 } 2489 2490 offs++; 2491 2492 if (time_after(jiffies, end)) { 2493 resched = true; 2494 break; 2495 } 2496 } 2497 iwl_trans_release_nic_access(trans); 2498 2499 if (resched) 2500 cond_resched(); 2501 } else { 2502 return -EBUSY; 2503 } 2504 } 2505 2506 return 0; 2507} 2508 2509int iwl_trans_pcie_read_config32(struct iwl_trans *trans, u32 ofs, 2510 u32 *val) 2511{ 2512 return pci_read_config_dword(IWL_TRANS_GET_PCIE_TRANS(trans)->pci_dev, 2513 ofs, val); 2514} 2515 2516#define IWL_FLUSH_WAIT_MS 2000 2517 2518int iwl_trans_pcie_rxq_dma_data(struct iwl_trans *trans, int queue, 2519 struct iwl_trans_rxq_dma_data *data) 2520{ 2521 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2522 2523 if (queue >= trans->info.num_rxqs || !trans_pcie->rxq) 2524 return -EINVAL; 2525 2526 data->fr_bd_cb = trans_pcie->rxq[queue].bd_dma; 2527 data->urbd_stts_wrptr = trans_pcie->rxq[queue].rb_stts_dma; 2528 data->ur_bd_cb = trans_pcie->rxq[queue].used_bd_dma; 2529 data->fr_bd_wid = 0; 2530 2531 return 0; 2532} 2533 2534int iwl_trans_pcie_wait_txq_empty(struct iwl_trans *trans, int txq_idx) 2535{ 2536 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2537 struct iwl_txq *txq; 2538 unsigned long now = jiffies; 2539 bool overflow_tx; 2540 u8 wr_ptr; 2541 2542 /* Make sure the NIC is still alive in the bus */ 2543 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 2544 return -ENODEV; 2545 2546 if (!test_bit(txq_idx, trans_pcie->txqs.queue_used)) 2547 return -EINVAL; 2548 2549 IWL_DEBUG_TX_QUEUES(trans, "Emptying queue %d...\n", txq_idx); 2550 txq = trans_pcie->txqs.txq[txq_idx]; 2551 2552 spin_lock_bh(&txq->lock); 2553 overflow_tx = txq->overflow_tx || 2554 !skb_queue_empty(&txq->overflow_q); 2555 spin_unlock_bh(&txq->lock); 2556 2557 wr_ptr = READ_ONCE(txq->write_ptr); 2558 2559 while ((txq->read_ptr != READ_ONCE(txq->write_ptr) || 2560 overflow_tx) && 2561 !time_after(jiffies, 2562 now + msecs_to_jiffies(IWL_FLUSH_WAIT_MS))) { 2563 u8 write_ptr = READ_ONCE(txq->write_ptr); 2564 2565 /* 2566 * If write pointer moved during the wait, warn only 2567 * if the TX came from op mode. In case TX came from 2568 * trans layer (overflow TX) don't warn. 2569 */ 2570 if (WARN_ONCE(wr_ptr != write_ptr && !overflow_tx, 2571 "WR pointer moved while flushing %d -> %d\n", 2572 wr_ptr, write_ptr)) 2573 return -ETIMEDOUT; 2574 wr_ptr = write_ptr; 2575 2576 usleep_range(1000, 2000); 2577 2578 spin_lock_bh(&txq->lock); 2579 overflow_tx = txq->overflow_tx || 2580 !skb_queue_empty(&txq->overflow_q); 2581 spin_unlock_bh(&txq->lock); 2582 } 2583 2584 if (txq->read_ptr != txq->write_ptr) { 2585 IWL_ERR(trans, 2586 "fail to flush all tx fifo queues Q %d\n", txq_idx); 2587 iwl_txq_log_scd_error(trans, txq); 2588 return -ETIMEDOUT; 2589 } 2590 2591 IWL_DEBUG_TX_QUEUES(trans, "Queue %d is now empty.\n", txq_idx); 2592 2593 return 0; 2594} 2595 2596int iwl_trans_pcie_wait_txqs_empty(struct iwl_trans *trans, u32 txq_bm) 2597{ 2598 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2599 int cnt; 2600 int ret = 0; 2601 2602 /* waiting for all the tx frames complete might take a while */ 2603 for (cnt = 0; 2604 cnt < trans->mac_cfg->base->num_of_queues; 2605 cnt++) { 2606 2607 if (cnt == trans->conf.cmd_queue) 2608 continue; 2609 if (!test_bit(cnt, trans_pcie->txqs.queue_used)) 2610 continue; 2611 if (!(BIT(cnt) & txq_bm)) 2612 continue; 2613 2614 ret = iwl_trans_pcie_wait_txq_empty(trans, cnt); 2615 if (ret) 2616 break; 2617 } 2618 2619 return ret; 2620} 2621 2622void iwl_trans_pcie_set_bits_mask(struct iwl_trans *trans, u32 reg, 2623 u32 mask, u32 value) 2624{ 2625 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2626 2627 spin_lock_bh(&trans_pcie->reg_lock); 2628 _iwl_trans_set_bits_mask(trans, reg, mask, value); 2629 spin_unlock_bh(&trans_pcie->reg_lock); 2630} 2631 2632static const char *get_csr_string(int cmd) 2633{ 2634#define IWL_CMD(x) case x: return #x 2635 switch (cmd) { 2636 IWL_CMD(CSR_HW_IF_CONFIG_REG); 2637 IWL_CMD(CSR_INT_COALESCING); 2638 IWL_CMD(CSR_INT); 2639 IWL_CMD(CSR_INT_MASK); 2640 IWL_CMD(CSR_FH_INT_STATUS); 2641 IWL_CMD(CSR_GPIO_IN); 2642 IWL_CMD(CSR_RESET); 2643 IWL_CMD(CSR_GP_CNTRL); 2644 IWL_CMD(CSR_HW_REV); 2645 IWL_CMD(CSR_EEPROM_REG); 2646 IWL_CMD(CSR_EEPROM_GP); 2647 IWL_CMD(CSR_OTP_GP_REG); 2648 IWL_CMD(CSR_GIO_REG); 2649 IWL_CMD(CSR_GP_UCODE_REG); 2650 IWL_CMD(CSR_GP_DRIVER_REG); 2651 IWL_CMD(CSR_UCODE_DRV_GP1); 2652 IWL_CMD(CSR_UCODE_DRV_GP2); 2653 IWL_CMD(CSR_LED_REG); 2654 IWL_CMD(CSR_DRAM_INT_TBL_REG); 2655 IWL_CMD(CSR_GIO_CHICKEN_BITS); 2656 IWL_CMD(CSR_ANA_PLL_CFG); 2657 IWL_CMD(CSR_HW_REV_WA_REG); 2658 IWL_CMD(CSR_MONITOR_STATUS_REG); 2659 IWL_CMD(CSR_DBG_HPET_MEM_REG); 2660 default: 2661 return "UNKNOWN"; 2662 } 2663#undef IWL_CMD 2664} 2665 2666void iwl_pcie_dump_csr(struct iwl_trans *trans) 2667{ 2668 int i; 2669 static const u32 csr_tbl[] = { 2670 CSR_HW_IF_CONFIG_REG, 2671 CSR_INT_COALESCING, 2672 CSR_INT, 2673 CSR_INT_MASK, 2674 CSR_FH_INT_STATUS, 2675 CSR_GPIO_IN, 2676 CSR_RESET, 2677 CSR_GP_CNTRL, 2678 CSR_HW_REV, 2679 CSR_EEPROM_REG, 2680 CSR_EEPROM_GP, 2681 CSR_OTP_GP_REG, 2682 CSR_GIO_REG, 2683 CSR_GP_UCODE_REG, 2684 CSR_GP_DRIVER_REG, 2685 CSR_UCODE_DRV_GP1, 2686 CSR_UCODE_DRV_GP2, 2687 CSR_LED_REG, 2688 CSR_DRAM_INT_TBL_REG, 2689 CSR_GIO_CHICKEN_BITS, 2690 CSR_ANA_PLL_CFG, 2691 CSR_MONITOR_STATUS_REG, 2692 CSR_HW_REV_WA_REG, 2693 CSR_DBG_HPET_MEM_REG 2694 }; 2695 IWL_ERR(trans, "CSR values:\n"); 2696 IWL_ERR(trans, "(2nd byte of CSR_INT_COALESCING is " 2697 "CSR_INT_PERIODIC_REG)\n"); 2698 for (i = 0; i < ARRAY_SIZE(csr_tbl); i++) { 2699 IWL_ERR(trans, " %25s: 0X%08x\n", 2700 get_csr_string(csr_tbl[i]), 2701 iwl_read32(trans, csr_tbl[i])); 2702 } 2703} 2704 2705#ifdef CONFIG_IWLWIFI_DEBUGFS 2706/* create and remove of files */ 2707#define DEBUGFS_ADD_FILE(name, parent, mode) do { \ 2708 debugfs_create_file(#name, mode, parent, trans, \ 2709 &iwl_dbgfs_##name##_ops); \ 2710} while (0) 2711 2712/* file operation */ 2713#define DEBUGFS_READ_FILE_OPS(name) \ 2714static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2715 .read = iwl_dbgfs_##name##_read, \ 2716 .open = simple_open, \ 2717 .llseek = generic_file_llseek, \ 2718}; 2719 2720#define DEBUGFS_WRITE_FILE_OPS(name) \ 2721static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2722 .write = iwl_dbgfs_##name##_write, \ 2723 .open = simple_open, \ 2724 .llseek = generic_file_llseek, \ 2725}; 2726 2727#define DEBUGFS_READ_WRITE_FILE_OPS(name) \ 2728static const struct file_operations iwl_dbgfs_##name##_ops = { \ 2729 .write = iwl_dbgfs_##name##_write, \ 2730 .read = iwl_dbgfs_##name##_read, \ 2731 .open = simple_open, \ 2732 .llseek = generic_file_llseek, \ 2733}; 2734 2735struct iwl_dbgfs_tx_queue_priv { 2736 struct iwl_trans *trans; 2737}; 2738 2739struct iwl_dbgfs_tx_queue_state { 2740 loff_t pos; 2741}; 2742 2743static void *iwl_dbgfs_tx_queue_seq_start(struct seq_file *seq, loff_t *pos) 2744{ 2745 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2746 struct iwl_dbgfs_tx_queue_state *state; 2747 2748 if (*pos >= priv->trans->mac_cfg->base->num_of_queues) 2749 return NULL; 2750 2751 state = kmalloc(sizeof(*state), GFP_KERNEL); 2752 if (!state) 2753 return NULL; 2754 state->pos = *pos; 2755 return state; 2756} 2757 2758static void *iwl_dbgfs_tx_queue_seq_next(struct seq_file *seq, 2759 void *v, loff_t *pos) 2760{ 2761 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2762 struct iwl_dbgfs_tx_queue_state *state = v; 2763 2764 *pos = ++state->pos; 2765 2766 if (*pos >= priv->trans->mac_cfg->base->num_of_queues) 2767 return NULL; 2768 2769 return state; 2770} 2771 2772static void iwl_dbgfs_tx_queue_seq_stop(struct seq_file *seq, void *v) 2773{ 2774 kfree(v); 2775} 2776 2777static int iwl_dbgfs_tx_queue_seq_show(struct seq_file *seq, void *v) 2778{ 2779 struct iwl_dbgfs_tx_queue_priv *priv = seq->private; 2780 struct iwl_dbgfs_tx_queue_state *state = v; 2781 struct iwl_trans *trans = priv->trans; 2782 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2783 struct iwl_txq *txq = trans_pcie->txqs.txq[state->pos]; 2784 2785 seq_printf(seq, "hwq %.3u: used=%d stopped=%d ", 2786 (unsigned int)state->pos, 2787 !!test_bit(state->pos, trans_pcie->txqs.queue_used), 2788 !!test_bit(state->pos, trans_pcie->txqs.queue_stopped)); 2789 if (txq) 2790 seq_printf(seq, 2791 "read=%u write=%u need_update=%d frozen=%d n_window=%d ampdu=%d", 2792 txq->read_ptr, txq->write_ptr, 2793 txq->need_update, txq->frozen, 2794 txq->n_window, txq->ampdu); 2795 else 2796 seq_puts(seq, "(unallocated)"); 2797 2798 if (state->pos == trans->conf.cmd_queue) 2799 seq_puts(seq, " (HCMD)"); 2800 seq_puts(seq, "\n"); 2801 2802 return 0; 2803} 2804 2805static const struct seq_operations iwl_dbgfs_tx_queue_seq_ops = { 2806 .start = iwl_dbgfs_tx_queue_seq_start, 2807 .next = iwl_dbgfs_tx_queue_seq_next, 2808 .stop = iwl_dbgfs_tx_queue_seq_stop, 2809 .show = iwl_dbgfs_tx_queue_seq_show, 2810}; 2811 2812static int iwl_dbgfs_tx_queue_open(struct inode *inode, struct file *filp) 2813{ 2814 struct iwl_dbgfs_tx_queue_priv *priv; 2815 2816 priv = __seq_open_private(filp, &iwl_dbgfs_tx_queue_seq_ops, 2817 sizeof(*priv)); 2818 2819 if (!priv) 2820 return -ENOMEM; 2821 2822 priv->trans = inode->i_private; 2823 return 0; 2824} 2825 2826static ssize_t iwl_dbgfs_rx_queue_read(struct file *file, 2827 char __user *user_buf, 2828 size_t count, loff_t *ppos) 2829{ 2830 struct iwl_trans *trans = file->private_data; 2831 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2832 char *buf; 2833 int pos = 0, i, ret; 2834 size_t bufsz; 2835 2836 bufsz = sizeof(char) * 121 * trans->info.num_rxqs; 2837 2838 if (!trans_pcie->rxq) 2839 return -EAGAIN; 2840 2841 buf = kzalloc(bufsz, GFP_KERNEL); 2842 if (!buf) 2843 return -ENOMEM; 2844 2845 for (i = 0; i < trans->info.num_rxqs && pos < bufsz; i++) { 2846 struct iwl_rxq *rxq = &trans_pcie->rxq[i]; 2847 2848 spin_lock_bh(&rxq->lock); 2849 2850 pos += scnprintf(buf + pos, bufsz - pos, "queue#: %2d\n", 2851 i); 2852 pos += scnprintf(buf + pos, bufsz - pos, "\tread: %u\n", 2853 rxq->read); 2854 pos += scnprintf(buf + pos, bufsz - pos, "\twrite: %u\n", 2855 rxq->write); 2856 pos += scnprintf(buf + pos, bufsz - pos, "\twrite_actual: %u\n", 2857 rxq->write_actual); 2858 pos += scnprintf(buf + pos, bufsz - pos, "\tneed_update: %2d\n", 2859 rxq->need_update); 2860 pos += scnprintf(buf + pos, bufsz - pos, "\tfree_count: %u\n", 2861 rxq->free_count); 2862 if (rxq->rb_stts) { 2863 u32 r = iwl_get_closed_rb_stts(trans, rxq); 2864 pos += scnprintf(buf + pos, bufsz - pos, 2865 "\tclosed_rb_num: %u\n", r); 2866 } else { 2867 pos += scnprintf(buf + pos, bufsz - pos, 2868 "\tclosed_rb_num: Not Allocated\n"); 2869 } 2870 spin_unlock_bh(&rxq->lock); 2871 } 2872 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2873 kfree(buf); 2874 2875 return ret; 2876} 2877 2878static ssize_t iwl_dbgfs_interrupt_read(struct file *file, 2879 char __user *user_buf, 2880 size_t count, loff_t *ppos) 2881{ 2882 struct iwl_trans *trans = file->private_data; 2883 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2884 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2885 2886 int pos = 0; 2887 char *buf; 2888 int bufsz = 24 * 64; /* 24 items * 64 char per item */ 2889 ssize_t ret; 2890 2891 buf = kzalloc(bufsz, GFP_KERNEL); 2892 if (!buf) 2893 return -ENOMEM; 2894 2895 pos += scnprintf(buf + pos, bufsz - pos, 2896 "Interrupt Statistics Report:\n"); 2897 2898 pos += scnprintf(buf + pos, bufsz - pos, "HW Error:\t\t\t %u\n", 2899 isr_stats->hw); 2900 pos += scnprintf(buf + pos, bufsz - pos, "SW Error:\t\t\t %u\n", 2901 isr_stats->sw); 2902 if (isr_stats->sw || isr_stats->hw) { 2903 pos += scnprintf(buf + pos, bufsz - pos, 2904 "\tLast Restarting Code: 0x%X\n", 2905 isr_stats->err_code); 2906 } 2907#ifdef CONFIG_IWLWIFI_DEBUG 2908 pos += scnprintf(buf + pos, bufsz - pos, "Frame transmitted:\t\t %u\n", 2909 isr_stats->sch); 2910 pos += scnprintf(buf + pos, bufsz - pos, "Alive interrupt:\t\t %u\n", 2911 isr_stats->alive); 2912#endif 2913 pos += scnprintf(buf + pos, bufsz - pos, 2914 "HW RF KILL switch toggled:\t %u\n", isr_stats->rfkill); 2915 2916 pos += scnprintf(buf + pos, bufsz - pos, "CT KILL:\t\t\t %u\n", 2917 isr_stats->ctkill); 2918 2919 pos += scnprintf(buf + pos, bufsz - pos, "Wakeup Interrupt:\t\t %u\n", 2920 isr_stats->wakeup); 2921 2922 pos += scnprintf(buf + pos, bufsz - pos, 2923 "Rx command responses:\t\t %u\n", isr_stats->rx); 2924 2925 pos += scnprintf(buf + pos, bufsz - pos, "Tx/FH interrupt:\t\t %u\n", 2926 isr_stats->tx); 2927 2928 pos += scnprintf(buf + pos, bufsz - pos, "Unexpected INTA:\t\t %u\n", 2929 isr_stats->unhandled); 2930 2931 ret = simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2932 kfree(buf); 2933 return ret; 2934} 2935 2936static ssize_t iwl_dbgfs_interrupt_write(struct file *file, 2937 const char __user *user_buf, 2938 size_t count, loff_t *ppos) 2939{ 2940 struct iwl_trans *trans = file->private_data; 2941 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2942 struct isr_statistics *isr_stats = &trans_pcie->isr_stats; 2943 u32 reset_flag; 2944 int ret; 2945 2946 ret = kstrtou32_from_user(user_buf, count, 16, &reset_flag); 2947 if (ret) 2948 return ret; 2949 if (reset_flag == 0) 2950 memset(isr_stats, 0, sizeof(*isr_stats)); 2951 2952 return count; 2953} 2954 2955static ssize_t iwl_dbgfs_csr_write(struct file *file, 2956 const char __user *user_buf, 2957 size_t count, loff_t *ppos) 2958{ 2959 struct iwl_trans *trans = file->private_data; 2960 2961 iwl_pcie_dump_csr(trans); 2962 2963 return count; 2964} 2965 2966static ssize_t iwl_dbgfs_fh_reg_read(struct file *file, 2967 char __user *user_buf, 2968 size_t count, loff_t *ppos) 2969{ 2970 struct iwl_trans *trans = file->private_data; 2971 char *buf = NULL; 2972 ssize_t ret; 2973 2974 ret = iwl_dump_fh(trans, &buf); 2975 if (ret < 0) 2976 return ret; 2977 if (!buf) 2978 return -EINVAL; 2979 ret = simple_read_from_buffer(user_buf, count, ppos, buf, ret); 2980 kfree(buf); 2981 return ret; 2982} 2983 2984static ssize_t iwl_dbgfs_rfkill_read(struct file *file, 2985 char __user *user_buf, 2986 size_t count, loff_t *ppos) 2987{ 2988 struct iwl_trans *trans = file->private_data; 2989 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 2990 char buf[100]; 2991 int pos; 2992 2993 pos = scnprintf(buf, sizeof(buf), "debug: %d\nhw: %d\n", 2994 trans_pcie->debug_rfkill, 2995 !(iwl_read32(trans, CSR_GP_CNTRL) & 2996 CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)); 2997 2998 return simple_read_from_buffer(user_buf, count, ppos, buf, pos); 2999} 3000 3001static ssize_t iwl_dbgfs_rfkill_write(struct file *file, 3002 const char __user *user_buf, 3003 size_t count, loff_t *ppos) 3004{ 3005 struct iwl_trans *trans = file->private_data; 3006 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3007 bool new_value; 3008 int ret; 3009 3010 ret = kstrtobool_from_user(user_buf, count, &new_value); 3011 if (ret) 3012 return ret; 3013 if (new_value == trans_pcie->debug_rfkill) 3014 return count; 3015 IWL_WARN(trans, "changing debug rfkill %d->%d\n", 3016 trans_pcie->debug_rfkill, new_value); 3017 trans_pcie->debug_rfkill = new_value; 3018 iwl_pcie_handle_rfkill_irq(trans, false); 3019 3020 return count; 3021} 3022 3023static int iwl_dbgfs_monitor_data_open(struct inode *inode, 3024 struct file *file) 3025{ 3026 struct iwl_trans *trans = inode->i_private; 3027 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3028 3029 if (!trans->dbg.dest_tlv || 3030 trans->dbg.dest_tlv->monitor_mode != EXTERNAL_MODE) { 3031 IWL_ERR(trans, "Debug destination is not set to DRAM\n"); 3032 return -ENOENT; 3033 } 3034 3035 if (trans_pcie->fw_mon_data.state != IWL_FW_MON_DBGFS_STATE_CLOSED) 3036 return -EBUSY; 3037 3038 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_OPEN; 3039 return simple_open(inode, file); 3040} 3041 3042static int iwl_dbgfs_monitor_data_release(struct inode *inode, 3043 struct file *file) 3044{ 3045 struct iwl_trans_pcie *trans_pcie = 3046 IWL_TRANS_GET_PCIE_TRANS(inode->i_private); 3047 3048 if (trans_pcie->fw_mon_data.state == IWL_FW_MON_DBGFS_STATE_OPEN) 3049 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3050 return 0; 3051} 3052 3053static bool iwl_write_to_user_buf(char __user *user_buf, ssize_t count, 3054 void *buf, ssize_t *size, 3055 ssize_t *bytes_copied) 3056{ 3057 ssize_t buf_size_left = count - *bytes_copied; 3058 3059 buf_size_left = buf_size_left - (buf_size_left % sizeof(u32)); 3060 if (*size > buf_size_left) 3061 *size = buf_size_left; 3062 3063 *size -= copy_to_user(user_buf, buf, *size); 3064 *bytes_copied += *size; 3065 3066 if (buf_size_left == *size) 3067 return true; 3068 return false; 3069} 3070 3071static ssize_t iwl_dbgfs_monitor_data_read(struct file *file, 3072 char __user *user_buf, 3073 size_t count, loff_t *ppos) 3074{ 3075 struct iwl_trans *trans = file->private_data; 3076 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3077 u8 *cpu_addr = (void *)trans->dbg.fw_mon.block, *curr_buf; 3078 struct cont_rec *data = &trans_pcie->fw_mon_data; 3079 u32 write_ptr_addr, wrap_cnt_addr, write_ptr, wrap_cnt; 3080 ssize_t size, bytes_copied = 0; 3081 bool b_full; 3082 3083 if (trans->dbg.dest_tlv) { 3084 write_ptr_addr = 3085 le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 3086 wrap_cnt_addr = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 3087 } else { 3088 write_ptr_addr = MON_BUFF_WRPTR; 3089 wrap_cnt_addr = MON_BUFF_CYCLE_CNT; 3090 } 3091 3092 if (unlikely(!trans->dbg.rec_on)) 3093 return 0; 3094 3095 mutex_lock(&data->mutex); 3096 if (data->state == 3097 IWL_FW_MON_DBGFS_STATE_DISABLED) { 3098 mutex_unlock(&data->mutex); 3099 return 0; 3100 } 3101 3102 /* write_ptr position in bytes rather then DW */ 3103 write_ptr = iwl_read_prph(trans, write_ptr_addr) * sizeof(u32); 3104 wrap_cnt = iwl_read_prph(trans, wrap_cnt_addr); 3105 3106 if (data->prev_wrap_cnt == wrap_cnt) { 3107 size = write_ptr - data->prev_wr_ptr; 3108 curr_buf = cpu_addr + data->prev_wr_ptr; 3109 b_full = iwl_write_to_user_buf(user_buf, count, 3110 curr_buf, &size, 3111 &bytes_copied); 3112 data->prev_wr_ptr += size; 3113 3114 } else if (data->prev_wrap_cnt == wrap_cnt - 1 && 3115 write_ptr < data->prev_wr_ptr) { 3116 size = trans->dbg.fw_mon.size - data->prev_wr_ptr; 3117 curr_buf = cpu_addr + data->prev_wr_ptr; 3118 b_full = iwl_write_to_user_buf(user_buf, count, 3119 curr_buf, &size, 3120 &bytes_copied); 3121 data->prev_wr_ptr += size; 3122 3123 if (!b_full) { 3124 size = write_ptr; 3125 b_full = iwl_write_to_user_buf(user_buf, count, 3126 cpu_addr, &size, 3127 &bytes_copied); 3128 data->prev_wr_ptr = size; 3129 data->prev_wrap_cnt++; 3130 } 3131 } else { 3132 if (data->prev_wrap_cnt == wrap_cnt - 1 && 3133 write_ptr > data->prev_wr_ptr) 3134 IWL_WARN(trans, 3135 "write pointer passed previous write pointer, start copying from the beginning\n"); 3136 else if (!unlikely(data->prev_wrap_cnt == 0 && 3137 data->prev_wr_ptr == 0)) 3138 IWL_WARN(trans, 3139 "monitor data is out of sync, start copying from the beginning\n"); 3140 3141 size = write_ptr; 3142 b_full = iwl_write_to_user_buf(user_buf, count, 3143 cpu_addr, &size, 3144 &bytes_copied); 3145 data->prev_wr_ptr = size; 3146 data->prev_wrap_cnt = wrap_cnt; 3147 } 3148 3149 mutex_unlock(&data->mutex); 3150 3151 return bytes_copied; 3152} 3153 3154static ssize_t iwl_dbgfs_rf_read(struct file *file, 3155 char __user *user_buf, 3156 size_t count, loff_t *ppos) 3157{ 3158 struct iwl_trans *trans = file->private_data; 3159 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3160 3161 if (!trans_pcie->rf_name[0]) 3162 return -ENODEV; 3163 3164 return simple_read_from_buffer(user_buf, count, ppos, 3165 trans_pcie->rf_name, 3166 strlen(trans_pcie->rf_name)); 3167} 3168 3169static ssize_t iwl_dbgfs_reset_write(struct file *file, 3170 const char __user *user_buf, 3171 size_t count, loff_t *ppos) 3172{ 3173 struct iwl_trans *trans = file->private_data; 3174 static const char * const modes[] = { 3175 [IWL_RESET_MODE_SW_RESET] = "sw", 3176 [IWL_RESET_MODE_REPROBE] = "reprobe", 3177 [IWL_RESET_MODE_TOP_RESET] = "top", 3178 [IWL_RESET_MODE_REMOVE_ONLY] = "remove", 3179 [IWL_RESET_MODE_RESCAN] = "rescan", 3180 [IWL_RESET_MODE_FUNC_RESET] = "function", 3181 [IWL_RESET_MODE_PROD_RESET] = "product", 3182 }; 3183 char buf[10] = {}; 3184 int mode; 3185 3186 if (count > sizeof(buf) - 1) 3187 return -EINVAL; 3188 3189 if (copy_from_user(buf, user_buf, count)) 3190 return -EFAULT; 3191 3192 mode = sysfs_match_string(modes, buf); 3193 if (mode < 0) 3194 return mode; 3195 3196 if (mode < IWL_RESET_MODE_REMOVE_ONLY) { 3197 if (!test_bit(STATUS_DEVICE_ENABLED, &trans->status)) 3198 return -EINVAL; 3199 if (mode == IWL_RESET_MODE_TOP_RESET) { 3200 if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_SC) 3201 return -EINVAL; 3202 trans->request_top_reset = 1; 3203 } 3204 iwl_op_mode_nic_error(trans->op_mode, IWL_ERR_TYPE_DEBUGFS); 3205 iwl_trans_schedule_reset(trans, IWL_ERR_TYPE_DEBUGFS); 3206 return count; 3207 } 3208 3209 iwl_trans_pcie_reset(trans, mode); 3210 3211 return count; 3212} 3213 3214DEBUGFS_READ_WRITE_FILE_OPS(interrupt); 3215DEBUGFS_READ_FILE_OPS(fh_reg); 3216DEBUGFS_READ_FILE_OPS(rx_queue); 3217DEBUGFS_WRITE_FILE_OPS(csr); 3218DEBUGFS_READ_WRITE_FILE_OPS(rfkill); 3219DEBUGFS_READ_FILE_OPS(rf); 3220DEBUGFS_WRITE_FILE_OPS(reset); 3221 3222static const struct file_operations iwl_dbgfs_tx_queue_ops = { 3223 .owner = THIS_MODULE, 3224 .open = iwl_dbgfs_tx_queue_open, 3225 .read = seq_read, 3226 .llseek = seq_lseek, 3227 .release = seq_release_private, 3228}; 3229 3230static const struct file_operations iwl_dbgfs_monitor_data_ops = { 3231 .read = iwl_dbgfs_monitor_data_read, 3232 .open = iwl_dbgfs_monitor_data_open, 3233 .release = iwl_dbgfs_monitor_data_release, 3234}; 3235 3236/* Create the debugfs files and directories */ 3237void iwl_trans_pcie_dbgfs_register(struct iwl_trans *trans) 3238{ 3239 struct dentry *dir = trans->dbgfs_dir; 3240 3241 DEBUGFS_ADD_FILE(rx_queue, dir, 0400); 3242 DEBUGFS_ADD_FILE(tx_queue, dir, 0400); 3243 DEBUGFS_ADD_FILE(interrupt, dir, 0600); 3244 DEBUGFS_ADD_FILE(csr, dir, 0200); 3245 DEBUGFS_ADD_FILE(fh_reg, dir, 0400); 3246 DEBUGFS_ADD_FILE(rfkill, dir, 0600); 3247 DEBUGFS_ADD_FILE(monitor_data, dir, 0400); 3248 DEBUGFS_ADD_FILE(rf, dir, 0400); 3249 DEBUGFS_ADD_FILE(reset, dir, 0200); 3250} 3251 3252void iwl_trans_pcie_debugfs_cleanup(struct iwl_trans *trans) 3253{ 3254 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3255 struct cont_rec *data = &trans_pcie->fw_mon_data; 3256 3257 mutex_lock(&data->mutex); 3258 data->state = IWL_FW_MON_DBGFS_STATE_DISABLED; 3259 mutex_unlock(&data->mutex); 3260} 3261#endif /*CONFIG_IWLWIFI_DEBUGFS */ 3262 3263static u32 iwl_trans_pcie_get_cmdlen(struct iwl_trans *trans, void *tfd) 3264{ 3265 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3266 u32 cmdlen = 0; 3267 int i; 3268 3269 for (i = 0; i < trans_pcie->txqs.tfd.max_tbs; i++) 3270 cmdlen += iwl_txq_gen1_tfd_tb_get_len(trans, tfd, i); 3271 3272 return cmdlen; 3273} 3274 3275static u32 iwl_trans_pcie_dump_rbs(struct iwl_trans *trans, 3276 struct iwl_fw_error_dump_data **data, 3277 int allocated_rb_nums) 3278{ 3279 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3280 int max_len = trans_pcie->rx_buf_bytes; 3281 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 3282 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3283 u32 i, r, j, rb_len = 0; 3284 3285 spin_lock_bh(&rxq->lock); 3286 3287 r = iwl_get_closed_rb_stts(trans, rxq); 3288 3289 for (i = rxq->read, j = 0; 3290 i != r && j < allocated_rb_nums; 3291 i = (i + 1) & RX_QUEUE_MASK, j++) { 3292 struct iwl_rx_mem_buffer *rxb = rxq->queue[i]; 3293 struct iwl_fw_error_dump_rb *rb; 3294 3295 dma_sync_single_for_cpu(trans->dev, rxb->page_dma, 3296 max_len, DMA_FROM_DEVICE); 3297 3298 rb_len += sizeof(**data) + sizeof(*rb) + max_len; 3299 3300 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RB); 3301 (*data)->len = cpu_to_le32(sizeof(*rb) + max_len); 3302 rb = (void *)(*data)->data; 3303 rb->index = cpu_to_le32(i); 3304 memcpy(rb->data, page_address(rxb->page), max_len); 3305 3306 *data = iwl_fw_error_next_data(*data); 3307 } 3308 3309 spin_unlock_bh(&rxq->lock); 3310 3311 return rb_len; 3312} 3313#define IWL_CSR_TO_DUMP (0x250) 3314 3315static u32 iwl_trans_pcie_dump_csr(struct iwl_trans *trans, 3316 struct iwl_fw_error_dump_data **data) 3317{ 3318 u32 csr_len = sizeof(**data) + IWL_CSR_TO_DUMP; 3319 __le32 *val; 3320 int i; 3321 3322 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_CSR); 3323 (*data)->len = cpu_to_le32(IWL_CSR_TO_DUMP); 3324 val = (void *)(*data)->data; 3325 3326 for (i = 0; i < IWL_CSR_TO_DUMP; i += 4) 3327 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3328 3329 *data = iwl_fw_error_next_data(*data); 3330 3331 return csr_len; 3332} 3333 3334static u32 iwl_trans_pcie_fh_regs_dump(struct iwl_trans *trans, 3335 struct iwl_fw_error_dump_data **data) 3336{ 3337 u32 fh_regs_len = FH_MEM_UPPER_BOUND - FH_MEM_LOWER_BOUND; 3338 __le32 *val; 3339 int i; 3340 3341 if (!iwl_trans_grab_nic_access(trans)) 3342 return 0; 3343 3344 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FH_REGS); 3345 (*data)->len = cpu_to_le32(fh_regs_len); 3346 val = (void *)(*data)->data; 3347 3348 if (!trans->mac_cfg->gen2) 3349 for (i = FH_MEM_LOWER_BOUND; i < FH_MEM_UPPER_BOUND; 3350 i += sizeof(u32)) 3351 *val++ = cpu_to_le32(iwl_trans_pcie_read32(trans, i)); 3352 else 3353 for (i = iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2); 3354 i < iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2); 3355 i += sizeof(u32)) 3356 *val++ = cpu_to_le32(iwl_trans_pcie_read_prph(trans, 3357 i)); 3358 3359 iwl_trans_release_nic_access(trans); 3360 3361 *data = iwl_fw_error_next_data(*data); 3362 3363 return sizeof(**data) + fh_regs_len; 3364} 3365 3366static u32 3367iwl_trans_pci_dump_marbh_monitor(struct iwl_trans *trans, 3368 struct iwl_fw_error_dump_fw_mon *fw_mon_data, 3369 u32 monitor_len) 3370{ 3371 u32 buf_size_in_dwords = (monitor_len >> 2); 3372 u32 *buffer = (u32 *)fw_mon_data->data; 3373 u32 i; 3374 3375 if (!iwl_trans_grab_nic_access(trans)) 3376 return 0; 3377 3378 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x1); 3379 for (i = 0; i < buf_size_in_dwords; i++) 3380 buffer[i] = iwl_read_umac_prph_no_grab(trans, 3381 MON_DMARB_RD_DATA_ADDR); 3382 iwl_write_umac_prph_no_grab(trans, MON_DMARB_RD_CTL_ADDR, 0x0); 3383 3384 iwl_trans_release_nic_access(trans); 3385 3386 return monitor_len; 3387} 3388 3389static void 3390iwl_trans_pcie_dump_pointers(struct iwl_trans *trans, 3391 struct iwl_fw_error_dump_fw_mon *fw_mon_data) 3392{ 3393 u32 base, base_high, write_ptr, write_ptr_val, wrap_cnt; 3394 3395 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3396 base = DBGC_CUR_DBGBUF_BASE_ADDR_LSB; 3397 base_high = DBGC_CUR_DBGBUF_BASE_ADDR_MSB; 3398 write_ptr = DBGC_CUR_DBGBUF_STATUS; 3399 wrap_cnt = DBGC_DBGBUF_WRAP_AROUND; 3400 } else if (trans->dbg.dest_tlv) { 3401 write_ptr = le32_to_cpu(trans->dbg.dest_tlv->write_ptr_reg); 3402 wrap_cnt = le32_to_cpu(trans->dbg.dest_tlv->wrap_count); 3403 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3404 } else { 3405 base = MON_BUFF_BASE_ADDR; 3406 write_ptr = MON_BUFF_WRPTR; 3407 wrap_cnt = MON_BUFF_CYCLE_CNT; 3408 } 3409 3410 write_ptr_val = iwl_read_prph(trans, write_ptr); 3411 fw_mon_data->fw_mon_cycle_cnt = 3412 cpu_to_le32(iwl_read_prph(trans, wrap_cnt)); 3413 fw_mon_data->fw_mon_base_ptr = 3414 cpu_to_le32(iwl_read_prph(trans, base)); 3415 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 3416 fw_mon_data->fw_mon_base_high_ptr = 3417 cpu_to_le32(iwl_read_prph(trans, base_high)); 3418 write_ptr_val &= DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK; 3419 /* convert wrtPtr to DWs, to align with all HWs */ 3420 write_ptr_val >>= 2; 3421 } 3422 fw_mon_data->fw_mon_wr_ptr = cpu_to_le32(write_ptr_val); 3423} 3424 3425static u32 3426iwl_trans_pcie_dump_monitor(struct iwl_trans *trans, 3427 struct iwl_fw_error_dump_data **data, 3428 u32 monitor_len) 3429{ 3430 struct iwl_dram_data *fw_mon = &trans->dbg.fw_mon; 3431 u32 len = 0; 3432 3433 if (trans->dbg.dest_tlv || 3434 (fw_mon->size && 3435 (trans->mac_cfg->device_family == IWL_DEVICE_FAMILY_7000 || 3436 trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210))) { 3437 struct iwl_fw_error_dump_fw_mon *fw_mon_data; 3438 3439 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_FW_MONITOR); 3440 fw_mon_data = (void *)(*data)->data; 3441 3442 iwl_trans_pcie_dump_pointers(trans, fw_mon_data); 3443 3444 len += sizeof(**data) + sizeof(*fw_mon_data); 3445 if (fw_mon->size) { 3446 memcpy(fw_mon_data->data, fw_mon->block, fw_mon->size); 3447 monitor_len = fw_mon->size; 3448 } else if (trans->dbg.dest_tlv->monitor_mode == SMEM_MODE) { 3449 u32 base = le32_to_cpu(fw_mon_data->fw_mon_base_ptr); 3450 /* 3451 * Update pointers to reflect actual values after 3452 * shifting 3453 */ 3454 if (trans->dbg.dest_tlv->version) { 3455 base = (iwl_read_prph(trans, base) & 3456 IWL_LDBG_M2S_BUF_BA_MSK) << 3457 trans->dbg.dest_tlv->base_shift; 3458 base *= IWL_M2S_UNIT_SIZE; 3459 base += trans->mac_cfg->base->smem_offset; 3460 } else { 3461 base = iwl_read_prph(trans, base) << 3462 trans->dbg.dest_tlv->base_shift; 3463 } 3464 3465 iwl_trans_pcie_read_mem(trans, base, fw_mon_data->data, 3466 monitor_len / sizeof(u32)); 3467 } else if (trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) { 3468 monitor_len = 3469 iwl_trans_pci_dump_marbh_monitor(trans, 3470 fw_mon_data, 3471 monitor_len); 3472 } else { 3473 /* Didn't match anything - output no monitor data */ 3474 monitor_len = 0; 3475 } 3476 3477 len += monitor_len; 3478 (*data)->len = cpu_to_le32(monitor_len + sizeof(*fw_mon_data)); 3479 } 3480 3481 return len; 3482} 3483 3484static int iwl_trans_get_fw_monitor_len(struct iwl_trans *trans, u32 *len) 3485{ 3486 if (trans->dbg.fw_mon.size) { 3487 *len += sizeof(struct iwl_fw_error_dump_data) + 3488 sizeof(struct iwl_fw_error_dump_fw_mon) + 3489 trans->dbg.fw_mon.size; 3490 return trans->dbg.fw_mon.size; 3491 } else if (trans->dbg.dest_tlv) { 3492 u32 base, end, cfg_reg, monitor_len; 3493 3494 if (trans->dbg.dest_tlv->version == 1) { 3495 cfg_reg = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3496 cfg_reg = iwl_read_prph(trans, cfg_reg); 3497 base = (cfg_reg & IWL_LDBG_M2S_BUF_BA_MSK) << 3498 trans->dbg.dest_tlv->base_shift; 3499 base *= IWL_M2S_UNIT_SIZE; 3500 base += trans->mac_cfg->base->smem_offset; 3501 3502 monitor_len = 3503 (cfg_reg & IWL_LDBG_M2S_BUF_SIZE_MSK) >> 3504 trans->dbg.dest_tlv->end_shift; 3505 monitor_len *= IWL_M2S_UNIT_SIZE; 3506 } else { 3507 base = le32_to_cpu(trans->dbg.dest_tlv->base_reg); 3508 end = le32_to_cpu(trans->dbg.dest_tlv->end_reg); 3509 3510 base = iwl_read_prph(trans, base) << 3511 trans->dbg.dest_tlv->base_shift; 3512 end = iwl_read_prph(trans, end) << 3513 trans->dbg.dest_tlv->end_shift; 3514 3515 /* Make "end" point to the actual end */ 3516 if (trans->mac_cfg->device_family >= 3517 IWL_DEVICE_FAMILY_8000 || 3518 trans->dbg.dest_tlv->monitor_mode == MARBH_MODE) 3519 end += (1 << trans->dbg.dest_tlv->end_shift); 3520 monitor_len = end - base; 3521 } 3522 *len += sizeof(struct iwl_fw_error_dump_data) + 3523 sizeof(struct iwl_fw_error_dump_fw_mon) + 3524 monitor_len; 3525 return monitor_len; 3526 } 3527 return 0; 3528} 3529 3530struct iwl_trans_dump_data * 3531iwl_trans_pcie_dump_data(struct iwl_trans *trans, u32 dump_mask, 3532 const struct iwl_dump_sanitize_ops *sanitize_ops, 3533 void *sanitize_ctx) 3534{ 3535 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3536 struct iwl_fw_error_dump_data *data; 3537 struct iwl_txq *cmdq = trans_pcie->txqs.txq[trans->conf.cmd_queue]; 3538 struct iwl_fw_error_dump_txcmd *txcmd; 3539 struct iwl_trans_dump_data *dump_data; 3540 u32 len, num_rbs = 0, monitor_len = 0; 3541 int i, ptr; 3542 bool dump_rbs = iwl_trans_is_fw_error(trans) && 3543 !trans->mac_cfg->mq_rx_supported && 3544 dump_mask & BIT(IWL_FW_ERROR_DUMP_RB); 3545 3546 if (!dump_mask) 3547 return NULL; 3548 3549 /* transport dump header */ 3550 len = sizeof(*dump_data); 3551 3552 /* host commands */ 3553 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) 3554 len += sizeof(*data) + 3555 cmdq->n_window * (sizeof(*txcmd) + 3556 TFD_MAX_PAYLOAD_SIZE); 3557 3558 /* FW monitor */ 3559 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3560 monitor_len = iwl_trans_get_fw_monitor_len(trans, &len); 3561 3562 /* CSR registers */ 3563 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3564 len += sizeof(*data) + IWL_CSR_TO_DUMP; 3565 3566 /* FH registers */ 3567 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) { 3568 if (trans->mac_cfg->gen2) 3569 len += sizeof(*data) + 3570 (iwl_umac_prph(trans, FH_MEM_UPPER_BOUND_GEN2) - 3571 iwl_umac_prph(trans, FH_MEM_LOWER_BOUND_GEN2)); 3572 else 3573 len += sizeof(*data) + 3574 (FH_MEM_UPPER_BOUND - 3575 FH_MEM_LOWER_BOUND); 3576 } 3577 3578 if (dump_rbs) { 3579 /* Dump RBs is supported only for pre-9000 devices (1 queue) */ 3580 struct iwl_rxq *rxq = &trans_pcie->rxq[0]; 3581 /* RBs */ 3582 spin_lock_bh(&rxq->lock); 3583 num_rbs = iwl_get_closed_rb_stts(trans, rxq); 3584 num_rbs = (num_rbs - rxq->read) & RX_QUEUE_MASK; 3585 spin_unlock_bh(&rxq->lock); 3586 3587 len += num_rbs * (sizeof(*data) + 3588 sizeof(struct iwl_fw_error_dump_rb) + 3589 (PAGE_SIZE << trans_pcie->rx_page_order)); 3590 } 3591 3592 /* Paged memory for gen2 HW */ 3593 if (trans->mac_cfg->gen2 && dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) 3594 for (i = 0; i < trans->init_dram.paging_cnt; i++) 3595 len += sizeof(*data) + 3596 sizeof(struct iwl_fw_error_dump_paging) + 3597 trans->init_dram.paging[i].size; 3598 3599 dump_data = vzalloc(len); 3600 if (!dump_data) 3601 return NULL; 3602 3603 len = 0; 3604 data = (void *)dump_data->data; 3605 3606 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_TXCMD) && cmdq) { 3607 u16 tfd_size = trans_pcie->txqs.tfd.size; 3608 3609 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXCMD); 3610 txcmd = (void *)data->data; 3611 spin_lock_bh(&cmdq->lock); 3612 ptr = cmdq->write_ptr; 3613 for (i = 0; i < cmdq->n_window; i++) { 3614 u8 idx = iwl_txq_get_cmd_index(cmdq, ptr); 3615 u8 tfdidx; 3616 u32 caplen, cmdlen; 3617 3618 if (trans->mac_cfg->gen2) 3619 tfdidx = idx; 3620 else 3621 tfdidx = ptr; 3622 3623 cmdlen = iwl_trans_pcie_get_cmdlen(trans, 3624 (u8 *)cmdq->tfds + 3625 tfd_size * tfdidx); 3626 caplen = min_t(u32, TFD_MAX_PAYLOAD_SIZE, cmdlen); 3627 3628 if (cmdlen) { 3629 len += sizeof(*txcmd) + caplen; 3630 txcmd->cmdlen = cpu_to_le32(cmdlen); 3631 txcmd->caplen = cpu_to_le32(caplen); 3632 memcpy(txcmd->data, cmdq->entries[idx].cmd, 3633 caplen); 3634 if (sanitize_ops && sanitize_ops->frob_hcmd) 3635 sanitize_ops->frob_hcmd(sanitize_ctx, 3636 txcmd->data, 3637 caplen); 3638 txcmd = (void *)((u8 *)txcmd->data + caplen); 3639 } 3640 3641 ptr = iwl_txq_dec_wrap(trans, ptr); 3642 } 3643 spin_unlock_bh(&cmdq->lock); 3644 3645 data->len = cpu_to_le32(len); 3646 len += sizeof(*data); 3647 data = iwl_fw_error_next_data(data); 3648 } 3649 3650 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_CSR)) 3651 len += iwl_trans_pcie_dump_csr(trans, &data); 3652 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FH_REGS)) 3653 len += iwl_trans_pcie_fh_regs_dump(trans, &data); 3654 if (dump_rbs) 3655 len += iwl_trans_pcie_dump_rbs(trans, &data, num_rbs); 3656 3657 /* Paged memory for gen2 HW */ 3658 if (trans->mac_cfg->gen2 && 3659 dump_mask & BIT(IWL_FW_ERROR_DUMP_PAGING)) { 3660 for (i = 0; i < trans->init_dram.paging_cnt; i++) { 3661 struct iwl_fw_error_dump_paging *paging; 3662 u32 page_len = trans->init_dram.paging[i].size; 3663 3664 data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 3665 data->len = cpu_to_le32(sizeof(*paging) + page_len); 3666 paging = (void *)data->data; 3667 paging->index = cpu_to_le32(i); 3668 memcpy(paging->data, 3669 trans->init_dram.paging[i].block, page_len); 3670 data = iwl_fw_error_next_data(data); 3671 3672 len += sizeof(*data) + sizeof(*paging) + page_len; 3673 } 3674 } 3675 if (dump_mask & BIT(IWL_FW_ERROR_DUMP_FW_MONITOR)) 3676 len += iwl_trans_pcie_dump_monitor(trans, &data, monitor_len); 3677 3678 dump_data->len = len; 3679 3680 return dump_data; 3681} 3682 3683void iwl_trans_pci_interrupts(struct iwl_trans *trans, bool enable) 3684{ 3685 if (enable) 3686 iwl_enable_interrupts(trans); 3687 else 3688 iwl_disable_interrupts(trans); 3689} 3690 3691void iwl_trans_pcie_sync_nmi(struct iwl_trans *trans) 3692{ 3693 u32 inta_addr, sw_err_bit; 3694 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3695 3696 if (trans_pcie->msix_enabled) { 3697 inta_addr = CSR_MSIX_HW_INT_CAUSES_AD; 3698 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 3699 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ; 3700 else 3701 sw_err_bit = MSIX_HW_INT_CAUSES_REG_SW_ERR; 3702 } else { 3703 inta_addr = CSR_INT; 3704 sw_err_bit = CSR_INT_BIT_SW_ERR; 3705 } 3706 3707 iwl_trans_sync_nmi_with_addr(trans, inta_addr, sw_err_bit); 3708} 3709 3710static int iwl_trans_pcie_alloc_txcmd_pool(struct iwl_trans *trans) 3711{ 3712 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3713 unsigned int txcmd_size, txcmd_align; 3714 3715 if (!trans->mac_cfg->gen2) { 3716 txcmd_size = sizeof(struct iwl_tx_cmd_v6); 3717 txcmd_align = sizeof(void *); 3718 } else if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_AX210) { 3719 txcmd_size = sizeof(struct iwl_tx_cmd_v9); 3720 txcmd_align = 64; 3721 } else { 3722 txcmd_size = sizeof(struct iwl_tx_cmd); 3723 txcmd_align = 128; 3724 } 3725 3726 txcmd_size += sizeof(struct iwl_cmd_header); 3727 txcmd_size += 36; /* biggest possible 802.11 header */ 3728 3729 /* Ensure device TX cmd cannot reach/cross a page boundary in gen2 */ 3730 if (WARN_ON((trans->mac_cfg->gen2 && txcmd_size >= txcmd_align))) 3731 return -EINVAL; 3732 3733 snprintf(trans_pcie->dev_cmd_pool_name, 3734 sizeof(trans_pcie->dev_cmd_pool_name), 3735 "iwl_cmd_pool:%s", dev_name(trans->dev)); 3736 3737 trans_pcie->dev_cmd_pool = 3738 kmem_cache_create(trans_pcie->dev_cmd_pool_name, 3739 txcmd_size, txcmd_align, 3740 SLAB_HWCACHE_ALIGN, NULL); 3741 if (!trans_pcie->dev_cmd_pool) 3742 return -ENOMEM; 3743 3744 return 0; 3745} 3746 3747static struct iwl_trans * 3748iwl_trans_pcie_alloc(struct pci_dev *pdev, 3749 const struct iwl_mac_cfg *mac_cfg, 3750 struct iwl_trans_info *info, u8 __iomem *hw_base) 3751{ 3752 struct iwl_trans_pcie *trans_pcie, **priv; 3753 struct iwl_trans *trans; 3754 unsigned int bc_tbl_n_entries; 3755 int ret, addr_size; 3756 3757 trans = iwl_trans_alloc(sizeof(struct iwl_trans_pcie), &pdev->dev, 3758 mac_cfg); 3759 if (!trans) 3760 return ERR_PTR(-ENOMEM); 3761 3762 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3763 3764 trans_pcie->hw_base = hw_base; 3765 3766 /* Initialize the wait queue for commands */ 3767 init_waitqueue_head(&trans_pcie->wait_command_queue); 3768 3769 ret = iwl_trans_pcie_alloc_txcmd_pool(trans); 3770 if (ret) 3771 goto out_free_trans; 3772 3773 if (trans->mac_cfg->gen2) { 3774 trans_pcie->txqs.tfd.addr_size = 64; 3775 trans_pcie->txqs.tfd.max_tbs = IWL_TFH_NUM_TBS; 3776 trans_pcie->txqs.tfd.size = sizeof(struct iwl_tfh_tfd); 3777 } else { 3778 trans_pcie->txqs.tfd.addr_size = 36; 3779 trans_pcie->txqs.tfd.max_tbs = IWL_NUM_OF_TBS; 3780 trans_pcie->txqs.tfd.size = sizeof(struct iwl_tfd); 3781 } 3782 3783 trans_pcie->supported_dma_mask = (u32)DMA_BIT_MASK(12); 3784 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 3785 trans_pcie->supported_dma_mask = (u32)DMA_BIT_MASK(11); 3786 3787 info->max_skb_frags = IWL_TRANS_PCIE_MAX_FRAGS(trans_pcie); 3788 3789 trans_pcie->txqs.tso_hdr_page = alloc_percpu(struct iwl_tso_hdr_page); 3790 if (!trans_pcie->txqs.tso_hdr_page) { 3791 ret = -ENOMEM; 3792 goto out_free_txcmd_pool; 3793 } 3794 3795 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) 3796 bc_tbl_n_entries = TFD_QUEUE_BC_SIZE_BZ; 3797 else if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 3798 bc_tbl_n_entries = TFD_QUEUE_BC_SIZE_AX210; 3799 else 3800 bc_tbl_n_entries = TFD_QUEUE_BC_SIZE; 3801 3802 trans_pcie->txqs.bc_tbl_size = 3803 sizeof(struct iwl_bc_tbl_entry) * bc_tbl_n_entries; 3804 /* 3805 * For gen2 devices, we use a single allocation for each byte-count 3806 * table, but they're pretty small (1k) so use a DMA pool that we 3807 * allocate here. 3808 */ 3809 if (trans->mac_cfg->gen2) { 3810 trans_pcie->txqs.bc_pool = 3811 dmam_pool_create("iwlwifi:bc", trans->dev, 3812 trans_pcie->txqs.bc_tbl_size, 3813 256, 0); 3814 if (!trans_pcie->txqs.bc_pool) { 3815 ret = -ENOMEM; 3816 goto out_free_tso; 3817 } 3818 } 3819 3820 /* Some things must not change even if the config does */ 3821 WARN_ON(trans_pcie->txqs.tfd.addr_size != 3822 (trans->mac_cfg->gen2 ? 64 : 36)); 3823 3824 /* Initialize NAPI here - it should be before registering to mac80211 3825 * in the opmode but after the HW struct is allocated. 3826 */ 3827 trans_pcie->napi_dev = alloc_netdev_dummy(sizeof(struct iwl_trans_pcie *)); 3828 if (!trans_pcie->napi_dev) { 3829 ret = -ENOMEM; 3830 goto out_free_tso; 3831 } 3832 /* The private struct in netdev is a pointer to struct iwl_trans_pcie */ 3833 priv = netdev_priv(trans_pcie->napi_dev); 3834 *priv = trans_pcie; 3835 3836 trans_pcie->trans = trans; 3837 trans_pcie->opmode_down = true; 3838 spin_lock_init(&trans_pcie->irq_lock); 3839 spin_lock_init(&trans_pcie->reg_lock); 3840 spin_lock_init(&trans_pcie->alloc_page_lock); 3841 mutex_init(&trans_pcie->mutex); 3842 init_waitqueue_head(&trans_pcie->ucode_write_waitq); 3843 init_waitqueue_head(&trans_pcie->fw_reset_waitq); 3844 init_waitqueue_head(&trans_pcie->imr_waitq); 3845 3846 trans_pcie->rba.alloc_wq = alloc_workqueue("rb_allocator", 3847 WQ_HIGHPRI | WQ_UNBOUND, 0); 3848 if (!trans_pcie->rba.alloc_wq) { 3849 ret = -ENOMEM; 3850 goto out_free_ndev; 3851 } 3852 INIT_WORK(&trans_pcie->rba.rx_alloc, iwl_pcie_rx_allocator_work); 3853 3854 trans_pcie->debug_rfkill = -1; 3855 3856 if (!mac_cfg->base->pcie_l1_allowed) { 3857 /* 3858 * W/A - seems to solve weird behavior. We need to remove this 3859 * if we don't want to stay in L1 all the time. This wastes a 3860 * lot of power. 3861 */ 3862 pci_disable_link_state(pdev, PCIE_LINK_STATE_L0S | 3863 PCIE_LINK_STATE_L1 | 3864 PCIE_LINK_STATE_CLKPM); 3865 } 3866 3867 addr_size = trans_pcie->txqs.tfd.addr_size; 3868 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(addr_size)); 3869 if (ret) { 3870 ret = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 3871 /* both attempts failed: */ 3872 if (ret) { 3873 dev_err(&pdev->dev, "No suitable DMA available\n"); 3874 goto out_no_pci; 3875 } 3876 } 3877 3878 /* We disable the RETRY_TIMEOUT register (0x41) to keep 3879 * PCI Tx retries from interfering with C3 CPU state */ 3880 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 3881 3882 trans_pcie->pci_dev = pdev; 3883 iwl_disable_interrupts(trans); 3884 3885 /* 3886 * In the 8000 HW family the format of the 4 bytes of CSR_HW_REV have 3887 * changed, and now the revision step also includes bit 0-1 (no more 3888 * "dash" value). To keep hw_rev backwards compatible - we'll store it 3889 * in the old format. 3890 */ 3891 if (mac_cfg->device_family >= IWL_DEVICE_FAMILY_8000) 3892 info->hw_rev_step = info->hw_rev & 0xF; 3893 else 3894 info->hw_rev_step = (info->hw_rev & 0xC) >> 2; 3895 3896 IWL_DEBUG_INFO(trans, "HW REV: 0x%0x\n", info->hw_rev); 3897 3898 iwl_pcie_set_interrupt_capa(pdev, trans, mac_cfg, info); 3899 3900 init_waitqueue_head(&trans_pcie->sx_waitq); 3901 3902 ret = iwl_pcie_alloc_invalid_tx_cmd(trans); 3903 if (ret) 3904 goto out_no_pci; 3905 3906 if (trans_pcie->msix_enabled) { 3907 ret = iwl_pcie_init_msix_handler(pdev, trans_pcie, info); 3908 if (ret) 3909 goto out_no_pci; 3910 } else { 3911 ret = iwl_pcie_alloc_ict(trans); 3912 if (ret) 3913 goto out_no_pci; 3914 3915 ret = devm_request_threaded_irq(&pdev->dev, pdev->irq, 3916 iwl_pcie_isr, 3917 iwl_pcie_irq_handler, 3918 IRQF_SHARED, DRV_NAME, trans); 3919 if (ret) { 3920 IWL_ERR(trans, "Error allocating IRQ %d\n", pdev->irq); 3921 goto out_free_ict; 3922 } 3923 } 3924 3925#ifdef CONFIG_IWLWIFI_DEBUGFS 3926 trans_pcie->fw_mon_data.state = IWL_FW_MON_DBGFS_STATE_CLOSED; 3927 mutex_init(&trans_pcie->fw_mon_data.mutex); 3928#endif 3929 3930 iwl_dbg_tlv_init(trans); 3931 3932 return trans; 3933 3934out_free_ict: 3935 iwl_pcie_free_ict(trans); 3936out_no_pci: 3937 destroy_workqueue(trans_pcie->rba.alloc_wq); 3938out_free_ndev: 3939 free_netdev(trans_pcie->napi_dev); 3940out_free_tso: 3941 free_percpu(trans_pcie->txqs.tso_hdr_page); 3942out_free_txcmd_pool: 3943 kmem_cache_destroy(trans_pcie->dev_cmd_pool); 3944out_free_trans: 3945 iwl_trans_free(trans); 3946 return ERR_PTR(ret); 3947} 3948 3949void iwl_trans_pcie_copy_imr_fh(struct iwl_trans *trans, 3950 u32 dst_addr, u64 src_addr, u32 byte_cnt) 3951{ 3952 iwl_write_prph(trans, IMR_UREG_CHICK, 3953 iwl_read_prph(trans, IMR_UREG_CHICK) | 3954 IMR_UREG_CHICK_HALT_UMAC_PERMANENTLY_MSK); 3955 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_SRAM_ADDR, dst_addr); 3956 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_LSB, 3957 (u32)(src_addr & 0xFFFFFFFF)); 3958 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_DRAM_ADDR_MSB, 3959 iwl_get_dma_hi_addr(src_addr)); 3960 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_BC, byte_cnt); 3961 iwl_write_prph(trans, IMR_TFH_SRV_DMA_CHNL0_CTRL, 3962 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_IRQ_TARGET_POS | 3963 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_DMA_EN_POS | 3964 IMR_TFH_SRV_DMA_CHNL0_CTRL_D2S_RS_MSK); 3965} 3966 3967int iwl_trans_pcie_copy_imr(struct iwl_trans *trans, 3968 u32 dst_addr, u64 src_addr, u32 byte_cnt) 3969{ 3970 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 3971 int ret = -1; 3972 3973 trans_pcie->imr_status = IMR_D2S_REQUESTED; 3974 iwl_trans_pcie_copy_imr_fh(trans, dst_addr, src_addr, byte_cnt); 3975 ret = wait_event_timeout(trans_pcie->imr_waitq, 3976 trans_pcie->imr_status != 3977 IMR_D2S_REQUESTED, 5 * HZ); 3978 if (!ret || trans_pcie->imr_status == IMR_D2S_ERROR) { 3979 IWL_ERR(trans, "Failed to copy IMR Memory chunk!\n"); 3980 iwl_trans_pcie_dump_regs(trans, trans_pcie->pci_dev); 3981 return -ETIMEDOUT; 3982 } 3983 trans_pcie->imr_status = IMR_D2S_IDLE; 3984 return 0; 3985} 3986 3987/* 3988 * Read rf id and cdb info from prph register and store it 3989 */ 3990static void get_crf_id(struct iwl_trans *iwl_trans, 3991 struct iwl_trans_info *info) 3992{ 3993 u32 sd_reg_ver_addr; 3994 u32 hw_wfpm_id; 3995 u32 val = 0; 3996 u8 step; 3997 3998 if (iwl_trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 3999 sd_reg_ver_addr = SD_REG_VER_GEN2; 4000 else 4001 sd_reg_ver_addr = SD_REG_VER; 4002 4003 /* Enable access to peripheral registers */ 4004 val = iwl_read_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG); 4005 val |= WFPM_AUX_CTL_AUX_IF_MAC_OWNER_MSK; 4006 iwl_write_umac_prph_no_grab(iwl_trans, WFPM_CTRL_REG, val); 4007 4008 /* Read crf info */ 4009 info->hw_crf_id = iwl_read_prph_no_grab(iwl_trans, sd_reg_ver_addr); 4010 4011 /* Read cnv info */ 4012 info->hw_cnv_id = iwl_read_prph_no_grab(iwl_trans, CNVI_AUX_MISC_CHIP); 4013 4014 /* For BZ-W, take B step also when A step is indicated */ 4015 if (CSR_HW_REV_TYPE(info->hw_rev) == IWL_CFG_MAC_TYPE_BZ_W) 4016 step = SILICON_B_STEP; 4017 4018 /* In BZ, the MAC step must be read from the CNVI aux register */ 4019 if (CSR_HW_REV_TYPE(info->hw_rev) == IWL_CFG_MAC_TYPE_BZ) { 4020 step = CNVI_AUX_MISC_CHIP_MAC_STEP(info->hw_cnv_id); 4021 4022 /* For BZ-U, take B step also when A step is indicated */ 4023 if ((CNVI_AUX_MISC_CHIP_PROD_TYPE(info->hw_cnv_id) == 4024 CNVI_AUX_MISC_CHIP_PROD_TYPE_BZ_U) && 4025 step == SILICON_A_STEP) 4026 step = SILICON_B_STEP; 4027 } 4028 4029 if (CSR_HW_REV_TYPE(info->hw_rev) == IWL_CFG_MAC_TYPE_BZ || 4030 CSR_HW_REV_TYPE(info->hw_rev) == IWL_CFG_MAC_TYPE_BZ_W) { 4031 info->hw_rev_step = step; 4032 info->hw_rev |= step; 4033 } 4034 4035 /* Read cdb info (also contains the jacket info if needed in the future */ 4036 hw_wfpm_id = iwl_read_umac_prph_no_grab(iwl_trans, WFPM_OTP_CFG1_ADDR); 4037 4038 IWL_INFO(iwl_trans, "Detected crf-id 0x%x, cnv-id 0x%x wfpm id 0x%x\n", 4039 info->hw_crf_id, info->hw_cnv_id, hw_wfpm_id); 4040} 4041 4042/* 4043 * In case that there is no OTP on the NIC, map the rf id and cdb info 4044 * from the prph registers. 4045 */ 4046static int map_crf_id(struct iwl_trans *iwl_trans, 4047 struct iwl_trans_info *info) 4048{ 4049 int ret = 0; 4050 u32 val = info->hw_crf_id; 4051 u32 step_id = REG_CRF_ID_STEP(val); 4052 u32 slave_id = REG_CRF_ID_SLAVE(val); 4053 u32 hw_wfpm_id = iwl_read_umac_prph_no_grab(iwl_trans, 4054 WFPM_OTP_CFG1_ADDR); 4055 u32 cdb_id_wfpm = WFPM_OTP_CFG1_IS_CDB(hw_wfpm_id); 4056 4057 /* Map between crf id to rf id */ 4058 switch (REG_CRF_ID_TYPE(val)) { 4059 case REG_CRF_ID_TYPE_JF_1: 4060 info->hw_rf_id = (IWL_CFG_RF_TYPE_JF1 << 12); 4061 break; 4062 case REG_CRF_ID_TYPE_JF_2: 4063 info->hw_rf_id = (IWL_CFG_RF_TYPE_JF2 << 12); 4064 break; 4065 case REG_CRF_ID_TYPE_HR_NONE_CDB_1X1: 4066 info->hw_rf_id = (IWL_CFG_RF_TYPE_HR1 << 12); 4067 break; 4068 case REG_CRF_ID_TYPE_HR_NONE_CDB: 4069 info->hw_rf_id = (IWL_CFG_RF_TYPE_HR2 << 12); 4070 break; 4071 case REG_CRF_ID_TYPE_HR_CDB: 4072 info->hw_rf_id = (IWL_CFG_RF_TYPE_HR2 << 12); 4073 break; 4074 case REG_CRF_ID_TYPE_GF: 4075 info->hw_rf_id = (IWL_CFG_RF_TYPE_GF << 12); 4076 break; 4077 case REG_CRF_ID_TYPE_FM: 4078 info->hw_rf_id = (IWL_CFG_RF_TYPE_FM << 12); 4079 break; 4080 case REG_CRF_ID_TYPE_WHP: 4081 info->hw_rf_id = (IWL_CFG_RF_TYPE_WH << 12); 4082 break; 4083 case REG_CRF_ID_TYPE_PE: 4084 info->hw_rf_id = (IWL_CFG_RF_TYPE_PE << 12); 4085 break; 4086 default: 4087 ret = -EIO; 4088 IWL_ERR(iwl_trans, 4089 "Can't find a correct rfid for crf id 0x%x\n", 4090 REG_CRF_ID_TYPE(val)); 4091 goto out; 4092 } 4093 4094 /* Set Step-id */ 4095 info->hw_rf_id |= (step_id << 8); 4096 4097 /* Set CDB capabilities */ 4098 if (cdb_id_wfpm || slave_id) { 4099 info->hw_rf_id += BIT(28); 4100 IWL_INFO(iwl_trans, "Adding cdb to rf id\n"); 4101 } 4102 4103 IWL_INFO(iwl_trans, 4104 "Detected rf-type 0x%x step-id 0x%x slave-id 0x%x from crf id 0x%x\n", 4105 REG_CRF_ID_TYPE(val), step_id, slave_id, info->hw_rf_id); 4106 IWL_INFO(iwl_trans, 4107 "Detected cdb-id 0x%x from wfpm id 0x%x\n", 4108 cdb_id_wfpm, hw_wfpm_id); 4109out: 4110 return ret; 4111} 4112 4113static void iwl_pcie_recheck_me_status(struct work_struct *wk) 4114{ 4115 struct iwl_trans_pcie *trans_pcie = container_of(wk, 4116 typeof(*trans_pcie), 4117 me_recheck_wk.work); 4118 u32 val; 4119 4120 val = iwl_read32(trans_pcie->trans, CSR_HW_IF_CONFIG_REG); 4121 trans_pcie->me_present = !!(val & CSR_HW_IF_CONFIG_REG_IAMT_UP); 4122} 4123 4124static void iwl_pcie_check_me_status(struct iwl_trans *trans) 4125{ 4126 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 4127 u32 val; 4128 4129 trans_pcie->me_present = -1; 4130 4131 INIT_DELAYED_WORK(&trans_pcie->me_recheck_wk, 4132 iwl_pcie_recheck_me_status); 4133 4134 /* we don't have a good way of determining this until BZ */ 4135 if (trans->mac_cfg->device_family < IWL_DEVICE_FAMILY_BZ) 4136 return; 4137 4138 val = iwl_read_prph(trans, CNVI_SCU_REG_FOR_ECO_1); 4139 if (val & CNVI_SCU_REG_FOR_ECO_1_WIAMT_KNOWN) { 4140 trans_pcie->me_present = 4141 !!(val & CNVI_SCU_REG_FOR_ECO_1_WIAMT_PRESENT); 4142 return; 4143 } 4144 4145 val = iwl_read32(trans, CSR_HW_IF_CONFIG_REG); 4146 if (val & (CSR_HW_IF_CONFIG_REG_ME_OWN | 4147 CSR_HW_IF_CONFIG_REG_IAMT_UP)) { 4148 trans_pcie->me_present = 1; 4149 return; 4150 } 4151 4152 /* recheck again later, ME might still be initializing */ 4153 schedule_delayed_work(&trans_pcie->me_recheck_wk, HZ); 4154} 4155 4156int iwl_pci_gen1_2_probe(struct pci_dev *pdev, 4157 const struct pci_device_id *ent, 4158 const struct iwl_mac_cfg *mac_cfg, 4159 u8 __iomem *hw_base, u32 hw_rev) 4160{ 4161 const struct iwl_dev_info *dev_info; 4162 struct iwl_trans_info info = { 4163 .hw_id = (pdev->device << 16) + pdev->subsystem_device, 4164 .hw_rev = hw_rev, 4165 }; 4166 struct iwl_trans *iwl_trans; 4167 struct iwl_trans_pcie *trans_pcie; 4168 int ret; 4169 4170 iwl_trans = iwl_trans_pcie_alloc(pdev, mac_cfg, &info, hw_base); 4171 if (IS_ERR(iwl_trans)) 4172 return PTR_ERR(iwl_trans); 4173 4174 trans_pcie = IWL_TRANS_GET_PCIE_TRANS(iwl_trans); 4175 4176 iwl_trans_pcie_check_product_reset_status(pdev); 4177 iwl_trans_pcie_check_product_reset_mode(pdev); 4178 4179 /* set the things we know so far for the grab NIC access */ 4180 iwl_trans_set_info(iwl_trans, &info); 4181 4182 /* 4183 * Let's try to grab NIC access early here. Sometimes, NICs may 4184 * fail to initialize, and if that happens it's better if we see 4185 * issues early on (and can reprobe, per the logic inside), than 4186 * first trying to load the firmware etc. and potentially only 4187 * detecting any problems when the first interface is brought up. 4188 */ 4189 ret = iwl_pcie_prepare_card_hw(iwl_trans); 4190 if (!ret) { 4191 ret = iwl_trans_activate_nic(iwl_trans); 4192 if (ret) 4193 goto out_free_trans; 4194 if (iwl_trans_grab_nic_access(iwl_trans)) { 4195 get_crf_id(iwl_trans, &info); 4196 /* all good */ 4197 iwl_trans_release_nic_access(iwl_trans); 4198 } else { 4199 ret = -EIO; 4200 goto out_free_trans; 4201 } 4202 } 4203 4204 info.hw_rf_id = iwl_read32(iwl_trans, CSR_HW_RF_ID); 4205 4206 /* 4207 * The RF_ID is set to zero in blank OTP so read version to 4208 * extract the RF_ID. 4209 * This is relevant only for family 9000 and up. 4210 */ 4211 if (iwl_trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_9000 && 4212 !CSR_HW_RFID_TYPE(info.hw_rf_id) && map_crf_id(iwl_trans, &info)) { 4213 ret = -EINVAL; 4214 goto out_free_trans; 4215 } 4216 4217 IWL_INFO(iwl_trans, "PCI dev %04x/%04x, rev=0x%x, rfid=0x%x\n", 4218 pdev->device, pdev->subsystem_device, 4219 info.hw_rev, info.hw_rf_id); 4220 4221#if !IS_ENABLED(CONFIG_IWLMLD) 4222 if (iwl_drv_is_wifi7_supported(iwl_trans)) { 4223 IWL_ERR(iwl_trans, 4224 "IWLMLD needs to be compiled to support this device\n"); 4225 ret = -EOPNOTSUPP; 4226 goto out_free_trans; 4227 } 4228#endif 4229 4230 dev_info = iwl_pci_find_dev_info(pdev->device, pdev->subsystem_device, 4231 CSR_HW_RFID_TYPE(info.hw_rf_id), 4232 CSR_HW_RFID_IS_CDB(info.hw_rf_id), 4233 IWL_SUBDEVICE_RF_ID(pdev->subsystem_device), 4234 IWL_SUBDEVICE_BW_LIM(pdev->subsystem_device), 4235 !iwl_trans->mac_cfg->integrated); 4236 if (dev_info) { 4237 iwl_trans->cfg = dev_info->cfg; 4238 info.name = dev_info->name; 4239 } 4240 4241#if IS_ENABLED(CONFIG_IWLMVM) 4242 4243 /* 4244 * special-case 7265D, it has the same PCI IDs. 4245 * 4246 * Note that because we already pass the cfg to the transport above, 4247 * all the parameters that the transport uses must, until that is 4248 * changed, be identical to the ones in the 7265D configuration. 4249 */ 4250 if (iwl_trans->cfg == &iwl7265_cfg && 4251 (info.hw_rev & CSR_HW_REV_TYPE_MSK) == CSR_HW_REV_TYPE_7265D) 4252 iwl_trans->cfg = &iwl7265d_cfg; 4253#endif 4254 if (!iwl_trans->cfg) { 4255 pr_err("No config found for PCI dev %04x/%04x, rev=0x%x, rfid=0x%x\n", 4256 pdev->device, pdev->subsystem_device, 4257 info.hw_rev, info.hw_rf_id); 4258 ret = -EINVAL; 4259 goto out_free_trans; 4260 } 4261 4262 IWL_INFO(iwl_trans, "Detected %s\n", info.name); 4263 4264 if (iwl_trans->mac_cfg->mq_rx_supported) { 4265 if (WARN_ON(!iwl_trans->cfg->num_rbds)) { 4266 ret = -EINVAL; 4267 goto out_free_trans; 4268 } 4269 trans_pcie->num_rx_bufs = iwl_trans_get_num_rbds(iwl_trans); 4270 } else { 4271 trans_pcie->num_rx_bufs = RX_QUEUE_SIZE; 4272 } 4273 4274 if (!iwl_trans->mac_cfg->integrated) { 4275 u16 link_status; 4276 4277 pcie_capability_read_word(pdev, PCI_EXP_LNKSTA, &link_status); 4278 4279 info.pcie_link_speed = 4280 u16_get_bits(link_status, PCI_EXP_LNKSTA_CLS); 4281 } 4282 4283 iwl_trans_set_info(iwl_trans, &info); 4284 4285 pci_set_drvdata(pdev, iwl_trans); 4286 4287 iwl_pcie_check_me_status(iwl_trans); 4288 4289 /* try to get ownership so that we'll know if we don't own it */ 4290 iwl_pcie_prepare_card_hw(iwl_trans); 4291 4292 iwl_trans->drv = iwl_drv_start(iwl_trans); 4293 4294 if (IS_ERR(iwl_trans->drv)) { 4295 ret = PTR_ERR(iwl_trans->drv); 4296 goto out_free_trans; 4297 } 4298 4299 /* register transport layer debugfs here */ 4300 iwl_trans_pcie_dbgfs_register(iwl_trans); 4301 4302 return 0; 4303 4304out_free_trans: 4305 iwl_trans_pcie_free(iwl_trans); 4306 return ret; 4307} 4308 4309void iwl_pcie_gen1_2_remove(struct iwl_trans *trans) 4310{ 4311 struct iwl_trans_pcie *trans_pcie = IWL_TRANS_GET_PCIE_TRANS(trans); 4312 4313 cancel_delayed_work_sync(&trans_pcie->me_recheck_wk); 4314 4315 iwl_drv_stop(trans->drv); 4316 4317 iwl_trans_pcie_free(trans); 4318} 4319 4320int iwl_pcie_gen1_2_activate_nic(struct iwl_trans *trans) 4321{ 4322 const struct iwl_mac_cfg *mac_cfg = trans->mac_cfg; 4323 u32 poll_ready; 4324 int err; 4325 4326 if (mac_cfg->bisr_workaround) { 4327 /* ensure the TOP FSM isn't still in previous reset */ 4328 mdelay(2); 4329 } 4330 4331 /* 4332 * Set "initialization complete" bit to move adapter from 4333 * D0U* --> D0A* (powered-up active) state. 4334 */ 4335 if (mac_cfg->device_family >= IWL_DEVICE_FAMILY_BZ) { 4336 iwl_set_bit(trans, CSR_GP_CNTRL, 4337 CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ | 4338 CSR_GP_CNTRL_REG_FLAG_MAC_INIT); 4339 poll_ready = CSR_GP_CNTRL_REG_FLAG_MAC_STATUS; 4340 } else { 4341 iwl_set_bit(trans, CSR_GP_CNTRL, 4342 CSR_GP_CNTRL_REG_FLAG_INIT_DONE); 4343 poll_ready = CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY; 4344 } 4345 4346 if (mac_cfg->device_family == IWL_DEVICE_FAMILY_8000) 4347 udelay(2); 4348 4349 /* 4350 * Wait for clock stabilization; once stabilized, access to 4351 * device-internal resources is supported, e.g. iwl_write_prph() 4352 * and accesses to uCode SRAM. 4353 */ 4354 err = iwl_poll_bits(trans, CSR_GP_CNTRL, poll_ready, 25000); 4355 if (err < 0) { 4356 IWL_DEBUG_INFO(trans, "Failed to wake NIC\n"); 4357 4358 iwl_pcie_dump_host_monitor(trans); 4359 } 4360 4361 if (mac_cfg->bisr_workaround) { 4362 /* ensure BISR shift has finished */ 4363 udelay(200); 4364 } 4365 4366 return err; 4367}
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