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iwl-trans.h
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linux-6.19.14/drivers/net/wireless/intel/iwlwifi/iwl-trans.h
1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */ 2/* 3 * Copyright (C) 2005-2014, 2018-2025 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2016-2017 Intel Deutschland GmbH 6 */ 7#ifndef __iwl_trans_h__ 8#define __iwl_trans_h__ 9 10#include <linux/ieee80211.h> 11#include <linux/mm.h> /* for page_address */ 12#include <linux/lockdep.h> 13#include <linux/kernel.h> 14 15#include "iwl-debug.h" 16#include "iwl-config.h" 17#include "fw/img.h" 18#include "iwl-op-mode.h" 19#include <linux/firmware.h> 20#include "fw/api/cmdhdr.h" 21#include "fw/api/txq.h" 22#include "fw/api/dbg-tlv.h" 23#include "iwl-dbg-tlv.h" 24 25/** 26 * DOC: Transport layer - what is it ? 27 * 28 * The transport layer is the layer that deals with the HW directly. It provides 29 * the PCIe access to the underlying hardwarwe. The transport layer doesn't 30 * provide any policy, algorithm or anything of this kind, but only mechanisms 31 * to make the HW do something. It is not completely stateless but close to it. 32 */ 33 34/** 35 * DOC: Life cycle of the transport layer 36 * 37 * The transport layer has a very precise life cycle. 38 * 39 * 1) A helper function is called during the module initialization and 40 * registers the bus driver's ops with the transport's alloc function. 41 * 2) Bus's probe calls to the transport layer's allocation functions. 42 * Of course this function is bus specific. 43 * 3) This allocation functions will spawn the upper layer which will 44 * register mac80211. 45 * 46 * 4) At some point (i.e. mac80211's start call), the op_mode will call 47 * the following sequence: 48 * start_hw 49 * start_fw 50 * 51 * 5) Then when finished (or reset): 52 * stop_device 53 * 54 * 6) Eventually, the free function will be called. 55 */ 56 57/* default preset 0 (start from bit 16)*/ 58#define IWL_FW_DBG_DOMAIN_POS 16 59#define IWL_FW_DBG_DOMAIN BIT(IWL_FW_DBG_DOMAIN_POS) 60 61#define IWL_TRANS_FW_DBG_DOMAIN(trans) IWL_FW_INI_DOMAIN_ALWAYS_ON 62 63#define FH_RSCSR_FRAME_SIZE_MSK 0x00003FFF /* bits 0-13 */ 64#define FH_RSCSR_FRAME_INVALID 0x55550000 65#define FH_RSCSR_FRAME_ALIGN 0x40 66#define FH_RSCSR_RPA_EN BIT(25) 67#define FH_RSCSR_RADA_EN BIT(26) 68#define FH_RSCSR_RXQ_POS 16 69#define FH_RSCSR_RXQ_MASK 0x3F0000 70 71struct iwl_rx_packet { 72 /* 73 * The first 4 bytes of the RX frame header contain both the RX frame 74 * size and some flags. 75 * Bit fields: 76 * 31: flag flush RB request 77 * 30: flag ignore TC (terminal counter) request 78 * 29: flag fast IRQ request 79 * 28-27: Reserved 80 * 26: RADA enabled 81 * 25: Offload enabled 82 * 24: RPF enabled 83 * 23: RSS enabled 84 * 22: Checksum enabled 85 * 21-16: RX queue 86 * 15-14: Reserved 87 * 13-00: RX frame size 88 */ 89 __le32 len_n_flags; 90 struct iwl_cmd_header hdr; 91 u8 data[]; 92} __packed; 93 94static inline u32 iwl_rx_packet_len(const struct iwl_rx_packet *pkt) 95{ 96 return le32_to_cpu(pkt->len_n_flags) & FH_RSCSR_FRAME_SIZE_MSK; 97} 98 99static inline u32 iwl_rx_packet_payload_len(const struct iwl_rx_packet *pkt) 100{ 101 return iwl_rx_packet_len(pkt) - sizeof(pkt->hdr); 102} 103 104/** 105 * enum CMD_MODE - how to send the host commands ? 106 * 107 * @CMD_ASYNC: Return right away and don't wait for the response 108 * @CMD_WANT_SKB: Not valid with CMD_ASYNC. The caller needs the buffer of 109 * the response. The caller needs to call iwl_free_resp when done. 110 * @CMD_SEND_IN_RFKILL: Send the command even if the NIC is in RF-kill. 111 * @CMD_BLOCK_TXQS: Block TXQs while the comment is executing. 112 */ 113enum CMD_MODE { 114 CMD_ASYNC = BIT(0), 115 CMD_WANT_SKB = BIT(1), 116 CMD_SEND_IN_RFKILL = BIT(2), 117 CMD_BLOCK_TXQS = BIT(3), 118}; 119#define CMD_MODE_BITS 5 120 121#define DEF_CMD_PAYLOAD_SIZE 320 122 123/** 124 * struct iwl_device_cmd - device command structure 125 * 126 * For allocation of the command and tx queues, this establishes the overall 127 * size of the largest command we send to uCode, except for commands that 128 * aren't fully copied and use other TFD space. 129 * 130 * @hdr: command header 131 * @payload: payload for the command 132 * @hdr_wide: wide command header 133 * @payload_wide: payload for the wide command 134 */ 135struct iwl_device_cmd { 136 union { 137 struct { 138 struct iwl_cmd_header hdr; /* uCode API */ 139 u8 payload[DEF_CMD_PAYLOAD_SIZE]; 140 }; 141 struct { 142 struct iwl_cmd_header_wide hdr_wide; 143 u8 payload_wide[DEF_CMD_PAYLOAD_SIZE - 144 sizeof(struct iwl_cmd_header_wide) + 145 sizeof(struct iwl_cmd_header)]; 146 }; 147 }; 148} __packed; 149 150/** 151 * struct iwl_device_tx_cmd - buffer for TX command 152 * @hdr: the header 153 * @payload: the payload placeholder 154 * 155 * The actual structure is sized dynamically according to need. 156 */ 157struct iwl_device_tx_cmd { 158 struct iwl_cmd_header hdr; 159 u8 payload[]; 160} __packed; 161 162#define TFD_MAX_PAYLOAD_SIZE (sizeof(struct iwl_device_cmd)) 163 164/* 165 * number of transfer buffers (fragments) per transmit frame descriptor; 166 * this is just the driver's idea, the hardware supports 20 167 */ 168#define IWL_MAX_CMD_TBS_PER_TFD 2 169 170/** 171 * enum iwl_hcmd_dataflag - flag for each one of the chunks of the command 172 * 173 * @IWL_HCMD_DFL_NOCOPY: By default, the command is copied to the host command's 174 * ring. The transport layer doesn't map the command's buffer to DMA, but 175 * rather copies it to a previously allocated DMA buffer. This flag tells 176 * the transport layer not to copy the command, but to map the existing 177 * buffer (that is passed in) instead. This saves the memcpy and allows 178 * commands that are bigger than the fixed buffer to be submitted. 179 * Note that a TFD entry after a NOCOPY one cannot be a normal copied one. 180 * @IWL_HCMD_DFL_DUP: Only valid without NOCOPY, duplicate the memory for this 181 * chunk internally and free it again after the command completes. This 182 * can (currently) be used only once per command. 183 * Note that a TFD entry after a DUP one cannot be a normal copied one. 184 */ 185enum iwl_hcmd_dataflag { 186 IWL_HCMD_DFL_NOCOPY = BIT(0), 187 IWL_HCMD_DFL_DUP = BIT(1), 188}; 189 190enum iwl_error_event_table_status { 191 IWL_ERROR_EVENT_TABLE_LMAC1 = BIT(0), 192 IWL_ERROR_EVENT_TABLE_LMAC2 = BIT(1), 193 IWL_ERROR_EVENT_TABLE_UMAC = BIT(2), 194 IWL_ERROR_EVENT_TABLE_TCM1 = BIT(3), 195 IWL_ERROR_EVENT_TABLE_TCM2 = BIT(4), 196 IWL_ERROR_EVENT_TABLE_RCM1 = BIT(5), 197 IWL_ERROR_EVENT_TABLE_RCM2 = BIT(6), 198}; 199 200/** 201 * struct iwl_host_cmd - Host command to the uCode 202 * 203 * @data: array of chunks that composes the data of the host command 204 * @resp_pkt: response packet, if %CMD_WANT_SKB was set 205 * @_rx_page_order: (internally used to free response packet) 206 * @_rx_page_addr: (internally used to free response packet) 207 * @flags: can be CMD_* 208 * @len: array of the lengths of the chunks in data 209 * @dataflags: IWL_HCMD_DFL_* 210 * @id: command id of the host command, for wide commands encoding the 211 * version and group as well 212 */ 213struct iwl_host_cmd { 214 const void *data[IWL_MAX_CMD_TBS_PER_TFD]; 215 struct iwl_rx_packet *resp_pkt; 216 unsigned long _rx_page_addr; 217 u32 _rx_page_order; 218 219 u32 flags; 220 u32 id; 221 u16 len[IWL_MAX_CMD_TBS_PER_TFD]; 222 u8 dataflags[IWL_MAX_CMD_TBS_PER_TFD]; 223}; 224 225static inline void iwl_free_resp(struct iwl_host_cmd *cmd) 226{ 227 free_pages(cmd->_rx_page_addr, cmd->_rx_page_order); 228} 229 230struct iwl_rx_cmd_buffer { 231 struct page *_page; 232 int _offset; 233 bool _page_stolen; 234 u32 _rx_page_order; 235 unsigned int truesize; 236}; 237 238static inline void *rxb_addr(struct iwl_rx_cmd_buffer *r) 239{ 240 return (void *)((unsigned long)page_address(r->_page) + r->_offset); 241} 242 243static inline int rxb_offset(struct iwl_rx_cmd_buffer *r) 244{ 245 return r->_offset; 246} 247 248static inline struct page *rxb_steal_page(struct iwl_rx_cmd_buffer *r) 249{ 250 r->_page_stolen = true; 251 get_page(r->_page); 252 return r->_page; 253} 254 255static inline void iwl_free_rxb(struct iwl_rx_cmd_buffer *r) 256{ 257 __free_pages(r->_page, r->_rx_page_order); 258} 259 260#define MAX_NO_RECLAIM_CMDS 6 261 262#define IWL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) 263 264/* 265 * Maximum number of HW queues the transport layer 266 * currently supports 267 */ 268#define IWL_MAX_HW_QUEUES 32 269#define IWL_MAX_TVQM_QUEUES 512 270 271#define IWL_MAX_TID_COUNT 8 272#define IWL_MGMT_TID 15 273#define IWL_FRAME_LIMIT 64 274#define IWL_MAX_RX_HW_QUEUES 16 275#define IWL_9000_MAX_RX_HW_QUEUES 1 276 277/** 278 * enum iwl_trans_status: transport status flags 279 * @STATUS_SYNC_HCMD_ACTIVE: a SYNC command is being processed 280 * @STATUS_DEVICE_ENABLED: APM is enabled 281 * @STATUS_TPOWER_PMI: the device might be asleep (need to wake it up) 282 * @STATUS_INT_ENABLED: interrupts are enabled 283 * @STATUS_RFKILL_HW: the actual HW state of the RF-kill switch 284 * @STATUS_RFKILL_OPMODE: RF-kill state reported to opmode 285 * @STATUS_FW_ERROR: the fw is in error state 286 * @STATUS_TRANS_DEAD: trans is dead - avoid any read/write operation 287 * @STATUS_IN_SW_RESET: device is undergoing reset, cleared by opmode 288 * via iwl_trans_finish_sw_reset() 289 * @STATUS_RESET_PENDING: reset worker was scheduled, but didn't dump 290 * the firmware state yet 291 * @STATUS_TRANS_RESET_IN_PROGRESS: reset is still in progress, don't 292 * attempt another reset yet 293 */ 294enum iwl_trans_status { 295 STATUS_SYNC_HCMD_ACTIVE, 296 STATUS_DEVICE_ENABLED, 297 STATUS_TPOWER_PMI, 298 STATUS_INT_ENABLED, 299 STATUS_RFKILL_HW, 300 STATUS_RFKILL_OPMODE, 301 STATUS_FW_ERROR, 302 STATUS_TRANS_DEAD, 303 STATUS_IN_SW_RESET, 304 STATUS_RESET_PENDING, 305 STATUS_TRANS_RESET_IN_PROGRESS, 306}; 307 308static inline int 309iwl_trans_get_rb_size_order(enum iwl_amsdu_size rb_size) 310{ 311 switch (rb_size) { 312 case IWL_AMSDU_2K: 313 return get_order(2 * 1024); 314 case IWL_AMSDU_4K: 315 return get_order(4 * 1024); 316 case IWL_AMSDU_8K: 317 return get_order(8 * 1024); 318 case IWL_AMSDU_12K: 319 return get_order(16 * 1024); 320 default: 321 WARN_ON(1); 322 return -1; 323 } 324} 325 326static inline int 327iwl_trans_get_rb_size(enum iwl_amsdu_size rb_size) 328{ 329 switch (rb_size) { 330 case IWL_AMSDU_2K: 331 return 2 * 1024; 332 case IWL_AMSDU_4K: 333 return 4 * 1024; 334 case IWL_AMSDU_8K: 335 return 8 * 1024; 336 case IWL_AMSDU_12K: 337 return 16 * 1024; 338 default: 339 WARN_ON(1); 340 return 0; 341 } 342} 343 344struct iwl_hcmd_names { 345 u8 cmd_id; 346 const char *const cmd_name; 347}; 348 349#define HCMD_NAME(x) \ 350 { .cmd_id = x, .cmd_name = #x } 351 352struct iwl_hcmd_arr { 353 const struct iwl_hcmd_names *arr; 354 int size; 355}; 356 357#define HCMD_ARR(x) \ 358 { .arr = x, .size = ARRAY_SIZE(x) } 359 360/** 361 * struct iwl_dump_sanitize_ops - dump sanitization operations 362 * @frob_txf: Scrub the TX FIFO data 363 * @frob_hcmd: Scrub a host command, the %hcmd pointer is to the header 364 * but that might be short or long (&struct iwl_cmd_header or 365 * &struct iwl_cmd_header_wide) 366 * @frob_mem: Scrub memory data 367 */ 368struct iwl_dump_sanitize_ops { 369 void (*frob_txf)(void *ctx, void *buf, size_t buflen); 370 void (*frob_hcmd)(void *ctx, void *hcmd, size_t buflen); 371 void (*frob_mem)(void *ctx, u32 mem_addr, void *mem, size_t buflen); 372}; 373 374/** 375 * struct iwl_trans_config - transport configuration 376 * 377 * These values should be set before iwl_trans_op_mode_enter(). 378 * 379 * @cmd_queue: the index of the command queue. 380 * Must be set before start_fw. 381 * @cmd_fifo: the fifo for host commands 382 * @no_reclaim_cmds: Some devices erroneously don't set the 383 * SEQ_RX_FRAME bit on some notifications, this is the 384 * list of such notifications to filter. Max length is 385 * %MAX_NO_RECLAIM_CMDS. 386 * @n_no_reclaim_cmds: # of commands in list 387 * @rx_buf_size: RX buffer size needed for A-MSDUs 388 * if unset 4k will be the RX buffer size 389 * @scd_set_active: should the transport configure the SCD for HCMD queue 390 * @command_groups: array of command groups, each member is an array of the 391 * commands in the group; for debugging only 392 * @command_groups_size: number of command groups, to avoid illegal access 393 * @cb_data_offs: offset inside skb->cb to store transport data at, must have 394 * space for at least two pointers 395 * @fw_reset_handshake: firmware supports reset flow handshake 396 * @queue_alloc_cmd_ver: queue allocation command version, set to 0 397 * for using the older SCD_QUEUE_CFG, set to the version of 398 * SCD_QUEUE_CONFIG_CMD otherwise. 399 * @wide_cmd_header: true when ucode supports wide command header format 400 * @rx_mpdu_cmd: MPDU RX command ID, must be assigned by opmode before 401 * starting the firmware, used for tracing 402 * @rx_mpdu_cmd_hdr_size: used for tracing, amount of data before the 403 * start of the 802.11 header in the @rx_mpdu_cmd 404 * @dsbr_urm_fw_dependent: switch to URM based on fw settings 405 * @dsbr_urm_permanent: switch to URM permanently 406 * @mbx_addr_0_step: step address data 0 407 * @mbx_addr_1_step: step address data 1 408 * @ext_32khz_clock_valid: if true, the external 32 KHz clock can be used 409 */ 410struct iwl_trans_config { 411 u8 cmd_queue; 412 u8 cmd_fifo; 413 u8 n_no_reclaim_cmds; 414 u8 no_reclaim_cmds[MAX_NO_RECLAIM_CMDS]; 415 416 enum iwl_amsdu_size rx_buf_size; 417 bool scd_set_active; 418 const struct iwl_hcmd_arr *command_groups; 419 int command_groups_size; 420 421 u8 cb_data_offs; 422 bool fw_reset_handshake; 423 u8 queue_alloc_cmd_ver; 424 425 bool wide_cmd_header; 426 u8 rx_mpdu_cmd, rx_mpdu_cmd_hdr_size; 427 428 u8 dsbr_urm_fw_dependent:1, 429 dsbr_urm_permanent:1, 430 ext_32khz_clock_valid:1; 431 432 u32 mbx_addr_0_step; 433 u32 mbx_addr_1_step; 434}; 435 436struct iwl_trans_dump_data { 437 u32 len; 438 u8 data[]; 439}; 440 441struct iwl_trans; 442 443struct iwl_trans_txq_scd_cfg { 444 u8 fifo; 445 u8 sta_id; 446 u8 tid; 447 bool aggregate; 448 int frame_limit; 449}; 450 451/** 452 * struct iwl_trans_rxq_dma_data - RX queue DMA data 453 * @fr_bd_cb: DMA address of free BD cyclic buffer 454 * @fr_bd_wid: Initial write index of the free BD cyclic buffer 455 * @urbd_stts_wrptr: DMA address of urbd_stts_wrptr 456 * @ur_bd_cb: DMA address of used BD cyclic buffer 457 */ 458struct iwl_trans_rxq_dma_data { 459 u64 fr_bd_cb; 460 u32 fr_bd_wid; 461 u64 urbd_stts_wrptr; 462 u64 ur_bd_cb; 463}; 464 465/* maximal number of DRAM MAP entries supported by FW */ 466#define IPC_DRAM_MAP_ENTRY_NUM_MAX 64 467 468/** 469 * struct iwl_pnvm_image - contains info about the parsed pnvm image 470 * @chunks: array of pointers to pnvm payloads and their sizes 471 * @n_chunks: the number of the pnvm payloads. 472 * @version: the version of the loaded PNVM image 473 */ 474struct iwl_pnvm_image { 475 struct { 476 const void *data; 477 u32 len; 478 } chunks[IPC_DRAM_MAP_ENTRY_NUM_MAX]; 479 u32 n_chunks; 480 u32 version; 481}; 482 483/** 484 * enum iwl_trans_state - state of the transport layer 485 * 486 * @IWL_TRANS_NO_FW: firmware wasn't started yet, or crashed 487 * @IWL_TRANS_FW_STARTED: FW was started, but not alive yet 488 * @IWL_TRANS_FW_ALIVE: FW has sent an alive response 489 */ 490enum iwl_trans_state { 491 IWL_TRANS_NO_FW, 492 IWL_TRANS_FW_STARTED, 493 IWL_TRANS_FW_ALIVE, 494}; 495 496/** 497 * DOC: Platform power management 498 * 499 * In system-wide power management the entire platform goes into a low 500 * power state (e.g. idle or suspend to RAM) at the same time and the 501 * device is configured as a wakeup source for the entire platform. 502 * This is usually triggered by userspace activity (e.g. the user 503 * presses the suspend button or a power management daemon decides to 504 * put the platform in low power mode). The device's behavior in this 505 * mode is dictated by the wake-on-WLAN configuration. 506 * 507 * The terms used for the device's behavior are as follows: 508 * 509 * - D0: the device is fully powered and the host is awake; 510 * - D3: the device is in low power mode and only reacts to 511 * specific events (e.g. magic-packet received or scan 512 * results found); 513 * 514 * These terms reflect the power modes in the firmware and are not to 515 * be confused with the physical device power state. 516 */ 517 518/** 519 * enum iwl_ini_cfg_state - debug config state 520 * @IWL_INI_CFG_STATE_NOT_LOADED: no debug cfg was given 521 * @IWL_INI_CFG_STATE_LOADED: debug cfg was found and loaded 522 * @IWL_INI_CFG_STATE_CORRUPTED: debug cfg was found and some of the TLVs 523 * are corrupted. The rest of the debug TLVs will still be used 524 */ 525enum iwl_ini_cfg_state { 526 IWL_INI_CFG_STATE_NOT_LOADED, 527 IWL_INI_CFG_STATE_LOADED, 528 IWL_INI_CFG_STATE_CORRUPTED, 529}; 530 531/* Max time to wait for nmi interrupt */ 532#define IWL_TRANS_NMI_TIMEOUT (HZ / 4) 533 534/** 535 * struct iwl_dram_data - DRAM data descriptor 536 * @physical: page phy pointer 537 * @block: pointer to the allocated block/page 538 * @size: size of the block/page 539 */ 540struct iwl_dram_data { 541 dma_addr_t physical; 542 void *block; 543 int size; 544}; 545 546/** 547 * struct iwl_dram_regions - DRAM regions container structure 548 * @drams: array of several DRAM areas that contains the pnvm and power 549 * reduction table payloads. 550 * @n_regions: number of DRAM regions that were allocated 551 * @prph_scratch_mem_desc: points to a structure allocated in dram, 552 * designed to show FW where all the payloads are. 553 */ 554struct iwl_dram_regions { 555 struct iwl_dram_data drams[IPC_DRAM_MAP_ENTRY_NUM_MAX]; 556 struct iwl_dram_data prph_scratch_mem_desc; 557 u8 n_regions; 558}; 559 560/** 561 * struct iwl_fw_mon - fw monitor per allocation id 562 * @num_frags: number of fragments 563 * @frags: an array of DRAM buffer fragments 564 */ 565struct iwl_fw_mon { 566 u32 num_frags; 567 struct iwl_dram_data *frags; 568}; 569 570/** 571 * struct iwl_self_init_dram - dram data used by self init process 572 * @fw: lmac and umac dram data 573 * @fw_cnt: total number of items in array 574 * @paging: paging dram data 575 * @paging_cnt: total number of items in array 576 */ 577struct iwl_self_init_dram { 578 struct iwl_dram_data *fw; 579 int fw_cnt; 580 struct iwl_dram_data *paging; 581 int paging_cnt; 582}; 583 584/** 585 * struct iwl_imr_data - imr dram data used during debug process 586 * @imr_enable: imr enable status received from fw 587 * @imr_size: imr dram size received from fw 588 * @sram_addr: sram address from debug tlv 589 * @sram_size: sram size from debug tlv 590 * @imr2sram_remainbyte: size remained after each dma transfer 591 * @imr_curr_addr: current dst address used during dma transfer 592 * @imr_base_addr: imr address received from fw 593 */ 594struct iwl_imr_data { 595 u32 imr_enable; 596 u32 imr_size; 597 u32 sram_addr; 598 u32 sram_size; 599 u32 imr2sram_remainbyte; 600 u64 imr_curr_addr; 601 __le64 imr_base_addr; 602}; 603 604#define IWL_TRANS_CURRENT_PC_NAME_MAX_BYTES 32 605 606/** 607 * struct iwl_pc_data - program counter details 608 * @pc_name: cpu name 609 * @pc_address: cpu program counter 610 */ 611struct iwl_pc_data { 612 u8 pc_name[IWL_TRANS_CURRENT_PC_NAME_MAX_BYTES]; 613 u32 pc_address; 614}; 615 616/** 617 * struct iwl_trans_debug - transport debug related data 618 * 619 * @n_dest_reg: num of reg_ops in %dbg_dest_tlv 620 * @rec_on: true iff there is a fw debug recording currently active 621 * @dest_tlv: points to the destination TLV for debug 622 * @lmac_error_event_table: addrs of lmacs error tables 623 * @umac_error_event_table: addr of umac error table 624 * @tcm_error_event_table: address(es) of TCM error table(s) 625 * @rcm_error_event_table: address(es) of RCM error table(s) 626 * @error_event_table_tlv_status: bitmap that indicates what error table 627 * pointers was recevied via TLV. uses enum &iwl_error_event_table_status 628 * @internal_ini_cfg: internal debug cfg state. Uses &enum iwl_ini_cfg_state 629 * @external_ini_cfg: external debug cfg state. Uses &enum iwl_ini_cfg_state 630 * @fw_mon_cfg: debug buffer allocation configuration 631 * @fw_mon_ini: DRAM buffer fragments per allocation id 632 * @fw_mon: DRAM buffer for firmware monitor 633 * @hw_error: equals true if hw error interrupt was received from the FW 634 * @ini_dest: debug monitor destination uses &enum iwl_fw_ini_buffer_location 635 * @unsupported_region_msk: unsupported regions out of active_regions 636 * @active_regions: active regions 637 * @debug_info_tlv_list: list of debug info TLVs 638 * @time_point: array of debug time points 639 * @periodic_trig_list: periodic triggers list 640 * @domains_bitmap: bitmap of active domains other than &IWL_FW_INI_DOMAIN_ALWAYS_ON 641 * @ucode_preset: preset based on ucode 642 * @restart_required: indicates debug restart is required 643 * @last_tp_resetfw: last handling of reset during debug timepoint 644 * @imr_data: IMR debug data allocation 645 * @num_pc: number of program counter for cpu 646 * @pc_data: details of the program counter 647 * @yoyo_bin_loaded: tells if a yoyo debug file has been loaded 648 */ 649struct iwl_trans_debug { 650 u8 n_dest_reg; 651 bool rec_on; 652 653 const struct iwl_fw_dbg_dest_tlv_v1 *dest_tlv; 654 655 u32 lmac_error_event_table[2]; 656 u32 umac_error_event_table; 657 u32 tcm_error_event_table[2]; 658 u32 rcm_error_event_table[2]; 659 unsigned int error_event_table_tlv_status; 660 661 enum iwl_ini_cfg_state internal_ini_cfg; 662 enum iwl_ini_cfg_state external_ini_cfg; 663 664 struct iwl_fw_ini_allocation_tlv fw_mon_cfg[IWL_FW_INI_ALLOCATION_NUM]; 665 struct iwl_fw_mon fw_mon_ini[IWL_FW_INI_ALLOCATION_NUM]; 666 667 struct iwl_dram_data fw_mon; 668 669 bool hw_error; 670 enum iwl_fw_ini_buffer_location ini_dest; 671 672 u64 unsupported_region_msk; 673 struct iwl_ucode_tlv *active_regions[IWL_FW_INI_MAX_REGION_ID]; 674 struct list_head debug_info_tlv_list; 675 struct iwl_dbg_tlv_time_point_data time_point[IWL_FW_INI_TIME_POINT_NUM]; 676 struct list_head periodic_trig_list; 677 678 u32 domains_bitmap; 679 u32 ucode_preset; 680 bool restart_required; 681 u32 last_tp_resetfw; 682 struct iwl_imr_data imr_data; 683 u32 num_pc; 684 struct iwl_pc_data *pc_data; 685 bool yoyo_bin_loaded; 686}; 687 688struct iwl_dma_ptr { 689 dma_addr_t dma; 690 void *addr; 691 size_t size; 692}; 693 694struct iwl_cmd_meta { 695 /* only for SYNC commands, iff the reply skb is wanted */ 696 struct iwl_host_cmd *source; 697 u32 flags: CMD_MODE_BITS; 698 /* sg_offset is valid if it is non-zero */ 699 u32 sg_offset: PAGE_SHIFT; 700 u32 tbs; 701}; 702 703/* 704 * The FH will write back to the first TB only, so we need to copy some data 705 * into the buffer regardless of whether it should be mapped or not. 706 * This indicates how big the first TB must be to include the scratch buffer 707 * and the assigned PN. 708 * Since PN location is 8 bytes at offset 12, it's 20 now. 709 * If we make it bigger then allocations will be bigger and copy slower, so 710 * that's probably not useful. 711 */ 712#define IWL_FIRST_TB_SIZE 20 713#define IWL_FIRST_TB_SIZE_ALIGN ALIGN(IWL_FIRST_TB_SIZE, 64) 714 715struct iwl_pcie_txq_entry { 716 void *cmd; 717 struct sk_buff *skb; 718 /* buffer to free after command completes */ 719 const void *free_buf; 720 struct iwl_cmd_meta meta; 721}; 722 723struct iwl_pcie_first_tb_buf { 724 u8 buf[IWL_FIRST_TB_SIZE_ALIGN]; 725}; 726 727/** 728 * struct iwl_txq - Tx Queue for DMA 729 * @tfds: transmit frame descriptors (DMA memory) 730 * @first_tb_bufs: start of command headers, including scratch buffers, for 731 * the writeback -- this is DMA memory and an array holding one buffer 732 * for each command on the queue 733 * @first_tb_dma: DMA address for the first_tb_bufs start 734 * @entries: transmit entries (driver state) 735 * @lock: queue lock 736 * @reclaim_lock: reclaim lock 737 * @stuck_timer: timer that fires if queue gets stuck 738 * @trans: pointer back to transport (for timer) 739 * @need_update: indicates need to update read/write index 740 * @ampdu: true if this queue is an ampdu queue for an specific RA/TID 741 * @wd_timeout: queue watchdog timeout (jiffies) - per queue 742 * @frozen: tx stuck queue timer is frozen 743 * @frozen_expiry_remainder: remember how long until the timer fires 744 * @block: queue is blocked 745 * @bc_tbl: byte count table of the queue (relevant only for gen2 transport) 746 * @write_ptr: 1-st empty entry (index) host_w 747 * @read_ptr: last used entry (index) host_r 748 * @dma_addr: physical addr for BD's 749 * @n_window: safe queue window 750 * @id: queue id 751 * @low_mark: low watermark, resume queue if free space more than this 752 * @high_mark: high watermark, stop queue if free space less than this 753 * @overflow_q: overflow queue for handling frames that didn't fit on HW queue 754 * @overflow_tx: need to transmit from overflow 755 * 756 * A Tx queue consists of circular buffer of BDs (a.k.a. TFDs, transmit frame 757 * descriptors) and required locking structures. 758 * 759 * Note the difference between TFD_QUEUE_SIZE_MAX and n_window: the hardware 760 * always assumes 256 descriptors, so TFD_QUEUE_SIZE_MAX is always 256 (unless 761 * there might be HW changes in the future). For the normal TX 762 * queues, n_window, which is the size of the software queue data 763 * is also 256; however, for the command queue, n_window is only 764 * 32 since we don't need so many commands pending. Since the HW 765 * still uses 256 BDs for DMA though, TFD_QUEUE_SIZE_MAX stays 256. 766 * This means that we end up with the following: 767 * HW entries: | 0 | ... | N * 32 | ... | N * 32 + 31 | ... | 255 | 768 * SW entries: | 0 | ... | 31 | 769 * where N is a number between 0 and 7. This means that the SW 770 * data is a window overlayed over the HW queue. 771 */ 772struct iwl_txq { 773 void *tfds; 774 struct iwl_pcie_first_tb_buf *first_tb_bufs; 775 dma_addr_t first_tb_dma; 776 struct iwl_pcie_txq_entry *entries; 777 /* lock for syncing changes on the queue */ 778 spinlock_t lock; 779 /* lock to prevent concurrent reclaim */ 780 spinlock_t reclaim_lock; 781 unsigned long frozen_expiry_remainder; 782 struct timer_list stuck_timer; 783 struct iwl_trans *trans; 784 bool need_update; 785 bool frozen; 786 bool ampdu; 787 int block; 788 unsigned long wd_timeout; 789 struct sk_buff_head overflow_q; 790 struct iwl_dma_ptr bc_tbl; 791 792 int write_ptr; 793 int read_ptr; 794 dma_addr_t dma_addr; 795 int n_window; 796 u32 id; 797 int low_mark; 798 int high_mark; 799 800 bool overflow_tx; 801}; 802 803/** 804 * struct iwl_trans_info - transport info for outside use 805 * @name: the device name 806 * @max_skb_frags: maximum number of fragments an SKB can have when transmitted. 807 * 0 indicates that frag SKBs (NETIF_F_SG) aren't supported. 808 * @hw_rev: the revision data of the HW 809 * @hw_rev_step: The mac step of the HW 810 * @hw_rf_id: the device RF ID 811 * @hw_cnv_id: the device CNV ID 812 * @hw_crf_id: the device CRF ID 813 * @hw_id: the ID of the device / sub-device 814 * Bits 0:15 represent the sub-device ID 815 * Bits 16:31 represent the device ID. 816 * @pcie_link_speed: current PCIe link speed (%PCI_EXP_LNKSTA_CLS_*), 817 * only valid for discrete (not integrated) NICs 818 * @num_rxqs: number of RX queues allocated by the transport 819 */ 820struct iwl_trans_info { 821 const char *name; 822 u32 max_skb_frags; 823 u32 hw_rev; 824 u32 hw_rev_step; 825 u32 hw_rf_id; 826 u32 hw_crf_id; 827 u32 hw_cnv_id; 828 u32 hw_id; 829 u8 pcie_link_speed; 830 u8 num_rxqs; 831}; 832 833/** 834 * struct iwl_trans - transport common data 835 * 836 * @csme_own: true if we couldn't get ownership on the device 837 * @op_mode: pointer to the op_mode 838 * @mac_cfg: the trans-specific configuration part 839 * @cfg: pointer to the configuration 840 * @drv: pointer to iwl_drv 841 * @conf: configuration set by the opmode before enter 842 * @state: current device state 843 * @status: a bit-mask of transport status flags 844 * @dev: pointer to struct device * that represents the device 845 * @info: device information for use by other layers 846 * @pnvm_loaded: indicates PNVM was loaded 847 * @suppress_cmd_error_once: suppress "FW error in SYNC CMD" once, 848 * e.g. for testing 849 * @fail_to_parse_pnvm_image: set to true if pnvm parsing failed 850 * @reduce_power_loaded: indicates reduced power section was loaded 851 * @failed_to_load_reduce_power_image: set to true if pnvm loading failed 852 * @dbgfs_dir: iwlwifi debugfs base dir for this device 853 * @sync_cmd_lockdep_map: lockdep map for checking sync commands 854 * @dbg: additional debug data, see &struct iwl_trans_debug 855 * @init_dram: FW initialization DMA data 856 * @reduced_cap_sku: reduced capability supported SKU 857 * @step_urm: STEP is in URM, no support for MCS>9 in 320 MHz 858 * @restart: restart worker data 859 * @restart.wk: restart worker 860 * @restart.mode: reset/restart error mode information 861 * @restart.during_reset: error occurred during previous software reset 862 * @trans_specific: data for the specific transport this is allocated for/with 863 * @request_top_reset: TOP reset was requested, used by the reset 864 * worker that should be scheduled (with appropriate reason) 865 * @do_top_reset: indication to the (PCIe) transport/context-info 866 * to do the TOP reset 867 */ 868struct iwl_trans { 869 bool csme_own; 870 struct iwl_op_mode *op_mode; 871 const struct iwl_mac_cfg *mac_cfg; 872 const struct iwl_rf_cfg *cfg; 873 struct iwl_drv *drv; 874 struct iwl_trans_config conf; 875 enum iwl_trans_state state; 876 unsigned long status; 877 878 struct device *dev; 879 880 const struct iwl_trans_info info; 881 bool reduced_cap_sku; 882 bool step_urm; 883 bool suppress_cmd_error_once; 884 885 u8 pnvm_loaded:1; 886 u8 fail_to_parse_pnvm_image:1; 887 u8 reduce_power_loaded:1; 888 u8 failed_to_load_reduce_power_image:1; 889 890 struct dentry *dbgfs_dir; 891 892#ifdef CONFIG_LOCKDEP 893 struct lockdep_map sync_cmd_lockdep_map; 894#endif 895 896 struct iwl_trans_debug dbg; 897 struct iwl_self_init_dram init_dram; 898 899 struct { 900 struct delayed_work wk; 901 struct iwl_fw_error_dump_mode mode; 902 bool during_reset; 903 } restart; 904 905 u8 request_top_reset:1, 906 do_top_reset:1; 907 908 /* pointer to trans specific struct */ 909 /*Ensure that this pointer will always be aligned to sizeof pointer */ 910 char trans_specific[] __aligned(sizeof(void *)); 911}; 912 913const char *iwl_get_cmd_string(struct iwl_trans *trans, u32 id); 914 915void iwl_trans_op_mode_enter(struct iwl_trans *trans, 916 struct iwl_op_mode *op_mode); 917 918int iwl_trans_start_hw(struct iwl_trans *trans); 919 920void iwl_trans_op_mode_leave(struct iwl_trans *trans); 921 922void iwl_trans_fw_alive(struct iwl_trans *trans); 923 924int iwl_trans_start_fw(struct iwl_trans *trans, const struct iwl_fw *fw, 925 enum iwl_ucode_type ucode_type, bool run_in_rfkill); 926 927void iwl_trans_stop_device(struct iwl_trans *trans); 928 929int iwl_trans_d3_suspend(struct iwl_trans *trans, bool reset); 930 931int iwl_trans_d3_resume(struct iwl_trans *trans, bool reset); 932 933struct iwl_trans_dump_data * 934iwl_trans_dump_data(struct iwl_trans *trans, u32 dump_mask, 935 const struct iwl_dump_sanitize_ops *sanitize_ops, 936 void *sanitize_ctx); 937 938struct iwl_device_tx_cmd *iwl_trans_alloc_tx_cmd(struct iwl_trans *trans); 939 940int iwl_trans_send_cmd(struct iwl_trans *trans, struct iwl_host_cmd *cmd); 941 942void iwl_trans_free_tx_cmd(struct iwl_trans *trans, 943 struct iwl_device_tx_cmd *dev_cmd); 944 945int iwl_trans_tx(struct iwl_trans *trans, struct sk_buff *skb, 946 struct iwl_device_tx_cmd *dev_cmd, int queue); 947 948void iwl_trans_reclaim(struct iwl_trans *trans, int queue, int ssn, 949 struct sk_buff_head *skbs, bool is_flush); 950 951void iwl_trans_set_q_ptrs(struct iwl_trans *trans, int queue, int ptr); 952 953void iwl_trans_txq_disable(struct iwl_trans *trans, int queue, 954 bool configure_scd); 955 956bool iwl_trans_txq_enable_cfg(struct iwl_trans *trans, int queue, u16 ssn, 957 const struct iwl_trans_txq_scd_cfg *cfg, 958 unsigned int queue_wdg_timeout); 959 960int iwl_trans_get_rxq_dma_data(struct iwl_trans *trans, int queue, 961 struct iwl_trans_rxq_dma_data *data); 962 963void iwl_trans_txq_free(struct iwl_trans *trans, int queue); 964 965int iwl_trans_txq_alloc(struct iwl_trans *trans, u32 flags, u32 sta_mask, 966 u8 tid, int size, unsigned int wdg_timeout); 967 968void iwl_trans_txq_set_shared_mode(struct iwl_trans *trans, 969 int txq_id, bool shared_mode); 970 971static inline void iwl_trans_txq_enable(struct iwl_trans *trans, int queue, 972 int fifo, int sta_id, int tid, 973 int frame_limit, u16 ssn, 974 unsigned int queue_wdg_timeout) 975{ 976 struct iwl_trans_txq_scd_cfg cfg = { 977 .fifo = fifo, 978 .sta_id = sta_id, 979 .tid = tid, 980 .frame_limit = frame_limit, 981 .aggregate = sta_id >= 0, 982 }; 983 984 iwl_trans_txq_enable_cfg(trans, queue, ssn, &cfg, queue_wdg_timeout); 985} 986 987static inline 988void iwl_trans_ac_txq_enable(struct iwl_trans *trans, int queue, int fifo, 989 unsigned int queue_wdg_timeout) 990{ 991 struct iwl_trans_txq_scd_cfg cfg = { 992 .fifo = fifo, 993 .sta_id = -1, 994 .tid = IWL_MAX_TID_COUNT, 995 .frame_limit = IWL_FRAME_LIMIT, 996 .aggregate = false, 997 }; 998 999 iwl_trans_txq_enable_cfg(trans, queue, 0, &cfg, queue_wdg_timeout); 1000} 1001 1002void iwl_trans_freeze_txq_timer(struct iwl_trans *trans, 1003 unsigned long txqs, bool freeze); 1004 1005int iwl_trans_wait_tx_queues_empty(struct iwl_trans *trans, u32 txqs); 1006 1007int iwl_trans_wait_txq_empty(struct iwl_trans *trans, int queue); 1008 1009void iwl_trans_write8(struct iwl_trans *trans, u32 ofs, u8 val); 1010 1011void iwl_trans_write32(struct iwl_trans *trans, u32 ofs, u32 val); 1012 1013u32 iwl_trans_read32(struct iwl_trans *trans, u32 ofs); 1014 1015u32 iwl_trans_read_prph(struct iwl_trans *trans, u32 ofs); 1016 1017void iwl_trans_write_prph(struct iwl_trans *trans, u32 ofs, u32 val); 1018 1019int iwl_trans_read_mem(struct iwl_trans *trans, u32 addr, 1020 void *buf, int dwords); 1021 1022int iwl_trans_read_config32(struct iwl_trans *trans, u32 ofs, 1023 u32 *val); 1024 1025#ifdef CONFIG_IWLWIFI_DEBUGFS 1026void iwl_trans_debugfs_cleanup(struct iwl_trans *trans); 1027#endif 1028 1029#define iwl_trans_read_mem_bytes(trans, addr, buf, bufsize) \ 1030 ({ \ 1031 if (__builtin_constant_p(bufsize)) \ 1032 BUILD_BUG_ON((bufsize) % sizeof(u32)); \ 1033 iwl_trans_read_mem(trans, addr, buf, \ 1034 (bufsize) / sizeof(u32)); \ 1035 }) 1036 1037int iwl_trans_write_imr_mem(struct iwl_trans *trans, u32 dst_addr, 1038 u64 src_addr, u32 byte_cnt); 1039 1040static inline u32 iwl_trans_read_mem32(struct iwl_trans *trans, u32 addr) 1041{ 1042 u32 value; 1043 1044 if (iwl_trans_read_mem(trans, addr, &value, 1)) 1045 return 0xa5a5a5a5; 1046 1047 return value; 1048} 1049 1050int iwl_trans_write_mem(struct iwl_trans *trans, u32 addr, 1051 const void *buf, int dwords); 1052 1053static inline u32 iwl_trans_write_mem32(struct iwl_trans *trans, u32 addr, 1054 u32 val) 1055{ 1056 return iwl_trans_write_mem(trans, addr, &val, 1); 1057} 1058 1059void iwl_trans_set_pmi(struct iwl_trans *trans, bool state); 1060 1061int iwl_trans_sw_reset(struct iwl_trans *trans); 1062 1063void iwl_trans_set_bits_mask(struct iwl_trans *trans, u32 reg, 1064 u32 mask, u32 value); 1065 1066bool _iwl_trans_grab_nic_access(struct iwl_trans *trans); 1067 1068#define iwl_trans_grab_nic_access(trans) \ 1069 __cond_lock(nic_access, \ 1070 likely(_iwl_trans_grab_nic_access(trans))) 1071 1072void __releases(nic_access) 1073iwl_trans_release_nic_access(struct iwl_trans *trans); 1074 1075static inline void iwl_trans_schedule_reset(struct iwl_trans *trans, 1076 enum iwl_fw_error_type type) 1077{ 1078 if (test_bit(STATUS_TRANS_DEAD, &trans->status)) 1079 return; 1080 /* clear this on device init, not cleared on any unbind/reprobe */ 1081 if (test_and_set_bit(STATUS_TRANS_RESET_IN_PROGRESS, &trans->status)) 1082 return; 1083 1084 trans->restart.mode.type = type; 1085 trans->restart.mode.context = IWL_ERR_CONTEXT_WORKER; 1086 1087 set_bit(STATUS_RESET_PENDING, &trans->status); 1088 1089 /* 1090 * keep track of whether or not this happened while resetting, 1091 * by the timer the worker runs it might have finished 1092 */ 1093 trans->restart.during_reset = test_bit(STATUS_IN_SW_RESET, 1094 &trans->status); 1095 queue_delayed_work(system_unbound_wq, &trans->restart.wk, 0); 1096} 1097 1098static inline void iwl_trans_fw_error(struct iwl_trans *trans, 1099 enum iwl_fw_error_type type) 1100{ 1101 if (WARN_ON_ONCE(!trans->op_mode)) 1102 return; 1103 1104 /* prevent double restarts due to the same erroneous FW */ 1105 if (!test_and_set_bit(STATUS_FW_ERROR, &trans->status)) { 1106 trans->state = IWL_TRANS_NO_FW; 1107 iwl_op_mode_nic_error(trans->op_mode, type); 1108 iwl_trans_schedule_reset(trans, type); 1109 } 1110} 1111 1112static inline void iwl_trans_opmode_sw_reset(struct iwl_trans *trans, 1113 enum iwl_fw_error_type type) 1114{ 1115 if (WARN_ON_ONCE(!trans->op_mode)) 1116 return; 1117 1118 set_bit(STATUS_IN_SW_RESET, &trans->status); 1119 1120 if (WARN_ON(type == IWL_ERR_TYPE_TOP_RESET_BY_BT)) 1121 return; 1122 1123 if (!trans->op_mode->ops->sw_reset || 1124 !trans->op_mode->ops->sw_reset(trans->op_mode, type)) 1125 clear_bit(STATUS_IN_SW_RESET, &trans->status); 1126} 1127 1128static inline bool iwl_trans_fw_running(struct iwl_trans *trans) 1129{ 1130 return trans->state == IWL_TRANS_FW_ALIVE; 1131} 1132 1133void iwl_trans_sync_nmi(struct iwl_trans *trans); 1134 1135void iwl_trans_sync_nmi_with_addr(struct iwl_trans *trans, u32 inta_addr, 1136 u32 sw_err_bit); 1137 1138int iwl_trans_load_pnvm(struct iwl_trans *trans, 1139 const struct iwl_pnvm_image *pnvm_data, 1140 const struct iwl_ucode_capabilities *capa); 1141 1142void iwl_trans_set_pnvm(struct iwl_trans *trans, 1143 const struct iwl_ucode_capabilities *capa); 1144 1145int iwl_trans_load_reduce_power(struct iwl_trans *trans, 1146 const struct iwl_pnvm_image *payloads, 1147 const struct iwl_ucode_capabilities *capa); 1148 1149void iwl_trans_set_reduce_power(struct iwl_trans *trans, 1150 const struct iwl_ucode_capabilities *capa); 1151 1152static inline bool iwl_trans_dbg_ini_valid(struct iwl_trans *trans) 1153{ 1154 return trans->dbg.internal_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED || 1155 trans->dbg.external_ini_cfg != IWL_INI_CFG_STATE_NOT_LOADED; 1156} 1157 1158void iwl_trans_interrupts(struct iwl_trans *trans, bool enable); 1159 1160static inline void iwl_trans_finish_sw_reset(struct iwl_trans *trans) 1161{ 1162 clear_bit(STATUS_IN_SW_RESET, &trans->status); 1163} 1164 1165/***************************************************** 1166 * transport helper functions 1167 *****************************************************/ 1168struct iwl_trans *iwl_trans_alloc(unsigned int priv_size, 1169 struct device *dev, 1170 const struct iwl_mac_cfg *mac_cfg); 1171void iwl_trans_free(struct iwl_trans *trans); 1172 1173static inline bool iwl_trans_is_hw_error_value(u32 val) 1174{ 1175 return ((val & ~0xf) == 0xa5a5a5a0) || ((val & ~0xf) == 0x5a5a5a50); 1176} 1177 1178void iwl_trans_free_restart_list(void); 1179 1180static inline u16 iwl_trans_get_num_rbds(struct iwl_trans *trans) 1181{ 1182 u16 result = trans->cfg->num_rbds; 1183 1184 /* 1185 * Since AX210 family (So/Ty) the device cannot put mutliple 1186 * frames into the same buffer, so double the value for them. 1187 */ 1188 if (trans->mac_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) 1189 return 2 * result; 1190 return result; 1191} 1192 1193static inline bool iwl_trans_device_enabled(struct iwl_trans *trans) 1194{ 1195 return test_bit(STATUS_DEVICE_ENABLED, &trans->status); 1196} 1197 1198static inline bool iwl_trans_is_dead(struct iwl_trans *trans) 1199{ 1200 return test_bit(STATUS_TRANS_DEAD, &trans->status); 1201} 1202 1203static inline bool iwl_trans_is_fw_error(struct iwl_trans *trans) 1204{ 1205 return test_bit(STATUS_FW_ERROR, &trans->status); 1206} 1207 1208/* 1209 * This function notifies the transport layer of firmware error, the recovery 1210 * will be handled by the op mode 1211 */ 1212static inline void iwl_trans_notify_fw_error(struct iwl_trans *trans) 1213{ 1214 trans->state = IWL_TRANS_NO_FW; 1215 set_bit(STATUS_FW_ERROR, &trans->status); 1216} 1217/***************************************************** 1218 * PCIe handling 1219 *****************************************************/ 1220int __must_check iwl_pci_register_driver(void); 1221void iwl_pci_unregister_driver(void); 1222 1223/* Note: order matters */ 1224enum iwl_reset_mode { 1225 /* upper level modes: */ 1226 IWL_RESET_MODE_SW_RESET, 1227 IWL_RESET_MODE_REPROBE, 1228 /* TOP reset doesn't require PCIe remove */ 1229 IWL_RESET_MODE_TOP_RESET, 1230 /* PCIE level modes: */ 1231 IWL_RESET_MODE_REMOVE_ONLY, 1232 IWL_RESET_MODE_RESCAN, 1233 IWL_RESET_MODE_FUNC_RESET, 1234 IWL_RESET_MODE_PROD_RESET, 1235 1236 /* keep last - special backoff value */ 1237 IWL_RESET_MODE_BACKOFF, 1238}; 1239 1240void iwl_trans_pcie_reset(struct iwl_trans *trans, enum iwl_reset_mode mode); 1241void iwl_trans_pcie_fw_reset_handshake(struct iwl_trans *trans); 1242 1243int iwl_trans_pcie_send_hcmd(struct iwl_trans *trans, 1244 struct iwl_host_cmd *cmd); 1245 1246/* Internal helper */ 1247static inline void iwl_trans_set_info(struct iwl_trans *trans, 1248 struct iwl_trans_info *info) 1249{ 1250 struct iwl_trans_info *write; 1251 1252 write = (void *)(uintptr_t)&trans->info; 1253 *write = *info; 1254} 1255 1256static inline u16 iwl_trans_get_device_id(struct iwl_trans *trans) 1257{ 1258 return u32_get_bits(trans->info.hw_id, GENMASK(31, 16)); 1259} 1260 1261bool iwl_trans_is_pm_supported(struct iwl_trans *trans); 1262 1263bool iwl_trans_is_ltr_enabled(struct iwl_trans *trans); 1264 1265#endif /* __iwl_trans_h__ */
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