iwl-csr.h

  1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
  2/*
  3 * Copyright (C) 2005-2014, 2018-2025 Intel Corporation
  4 * Copyright (C) 2013-2014 Intel Mobile Communications GmbH
  5 * Copyright (C) 2016 Intel Deutschland GmbH
  6 */
  7#ifndef __iwl_csr_h__
  8#define __iwl_csr_h__
  9/*
 10 * CSR (control and status registers)
 11 *
 12 * CSR registers are mapped directly into PCI bus space, and are accessible
 13 * whenever platform supplies power to device, even when device is in
 14 * low power states due to driver-invoked device resets
 15 * (e.g. CSR_RESET_REG_FLAG_SW_RESET) or uCode-driven power-saving modes.
 16 *
 17 * Use iwl_write32() and iwl_read32() family to access these registers;
 18 * these provide simple PCI bus access, without waking up the MAC.
 19 * Do not use iwl_write_direct32() family for these registers;
 20 * no need to "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ.
 21 * The MAC (uCode processor, etc.) does not need to be powered up for accessing
 22 * the CSR registers.
 23 *
 24 * NOTE:  Device does need to be awake in order to read this memory
 25 *        via CSR_EEPROM and CSR_OTP registers
 26 */
 27#define CSR_BASE    (0x000)
 28
 29#define CSR_HW_IF_CONFIG_REG    (CSR_BASE+0x000) /* hardware interface config */
 30#define CSR_INT_COALESCING      (CSR_BASE+0x004) /* accum ints, 32-usec units */
 31#define CSR_INT                 (CSR_BASE+0x008) /* host interrupt status/ack */
 32#define CSR_INT_MASK            (CSR_BASE+0x00c) /* host interrupt enable */
 33#define CSR_FH_INT_STATUS       (CSR_BASE+0x010) /* busmaster int status/ack*/
 34#define CSR_GPIO_IN             (CSR_BASE+0x018) /* read external chip pins */
 35#define CSR_RESET               (CSR_BASE+0x020) /* busmaster enable, NMI, etc*/
 36#define CSR_GP_CNTRL            (CSR_BASE+0x024)
 37#define CSR_FUNC_SCRATCH        (CSR_BASE+0x02c) /* Scratch register - used for FW dbg */
 38
 39/* 2nd byte of CSR_INT_COALESCING, not accessible via iwl_write32()! */
 40#define CSR_INT_PERIODIC_REG	(CSR_BASE+0x005)
 41
 42/*
 43 * Hardware revision info
 44 * Bit fields:
 45 * 31-16:  Reserved
 46 *  15-4:  Type of device:  see CSR_HW_REV_TYPE_xxx definitions
 47 *  3-2:  Revision step:  0 = A, 1 = B, 2 = C, 3 = D
 48 *  1-0:  "Dash" (-) value, as in A-1, etc.
 49 */
 50#define CSR_HW_REV              (CSR_BASE+0x028)
 51
 52/*
 53 * RF ID revision info
 54 * Bit fields:
 55 * 31:24: Reserved (set to 0x0)
 56 * 23:12: Type
 57 * 11:8:  Step (A - 0x0, B - 0x1, etc)
 58 * 7:4:   Dash
 59 * 3:0:   Flavor
 60 */
 61#define CSR_HW_RF_ID		(CSR_BASE+0x09c)
 62
 63/*
 64 * EEPROM and OTP (one-time-programmable) memory reads
 65 *
 66 * NOTE:  Device must be awake, initialized via apm_ops.init(),
 67 *        in order to read.
 68 */
 69#define CSR_EEPROM_REG          (CSR_BASE+0x02c)
 70#define CSR_EEPROM_GP           (CSR_BASE+0x030)
 71#define CSR_OTP_GP_REG   	(CSR_BASE+0x034)
 72
 73#define CSR_GIO_REG		(CSR_BASE+0x03C)
 74#define CSR_GP_UCODE_REG	(CSR_BASE+0x048)
 75#define CSR_GP_DRIVER_REG	(CSR_BASE+0x050)
 76
 77/*
 78 * UCODE-DRIVER GP (general purpose) mailbox registers.
 79 * SET/CLR registers set/clear bit(s) if "1" is written.
 80 */
 81#define CSR_UCODE_DRV_GP1       (CSR_BASE+0x054)
 82#define CSR_UCODE_DRV_GP1_SET   (CSR_BASE+0x058)
 83#define CSR_UCODE_DRV_GP1_CLR   (CSR_BASE+0x05c)
 84#define CSR_UCODE_DRV_GP2       (CSR_BASE+0x060)
 85
 86#define CSR_MBOX_SET_REG	(CSR_BASE + 0x88)
 87
 88#define CSR_LED_REG             (CSR_BASE+0x094)
 89#define CSR_DRAM_INT_TBL_REG	(CSR_BASE+0x0A0)
 90#define CSR_MAC_SHADOW_REG_CTRL		(CSR_BASE + 0x0A8) /* 6000 and up */
 91#define CSR_MAC_SHADOW_REG_CTRL_RX_WAKE	BIT(20)
 92#define CSR_MAC_SHADOW_REG_CTL2		(CSR_BASE + 0x0AC)
 93#define CSR_MAC_SHADOW_REG_CTL2_RX_WAKE	0xFFFF
 94
 95/* LTR control (since IWL_DEVICE_FAMILY_22000) */
 96#define CSR_LTR_LONG_VAL_AD			(CSR_BASE + 0x0D4)
 97#define CSR_LTR_LONG_VAL_AD_NO_SNOOP_REQ	0x80000000
 98#define CSR_LTR_LONG_VAL_AD_NO_SNOOP_SCALE	0x1c000000
 99#define CSR_LTR_LONG_VAL_AD_NO_SNOOP_VAL	0x03ff0000
100#define CSR_LTR_LONG_VAL_AD_SNOOP_REQ		0x00008000
101#define CSR_LTR_LONG_VAL_AD_SNOOP_SCALE		0x00001c00
102#define CSR_LTR_LONG_VAL_AD_SNOOP_VAL		0x000003ff
103#define CSR_LTR_LONG_VAL_AD_SCALE_USEC		2
104
105#define CSR_LTR_LAST_MSG			(CSR_BASE + 0x0DC)
106
107/* GIO Chicken Bits (PCI Express bus link power management) */
108#define CSR_GIO_CHICKEN_BITS    (CSR_BASE+0x100)
109
110#define CSR_IPC_STATE		(CSR_BASE + 0x110)
111#define CSR_IPC_STATE_RESET	0x00000030
112#define CSR_IPC_STATE_RESET_NONE		0
113#define CSR_IPC_STATE_RESET_SW_READY		1
114#define CSR_IPC_STATE_RESET_TOP_READY		2
115#define CSR_IPC_STATE_RESET_TOP_FOLLOWER	3
116#define CSR_IPC_STATE_TOP_RESET_REQ		BIT(6)
117
118#define CSR_IPC_SLEEP_CONTROL	(CSR_BASE + 0x114)
119#define CSR_IPC_SLEEP_CONTROL_SUSPEND	0x3
120#define CSR_IPC_SLEEP_CONTROL_RESUME	0
121
122/* Doorbell - since Bz
123 * connected to UREG_DOORBELL_TO_ISR6 (lower 16 bits only)
124 */
125#define CSR_DOORBELL_VECTOR	(CSR_BASE + 0x130)
126
127/* host chicken bits */
128#define CSR_HOST_CHICKEN	(CSR_BASE + 0x204)
129#define CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME	BIT(19)
130
131/* Analog phase-lock-loop configuration  */
132#define CSR_ANA_PLL_CFG         (CSR_BASE+0x20c)
133
134/*
135 * CSR HW resources monitor registers
136 */
137#define CSR_MONITOR_CFG_REG		(CSR_BASE+0x214)
138#define CSR_MONITOR_STATUS_REG		(CSR_BASE+0x228)
139#define CSR_MONITOR_XTAL_RESOURCES	(0x00000010)
140
141/*
142 * CSR Hardware Revision Workaround Register.  Indicates hardware rev;
143 * "step" determines CCK backoff for txpower calculation.
144 * See also CSR_HW_REV register.
145 * Bit fields:
146 *  3-2:  0 = A, 1 = B, 2 = C, 3 = D step
147 *  1-0:  "Dash" (-) value, as in C-1, etc.
148 */
149#define CSR_HW_REV_WA_REG		(CSR_BASE+0x22C)
150
151#define CSR_DBG_HPET_MEM_REG		(CSR_BASE+0x240)
152#define CSR_DBG_LINK_PWR_MGMT_REG	(CSR_BASE+0x250)
153
154/*
155 * Scratch register initial configuration - this is set on init, and read
156 * during a error FW error.
157 */
158#define CSR_FUNC_SCRATCH_INIT_VALUE		(0x01010101)
159#define CSR_FUNC_SCRATCH_POWER_OFF_MASK		0xFFFF
160
161/* Bits for CSR_HW_IF_CONFIG_REG */
162#define CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP_DASH	(0x0000000F)
163#define CSR_HW_IF_CONFIG_REG_BIT_MONITOR_SRAM	(0x00000080)
164#define CSR_HW_IF_CONFIG_REG_MSK_BOARD_VER	(0x000000C0)
165#define CSR_HW_IF_CONFIG_REG_BIT_MAC_SI		(0x00000100)
166#define CSR_HW_IF_CONFIG_REG_BIT_RADIO_SI	(0x00000200)
167#define CSR_HW_IF_CONFIG_REG_D3_DEBUG		(0x00000200)
168#define CSR_HW_IF_CONFIG_REG_MSK_PHY_TYPE	(0x00000C00)
169#define CSR_HW_IF_CONFIG_REG_MSK_PHY_DASH	(0x00003000)
170#define CSR_HW_IF_CONFIG_REG_MSK_PHY_STEP	(0x0000C000)
171
172#define CSR_HW_IF_CONFIG_REG_POS_MAC_DASH	(0)
173#define CSR_HW_IF_CONFIG_REG_POS_MAC_STEP	(2)
174#define CSR_HW_IF_CONFIG_REG_POS_BOARD_VER	(6)
175#define CSR_HW_IF_CONFIG_REG_POS_PHY_TYPE	(10)
176#define CSR_HW_IF_CONFIG_REG_POS_PHY_DASH	(12)
177#define CSR_HW_IF_CONFIG_REG_POS_PHY_STEP	(14)
178
179#define CSR_HW_IF_CONFIG_REG_HAP_WAKE			0x00080000
180/* NOTE: EEPROM_OWN_SEM is no longer defined for new HW */
181#define CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM		0x00200000
182#define CSR_HW_IF_CONFIG_REG_PCI_OWN_SET		0x00400000
183#define CSR_HW_IF_CONFIG_REG_IAMT_UP			0x01000000
184#define CSR_HW_IF_CONFIG_REG_ME_OWN			0x02000000
185#define CSR_HW_IF_CONFIG_REG_WAKE_ME			0x08000000
186#define CSR_HW_IF_CONFIG_REG_WAKE_ME_PCIE_OWNER_EN	0x10000000
187#define CSR_HW_IF_CONFIG_REG_PERSISTENCE		0x40000000
188
189#define CSR_MBOX_SET_REG_OS_ALIVE		BIT(5)
190
191#define CSR_INT_PERIODIC_DIS			(0x00) /* disable periodic int*/
192#define CSR_INT_PERIODIC_ENA			(0xFF) /* 255*32 usec ~ 8 msec*/
193
194/* interrupt flags in INTA, set by uCode or hardware (e.g. dma),
195 * acknowledged (reset) by host writing "1" to flagged bits. */
196#define CSR_INT_BIT_FH_RX        (1 << 31) /* Rx DMA, cmd responses, FH_INT[17:16] */
197#define CSR_INT_BIT_HW_ERR       (1 << 29) /* DMA hardware error FH_INT[31] */
198#define CSR_INT_BIT_RX_PERIODIC	 (1 << 28) /* Rx periodic */
199#define CSR_INT_BIT_FH_TX        (1 << 27) /* Tx DMA FH_INT[1:0] */
200#define CSR_INT_BIT_SCD          (1 << 26) /* TXQ pointer advanced */
201#define CSR_INT_BIT_SW_ERR       (1 << 25) /* uCode error */
202#define CSR_INT_BIT_RF_KILL      (1 << 7)  /* HW RFKILL switch GP_CNTRL[27] toggled */
203#define CSR_INT_BIT_CT_KILL      (1 << 6)  /* Critical temp (chip too hot) rfkill */
204#define CSR_INT_BIT_SW_RX        (1 << 3)  /* Rx, command responses */
205#define CSR_INT_BIT_RESET_DONE   (1 << 2)  /* reset handshake with firmware is done */
206#define CSR_INT_BIT_WAKEUP       (1 << 1)  /* NIC controller waking up (pwr mgmt) */
207#define CSR_INT_BIT_ALIVE        (1 << 0)  /* uCode interrupts once it initializes */
208
209#define CSR_INI_SET_MASK	(CSR_INT_BIT_FH_RX	| \
210				 CSR_INT_BIT_HW_ERR	| \
211				 CSR_INT_BIT_FH_TX	| \
212				 CSR_INT_BIT_SW_ERR	| \
213				 CSR_INT_BIT_RF_KILL	| \
214				 CSR_INT_BIT_SW_RX	| \
215				 CSR_INT_BIT_WAKEUP	| \
216				 CSR_INT_BIT_RESET_DONE	| \
217				 CSR_INT_BIT_ALIVE	| \
218				 CSR_INT_BIT_RX_PERIODIC)
219
220/* interrupt flags in FH (flow handler) (PCI busmaster DMA) */
221#define CSR_FH_INT_BIT_ERR       (1 << 31) /* Error */
222#define CSR_FH_INT_BIT_HI_PRIOR  (1 << 30) /* High priority Rx, bypass coalescing */
223#define CSR_FH_INT_BIT_RX_CHNL1  (1 << 17) /* Rx channel 1 */
224#define CSR_FH_INT_BIT_RX_CHNL0  (1 << 16) /* Rx channel 0 */
225#define CSR_FH_INT_BIT_TX_CHNL1  (1 << 1)  /* Tx channel 1 */
226#define CSR_FH_INT_BIT_TX_CHNL0  (1 << 0)  /* Tx channel 0 */
227
228#define CSR_FH_INT_RX_MASK	(CSR_FH_INT_BIT_HI_PRIOR | \
229				CSR_FH_INT_BIT_RX_CHNL1 | \
230				CSR_FH_INT_BIT_RX_CHNL0)
231
232#define CSR_FH_INT_TX_MASK	(CSR_FH_INT_BIT_TX_CHNL1 | \
233				CSR_FH_INT_BIT_TX_CHNL0)
234
235/* GPIO */
236#define CSR_GPIO_IN_BIT_AUX_POWER                   (0x00000200)
237#define CSR_GPIO_IN_VAL_VAUX_PWR_SRC                (0x00000000)
238#define CSR_GPIO_IN_VAL_VMAIN_PWR_SRC               (0x00000200)
239
240/* RESET */
241#define CSR_RESET_REG_FLAG_NEVO_RESET                (0x00000001)
242#define CSR_RESET_REG_FLAG_FORCE_NMI                 (0x00000002)
243#define CSR_RESET_REG_FLAG_SW_RESET		     (0x00000080)
244#define CSR_RESET_REG_FLAG_MASTER_DISABLED           (0x00000100)
245#define CSR_RESET_REG_FLAG_STOP_MASTER               (0x00000200)
246#define CSR_RESET_LINK_PWR_MGMT_DISABLED             (0x80000000)
247
248/*
249 * GP (general purpose) CONTROL REGISTER
250 * Bit fields:
251 *    27:  HW_RF_KILL_SW
252 *         Indicates state of (platform's) hardware RF-Kill switch
253 * 26-24:  POWER_SAVE_TYPE
254 *         Indicates current power-saving mode:
255 *         000 -- No power saving
256 *         001 -- MAC power-down
257 *         010 -- PHY (radio) power-down
258 *         011 -- Error
259 *    10:  XTAL ON request
260 *   9-6:  SYS_CONFIG
261 *         Indicates current system configuration, reflecting pins on chip
262 *         as forced high/low by device circuit board.
263 *     4:  GOING_TO_SLEEP
264 *         Indicates MAC is entering a power-saving sleep power-down.
265 *         Not a good time to access device-internal resources.
266 *     3:  MAC_ACCESS_REQ
267 *         Host sets this to request and maintain MAC wakeup, to allow host
268 *         access to device-internal resources.  Host must wait for
269 *         MAC_CLOCK_READY (and !GOING_TO_SLEEP) before accessing non-CSR
270 *         device registers.
271 *     2:  INIT_DONE
272 *         Host sets this to put device into fully operational D0 power mode.
273 *         Host resets this after SW_RESET to put device into low power mode.
274 *     0:  MAC_CLOCK_READY
275 *         Indicates MAC (ucode processor, etc.) is powered up and can run.
276 *         Internal resources are accessible.
277 *         NOTE:  This does not indicate that the processor is actually running.
278 *         NOTE:  This does not indicate that device has completed
279 *                init or post-power-down restore of internal SRAM memory.
280 *                Use CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP as indication that
281 *                SRAM is restored and uCode is in normal operation mode.
282 *                Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
283 *                do not need to save/restore it.
284 *         NOTE:  After device reset, this bit remains "0" until host sets
285 *                INIT_DONE
286 */
287#define CSR_GP_CNTRL_REG_FLAG_MAC_CLOCK_READY	     (0x00000001)
288#define CSR_GP_CNTRL_REG_FLAG_INIT_DONE		     (0x00000004)
289#define CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ	     (0x00000008)
290#define CSR_GP_CNTRL_REG_FLAG_GOING_TO_SLEEP	     (0x00000010)
291#define CSR_GP_CNTRL_REG_FLAG_XTAL_ON		     (0x00000400)
292
293#define CSR_GP_CNTRL_REG_VAL_MAC_ACCESS_EN	     (0x00000001)
294
295#define CSR_GP_CNTRL_REG_MSK_POWER_SAVE_TYPE         (0x07000000)
296#define CSR_GP_CNTRL_REG_FLAG_RFKILL_WAKE_L1A_EN     (0x04000000)
297#define CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW          (0x08000000)
298
299/* From Bz we use these instead during init/reset flow */
300#define CSR_GP_CNTRL_REG_FLAG_MAC_INIT			BIT(6)
301#define CSR_GP_CNTRL_REG_FLAG_ROM_START			BIT(7)
302#define CSR_GP_CNTRL_REG_FLAG_MAC_STATUS		BIT(20)
303#define CSR_GP_CNTRL_REG_FLAG_BZ_MAC_ACCESS_REQ		BIT(21)
304#define CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_STATUS	BIT(28)
305#define CSR_GP_CNTRL_REG_FLAG_BUS_MASTER_DISABLE_REQ	BIT(29)
306#define CSR_GP_CNTRL_REG_FLAG_SW_RESET			BIT(31)
307
308/* HW REV */
309#define CSR_HW_REV_STEP_DASH(_val)     ((_val) & CSR_HW_IF_CONFIG_REG_MSK_MAC_STEP_DASH)
310#define CSR_HW_REV_TYPE(_val)          (((_val) & 0x000FFF0) >> 4)
311
312/* HW RFID */
313#define CSR_HW_RFID_FLAVOR(_val)       (((_val) & 0x000000F) >> 0)
314#define CSR_HW_RFID_DASH(_val)         (((_val) & 0x00000F0) >> 4)
315#define CSR_HW_RFID_STEP(_val)         (((_val) & 0x0000F00) >> 8)
316#define CSR_HW_RFID_TYPE(_val)         (((_val) & 0x0FFF000) >> 12)
317#define CSR_HW_RFID_IS_CDB(_val)       (((_val) & 0x10000000) >> 28)
318#define CSR_HW_RFID_IS_JACKET(_val)    (((_val) & 0x20000000) >> 29)
319
320/* hw_rev values */
321enum {
322	SILICON_A_STEP = 0,
323	SILICON_B_STEP,
324	SILICON_C_STEP,
325	SILICON_D_STEP,
326	SILICON_E_STEP,
327	SILICON_TC_STEP = 0xe,
328	SILICON_Z_STEP = 0xf,
329};
330
331
332#define CSR_HW_REV_TYPE_MSK		(0x000FFF0)
333#define CSR_HW_REV_TYPE_5300		(0x0000020)
334#define CSR_HW_REV_TYPE_5350		(0x0000030)
335#define CSR_HW_REV_TYPE_5100		(0x0000050)
336#define CSR_HW_REV_TYPE_5150		(0x0000040)
337#define CSR_HW_REV_TYPE_1000		(0x0000060)
338#define CSR_HW_REV_TYPE_6x00		(0x0000070)
339#define CSR_HW_REV_TYPE_6x50		(0x0000080)
340#define CSR_HW_REV_TYPE_6150		(0x0000084)
341#define CSR_HW_REV_TYPE_6x05		(0x00000B0)
342#define CSR_HW_REV_TYPE_6x30		CSR_HW_REV_TYPE_6x05
343#define CSR_HW_REV_TYPE_6x35		CSR_HW_REV_TYPE_6x05
344#define CSR_HW_REV_TYPE_2x30		(0x00000C0)
345#define CSR_HW_REV_TYPE_2x00		(0x0000100)
346#define CSR_HW_REV_TYPE_105		(0x0000110)
347#define CSR_HW_REV_TYPE_135		(0x0000120)
348#define CSR_HW_REV_TYPE_3160		(0x0000164)
349#define CSR_HW_REV_TYPE_7265D		(0x0000210)
350#define CSR_HW_REV_TYPE_NONE		(0x00001F0)
351#define CSR_HW_REV_TYPE_QNJ		(0x0000360)
352#define CSR_HW_REV_TYPE_QNJ_B0		(0x0000361)
353#define CSR_HW_REV_TYPE_QU_B0		(0x0000331)
354#define CSR_HW_REV_TYPE_QU_C0		(0x0000332)
355#define CSR_HW_REV_TYPE_QUZ		(0x0000351)
356#define CSR_HW_REV_TYPE_HR_CDB		(0x0000340)
357#define CSR_HW_REV_TYPE_SO		(0x0000370)
358#define CSR_HW_REV_TYPE_TY		(0x0000420)
359
360/* RF_ID value */
361#define CSR_HW_RF_ID_TYPE_JF		(0x00105100)
362#define CSR_HW_RF_ID_TYPE_HR		(0x0010A000)
363#define CSR_HW_RF_ID_TYPE_HR1		(0x0010c100)
364#define CSR_HW_RF_ID_TYPE_HRCDB		(0x00109F00)
365#define CSR_HW_RF_ID_TYPE_GF		(0x0010D000)
366#define CSR_HW_RF_ID_TYPE_GF4		(0x0010E000)
367#define CSR_HW_RF_ID_TYPE_FM		(0x00112000)
368#define CSR_HW_RF_ID_TYPE_WP		(0x00113000)
369
370/* HW_RF CHIP STEP  */
371#define CSR_HW_RF_STEP(_val) (((_val) >> 8) & 0xF)
372
373/* EEPROM REG */
374#define CSR_EEPROM_REG_READ_VALID_MSK	(0x00000001)
375#define CSR_EEPROM_REG_BIT_CMD		(0x00000002)
376#define CSR_EEPROM_REG_MSK_ADDR		(0x0000FFFC)
377#define CSR_EEPROM_REG_MSK_DATA		(0xFFFF0000)
378
379/* EEPROM GP */
380#define CSR_EEPROM_GP_VALID_MSK		(0x00000007) /* signature */
381#define CSR_EEPROM_GP_IF_OWNER_MSK	(0x00000180)
382#define CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP	(0x00000000)
383#define CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP		(0x00000001)
384#define CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K		(0x00000002)
385#define CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K		(0x00000004)
386
387/* One-time-programmable memory general purpose reg */
388#define CSR_OTP_GP_REG_DEVICE_SELECT	(0x00010000) /* 0 - EEPROM, 1 - OTP */
389#define CSR_OTP_GP_REG_OTP_ACCESS_MODE	(0x00020000) /* 0 - absolute, 1 - relative */
390#define CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK          (0x00100000) /* bit 20 */
391#define CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK        (0x00200000) /* bit 21 */
392
393/* GP REG */
394#define CSR_GP_REG_POWER_SAVE_STATUS_MSK            (0x03000000) /* bit 24/25 */
395#define CSR_GP_REG_NO_POWER_SAVE            (0x00000000)
396#define CSR_GP_REG_MAC_POWER_SAVE           (0x01000000)
397#define CSR_GP_REG_PHY_POWER_SAVE           (0x02000000)
398#define CSR_GP_REG_POWER_SAVE_ERROR         (0x03000000)
399
400
401/* CSR GIO */
402#define CSR_GIO_REG_VAL_L0S_DISABLED	(0x00000002)
403
404/*
405 * UCODE-DRIVER GP (general purpose) mailbox register 1
406 * Host driver and uCode write and/or read this register to communicate with
407 * each other.
408 * Bit fields:
409 *     4:  UCODE_DISABLE
410 *         Host sets this to request permanent halt of uCode, same as
411 *         sending CARD_STATE command with "halt" bit set.
412 *     3:  CT_KILL_EXIT
413 *         Host sets this to request exit from CT_KILL state, i.e. host thinks
414 *         device temperature is low enough to continue normal operation.
415 *     2:  CMD_BLOCKED
416 *         Host sets this during RF KILL power-down sequence (HW, SW, CT KILL)
417 *         to release uCode to clear all Tx and command queues, enter
418 *         unassociated mode, and power down.
419 *         NOTE:  Some devices also use HBUS_TARG_MBX_C register for this bit.
420 *     1:  SW_BIT_RFKILL
421 *         Host sets this when issuing CARD_STATE command to request
422 *         device sleep.
423 *     0:  MAC_SLEEP
424 *         uCode sets this when preparing a power-saving power-down.
425 *         uCode resets this when power-up is complete and SRAM is sane.
426 *         NOTE:  device saves internal SRAM data to host when powering down,
427 *                and must restore this data after powering back up.
428 *                MAC_SLEEP is the best indication that restore is complete.
429 *                Later devices (5xxx/6xxx/1xxx) use non-volatile SRAM, and
430 *                do not need to save/restore it.
431 */
432#define CSR_UCODE_DRV_GP1_BIT_MAC_SLEEP             (0x00000001)
433#define CSR_UCODE_SW_BIT_RFKILL                     (0x00000002)
434#define CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED           (0x00000004)
435#define CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT      (0x00000008)
436#define CSR_UCODE_DRV_GP1_BIT_D3_CFG_COMPLETE       (0x00000020)
437
438/* GP Driver */
439#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_MSK	    (0x00000003)
440#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_3x3_HYB	    (0x00000000)
441#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_HYB	    (0x00000001)
442#define CSR_GP_DRIVER_REG_BIT_RADIO_SKU_2x2_IPA	    (0x00000002)
443#define CSR_GP_DRIVER_REG_BIT_CALIB_VERSION6	    (0x00000004)
444#define CSR_GP_DRIVER_REG_BIT_6050_1x2		    (0x00000008)
445
446#define CSR_GP_DRIVER_REG_BIT_RADIO_IQ_INVER	    (0x00000080)
447
448/* GIO Chicken Bits (PCI Express bus link power management) */
449#define CSR_GIO_CHICKEN_BITS_REG_BIT_L1A_NO_L0S_RX  (0x00800000)
450#define CSR_GIO_CHICKEN_BITS_REG_BIT_DIS_L0S_EXIT_TIMER  (0x20000000)
451
452/* LED */
453#define CSR_LED_BSM_CTRL_MSK (0xFFFFFFDF)
454#define CSR_LED_REG_TURN_ON (0x60)
455#define CSR_LED_REG_TURN_OFF (0x20)
456
457/* ANA_PLL */
458#define CSR50_ANA_PLL_CFG_VAL        (0x00880300)
459
460/* HPET MEM debug */
461#define CSR_DBG_HPET_MEM_REG_VAL	(0xFFFF0000)
462
463/* DRAM INT TABLE */
464#define CSR_DRAM_INT_TBL_ENABLE		(1 << 31)
465#define CSR_DRAM_INIT_TBL_WRITE_POINTER	(1 << 28)
466#define CSR_DRAM_INIT_TBL_WRAP_CHECK	(1 << 27)
467
468/*
469 * SHR target access (Shared block memory space)
470 *
471 * Shared internal registers can be accessed directly from PCI bus through SHR
472 * arbiter without need for the MAC HW to be powered up. This is possible due to
473 * indirect read/write via HEEP_CTRL_WRD_PCIEX_CTRL (0xEC) and
474 * HEEP_CTRL_WRD_PCIEX_DATA (0xF4) registers.
475 *
476 * Use iwl_write32()/iwl_read32() family to access these registers. The MAC HW
477 * need not be powered up so no "grab inc access" is required.
478 */
479
480/*
481 * Registers for accessing shared registers (e.g. SHR_APMG_GP1,
482 * SHR_APMG_XTAL_CFG). For example, to read from SHR_APMG_GP1 register (0x1DC),
483 * first, write to the control register:
484 * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
485 * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 2 (read access)
486 * second, read from the data register HEEP_CTRL_WRD_PCIEX_DATA[31:0].
487 *
488 * To write the register, first, write to the data register
489 * HEEP_CTRL_WRD_PCIEX_DATA[31:0] and then:
490 * HEEP_CTRL_WRD_PCIEX_CTRL[15:0] = 0x1DC (offset of the SHR_APMG_GP1 register)
491 * HEEP_CTRL_WRD_PCIEX_CTRL[29:28] = 3 (write access)
492 */
493#define HEEP_CTRL_WRD_PCIEX_CTRL_REG	(CSR_BASE+0x0ec)
494#define HEEP_CTRL_WRD_PCIEX_DATA_REG	(CSR_BASE+0x0f4)
495
496/*
497 * HBUS (Host-side Bus)
498 *
499 * HBUS registers are mapped directly into PCI bus space, but are used
500 * to indirectly access device's internal memory or registers that
501 * may be powered-down.
502 *
503 * Use iwl_write_direct32()/iwl_read_direct32() family for these registers;
504 * host must "grab nic access" via CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ
505 * to make sure the MAC (uCode processor, etc.) is powered up for accessing
506 * internal resources.
507 *
508 * Do not use iwl_write32()/iwl_read32() family to access these registers;
509 * these provide only simple PCI bus access, without waking up the MAC.
510 */
511#define HBUS_BASE	(0x400)
512
513/*
514 * Registers for accessing device's internal SRAM memory (e.g. SCD SRAM
515 * structures, error log, event log, verifying uCode load).
516 * First write to address register, then read from or write to data register
517 * to complete the job.  Once the address register is set up, accesses to
518 * data registers auto-increment the address by one dword.
519 * Bit usage for address registers (read or write):
520 *  0-31:  memory address within device
521 */
522#define HBUS_TARG_MEM_RADDR     (HBUS_BASE+0x00c)
523#define HBUS_TARG_MEM_WADDR     (HBUS_BASE+0x010)
524#define HBUS_TARG_MEM_WDAT      (HBUS_BASE+0x018)
525#define HBUS_TARG_MEM_RDAT      (HBUS_BASE+0x01c)
526
527/* Mailbox C, used as workaround alternative to CSR_UCODE_DRV_GP1 mailbox */
528#define HBUS_TARG_MBX_C         (HBUS_BASE+0x030)
529#define HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED         (0x00000004)
530
531/*
532 * Registers for accessing device's internal peripheral registers
533 * (e.g. SCD, BSM, etc.).  First write to address register,
534 * then read from or write to data register to complete the job.
535 * Bit usage for address registers (read or write):
536 *  0-15:  register address (offset) within device
537 * 24-25:  (# bytes - 1) to read or write (e.g. 3 for dword)
538 */
539#define HBUS_TARG_PRPH_WADDR    (HBUS_BASE+0x044)
540#define HBUS_TARG_PRPH_RADDR    (HBUS_BASE+0x048)
541#define HBUS_TARG_PRPH_WDAT     (HBUS_BASE+0x04c)
542#define HBUS_TARG_PRPH_RDAT     (HBUS_BASE+0x050)
543
544/* Used to enable DBGM */
545#define HBUS_TARG_TEST_REG	(HBUS_BASE+0x05c)
546
547/*
548 * Per-Tx-queue write pointer (index, really!)
549 * Indicates index to next TFD that driver will fill (1 past latest filled).
550 * Bit usage:
551 *  0-7:  queue write index
552 * 11-8:  queue selector
553 */
554#define HBUS_TARG_WRPTR         (HBUS_BASE+0x060)
555/* This register is common for Tx and Rx, Rx queues start from 512 */
556#define HBUS_TARG_WRPTR_Q_SHIFT (16)
557#define HBUS_TARG_WRPTR_RX_Q(q) (((q) + 512) << HBUS_TARG_WRPTR_Q_SHIFT)
558
559/**********************************************************
560 * CSR values
561 **********************************************************/
562 /*
563 * host interrupt timeout value
564 * used with setting interrupt coalescing timer
565 * the CSR_INT_COALESCING is an 8 bit register in 32-usec unit
566 *
567 * default interrupt coalescing timer is 64 x 32 = 2048 usecs
568 */
569#define IWL_HOST_INT_TIMEOUT_MAX	(0xFF)
570#define IWL_HOST_INT_TIMEOUT_DEF	(0x40)
571#define IWL_HOST_INT_TIMEOUT_MIN	(0x0)
572#define IWL_HOST_INT_OPER_MODE		BIT(31)
573
574/*****************************************************************************
575 *                        7000/3000 series SHR DTS addresses                 *
576 *****************************************************************************/
577
578/* Diode Results Register Structure: */
579enum dtd_diode_reg {
580	DTS_DIODE_REG_DIG_VAL			= 0x000000FF, /* bits [7:0] */
581	DTS_DIODE_REG_VREF_LOW			= 0x0000FF00, /* bits [15:8] */
582	DTS_DIODE_REG_VREF_HIGH			= 0x00FF0000, /* bits [23:16] */
583	DTS_DIODE_REG_VREF_ID			= 0x03000000, /* bits [25:24] */
584	DTS_DIODE_REG_PASS_ONCE			= 0x80000000, /* bits [31:31] */
585	DTS_DIODE_REG_FLAGS_MSK			= 0xFF000000, /* bits [31:24] */
586/* Those are the masks INSIDE the flags bit-field: */
587	DTS_DIODE_REG_FLAGS_VREFS_ID_POS	= 0,
588	DTS_DIODE_REG_FLAGS_VREFS_ID		= 0x00000003, /* bits [1:0] */
589	DTS_DIODE_REG_FLAGS_PASS_ONCE_POS	= 7,
590	DTS_DIODE_REG_FLAGS_PASS_ONCE		= 0x00000080, /* bits [7:7] */
591};
592
593/*****************************************************************************
594 *                        MSIX related registers                             *
595 *****************************************************************************/
596
597#define CSR_MSIX_BASE			(0x2000)
598#define CSR_MSIX_FH_INT_CAUSES_AD	(CSR_MSIX_BASE + 0x800)
599#define CSR_MSIX_FH_INT_MASK_AD		(CSR_MSIX_BASE + 0x804)
600#define CSR_MSIX_HW_INT_CAUSES_AD	(CSR_MSIX_BASE + 0x808)
601#define CSR_MSIX_HW_INT_MASK_AD		(CSR_MSIX_BASE + 0x80C)
602#define CSR_MSIX_AUTOMASK_ST_AD		(CSR_MSIX_BASE + 0x810)
603#define CSR_MSIX_RX_IVAR_AD_REG		(CSR_MSIX_BASE + 0x880)
604#define CSR_MSIX_IVAR_AD_REG		(CSR_MSIX_BASE + 0x890)
605#define CSR_MSIX_PENDING_PBA_AD		(CSR_MSIX_BASE + 0x1000)
606#define CSR_MSIX_RX_IVAR(cause)		(CSR_MSIX_RX_IVAR_AD_REG + (cause))
607#define CSR_MSIX_IVAR(cause)		(CSR_MSIX_IVAR_AD_REG + (cause))
608
609#define MSIX_FH_INT_CAUSES_Q(q)		(q)
610
611/*
612 * Causes for the FH register interrupts
613 */
614enum msix_fh_int_causes {
615	MSIX_FH_INT_CAUSES_Q0			= BIT(0),
616	MSIX_FH_INT_CAUSES_Q1			= BIT(1),
617	MSIX_FH_INT_CAUSES_D2S_CH0_NUM		= BIT(16),
618	MSIX_FH_INT_CAUSES_D2S_CH1_NUM		= BIT(17),
619	MSIX_FH_INT_CAUSES_S2D			= BIT(19),
620	MSIX_FH_INT_CAUSES_FH_ERR		= BIT(21),
621};
622
623/* The low 16 bits are for rx data queue indication */
624#define MSIX_FH_INT_CAUSES_DATA_QUEUE 0xffff
625
626/*
627 * Causes for the HW register interrupts
628 */
629enum msix_hw_int_causes {
630	MSIX_HW_INT_CAUSES_REG_ALIVE		= BIT(0),
631	MSIX_HW_INT_CAUSES_REG_WAKEUP		= BIT(1),
632	MSIX_HW_INT_CAUSES_REG_IML              = BIT(1),
633	MSIX_HW_INT_CAUSES_REG_RESET_DONE	= BIT(2),
634	MSIX_HW_INT_CAUSES_REG_TOP_FATAL_ERR	= BIT(3),
635	MSIX_HW_INT_CAUSES_REG_SW_ERR_BZ	= BIT(5),
636	MSIX_HW_INT_CAUSES_REG_CT_KILL		= BIT(6),
637	MSIX_HW_INT_CAUSES_REG_RF_KILL		= BIT(7),
638	MSIX_HW_INT_CAUSES_REG_PERIODIC		= BIT(8),
639	MSIX_HW_INT_CAUSES_REG_SW_ERR		= BIT(25),
640	MSIX_HW_INT_CAUSES_REG_SCD		= BIT(26),
641	MSIX_HW_INT_CAUSES_REG_FH_TX		= BIT(27),
642	MSIX_HW_INT_CAUSES_REG_HW_ERR		= BIT(29),
643	MSIX_HW_INT_CAUSES_REG_HAP		= BIT(30),
644};
645
646#define MSIX_MIN_INTERRUPT_VECTORS		2
647#define MSIX_AUTO_CLEAR_CAUSE			0
648#define MSIX_NON_AUTO_CLEAR_CAUSE		BIT(7)
649
650/*****************************************************************************
651 *                     HW address related registers                          *
652 *****************************************************************************/
653
654#define CSR_ADDR_BASE(trans)			((trans)->mac_cfg->base->mac_addr_from_csr)
655#define CSR_MAC_ADDR0_OTP(trans)		(CSR_ADDR_BASE(trans) + 0x00)
656#define CSR_MAC_ADDR1_OTP(trans)		(CSR_ADDR_BASE(trans) + 0x04)
657#define CSR_MAC_ADDR0_STRAP(trans)		(CSR_ADDR_BASE(trans) + 0x08)
658#define CSR_MAC_ADDR1_STRAP(trans)		(CSR_ADDR_BASE(trans) + 0x0c)
659
660#endif /* !__iwl_csr_h__ */