iwl-config.h

  1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
  2/*
  3 * Copyright (C) 2005-2014, 2018-2021 Intel Corporation
  4 * Copyright (C) 2016-2017 Intel Deutschland GmbH
  5 * Copyright (C) 2018-2025 Intel Corporation
  6 */
  7#ifndef __IWL_CONFIG_H__
  8#define __IWL_CONFIG_H__
  9
 10#include <linux/types.h>
 11#include <linux/netdevice.h>
 12#include <linux/ieee80211.h>
 13#include <linux/nl80211.h>
 14#include <linux/module.h>
 15#include <linux/mod_devicetable.h>
 16#include "iwl-csr.h"
 17#include "iwl-drv.h"
 18
 19enum iwl_device_family {
 20	IWL_DEVICE_FAMILY_UNDEFINED,
 21	IWL_DEVICE_FAMILY_1000,
 22	IWL_DEVICE_FAMILY_100,
 23	IWL_DEVICE_FAMILY_2000,
 24	IWL_DEVICE_FAMILY_2030,
 25	IWL_DEVICE_FAMILY_105,
 26	IWL_DEVICE_FAMILY_135,
 27	IWL_DEVICE_FAMILY_5000,
 28	IWL_DEVICE_FAMILY_5150,
 29	IWL_DEVICE_FAMILY_6000,
 30	IWL_DEVICE_FAMILY_6000i,
 31	IWL_DEVICE_FAMILY_6005,
 32	IWL_DEVICE_FAMILY_6030,
 33	IWL_DEVICE_FAMILY_6050,
 34	IWL_DEVICE_FAMILY_6150,
 35	IWL_DEVICE_FAMILY_7000,
 36	IWL_DEVICE_FAMILY_8000,
 37	IWL_DEVICE_FAMILY_9000,
 38	IWL_DEVICE_FAMILY_22000,
 39	IWL_DEVICE_FAMILY_AX210,
 40	IWL_DEVICE_FAMILY_BZ,
 41	IWL_DEVICE_FAMILY_SC,
 42	IWL_DEVICE_FAMILY_DR,
 43};
 44
 45/*
 46 * LED mode
 47 *    IWL_LED_DEFAULT:  use device default
 48 *    IWL_LED_RF_STATE: turn LED on/off based on RF state
 49 *			LED ON  = RF ON
 50 *			LED OFF = RF OFF
 51 *    IWL_LED_BLINK:    adjust led blink rate based on blink table
 52 *    IWL_LED_DISABLE:	led disabled
 53 */
 54enum iwl_led_mode {
 55	IWL_LED_DEFAULT,
 56	IWL_LED_RF_STATE,
 57	IWL_LED_BLINK,
 58	IWL_LED_DISABLE,
 59};
 60
 61/**
 62 * enum iwl_nvm_type - nvm formats
 63 * @IWL_NVM: the regular format
 64 * @IWL_NVM_EXT: extended NVM format
 65 * @IWL_NVM_SDP: NVM format used by 3168 series
 66 */
 67enum iwl_nvm_type {
 68	IWL_NVM,
 69	IWL_NVM_EXT,
 70	IWL_NVM_SDP,
 71};
 72
 73/*
 74 * This is the threshold value of plcp error rate per 100mSecs.  It is
 75 * used to set and check for the validity of plcp_delta.
 76 */
 77#define IWL_MAX_PLCP_ERR_THRESHOLD_MIN		1
 78#define IWL_MAX_PLCP_ERR_THRESHOLD_DEF		50
 79#define IWL_MAX_PLCP_ERR_LONG_THRESHOLD_DEF	100
 80#define IWL_MAX_PLCP_ERR_EXT_LONG_THRESHOLD_DEF	200
 81#define IWL_MAX_PLCP_ERR_THRESHOLD_MAX		255
 82#define IWL_MAX_PLCP_ERR_THRESHOLD_DISABLE	0
 83
 84/* TX queue watchdog timeouts in mSecs */
 85#define IWL_WATCHDOG_DISABLED	0
 86#define IWL_DEF_WD_TIMEOUT	2500
 87#define IWL_LONG_WD_TIMEOUT	10000
 88#define IWL_MAX_WD_TIMEOUT	120000
 89
 90#define IWL_DEFAULT_MAX_TX_POWER 22
 91#define IWL_TX_CSUM_NETIF_FLAGS (NETIF_F_IPV6_CSUM | NETIF_F_IP_CSUM |\
 92				 NETIF_F_TSO | NETIF_F_TSO6)
 93#define IWL_CSUM_NETIF_FLAGS_MASK (IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM)
 94
 95/* Antenna presence definitions */
 96#define	ANT_NONE	0x0
 97#define	ANT_INVALID	0xff
 98#define	ANT_A		BIT(0)
 99#define	ANT_B		BIT(1)
100#define ANT_C		BIT(2)
101#define	ANT_AB		(ANT_A | ANT_B)
102#define	ANT_AC		(ANT_A | ANT_C)
103#define ANT_BC		(ANT_B | ANT_C)
104#define ANT_ABC		(ANT_A | ANT_B | ANT_C)
105
106
107#define IWL_FW_AND_PNVM(pfx, api)				\
108	MODULE_FIRMWARE(pfx "-" __stringify(api) ".ucode");	\
109	MODULE_FIRMWARE(pfx ".pnvm")
110
111#define IWL_CORE_FW(pfx, core)					\
112	MODULE_FIRMWARE(pfx "-c" __stringify(core) ".ucode")
113
114static inline u8 num_of_ant(u8 mask)
115{
116	return  !!((mask) & ANT_A) +
117		!!((mask) & ANT_B) +
118		!!((mask) & ANT_C);
119}
120
121/**
122 * struct iwl_fw_mon_reg - FW monitor register info
123 * @addr: register address
124 * @mask: register mask
125 */
126struct iwl_fw_mon_reg {
127	u32 addr;
128	u32 mask;
129};
130
131/**
132 * struct iwl_fw_mon_regs - FW monitor registers
133 * @write_ptr: write pointer register
134 * @cycle_cnt: cycle count register
135 * @cur_frag: current fragment in use
136 */
137struct iwl_fw_mon_regs {
138	struct iwl_fw_mon_reg write_ptr;
139	struct iwl_fw_mon_reg cycle_cnt;
140	struct iwl_fw_mon_reg cur_frag;
141};
142
143/**
144 * struct iwl_family_base_params - base parameters for an entire family
145 * @max_ll_items: max number of OTP blocks
146 * @shadow_ram_support: shadow support for OTP memory
147 * @led_compensation: compensate on the led on/off time per HW according
148 *	to the deviation to achieve the desired led frequency.
149 *	The detail algorithm is described in iwl-led.c
150 * @wd_timeout: TX queues watchdog timeout
151 * @max_event_log_size: size of event log buffer size for ucode event logging
152 * @shadow_reg_enable: HW shadow register support
153 * @apmg_not_supported: there's no APMG
154 * @apmg_wake_up_wa: should the MAC access REQ be asserted when a command
155 *	is in flight. This is due to a HW bug in 7260, 3160 and 7265.
156 * @scd_chain_ext_wa: should the chain extension feature in SCD be disabled.
157 * @max_tfd_queue_size: max number of entries in tfd queue.
158 * @eeprom_size: EEPROM size
159 * @num_of_queues: number of HW TX queues supported
160 * @pcie_l1_allowed: PCIe L1 state is allowed
161 * @pll_cfg: PLL configuration needed
162 * @nvm_hw_section_num: the ID of the HW NVM section
163 * @features: hw features, any combination of feature_passlist
164 * @smem_offset: offset from which the SMEM begins
165 * @smem_len: the length of SMEM
166 * @mac_addr_from_csr: read HW address from CSR registers at this offset
167 * @d3_debug_data_base_addr: base address where D3 debug data is stored
168 * @d3_debug_data_length: length of the D3 debug data
169 * @min_ba_txq_size: minimum number of slots required in a TX queue used
170 *	for aggregation
171 * @min_txq_size: minimum number of slots required in a TX queue
172 * @gp2_reg_addr: GP2 (timer) register address
173 * @mon_dbgi_regs: monitor DBGI registers
174 * @mon_dram_regs: monitor DRAM registers
175 * @mon_smem_regs: monitor SMEM registers
176 * @ucode_api_max: Highest version of uCode API supported by driver.
177 * @ucode_api_min: Lowest version of uCode API supported by driver.
178 */
179struct iwl_family_base_params {
180	unsigned int wd_timeout;
181
182	u16 eeprom_size;
183	u16 max_event_log_size;
184
185	u8 pll_cfg:1, /* for iwl_pcie_apm_init() */
186	   shadow_ram_support:1,
187	   shadow_reg_enable:1,
188	   pcie_l1_allowed:1,
189	   apmg_wake_up_wa:1,
190	   apmg_not_supported:1,
191	   scd_chain_ext_wa:1;
192
193	u16 num_of_queues;	/* def: HW dependent */
194	u32 max_tfd_queue_size;	/* def: HW dependent */
195
196	u8 max_ll_items;
197	u8 led_compensation;
198	u16 ucode_api_max;
199	u16 ucode_api_min;
200	u32 mac_addr_from_csr:10;
201	u8 nvm_hw_section_num;
202	netdev_features_t features;
203	u32 smem_offset;
204	u32 smem_len;
205	u32 d3_debug_data_base_addr;
206	u32 d3_debug_data_length;
207	u32 min_txq_size;
208	u32 gp2_reg_addr;
209	u32 min_ba_txq_size;
210	const struct iwl_fw_mon_regs mon_dram_regs;
211	const struct iwl_fw_mon_regs mon_smem_regs;
212	const struct iwl_fw_mon_regs mon_dbgi_regs;
213};
214
215/*
216 * FW is released as "core N release", and we used to have a
217 * gap of 3 between the API version and core number. Now the
218 * reported API version will be 1000 + core and we encode it
219 * in the filename as "c<core>".
220 */
221#define API_IS_CORE_START		1000
222#define API_TO_CORE_OFFS		3
223#define ENCODE_CORE_AS_API(core)	(API_IS_CORE_START + (core))
224
225static inline bool iwl_api_is_core_number(int api)
226{
227	return api >= API_IS_CORE_START;
228}
229
230static inline int iwl_api_to_core(int api)
231{
232	if (iwl_api_is_core_number(api))
233		return api - API_IS_CORE_START;
234
235	return api - API_TO_CORE_OFFS;
236}
237
238#define FW_API_FMT			"%s%d"
239#define FW_API_ARG(n)						\
240	iwl_api_is_core_number(n) ? "c" : "",			\
241	iwl_api_is_core_number(n) ? (n) - API_IS_CORE_START : (n)
242
243/*
244 * @stbc: support Tx STBC and 1*SS Rx STBC
245 * @ldpc: support Tx/Rx with LDPC
246 * @use_rts_for_aggregation: use rts/cts protection for HT traffic
247 * @ht40_bands: bitmap of bands (using %NL80211_BAND_*) that support HT40
248 */
249struct iwl_ht_params {
250	u8 ht_greenfield_support:1,
251	   stbc:1,
252	   ldpc:1,
253	   use_rts_for_aggregation:1;
254	u8 ht40_bands;
255};
256
257/*
258 * Tx-backoff threshold
259 * @temperature: The threshold in Celsius
260 * @backoff: The tx-backoff in uSec
261 */
262struct iwl_tt_tx_backoff {
263	s32 temperature;
264	u32 backoff;
265};
266
267#define TT_TX_BACKOFF_SIZE 6
268
269/**
270 * struct iwl_tt_params - thermal throttling parameters
271 * @ct_kill_entry: CT Kill entry threshold
272 * @ct_kill_exit: CT Kill exit threshold
273 * @ct_kill_duration: The time  intervals (in uSec) in which the driver needs
274 *	to checks whether to exit CT Kill.
275 * @dynamic_smps_entry: Dynamic SMPS entry threshold
276 * @dynamic_smps_exit: Dynamic SMPS exit threshold
277 * @tx_protection_entry: TX protection entry threshold
278 * @tx_protection_exit: TX protection exit threshold
279 * @tx_backoff: Array of thresholds for tx-backoff , in ascending order.
280 * @support_ct_kill: Support CT Kill?
281 * @support_dynamic_smps: Support dynamic SMPS?
282 * @support_tx_protection: Support tx protection?
283 * @support_tx_backoff: Support tx-backoff?
284 */
285struct iwl_tt_params {
286	u32 ct_kill_entry;
287	u32 ct_kill_exit;
288	u32 ct_kill_duration;
289	u32 dynamic_smps_entry;
290	u32 dynamic_smps_exit;
291	u32 tx_protection_entry;
292	u32 tx_protection_exit;
293	struct iwl_tt_tx_backoff tx_backoff[TT_TX_BACKOFF_SIZE];
294	u8 support_ct_kill:1,
295	   support_dynamic_smps:1,
296	   support_tx_protection:1,
297	   support_tx_backoff:1;
298};
299
300/*
301 * information on how to parse the EEPROM
302 */
303#define EEPROM_REG_BAND_1_CHANNELS		0x08
304#define EEPROM_REG_BAND_2_CHANNELS		0x26
305#define EEPROM_REG_BAND_3_CHANNELS		0x42
306#define EEPROM_REG_BAND_4_CHANNELS		0x5C
307#define EEPROM_REG_BAND_5_CHANNELS		0x74
308#define EEPROM_REG_BAND_24_HT40_CHANNELS	0x82
309#define EEPROM_REG_BAND_52_HT40_CHANNELS	0x92
310#define EEPROM_6000_REG_BAND_24_HT40_CHANNELS	0x80
311#define EEPROM_REGULATORY_BAND_NO_HT40		0
312
313/* lower blocks contain EEPROM image and calibration data */
314#define OTP_LOW_IMAGE_SIZE_2K		(2 * 512 * sizeof(u16))  /*  2 KB */
315#define OTP_LOW_IMAGE_SIZE_16K		(16 * 512 * sizeof(u16)) /* 16 KB */
316#define OTP_LOW_IMAGE_SIZE_32K		(32 * 512 * sizeof(u16)) /* 32 KB */
317
318struct iwl_eeprom_params {
319	const u8 regulatory_bands[7];
320	bool enhanced_txpower;
321};
322
323/* Tx-backoff power threshold
324 * @pwr: The power limit in mw
325 * @backoff: The tx-backoff in uSec
326 */
327struct iwl_pwr_tx_backoff {
328	u32 pwr;
329	u32 backoff;
330};
331
332enum iwl_mac_cfg_ltr_delay {
333	IWL_CFG_TRANS_LTR_DELAY_NONE	= 0,
334	IWL_CFG_TRANS_LTR_DELAY_200US	= 1,
335	IWL_CFG_TRANS_LTR_DELAY_2500US	= 2,
336	IWL_CFG_TRANS_LTR_DELAY_1820US	= 3,
337};
338
339/**
340 * struct iwl_mac_cfg - information about the MAC-specific device part
341 *
342 * These values are specific to the device ID and do not change when
343 * multiple configs are used for a single device ID.  They values are
344 * used, among other things, to boot the NIC so that the HW REV or
345 * RFID can be read before deciding the remaining parameters to use.
346 *
347 * @base: pointer to basic parameters
348 * @device_family: the device family
349 * @umac_prph_offset: offset to add to UMAC periphery address
350 * @xtal_latency: power up latency to get the xtal stabilized
351 * @extra_phy_cfg_flags: extra configuration flags to pass to the PHY
352 * @gen2: 22000 and on transport operation
353 * @mq_rx_supported: multi-queue rx support
354 * @integrated: discrete or integrated
355 * @low_latency_xtal: use the low latency xtal if supported
356 * @bisr_workaround: BISR hardware workaround (for 22260 series devices)
357 * @ltr_delay: LTR delay parameter, &enum iwl_mac_cfg_ltr_delay.
358 * @imr_enabled: use the IMR if supported.
359 */
360struct iwl_mac_cfg {
361	const struct iwl_family_base_params *base;
362	enum iwl_device_family device_family;
363	u32 umac_prph_offset;
364	u32 xtal_latency;
365	u32 extra_phy_cfg_flags;
366	u32 gen2:1,
367	    mq_rx_supported:1,
368	    integrated:1,
369	    low_latency_xtal:1,
370	    bisr_workaround:1,
371	    ltr_delay:2,
372	    imr_enabled:1;
373};
374
375/*
376 * These sizes were picked according to 8 MSDUs inside 64/256/612 A-MSDUs
377 * in an A-MPDU, with additional overhead to account for processing time.
378 * They will be doubled for MACs starting from So/Ty that don't support
379 * putting multiple frames into a single buffer.
380 */
381#define IWL_NUM_RBDS_NON_HE		(64 * 8)
382#define IWL_NUM_RBDS_HE			(256 * 8)
383#define IWL_NUM_RBDS_EHT		(512 * 8)
384
385/**
386 * struct iwl_rf_cfg - RF/CRF configuration data
387 * @fw_name_pre: Firmware filename prefix. The api version and extension
388 *	(.ucode) will be added to filename before loading from disk. The
389 *	filename is constructed as <fw_name_pre>-<api>.ucode.
390 *	name will be generated dynamically
391 * @ucode_api_max: Highest version of uCode API supported by driver.
392 * @ucode_api_min: Lowest version of uCode API supported by driver.
393 * @max_inst_size: The maximal length of the fw inst section (only DVM)
394 * @max_data_size: The maximal length of the fw data section (only DVM)
395 * @valid_tx_ant: valid transmit antenna
396 * @valid_rx_ant: valid receive antenna
397 * @non_shared_ant: the antenna that is for WiFi only
398 * @nvm_ver: NVM version
399 * @nvm_calib_ver: NVM calibration version
400 * @bw_limit: bandwidth limit for this device, if non-zero
401 * @ht_params: point to ht parameters
402 * @eeprom_params: EEPROM parameters (old devices)
403 * @thermal_params: Thermal throttling parameters
404 * @lp_xtal_workaround: low-power crystal workaround needed
405 * @led_mode: 0=blinking, 1=On(RF On)/Off(RF Off)
406 * @rx_with_siso_diversity: 1x1 device with rx antenna diversity
407 * @tx_with_siso_diversity: 1x1 device with tx antenna diversity
408 * @internal_wimax_coex: internal wifi/wimax combo device
409 * @host_interrupt_operation_mode: device needs host interrupt operation
410 *	mode set
411 * @pwr_tx_backoffs: translation table between power limits and backoffs
412 * @dccm_offset: offset from which DCCM begins
413 * @dccm_len: length of DCCM (including runtime stack CCM)
414 * @dccm2_offset: offset from which the second DCCM begins
415 * @dccm2_len: length of the second DCCM
416 * @vht_mu_mimo_supported: VHT MU-MIMO support
417 * @nvm_type: see &enum iwl_nvm_type
418 * @uhb_supported: ultra high band channels supported
419 * @eht_supported: EHT supported
420 * @num_rbds: number of receive buffer descriptors to use
421 *	(only used for multi-queue capable devices)
422 *
423 * We enable the driver to be backward compatible wrt. hardware features.
424 * API differences in uCode shouldn't be handled here but through TLVs
425 * and/or the uCode API version instead.
426 */
427struct iwl_rf_cfg {
428	/* params specific to an individual device within a device family */
429	const char *fw_name_pre;
430	/* params likely to change within a device family */
431	const struct iwl_ht_params ht_params;
432	const struct iwl_eeprom_params *eeprom_params;
433	const struct iwl_pwr_tx_backoff *pwr_tx_backoffs;
434	const struct iwl_tt_params *thermal_params;
435	enum iwl_led_mode led_mode;
436	enum iwl_nvm_type nvm_type;
437	u32 max_data_size;
438	u32 max_inst_size;
439	u32 dccm_offset;
440	u32 dccm_len;
441	u32 dccm2_offset;
442	u32 dccm2_len;
443	u16 nvm_ver;
444	u16 nvm_calib_ver;
445	u16 bw_limit;
446	u32 rx_with_siso_diversity:1,
447	    tx_with_siso_diversity:1,
448	    internal_wimax_coex:1,
449	    host_interrupt_operation_mode:1,
450	    lp_xtal_workaround:1,
451	    vht_mu_mimo_supported:1,
452	    uhb_supported:1,
453	    eht_supported:1;
454	u8 valid_tx_ant;
455	u8 valid_rx_ant;
456	u8 non_shared_ant;
457	u16 ucode_api_max;
458	u16 ucode_api_min;
459	u16 num_rbds;
460};
461
462#define IWL_CFG_ANY (~0)
463
464#define IWL_CFG_MAC_TYPE_PU		0x31
465#define IWL_CFG_MAC_TYPE_TH		0x32
466#define IWL_CFG_MAC_TYPE_QU		0x33
467#define IWL_CFG_MAC_TYPE_CC		0x34
468#define IWL_CFG_MAC_TYPE_QUZ		0x35
469#define IWL_CFG_MAC_TYPE_SO		0x37
470#define IWL_CFG_MAC_TYPE_TY		0x42
471#define IWL_CFG_MAC_TYPE_SOF		0x43
472#define IWL_CFG_MAC_TYPE_MA		0x44
473#define IWL_CFG_MAC_TYPE_BZ		0x46
474#define IWL_CFG_MAC_TYPE_GL		0x47
475#define IWL_CFG_MAC_TYPE_SC		0x48
476#define IWL_CFG_MAC_TYPE_SC2		0x49
477#define IWL_CFG_MAC_TYPE_SC2F		0x4A
478#define IWL_CFG_MAC_TYPE_BZ_W		0x4B
479#define IWL_CFG_MAC_TYPE_BR		0x4C
480#define IWL_CFG_MAC_TYPE_DR		0x4D
481
482#define IWL_CFG_RF_TYPE_JF2		0x105
483#define IWL_CFG_RF_TYPE_JF1		0x108
484#define IWL_CFG_RF_TYPE_HR2		0x10A
485#define IWL_CFG_RF_TYPE_HR1		0x10C
486#define IWL_CFG_RF_TYPE_GF		0x10D
487#define IWL_CFG_RF_TYPE_FM		0x112
488#define IWL_CFG_RF_TYPE_WH		0x113
489#define IWL_CFG_RF_TYPE_PE		0x114
490
491#define IWL_CFG_RF_ID_TH		0x1
492#define IWL_CFG_RF_ID_TH1		0x1
493#define IWL_CFG_RF_ID_JF		0x3
494#define IWL_CFG_RF_ID_JF1		0x6
495#define IWL_CFG_RF_ID_JF1_DIV		0xA
496#define IWL_CFG_RF_ID_HR		0x7
497#define IWL_CFG_RF_ID_HR1		0x4
498
499#define IWL_CFG_CORES_BT		0x0
500#define IWL_CFG_CORES_BT_GNSS		0x5
501
502#define IWL_CFG_NO_CDB			0x0
503#define IWL_CFG_CDB			0x1
504
505#define IWL_CFG_NO_JACKET		0x0
506#define IWL_CFG_IS_JACKET		0x1
507
508#define IWL_SUBDEVICE_RF_ID(subdevice)	((u16)((subdevice) & 0x00F0) >> 4)
509#define IWL_SUBDEVICE_BW_LIM(subdevice)	((u16)((subdevice) & 0x0200) >> 9)
510#define IWL_SUBDEVICE_CORES(subdevice)	((u16)((subdevice) & 0x1C00) >> 10)
511
512struct iwl_dev_info {
513	const struct iwl_rf_cfg *cfg;
514	const char *name;
515	u16 device;
516	u16 subdevice;
517	u32 subdevice_m_l:4,
518	    subdevice_m_h:4,
519	    match_rf_type:1,
520	    rf_type:9,
521	    match_bw_limit:1,
522	    bw_limit:1,
523	    match_discrete:1,
524	    discrete:1,
525	    match_rf_id:1,
526	    rf_id:4,
527	    match_cdb:1,
528	    cdb:1;
529};
530
531#if IS_ENABLED(CONFIG_IWLWIFI_KUNIT_TESTS)
532extern const struct iwl_dev_info iwl_dev_info_table[];
533extern const unsigned int iwl_dev_info_table_size;
534extern const struct pci_device_id iwl_hw_card_ids[];
535#endif
536
537const struct iwl_dev_info *
538iwl_pci_find_dev_info(u16 device, u16 subsystem_device, u16 rf_type, u8 cdb,
539		      u8 rf_id, u8 bw_limit, bool discrete);
540
541/*
542 * This list declares the config structures for all devices.
543 */
544extern const struct iwl_mac_cfg iwl1000_mac_cfg;
545extern const struct iwl_mac_cfg iwl5000_mac_cfg;
546extern const struct iwl_mac_cfg iwl2000_mac_cfg;
547extern const struct iwl_mac_cfg iwl2030_mac_cfg;
548extern const struct iwl_mac_cfg iwl105_mac_cfg;
549extern const struct iwl_mac_cfg iwl135_mac_cfg;
550extern const struct iwl_mac_cfg iwl5150_mac_cfg;
551extern const struct iwl_mac_cfg iwl6005_mac_cfg;
552extern const struct iwl_mac_cfg iwl6030_mac_cfg;
553extern const struct iwl_mac_cfg iwl6000i_mac_cfg;
554extern const struct iwl_mac_cfg iwl6050_mac_cfg;
555extern const struct iwl_mac_cfg iwl6150_mac_cfg;
556extern const struct iwl_mac_cfg iwl6000_mac_cfg;
557extern const struct iwl_mac_cfg iwl7000_mac_cfg;
558extern const struct iwl_mac_cfg iwl8000_mac_cfg;
559extern const struct iwl_mac_cfg iwl9000_mac_cfg;
560extern const struct iwl_mac_cfg iwl9560_mac_cfg;
561extern const struct iwl_mac_cfg iwl9560_long_latency_mac_cfg;
562extern const struct iwl_mac_cfg iwl9560_shared_clk_mac_cfg;
563extern const struct iwl_mac_cfg iwl_qu_mac_cfg;
564extern const struct iwl_mac_cfg iwl_qu_medium_latency_mac_cfg;
565extern const struct iwl_mac_cfg iwl_qu_long_latency_mac_cfg;
566extern const struct iwl_mac_cfg iwl_ax200_mac_cfg;
567extern const struct iwl_mac_cfg iwl_ty_mac_cfg;
568extern const struct iwl_mac_cfg iwl_so_mac_cfg;
569extern const struct iwl_mac_cfg iwl_so_long_latency_mac_cfg;
570extern const struct iwl_mac_cfg iwl_so_long_latency_imr_mac_cfg;
571extern const struct iwl_mac_cfg iwl_ma_mac_cfg;
572extern const struct iwl_mac_cfg iwl_bz_mac_cfg;
573extern const struct iwl_mac_cfg iwl_gl_mac_cfg;
574extern const struct iwl_mac_cfg iwl_sc_mac_cfg;
575extern const struct iwl_mac_cfg iwl_dr_mac_cfg;
576
577extern const char iwl1000_bgn_name[];
578extern const char iwl1000_bg_name[];
579extern const char iwl100_bgn_name[];
580extern const char iwl100_bg_name[];
581extern const char iwl2000_2bgn_name[];
582extern const char iwl2000_2bgn_d_name[];
583extern const char iwl2030_2bgn_name[];
584extern const char iwl105_bgn_name[];
585extern const char iwl105_bgn_d_name[];
586extern const char iwl135_bgn_name[];
587extern const char iwl5300_agn_name[];
588extern const char iwl5100_bgn_name[];
589extern const char iwl5100_abg_name[];
590extern const char iwl5100_agn_name[];
591extern const char iwl5350_agn_name[];
592extern const char iwl5150_agn_name[];
593extern const char iwl5150_abg_name[];
594extern const char iwl6005_2agn_name[];
595extern const char iwl6005_2abg_name[];
596extern const char iwl6005_2bg_name[];
597extern const char iwl6005_2agn_sff_name[];
598extern const char iwl6005_2agn_d_name[];
599extern const char iwl6005_2agn_mow1_name[];
600extern const char iwl6005_2agn_mow2_name[];
601extern const char iwl6030_2agn_name[];
602extern const char iwl6030_2abg_name[];
603extern const char iwl6030_2bgn_name[];
604extern const char iwl6030_2bg_name[];
605extern const char iwl6035_2agn_name[];
606extern const char iwl6035_2agn_sff_name[];
607extern const char iwl1030_bgn_name[];
608extern const char iwl1030_bg_name[];
609extern const char iwl130_bgn_name[];
610extern const char iwl130_bg_name[];
611extern const char iwl6000i_2agn_name[];
612extern const char iwl6000i_2abg_name[];
613extern const char iwl6000i_2bg_name[];
614extern const char iwl6050_2agn_name[];
615extern const char iwl6050_2abg_name[];
616extern const char iwl6150_bgn_name[];
617extern const char iwl6150_bg_name[];
618extern const char iwl6000_3agn_name[];
619extern const char iwl7260_2ac_name[];
620extern const char iwl7260_2n_name[];
621extern const char iwl7260_n_name[];
622extern const char iwl3160_2ac_name[];
623extern const char iwl3160_2n_name[];
624extern const char iwl3160_n_name[];
625extern const char iwl3165_2ac_name[];
626extern const char iwl3168_2ac_name[];
627extern const char iwl7265_2ac_name[];
628extern const char iwl7265_2n_name[];
629extern const char iwl7265_n_name[];
630extern const char iwl8260_2n_name[];
631extern const char iwl8260_2ac_name[];
632extern const char iwl8265_2ac_name[];
633extern const char iwl8275_2ac_name[];
634extern const char iwl4165_2ac_name[];
635extern const char iwl_killer_1435i_name[];
636extern const char iwl_killer_1434_kix_name[];
637extern const char iwl9162_name[];
638extern const char iwl9260_name[];
639extern const char iwl9260_1_name[];
640extern const char iwl9270_name[];
641extern const char iwl9461_name[];
642extern const char iwl9462_name[];
643extern const char iwl9560_name[];
644extern const char iwl9162_160_name[];
645extern const char iwl9260_160_name[];
646extern const char iwl9270_160_name[];
647extern const char iwl9461_160_name[];
648extern const char iwl9462_160_name[];
649extern const char iwl9560_160_name[];
650extern const char iwl9260_killer_1550_name[];
651extern const char iwl9560_killer_1550i_name[];
652extern const char iwl9560_killer_1550s_name[];
653extern const char iwl_ax200_name[];
654extern const char iwl_ax203_name[];
655extern const char iwl_ax201_name[];
656extern const char iwl_ax101_name[];
657extern const char iwl_ax200_killer_1650w_name[];
658extern const char iwl_ax200_killer_1650x_name[];
659extern const char iwl_ax201_killer_1650s_name[];
660extern const char iwl_ax201_killer_1650i_name[];
661extern const char iwl_ax210_killer_1675w_name[];
662extern const char iwl_ax210_killer_1675x_name[];
663extern const char iwl9560_killer_1550i_160_name[];
664extern const char iwl9560_killer_1550s_160_name[];
665extern const char iwl_ax211_killer_1675s_name[];
666extern const char iwl_ax211_killer_1675i_name[];
667extern const char iwl_ax411_killer_1690s_name[];
668extern const char iwl_ax411_killer_1690i_name[];
669extern const char iwl_ax210_name[];
670extern const char iwl_ax211_name[];
671extern const char iwl_ax411_name[];
672extern const char iwl_killer_be1750s_name[];
673extern const char iwl_killer_be1750i_name[];
674extern const char iwl_killer_be1750w_name[];
675extern const char iwl_killer_be1750x_name[];
676extern const char iwl_killer_be1790s_name[];
677extern const char iwl_killer_be1790i_name[];
678extern const char iwl_be201_name[];
679extern const char iwl_be200_name[];
680extern const char iwl_be202_name[];
681extern const char iwl_be401_name[];
682extern const char iwl_be213_name[];
683extern const char iwl_killer_be1775s_name[];
684extern const char iwl_killer_be1775i_name[];
685extern const char iwl_be211_name[];
686extern const char iwl_killer_bn1850w2_name[];
687extern const char iwl_killer_bn1850i_name[];
688extern const char iwl_bn201_name[];
689extern const char iwl_bn203_name[];
690extern const char iwl_be221_name[];
691extern const char iwl_be223_name[];
692extern const char iwl_ax221_name[];
693#if IS_ENABLED(CONFIG_IWLDVM)
694extern const struct iwl_rf_cfg iwl5300_agn_cfg;
695extern const struct iwl_rf_cfg iwl5350_agn_cfg;
696extern const struct iwl_rf_cfg iwl5100_n_cfg;
697extern const struct iwl_rf_cfg iwl5100_abg_cfg;
698extern const struct iwl_rf_cfg iwl5150_agn_cfg;
699extern const struct iwl_rf_cfg iwl5150_abg_cfg;
700extern const struct iwl_rf_cfg iwl6005_non_n_cfg;
701extern const struct iwl_rf_cfg iwl6005_n_cfg;
702extern const struct iwl_rf_cfg iwl6030_n_cfg;
703extern const struct iwl_rf_cfg iwl6030_non_n_cfg;
704extern const struct iwl_rf_cfg iwl6000i_2agn_cfg;
705extern const struct iwl_rf_cfg iwl6000i_non_n_cfg;
706extern const struct iwl_rf_cfg iwl6000i_non_n_cfg;
707extern const struct iwl_rf_cfg iwl6000_3agn_cfg;
708extern const struct iwl_rf_cfg iwl6050_2agn_cfg;
709extern const struct iwl_rf_cfg iwl6050_2abg_cfg;
710extern const struct iwl_rf_cfg iwl6150_bgn_cfg;
711extern const struct iwl_rf_cfg iwl6150_bg_cfg;
712extern const struct iwl_rf_cfg iwl1000_bgn_cfg;
713extern const struct iwl_rf_cfg iwl1000_bg_cfg;
714extern const struct iwl_rf_cfg iwl100_bgn_cfg;
715extern const struct iwl_rf_cfg iwl100_bg_cfg;
716extern const struct iwl_rf_cfg iwl130_bgn_cfg;
717extern const struct iwl_rf_cfg iwl130_bg_cfg;
718extern const struct iwl_rf_cfg iwl2000_2bgn_cfg;
719extern const struct iwl_rf_cfg iwl2030_2bgn_cfg;
720extern const struct iwl_rf_cfg iwl6035_2agn_cfg;
721extern const struct iwl_rf_cfg iwl105_bgn_cfg;
722extern const struct iwl_rf_cfg iwl135_bgn_cfg;
723#endif /* CONFIG_IWLDVM */
724#if IS_ENABLED(CONFIG_IWLMVM)
725extern const struct iwl_rf_cfg iwl7260_cfg;
726extern const struct iwl_rf_cfg iwl7260_high_temp_cfg;
727extern const struct iwl_rf_cfg iwl3160_cfg;
728extern const struct iwl_rf_cfg iwl3165_2ac_cfg;
729extern const struct iwl_rf_cfg iwl3168_2ac_cfg;
730extern const struct iwl_rf_cfg iwl7265_cfg;
731extern const struct iwl_rf_cfg iwl7265d_cfg;
732extern const struct iwl_rf_cfg iwl8260_cfg;
733extern const struct iwl_rf_cfg iwl8265_cfg;
734extern const struct iwl_rf_cfg iwl_rf_jf;
735extern const struct iwl_rf_cfg iwl_rf_jf_80mhz;
736extern const struct iwl_rf_cfg iwl_rf_hr1;
737extern const struct iwl_rf_cfg iwl_rf_hr;
738extern const struct iwl_rf_cfg iwl_rf_hr_80mhz;
739
740extern const struct iwl_rf_cfg iwl_rf_gf;
741#endif /* CONFIG_IWLMVM */
742
743#if IS_ENABLED(CONFIG_IWLMLD)
744extern const struct iwl_rf_cfg iwl_rf_fm;
745extern const struct iwl_rf_cfg iwl_rf_fm_160mhz;
746#define iwl_rf_wh iwl_rf_fm
747#define iwl_rf_wh_160mhz iwl_rf_fm_160mhz
748extern const struct iwl_rf_cfg iwl_rf_wh_non_eht;
749#define iwl_rf_pe iwl_rf_fm
750#endif /* CONFIG_IWLMLD */
751
752#endif /* __IWL_CONFIG_H__ */