rs.h

  1/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
  2/*
  3 * Copyright (C) 2012-2014, 2018-2022, 2024-2025 Intel Corporation
  4 * Copyright (C) 2017 Intel Deutschland GmbH
  5 */
  6#ifndef __iwl_fw_api_rs_h__
  7#define __iwl_fw_api_rs_h__
  8#include <linux/bitfield.h>
  9#include <linux/types.h>
 10#include <linux/bits.h>
 11#include "mac.h"
 12
 13/**
 14 * enum iwl_tlc_mng_cfg_flags - options for TLC config flags
 15 * @IWL_TLC_MNG_CFG_FLAGS_STBC_MSK: enable STBC. For HE this enables STBC for
 16 *				    bandwidths <= 80MHz
 17 * @IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK: enable LDPC
 18 * @IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK: enable STBC in HE at 160MHz
 19 *					      bandwidth
 20 * @IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK: enable HE Dual Carrier Modulation
 21 *					    for BPSK (MCS 0) with 1 spatial
 22 *					    stream
 23 * @IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK: enable HE Dual Carrier Modulation
 24 *					    for BPSK (MCS 0) with 2 spatial
 25 *					    streams
 26 * @IWL_TLC_MNG_CFG_FLAGS_EHT_EXTRA_LTF_MSK: enable support for EHT extra LTF
 27 * @IWL_TLC_MNG_CFG_FLAGS_UHR_ELR_1_5_MBPS_MSK: support ELR 1.5 Mbps
 28 * @IWL_TLC_MNG_CFG_FLAGS_UHR_ELR_3_MBPS_MSK: support ELR 3 Mbps
 29 */
 30enum iwl_tlc_mng_cfg_flags {
 31	IWL_TLC_MNG_CFG_FLAGS_STBC_MSK			= BIT(0),
 32	IWL_TLC_MNG_CFG_FLAGS_LDPC_MSK			= BIT(1),
 33	IWL_TLC_MNG_CFG_FLAGS_HE_STBC_160MHZ_MSK	= BIT(2),
 34	IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_1_MSK		= BIT(3),
 35	IWL_TLC_MNG_CFG_FLAGS_HE_DCM_NSS_2_MSK		= BIT(4),
 36	IWL_TLC_MNG_CFG_FLAGS_EHT_EXTRA_LTF_MSK		= BIT(6),
 37	IWL_TLC_MNG_CFG_FLAGS_UHR_ELR_1_5_MBPS_MSK	= BIT(7),
 38	IWL_TLC_MNG_CFG_FLAGS_UHR_ELR_3_MBPS_MSK	= BIT(8),
 39};
 40
 41/**
 42 * enum iwl_tlc_mng_cfg_cw - channel width options
 43 * @IWL_TLC_MNG_CH_WIDTH_20MHZ: 20MHZ channel
 44 * @IWL_TLC_MNG_CH_WIDTH_40MHZ: 40MHZ channel
 45 * @IWL_TLC_MNG_CH_WIDTH_80MHZ: 80MHZ channel
 46 * @IWL_TLC_MNG_CH_WIDTH_160MHZ: 160MHZ channel
 47 * @IWL_TLC_MNG_CH_WIDTH_320MHZ: 320MHZ channel
 48 */
 49enum iwl_tlc_mng_cfg_cw {
 50	IWL_TLC_MNG_CH_WIDTH_20MHZ,
 51	IWL_TLC_MNG_CH_WIDTH_40MHZ,
 52	IWL_TLC_MNG_CH_WIDTH_80MHZ,
 53	IWL_TLC_MNG_CH_WIDTH_160MHZ,
 54	IWL_TLC_MNG_CH_WIDTH_320MHZ,
 55};
 56
 57/**
 58 * enum iwl_tlc_mng_cfg_chains - possible chains
 59 * @IWL_TLC_MNG_CHAIN_A_MSK: chain A
 60 * @IWL_TLC_MNG_CHAIN_B_MSK: chain B
 61 */
 62enum iwl_tlc_mng_cfg_chains {
 63	IWL_TLC_MNG_CHAIN_A_MSK = BIT(0),
 64	IWL_TLC_MNG_CHAIN_B_MSK = BIT(1),
 65};
 66
 67/**
 68 * enum iwl_tlc_mng_cfg_mode - supported modes
 69 * @IWL_TLC_MNG_MODE_CCK: enable CCK
 70 * @IWL_TLC_MNG_MODE_OFDM_NON_HT: enable OFDM (non HT)
 71 * @IWL_TLC_MNG_MODE_NON_HT: enable non HT
 72 * @IWL_TLC_MNG_MODE_HT: enable HT
 73 * @IWL_TLC_MNG_MODE_VHT: enable VHT
 74 * @IWL_TLC_MNG_MODE_HE: enable HE
 75 * @IWL_TLC_MNG_MODE_EHT: enable EHT
 76 */
 77enum iwl_tlc_mng_cfg_mode {
 78	IWL_TLC_MNG_MODE_CCK = 0,
 79	IWL_TLC_MNG_MODE_OFDM_NON_HT = IWL_TLC_MNG_MODE_CCK,
 80	IWL_TLC_MNG_MODE_NON_HT = IWL_TLC_MNG_MODE_CCK,
 81	IWL_TLC_MNG_MODE_HT,
 82	IWL_TLC_MNG_MODE_VHT,
 83	IWL_TLC_MNG_MODE_HE,
 84	IWL_TLC_MNG_MODE_EHT,
 85};
 86
 87/**
 88 * enum iwl_tlc_mng_ht_rates - HT/VHT/HE rates
 89 * @IWL_TLC_MNG_HT_RATE_MCS0: index of MCS0
 90 * @IWL_TLC_MNG_HT_RATE_MCS1: index of MCS1
 91 * @IWL_TLC_MNG_HT_RATE_MCS2: index of MCS2
 92 * @IWL_TLC_MNG_HT_RATE_MCS3: index of MCS3
 93 * @IWL_TLC_MNG_HT_RATE_MCS4: index of MCS4
 94 * @IWL_TLC_MNG_HT_RATE_MCS5: index of MCS5
 95 * @IWL_TLC_MNG_HT_RATE_MCS6: index of MCS6
 96 * @IWL_TLC_MNG_HT_RATE_MCS7: index of MCS7
 97 * @IWL_TLC_MNG_HT_RATE_MCS8: index of MCS8
 98 * @IWL_TLC_MNG_HT_RATE_MCS9: index of MCS9
 99 * @IWL_TLC_MNG_HT_RATE_MCS10: index of MCS10
100 * @IWL_TLC_MNG_HT_RATE_MCS11: index of MCS11
101 * @IWL_TLC_MNG_HT_RATE_MAX: maximal rate for HT/VHT
102 */
103enum iwl_tlc_mng_ht_rates {
104	IWL_TLC_MNG_HT_RATE_MCS0 = 0,
105	IWL_TLC_MNG_HT_RATE_MCS1,
106	IWL_TLC_MNG_HT_RATE_MCS2,
107	IWL_TLC_MNG_HT_RATE_MCS3,
108	IWL_TLC_MNG_HT_RATE_MCS4,
109	IWL_TLC_MNG_HT_RATE_MCS5,
110	IWL_TLC_MNG_HT_RATE_MCS6,
111	IWL_TLC_MNG_HT_RATE_MCS7,
112	IWL_TLC_MNG_HT_RATE_MCS8,
113	IWL_TLC_MNG_HT_RATE_MCS9,
114	IWL_TLC_MNG_HT_RATE_MCS10,
115	IWL_TLC_MNG_HT_RATE_MCS11,
116	IWL_TLC_MNG_HT_RATE_MAX = IWL_TLC_MNG_HT_RATE_MCS11,
117};
118
119enum IWL_TLC_MNG_NSS {
120	IWL_TLC_NSS_1,
121	IWL_TLC_NSS_2,
122	IWL_TLC_NSS_MAX
123};
124
125/**
126 * enum IWL_TLC_MCS_PER_BW - mcs index per BW
127 * @IWL_TLC_MCS_PER_BW_80: mcs for bw - 20Hhz, 40Hhz, 80Hhz
128 * @IWL_TLC_MCS_PER_BW_160: mcs for bw - 160Mhz
129 * @IWL_TLC_MCS_PER_BW_320: mcs for bw - 320Mhz
130 * @IWL_TLC_MCS_PER_BW_NUM_V3: number of entries up to version 3
131 * @IWL_TLC_MCS_PER_BW_NUM_V4: number of entries from version 4
132 */
133enum IWL_TLC_MCS_PER_BW {
134	IWL_TLC_MCS_PER_BW_80,
135	IWL_TLC_MCS_PER_BW_160,
136	IWL_TLC_MCS_PER_BW_320,
137	IWL_TLC_MCS_PER_BW_NUM_V3 = IWL_TLC_MCS_PER_BW_160 + 1,
138	IWL_TLC_MCS_PER_BW_NUM_V4 = IWL_TLC_MCS_PER_BW_320 + 1,
139};
140
141/**
142 * struct iwl_tlc_config_cmd_v3 - TLC configuration
143 * @sta_id: station id
144 * @reserved1: reserved
145 * @max_ch_width: max supported channel width from @enum iwl_tlc_mng_cfg_cw
146 * @mode: &enum iwl_tlc_mng_cfg_mode
147 * @chains: bitmask of &enum iwl_tlc_mng_cfg_chains
148 * @amsdu: TX amsdu is supported
149 * @flags: bitmask of &enum iwl_tlc_mng_cfg_flags
150 * @non_ht_rates: bitmap of supported legacy rates
151 * @ht_rates: bitmap of &enum iwl_tlc_mng_ht_rates, per &enum IWL_TLC_MCS_PER_BW
152 *	      <nss, channel-width> pair (0 - 80mhz width and below, 1 - 160mhz).
153 * @max_mpdu_len: max MPDU length, in bytes
154 * @sgi_ch_width_supp: bitmap of SGI support per channel width
155 *		       use BIT(@enum iwl_tlc_mng_cfg_cw)
156 * @reserved2: reserved
157 * @max_tx_op: max TXOP in uSecs for all AC (BK, BE, VO, VI),
158 *	       set zero for no limit.
159 */
160struct iwl_tlc_config_cmd_v3 {
161	u8 sta_id;
162	u8 reserved1[3];
163	u8 max_ch_width;
164	u8 mode;
165	u8 chains;
166	u8 amsdu;
167	__le16 flags;
168	__le16 non_ht_rates;
169	__le16 ht_rates[IWL_TLC_NSS_MAX][IWL_TLC_MCS_PER_BW_NUM_V3];
170	__le16 max_mpdu_len;
171	u8 sgi_ch_width_supp;
172	u8 reserved2;
173	__le32 max_tx_op;
174} __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_3 */
175
176/**
177 * struct iwl_tlc_config_cmd_v4 - TLC configuration
178 * @sta_id: station id
179 * @reserved1: reserved
180 * @max_ch_width: max supported channel width from &enum iwl_tlc_mng_cfg_cw
181 * @mode: &enum iwl_tlc_mng_cfg_mode
182 * @chains: bitmask of &enum iwl_tlc_mng_cfg_chains
183 * @sgi_ch_width_supp: bitmap of SGI support per channel width
184 *		       use BIT(&enum iwl_tlc_mng_cfg_cw)
185 * @flags: bitmask of &enum iwl_tlc_mng_cfg_flags
186 * @non_ht_rates: bitmap of supported legacy rates
187 * @ht_rates: bitmap of &enum iwl_tlc_mng_ht_rates, per <nss, channel-width>
188 *	      pair (0 - 80mhz width and below, 1 - 160mhz, 2 - 320mhz).
189 * @max_mpdu_len: max MPDU length, in bytes
190 * @max_tx_op: max TXOP in uSecs for all AC (BK, BE, VO, VI),
191 *	       set zero for no limit.
192 */
193struct iwl_tlc_config_cmd_v4 {
194	u8 sta_id;
195	u8 reserved1[3];
196	u8 max_ch_width;
197	u8 mode;
198	u8 chains;
199	u8 sgi_ch_width_supp;
200	__le16 flags;
201	__le16 non_ht_rates;
202	__le16 ht_rates[IWL_TLC_NSS_MAX][IWL_TLC_MCS_PER_BW_NUM_V4];
203	__le16 max_mpdu_len;
204	__le16 max_tx_op;
205} __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_4 */
206
207/**
208 * struct iwl_tlc_config_cmd - TLC configuration
209 * @sta_id: station id
210 * @reserved1: reserved
211 * @max_ch_width: max supported channel width from &enum iwl_tlc_mng_cfg_cw
212 * @mode: &enum iwl_tlc_mng_cfg_mode
213 * @chains: bitmask of &enum iwl_tlc_mng_cfg_chains
214 * @sgi_ch_width_supp: bitmap of SGI support per channel width
215 *		       use BIT(&enum iwl_tlc_mng_cfg_cw)
216 * @flags: bitmask of &enum iwl_tlc_mng_cfg_flags
217 * @non_ht_rates: bitmap of supported legacy rates
218 * @ht_rates: bitmap of &enum iwl_tlc_mng_ht_rates, per <nss, channel-width>
219 *	      pair (0 - 80mhz width and below, 1 - 160mhz, 2 - 320mhz).
220 * @max_mpdu_len: max MPDU length, in bytes
221 * @max_tx_op: max TXOP in uSecs for all AC (BK, BE, VO, VI),
222 *	       set zero for no limit.
223 */
224struct iwl_tlc_config_cmd {
225	u8 sta_id;
226	u8 reserved1[3];
227	u8 max_ch_width;
228	u8 mode;
229	u8 chains;
230	u8 sgi_ch_width_supp;
231	__le16 flags;
232	__le16 non_ht_rates;
233	__le32 ht_rates[IWL_TLC_NSS_MAX][IWL_TLC_MCS_PER_BW_NUM_V4];
234	__le16 max_mpdu_len;
235	__le16 max_tx_op;
236} __packed; /* TLC_MNG_CONFIG_CMD_API_S_VER_5 */
237
238/**
239 * enum iwl_tlc_update_flags - updated fields
240 * @IWL_TLC_NOTIF_FLAG_RATE: last initial rate update
241 * @IWL_TLC_NOTIF_FLAG_AMSDU: umsdu parameters update
242 */
243enum iwl_tlc_update_flags {
244	IWL_TLC_NOTIF_FLAG_RATE  = BIT(0),
245	IWL_TLC_NOTIF_FLAG_AMSDU = BIT(1),
246};
247
248/**
249 * struct iwl_tlc_update_notif - TLC notification from FW
250 * @sta_id: station id
251 * @reserved: reserved
252 * @flags: bitmap of notifications reported
253 * @rate: current initial rate, format depends on the notification
254 *	version
255 * @amsdu_size: Max AMSDU size, in bytes
256 * @amsdu_enabled: bitmap for per-TID AMSDU enablement
257 */
258struct iwl_tlc_update_notif {
259	u8 sta_id;
260	u8 reserved[3];
261	__le32 flags;
262	__le32 rate;
263	__le32 amsdu_size;
264	__le32 amsdu_enabled;
265} __packed; /* TLC_MNG_UPDATE_NTFY_API_S_VER_2, _VER_3, _VER_4 */
266
267/**
268 * enum iwl_tlc_debug_types - debug options
269 */
270enum iwl_tlc_debug_types {
271	/**
272	 *  @IWL_TLC_DEBUG_FIXED_RATE: set fixed rate for rate scaling
273	 */
274	IWL_TLC_DEBUG_FIXED_RATE,
275	/**
276	 * @IWL_TLC_DEBUG_AGG_DURATION_LIM: time limit for a BA
277	 * session, in usec
278	 */
279	IWL_TLC_DEBUG_AGG_DURATION_LIM,
280	/**
281	 * @IWL_TLC_DEBUG_AGG_FRAME_CNT_LIM: set max number of frames
282	 * in an aggregation
283	 */
284	IWL_TLC_DEBUG_AGG_FRAME_CNT_LIM,
285	/**
286	 * @IWL_TLC_DEBUG_TPC_ENABLED: enable or disable tpc
287	 */
288	IWL_TLC_DEBUG_TPC_ENABLED,
289	/**
290	 * @IWL_TLC_DEBUG_TPC_STATS: get number of frames Tx'ed in each
291	 * tpc step
292	 */
293	IWL_TLC_DEBUG_TPC_STATS,
294	/**
295	 * @IWL_TLC_DEBUG_RTS_DISABLE: disable RTS (bool true/false).
296	 */
297	IWL_TLC_DEBUG_RTS_DISABLE,
298	/**
299	 * @IWL_TLC_DEBUG_PARTIAL_FIXED_RATE: set partial fixed rate to fw
300	 */
301	IWL_TLC_DEBUG_PARTIAL_FIXED_RATE,
302}; /* TLC_MNG_DEBUG_TYPES_API_E */
303
304#define MAX_DATA_IN_DHC_TLC_CMD 10
305
306/**
307 * struct iwl_dhc_tlc_cmd - fixed debug config
308 * @sta_id: bit 0 - enable/disable, bits 1 - 7 hold station id
309 * @reserved1: reserved
310 * @type: type id of %enum iwl_tlc_debug_types
311 * @data: data to send
312 */
313struct iwl_dhc_tlc_cmd {
314	u8 sta_id;
315	u8 reserved1[3];
316	__le32 type;
317	__le32 data[MAX_DATA_IN_DHC_TLC_CMD];
318} __packed; /* TLC_MNG_DEBUG_CMD_S */
319
320#define IWL_MAX_MCS_DISPLAY_SIZE        12
321
322struct iwl_rate_mcs_info {
323	char    mbps[IWL_MAX_MCS_DISPLAY_SIZE];
324	char    mcs[IWL_MAX_MCS_DISPLAY_SIZE];
325};
326
327/*
328 * These serve as indexes into
329 * struct iwl_rate_info fw_rate_idx_to_plcp[IWL_RATE_COUNT];
330 * TODO: avoid overlap between legacy and HT rates
331 */
332enum {
333	IWL_RATE_1M_INDEX = 0,
334	IWL_FIRST_CCK_RATE = IWL_RATE_1M_INDEX,
335	IWL_RATE_2M_INDEX,
336	IWL_RATE_5M_INDEX,
337	IWL_RATE_11M_INDEX,
338	IWL_LAST_CCK_RATE = IWL_RATE_11M_INDEX,
339	IWL_RATE_6M_INDEX,
340	IWL_FIRST_OFDM_RATE = IWL_RATE_6M_INDEX,
341	IWL_RATE_MCS_0_INDEX = IWL_RATE_6M_INDEX,
342	IWL_FIRST_HT_RATE = IWL_RATE_MCS_0_INDEX,
343	IWL_FIRST_VHT_RATE = IWL_RATE_MCS_0_INDEX,
344	IWL_RATE_9M_INDEX,
345	IWL_RATE_12M_INDEX,
346	IWL_RATE_MCS_1_INDEX = IWL_RATE_12M_INDEX,
347	IWL_RATE_18M_INDEX,
348	IWL_RATE_MCS_2_INDEX = IWL_RATE_18M_INDEX,
349	IWL_RATE_24M_INDEX,
350	IWL_RATE_MCS_3_INDEX = IWL_RATE_24M_INDEX,
351	IWL_RATE_36M_INDEX,
352	IWL_RATE_MCS_4_INDEX = IWL_RATE_36M_INDEX,
353	IWL_RATE_48M_INDEX,
354	IWL_RATE_MCS_5_INDEX = IWL_RATE_48M_INDEX,
355	IWL_RATE_54M_INDEX,
356	IWL_RATE_MCS_6_INDEX = IWL_RATE_54M_INDEX,
357	IWL_LAST_NON_HT_RATE = IWL_RATE_54M_INDEX,
358	IWL_RATE_60M_INDEX,
359	IWL_RATE_MCS_7_INDEX = IWL_RATE_60M_INDEX,
360	IWL_LAST_HT_RATE = IWL_RATE_MCS_7_INDEX,
361	IWL_RATE_MCS_8_INDEX,
362	IWL_RATE_MCS_9_INDEX,
363	IWL_LAST_VHT_RATE = IWL_RATE_MCS_9_INDEX,
364	IWL_RATE_MCS_10_INDEX,
365	IWL_RATE_MCS_11_INDEX,
366	IWL_LAST_HE_RATE = IWL_RATE_MCS_11_INDEX,
367	IWL_RATE_COUNT_LEGACY = IWL_LAST_NON_HT_RATE + 1,
368	IWL_RATE_COUNT = IWL_LAST_HE_RATE + 1,
369	IWL_RATE_INVM_INDEX = IWL_RATE_COUNT,
370	IWL_RATE_INVALID = IWL_RATE_COUNT,
371};
372
373#define IWL_RATE_BIT_MSK(r) BIT(IWL_RATE_##r##M_INDEX)
374
375/* fw API values for legacy bit rates, both OFDM and CCK */
376enum {
377	IWL_RATE_6M_PLCP  = 13,
378	IWL_RATE_9M_PLCP  = 15,
379	IWL_RATE_12M_PLCP = 5,
380	IWL_RATE_18M_PLCP = 7,
381	IWL_RATE_24M_PLCP = 9,
382	IWL_RATE_36M_PLCP = 11,
383	IWL_RATE_48M_PLCP = 1,
384	IWL_RATE_54M_PLCP = 3,
385	IWL_RATE_1M_PLCP  = 10,
386	IWL_RATE_2M_PLCP  = 20,
387	IWL_RATE_5M_PLCP  = 55,
388	IWL_RATE_11M_PLCP = 110,
389	IWL_RATE_INVM_PLCP = -1,
390};
391
392/*
393 * rate_n_flags bit fields version 1
394 *
395 * The 32-bit value has different layouts in the low 8 bites depending on the
396 * format. There are three formats, HT, VHT and legacy (11abg, with subformats
397 * for CCK and OFDM).
398 *
399 * High-throughput (HT) rate format
400 *	bit 8 is 1, bit 26 is 0, bit 9 is 0 (OFDM)
401 * Very High-throughput (VHT) rate format
402 *	bit 8 is 0, bit 26 is 1, bit 9 is 0 (OFDM)
403 * Legacy OFDM rate format for bits 7:0
404 *	bit 8 is 0, bit 26 is 0, bit 9 is 0 (OFDM)
405 * Legacy CCK rate format for bits 7:0:
406 *	bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK)
407 */
408
409/* Bit 8: (1) HT format, (0) legacy or VHT format */
410#define RATE_MCS_HT_POS 8
411#define RATE_MCS_HT_MSK_V1 BIT(RATE_MCS_HT_POS)
412
413/* Bit 9: (1) CCK, (0) OFDM.  HT (bit 8) must be "0" for this bit to be valid */
414#define RATE_MCS_CCK_POS_V1 9
415#define RATE_MCS_CCK_MSK_V1 BIT(RATE_MCS_CCK_POS_V1)
416
417/* Bit 26: (1) VHT format, (0) legacy format in bits 8:0 */
418#define RATE_MCS_VHT_POS_V1 26
419#define RATE_MCS_VHT_MSK_V1 BIT(RATE_MCS_VHT_POS_V1)
420
421
422/*
423 * High-throughput (HT) rate format for bits 7:0
424 *
425 *  2-0:  MCS rate base
426 *        0)   6 Mbps
427 *        1)  12 Mbps
428 *        2)  18 Mbps
429 *        3)  24 Mbps
430 *        4)  36 Mbps
431 *        5)  48 Mbps
432 *        6)  54 Mbps
433 *        7)  60 Mbps
434 *  4-3:  0)  Single stream (SISO)
435 *        1)  Dual stream (MIMO)
436 *        2)  Triple stream (MIMO)
437 *    5:  Value of 0x20 in bits 7:0 indicates 6 Mbps HT40 duplicate data
438 *  (bits 7-6 are zero)
439 *
440 * Together the low 5 bits work out to the MCS index because we don't
441 * support MCSes above 15/23, and 0-7 have one stream, 8-15 have two
442 * streams and 16-23 have three streams. We could also support MCS 32
443 * which is the duplicate 20 MHz MCS (bit 5 set, all others zero.)
444 */
445#define RATE_HT_MCS_RATE_CODE_MSK_V1	0x7
446#define RATE_HT_MCS_NSS_POS_V1          3
447#define RATE_HT_MCS_NSS_MSK_V1          (3 << RATE_HT_MCS_NSS_POS_V1)
448#define RATE_HT_MCS_MIMO2_MSK		BIT(RATE_HT_MCS_NSS_POS_V1)
449
450/* Bit 10: (1) Use Green Field preamble */
451#define RATE_HT_MCS_GF_POS		10
452#define RATE_HT_MCS_GF_MSK		(1 << RATE_HT_MCS_GF_POS)
453
454#define RATE_HT_MCS_INDEX_MSK_V1	0x3f
455
456/*
457 * Very High-throughput (VHT) rate format for bits 7:0
458 *
459 *  3-0:  VHT MCS (0-9)
460 *  5-4:  number of streams - 1:
461 *        0)  Single stream (SISO)
462 *        1)  Dual stream (MIMO)
463 *        2)  Triple stream (MIMO)
464 */
465
466/* Bit 4-5: (0) SISO, (1) MIMO2 (2) MIMO3 */
467#define RATE_VHT_MCS_RATE_CODE_MSK	0xf
468#define RATE_VHT_MCS_NSS_MSK		0x30
469
470/*
471 * Legacy OFDM rate format for bits 7:0
472 *
473 *  3-0:  0xD)   6 Mbps
474 *        0xF)   9 Mbps
475 *        0x5)  12 Mbps
476 *        0x7)  18 Mbps
477 *        0x9)  24 Mbps
478 *        0xB)  36 Mbps
479 *        0x1)  48 Mbps
480 *        0x3)  54 Mbps
481 * (bits 7-4 are 0)
482 *
483 * Legacy CCK rate format for bits 7:0:
484 * bit 8 is 0, bit 26 is 0, bit 9 is 1 (CCK):
485 *
486 *  6-0:   10)  1 Mbps
487 *         20)  2 Mbps
488 *         55)  5.5 Mbps
489 *        110)  11 Mbps
490 * (bit 7 is 0)
491 */
492#define RATE_LEGACY_RATE_MSK_V1 0xff
493
494/* Bit 10 - OFDM HE */
495#define RATE_MCS_HE_POS_V1	10
496#define RATE_MCS_HE_MSK_V1	BIT(RATE_MCS_HE_POS_V1)
497
498/*
499 * Bit 11-12: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz
500 * 0 and 1 are valid for HT and VHT, 2 and 3 only for VHT
501 */
502#define RATE_MCS_CHAN_WIDTH_POS		11
503#define RATE_MCS_CHAN_WIDTH_MSK_V1	(3 << RATE_MCS_CHAN_WIDTH_POS)
504
505/* Bit 13: (1) Short guard interval (0.4 usec), (0) normal GI (0.8 usec) */
506#define RATE_MCS_SGI_POS_V1		13
507#define RATE_MCS_SGI_MSK_V1		BIT(RATE_MCS_SGI_POS_V1)
508
509/* Bit 14-16: Antenna selection (1) Ant A, (2) Ant B, (4) Ant C */
510#define RATE_MCS_ANT_POS		14
511#define RATE_MCS_ANT_A_MSK		(1 << RATE_MCS_ANT_POS)
512#define RATE_MCS_ANT_B_MSK		(2 << RATE_MCS_ANT_POS)
513#define RATE_MCS_ANT_AB_MSK		(RATE_MCS_ANT_A_MSK | \
514					 RATE_MCS_ANT_B_MSK)
515#define RATE_MCS_ANT_MSK		RATE_MCS_ANT_AB_MSK
516
517/* Bit 17: (0) SS, (1) SS*2 */
518#define RATE_MCS_STBC_POS		17
519#define RATE_MCS_STBC_MSK		BIT(RATE_MCS_STBC_POS)
520
521/* Bit 18: OFDM-HE dual carrier mode */
522#define RATE_HE_DUAL_CARRIER_MODE	18
523#define RATE_HE_DUAL_CARRIER_MODE_MSK	BIT(RATE_HE_DUAL_CARRIER_MODE)
524
525/* Bit 19: (0) Beamforming is off, (1) Beamforming is on */
526#define RATE_MCS_BF_POS			19
527#define RATE_MCS_BF_MSK			(1 << RATE_MCS_BF_POS)
528
529/*
530 * Bit 20-21: HE LTF type and guard interval
531 * HE (ext) SU:
532 *	0			1xLTF+0.8us
533 *	1			2xLTF+0.8us
534 *	2			2xLTF+1.6us
535 *	3 & SGI (bit 13) clear	4xLTF+3.2us
536 *	3 & SGI (bit 13) set	4xLTF+0.8us
537 * HE MU:
538 *	0			4xLTF+0.8us
539 *	1			2xLTF+0.8us
540 *	2			2xLTF+1.6us
541 *	3			4xLTF+3.2us
542 * HE-EHT TRIG:
543 *	0			1xLTF+1.6us
544 *	1			2xLTF+1.6us
545 *	2			4xLTF+3.2us
546 *	3			(does not occur)
547 * EHT MU:
548 *	0			2xLTF+0.8us
549 *	1			2xLTF+1.6us
550 *	2			4xLTF+0.8us
551 *	3			4xLTF+3.2us
552 */
553#define RATE_MCS_HE_GI_LTF_POS		20
554#define RATE_MCS_HE_GI_LTF_MSK_V1		(3 << RATE_MCS_HE_GI_LTF_POS)
555
556/* Bit 22-23: HE type. (0) SU, (1) SU_EXT, (2) MU, (3) trigger based */
557#define RATE_MCS_HE_TYPE_POS_V1		22
558#define RATE_MCS_HE_TYPE_SU_V1		(0 << RATE_MCS_HE_TYPE_POS_V1)
559#define RATE_MCS_HE_TYPE_EXT_SU_V1		BIT(RATE_MCS_HE_TYPE_POS_V1)
560#define RATE_MCS_HE_TYPE_MU_V1		(2 << RATE_MCS_HE_TYPE_POS_V1)
561#define RATE_MCS_HE_TYPE_TRIG_V1	(3 << RATE_MCS_HE_TYPE_POS_V1)
562#define RATE_MCS_HE_TYPE_MSK_V1		(3 << RATE_MCS_HE_TYPE_POS_V1)
563
564/* Bit 24-25: (0) 20MHz (no dup), (1) 2x20MHz, (2) 4x20MHz, 3 8x20MHz */
565#define RATE_MCS_DUP_POS_V1		24
566#define RATE_MCS_DUP_MSK_V1		(3 << RATE_MCS_DUP_POS_V1)
567
568/* Bit 27: (1) LDPC enabled, (0) LDPC disabled */
569#define RATE_MCS_LDPC_POS_V1		27
570#define RATE_MCS_LDPC_MSK_V1		BIT(RATE_MCS_LDPC_POS_V1)
571
572/* Bit 28: (1) 106-tone RX (8 MHz RU), (0) normal bandwidth */
573#define RATE_MCS_HE_106T_POS_V1		28
574#define RATE_MCS_HE_106T_MSK_V1		BIT(RATE_MCS_HE_106T_POS_V1)
575
576/* Bit 30-31: (1) RTS, (2) CTS */
577#define RATE_MCS_RTS_REQUIRED_POS  (30)
578#define RATE_MCS_RTS_REQUIRED_MSK  (0x1 << RATE_MCS_RTS_REQUIRED_POS)
579
580#define RATE_MCS_CTS_REQUIRED_POS  (31)
581#define RATE_MCS_CTS_REQUIRED_MSK  (0x1 << RATE_MCS_CTS_REQUIRED_POS)
582
583/* rate_n_flags bit field version 2 and 3
584 *
585 * The 32-bit value has different layouts in the low 8 bits depending on the
586 * format. There are three formats, HT, VHT and legacy (11abg, with subformats
587 * for CCK and OFDM).
588 *
589 */
590
591/* Bits 10-8: rate format
592 * (0) Legacy CCK (1) Legacy OFDM (2) High-throughput (HT)
593 * (3) Very High-throughput (VHT) (4) High-efficiency (HE)
594 * (5) Extremely High-throughput (EHT)
595 * (6) Ultra High Reliability (UHR) (v3 rate format only)
596 */
597#define RATE_MCS_MOD_TYPE_POS		8
598#define RATE_MCS_MOD_TYPE_MSK		(0x7 << RATE_MCS_MOD_TYPE_POS)
599#define RATE_MCS_MOD_TYPE_CCK		(0 << RATE_MCS_MOD_TYPE_POS)
600#define RATE_MCS_MOD_TYPE_LEGACY_OFDM	(1 << RATE_MCS_MOD_TYPE_POS)
601#define RATE_MCS_MOD_TYPE_HT		(2 << RATE_MCS_MOD_TYPE_POS)
602#define RATE_MCS_MOD_TYPE_VHT		(3 << RATE_MCS_MOD_TYPE_POS)
603#define RATE_MCS_MOD_TYPE_HE		(4 << RATE_MCS_MOD_TYPE_POS)
604#define RATE_MCS_MOD_TYPE_EHT		(5 << RATE_MCS_MOD_TYPE_POS)
605#define RATE_MCS_MOD_TYPE_UHR		(6 << RATE_MCS_MOD_TYPE_POS)
606
607/*
608 * Legacy CCK rate format for bits 0:3:
609 *
610 * (0) 1 Mbps
611 * (1) 2 Mbps
612 * (2) 5.5 Mbps
613 * (3) 11 Mbps
614 *
615 * Legacy OFDM rate format for bis 3:0:
616 *
617 * (0) 6 Mbps
618 * (1) 9 Mbps
619 * (2) 12 Mbps
620 * (3) 18 Mbps
621 * (4) 24 Mbps
622 * (5) 36 Mbps
623 * (6) 48 Mbps
624 * (7) 54 Mbps
625 *
626 */
627#define RATE_LEGACY_RATE_MSK		0x7
628
629/*
630 * HT, VHT, HE, EHT, UHR rate format
631 * Version 2: (not applicable for UHR)
632 *   3-0: MCS
633 *   4: NSS==2 indicator
634 * Version 3:
635 *   4-0: MCS
636 *   5: NSS==2 indicator
637 */
638#define RATE_HT_MCS_CODE_MSK		0x7
639#define RATE_MCS_NSS_MSK_V2		0x10
640#define RATE_MCS_NSS_MSK		0x20
641#define RATE_MCS_CODE_MSK		0x1f
642#define RATE_HT_MCS_INDEX(r)		((((r) & RATE_MCS_NSS_MSK) >> 2) | \
643					 ((r) & RATE_HT_MCS_CODE_MSK))
644
645/* Bits 7-5: reserved */
646
647/*
648 * Bits 13-11: (0) 20MHz, (1) 40MHz, (2) 80MHz, (3) 160MHz, (4) 320MHz
649 */
650#define RATE_MCS_CHAN_WIDTH_MSK		(0x7 << RATE_MCS_CHAN_WIDTH_POS)
651#define RATE_MCS_CHAN_WIDTH_20_VAL	0
652#define RATE_MCS_CHAN_WIDTH_20		(RATE_MCS_CHAN_WIDTH_20_VAL << RATE_MCS_CHAN_WIDTH_POS)
653#define RATE_MCS_CHAN_WIDTH_40_VAL	1
654#define RATE_MCS_CHAN_WIDTH_40		(RATE_MCS_CHAN_WIDTH_40_VAL << RATE_MCS_CHAN_WIDTH_POS)
655#define RATE_MCS_CHAN_WIDTH_80_VAL	2
656#define RATE_MCS_CHAN_WIDTH_80		(RATE_MCS_CHAN_WIDTH_80_VAL << RATE_MCS_CHAN_WIDTH_POS)
657#define RATE_MCS_CHAN_WIDTH_160_VAL	3
658#define RATE_MCS_CHAN_WIDTH_160		(RATE_MCS_CHAN_WIDTH_160_VAL << RATE_MCS_CHAN_WIDTH_POS)
659#define RATE_MCS_CHAN_WIDTH_320_VAL	4
660#define RATE_MCS_CHAN_WIDTH_320		(RATE_MCS_CHAN_WIDTH_320_VAL << RATE_MCS_CHAN_WIDTH_POS)
661
662/* Bit 15-14: Antenna selection:
663 * Bit 14: Ant A active
664 * Bit 15: Ant B active
665 *
666 * All relevant definitions are same as in v1
667 */
668
669/* Bit 16 (1) LDPC enables, (0) LDPC disabled */
670#define RATE_MCS_LDPC_POS	16
671#define RATE_MCS_LDPC_MSK	(1 << RATE_MCS_LDPC_POS)
672
673/* Bit 17: (0) SS, (1) SS*2 (same as v1) */
674
675/* Bit 18: OFDM-HE dual carrier mode (same as v1) */
676
677/* Bit 19: (0) Beamforming is off, (1) Beamforming is on (same as v1) */
678
679/*
680 * Bit 22-20: HE LTF type and guard interval
681 * CCK:
682 *	0			long preamble
683 *	1			short preamble
684 * HT/VHT:
685 *	0			0.8us
686 *	1			0.4us
687 * HE (ext) SU:
688 *	0			1xLTF+0.8us
689 *	1			2xLTF+0.8us
690 *	2			2xLTF+1.6us
691 *	3			4xLTF+3.2us
692 *	4			4xLTF+0.8us
693 * HE MU:
694 *	0			4xLTF+0.8us
695 *	1			2xLTF+0.8us
696 *	2			2xLTF+1.6us
697 *	3			4xLTF+3.2us
698 * HE TRIG:
699 *	0			1xLTF+1.6us
700 *	1			2xLTF+1.6us
701 *	2			4xLTF+3.2us
702 * */
703#define RATE_MCS_HE_GI_LTF_MSK		(0x7 << RATE_MCS_HE_GI_LTF_POS)
704#define RATE_MCS_SGI_POS		RATE_MCS_HE_GI_LTF_POS
705#define RATE_MCS_SGI_MSK		(1 << RATE_MCS_SGI_POS)
706#define RATE_MCS_HE_SU_4_LTF		3
707#define RATE_MCS_HE_SU_4_LTF_08_GI	4
708
709/* Bit 24-23: HE type. (0) SU, (1) SU_EXT, (2) MU, (3) trigger based */
710#define RATE_MCS_HE_TYPE_POS		23
711#define RATE_MCS_HE_TYPE_SU		(0 << RATE_MCS_HE_TYPE_POS)
712#define RATE_MCS_HE_TYPE_EXT_SU		(1 << RATE_MCS_HE_TYPE_POS)
713#define RATE_MCS_HE_TYPE_MU		(2 << RATE_MCS_HE_TYPE_POS)
714#define RATE_MCS_HE_TYPE_TRIG		(3 << RATE_MCS_HE_TYPE_POS)
715#define RATE_MCS_HE_TYPE_MSK		(3 << RATE_MCS_HE_TYPE_POS)
716
717/* Bit 25: duplicate channel enabled
718 *
719 * if this bit is set, duplicate is according to BW (bits 11-13):
720 *
721 * CCK:  2x 20MHz
722 * OFDM Legacy: N x 20Mhz, (N = BW \ 2 , either 2, 4, 8, 16)
723 * EHT: 2 x BW/2, (80 - 2x40, 160 - 2x80, 320 - 2x160)
724 * */
725#define RATE_MCS_DUP_POS		25
726#define RATE_MCS_DUP_MSK		(1 << RATE_MCS_DUP_POS)
727
728/* Bit 26: (1) 106-tone RX (8 MHz RU), (0) normal bandwidth */
729#define RATE_MCS_HE_106T_POS		26
730#define RATE_MCS_HE_106T_MSK		(1 << RATE_MCS_HE_106T_POS)
731
732/* Bit 27: EHT extra LTF:
733 * instead of 1 LTF for SISO use 2 LTFs,
734 * instead of 2 LTFs for NSTS=2 use 4 LTFs*/
735#define RATE_MCS_EHT_EXTRA_LTF_POS	27
736#define RATE_MCS_EHT_EXTRA_LTF_MSK	(1 << RATE_MCS_EHT_EXTRA_LTF_POS)
737
738/* Bit 31-28: reserved */
739
740/* Link Quality definitions */
741
742/* # entries in rate scale table to support Tx retries */
743#define  LQ_MAX_RETRY_NUM 16
744
745/* Link quality command flags bit fields */
746
747/* Bit 0: (0) Don't use RTS (1) Use RTS */
748#define LQ_FLAG_USE_RTS_POS             0
749#define LQ_FLAG_USE_RTS_MSK	        (1 << LQ_FLAG_USE_RTS_POS)
750
751/* Bit 1-3: LQ command color. Used to match responses to LQ commands */
752#define LQ_FLAG_COLOR_POS               1
753#define LQ_FLAG_COLOR_MSK               (7 << LQ_FLAG_COLOR_POS)
754#define LQ_FLAG_COLOR_GET(_f)		(((_f) & LQ_FLAG_COLOR_MSK) >>\
755					 LQ_FLAG_COLOR_POS)
756#define LQ_FLAGS_COLOR_INC(_c)		((((_c) + 1) << LQ_FLAG_COLOR_POS) &\
757					 LQ_FLAG_COLOR_MSK)
758#define LQ_FLAG_COLOR_SET(_f, _c)	((_c) | ((_f) & ~LQ_FLAG_COLOR_MSK))
759
760/* Bit 4-5: Tx RTS BW Signalling
761 * (0) No RTS BW signalling
762 * (1) Static BW signalling
763 * (2) Dynamic BW signalling
764 */
765#define LQ_FLAG_RTS_BW_SIG_POS          4
766#define LQ_FLAG_RTS_BW_SIG_NONE         (0 << LQ_FLAG_RTS_BW_SIG_POS)
767#define LQ_FLAG_RTS_BW_SIG_STATIC       (1 << LQ_FLAG_RTS_BW_SIG_POS)
768#define LQ_FLAG_RTS_BW_SIG_DYNAMIC      (2 << LQ_FLAG_RTS_BW_SIG_POS)
769
770/* Bit 6: (0) No dynamic BW selection (1) Allow dynamic BW selection
771 * Dyanmic BW selection allows Tx with narrower BW then requested in rates
772 */
773#define LQ_FLAG_DYNAMIC_BW_POS          6
774#define LQ_FLAG_DYNAMIC_BW_MSK          (1 << LQ_FLAG_DYNAMIC_BW_POS)
775
776/* Single Stream Tx Parameters (lq_cmd->ss_params)
777 * Flags to control a smart FW decision about whether BFER/STBC/SISO will be
778 * used for single stream Tx.
779 */
780
781/* Bit 0-1: Max STBC streams allowed. Can be 0-3.
782 * (0) - No STBC allowed
783 * (1) - 2x1 STBC allowed (HT/VHT)
784 * (2) - 4x2 STBC allowed (HT/VHT)
785 * (3) - 3x2 STBC allowed (HT only)
786 * All our chips are at most 2 antennas so only (1) is valid for now.
787 */
788#define LQ_SS_STBC_ALLOWED_POS          0
789#define LQ_SS_STBC_ALLOWED_MSK		(3 << LQ_SS_STBC_ALLOWED_MSK)
790
791/* 2x1 STBC is allowed */
792#define LQ_SS_STBC_1SS_ALLOWED		(1 << LQ_SS_STBC_ALLOWED_POS)
793
794/* Bit 2: Beamformer (VHT only) is allowed */
795#define LQ_SS_BFER_ALLOWED_POS		2
796#define LQ_SS_BFER_ALLOWED		(1 << LQ_SS_BFER_ALLOWED_POS)
797
798/* Bit 3: Force BFER or STBC for testing
799 * If this is set:
800 * If BFER is allowed then force the ucode to choose BFER else
801 * If STBC is allowed then force the ucode to choose STBC over SISO
802 */
803#define LQ_SS_FORCE_POS			3
804#define LQ_SS_FORCE			(1 << LQ_SS_FORCE_POS)
805
806/* Bit 31: ss_params field is valid. Used for FW backward compatibility
807 * with other drivers which don't support the ss_params API yet
808 */
809#define LQ_SS_PARAMS_VALID_POS		31
810#define LQ_SS_PARAMS_VALID		(1 << LQ_SS_PARAMS_VALID_POS)
811
812/**
813 * struct iwl_lq_cmd - link quality command
814 * @sta_id: station to update
815 * @reduced_tpc: reduced transmit power control value
816 * @control: not used
817 * @flags: combination of LQ_FLAG_*
818 * @mimo_delim: the first SISO index in rs_table, which separates MIMO
819 *	and SISO rates
820 * @single_stream_ant_msk: best antenna for SISO (can be dual in CDD).
821 *	Should be ANT_[ABC]
822 * @dual_stream_ant_msk: best antennas for MIMO, combination of ANT_[ABC]
823 * @initial_rate_index: first index from rs_table per AC category
824 * @agg_time_limit: aggregation max time threshold in usec/100, meaning
825 *	value of 100 is one usec. Range is 100 to 8000
826 * @agg_disable_start_th: try-count threshold for starting aggregation.
827 *	If a frame has higher try-count, it should not be selected for
828 *	starting an aggregation sequence.
829 * @agg_frame_cnt_limit: max frame count in an aggregation.
830 *	0: no limit
831 *	1: no aggregation (one frame per aggregation)
832 *	2 - 0x3f: maximal number of frames (up to 3f == 63)
833 * @reserved2: reserved
834 * @rs_table: array of rates for each TX try, each is rate_n_flags,
835 *	meaning it is a combination of RATE_MCS_* and IWL_RATE_*_PLCP
836 * @ss_params: single stream features. declare whether STBC or BFER are allowed.
837 */
838struct iwl_lq_cmd {
839	u8 sta_id;
840	u8 reduced_tpc;
841	__le16 control;
842	/* LINK_QUAL_GENERAL_PARAMS_API_S_VER_1 */
843	u8 flags;
844	u8 mimo_delim;
845	u8 single_stream_ant_msk;
846	u8 dual_stream_ant_msk;
847	u8 initial_rate_index[AC_NUM];
848	/* LINK_QUAL_AGG_PARAMS_API_S_VER_1 */
849	__le16 agg_time_limit;
850	u8 agg_disable_start_th;
851	u8 agg_frame_cnt_limit;
852	__le32 reserved2;
853	__le32 rs_table[LQ_MAX_RETRY_NUM];
854	__le32 ss_params;
855}; /* LINK_QUALITY_CMD_API_S_VER_1 */
856
857u8 iwl_fw_rate_idx_to_plcp(int idx);
858const struct iwl_rate_mcs_info *iwl_rate_mcs(int idx);
859const char *iwl_rs_pretty_ant(u8 ant);
860const char *iwl_rs_pretty_bw(int bw);
861int rs_pretty_print_rate(char *buf, int bufsz, const u32 rate);
862bool iwl_he_is_sgi(u32 rate_n_flags);
863
864static inline u32 iwl_v3_rate_from_v2_v3(__le32 rate, bool fw_v3)
865{
866	u32 val;
867
868	if (fw_v3)
869		return le32_to_cpu(rate);
870
871	val = le32_to_cpu(rate) & ~RATE_MCS_NSS_MSK_V2;
872	val |= u32_encode_bits(le32_get_bits(rate, RATE_MCS_NSS_MSK_V2),
873			       RATE_MCS_NSS_MSK);
874
875	return val;
876}
877
878static inline __le32 iwl_v3_rate_to_v2_v3(u32 rate, bool fw_v3)
879{
880	__le32 val;
881
882	if (fw_v3)
883		return cpu_to_le32(rate);
884
885	val = cpu_to_le32(rate & ~RATE_MCS_NSS_MSK);
886	val |= le32_encode_bits(u32_get_bits(rate, RATE_MCS_NSS_MSK),
887				RATE_MCS_NSS_MSK_V2);
888
889	return val;
890}
891
892#endif /* __iwl_fw_api_rs_h__ */