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eeprom.c
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linux-6.19.14/drivers/net/wireless/intel/iwlwifi/dvm/eeprom.c
1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2/* 3 * Copyright (C) 2005-2014, 2018-2019, 2021, 2024-2025 Intel Corporation 4 */ 5#include <linux/types.h> 6#include <linux/slab.h> 7#include <linux/export.h> 8 9#include "iwl-drv.h" 10#include "iwl-debug.h" 11#include "iwl-io.h" 12#include "iwl-prph.h" 13#include "iwl-csr.h" 14#include "agn.h" 15 16/* EEPROM offset definitions */ 17 18/* indirect access definitions */ 19#define ADDRESS_MSK 0x0000FFFF 20#define INDIRECT_TYPE_MSK 0x000F0000 21#define INDIRECT_HOST 0x00010000 22#define INDIRECT_GENERAL 0x00020000 23#define INDIRECT_REGULATORY 0x00030000 24#define INDIRECT_CALIBRATION 0x00040000 25#define INDIRECT_PROCESS_ADJST 0x00050000 26#define INDIRECT_OTHERS 0x00060000 27#define INDIRECT_TXP_LIMIT 0x00070000 28#define INDIRECT_TXP_LIMIT_SIZE 0x00080000 29#define INDIRECT_ADDRESS 0x00100000 30 31/* corresponding link offsets in EEPROM */ 32#define EEPROM_LINK_HOST (2*0x64) 33#define EEPROM_LINK_GENERAL (2*0x65) 34#define EEPROM_LINK_REGULATORY (2*0x66) 35#define EEPROM_LINK_CALIBRATION (2*0x67) 36#define EEPROM_LINK_PROCESS_ADJST (2*0x68) 37#define EEPROM_LINK_OTHERS (2*0x69) 38#define EEPROM_LINK_TXP_LIMIT (2*0x6a) 39#define EEPROM_LINK_TXP_LIMIT_SIZE (2*0x6b) 40 41/* General */ 42#define EEPROM_DEVICE_ID (2*0x08) /* 2 bytes */ 43#define EEPROM_SUBSYSTEM_ID (2*0x0A) /* 2 bytes */ 44#define EEPROM_MAC_ADDRESS (2*0x15) /* 6 bytes */ 45#define EEPROM_BOARD_REVISION (2*0x35) /* 2 bytes */ 46#define EEPROM_BOARD_PBA_NUMBER (2*0x3B+1) /* 9 bytes */ 47#define EEPROM_VERSION (2*0x44) /* 2 bytes */ 48#define EEPROM_SKU_CAP (2*0x45) /* 2 bytes */ 49#define EEPROM_OEM_MODE (2*0x46) /* 2 bytes */ 50#define EEPROM_RADIO_CONFIG (2*0x48) /* 2 bytes */ 51#define EEPROM_NUM_MAC_ADDRESS (2*0x4C) /* 2 bytes */ 52 53/* calibration */ 54struct iwl_eeprom_calib_hdr { 55 u8 version; 56 u8 pa_type; 57 __le16 voltage; 58} __packed; 59 60#define EEPROM_CALIB_ALL (INDIRECT_ADDRESS | INDIRECT_CALIBRATION) 61#define EEPROM_XTAL ((2*0x128) | EEPROM_CALIB_ALL) 62 63/* temperature */ 64#define EEPROM_KELVIN_TEMPERATURE ((2*0x12A) | EEPROM_CALIB_ALL) 65#define EEPROM_RAW_TEMPERATURE ((2*0x12B) | EEPROM_CALIB_ALL) 66 67/* SKU Capabilities (actual values from EEPROM definition) */ 68enum eeprom_sku_bits { 69 EEPROM_SKU_CAP_BAND_24GHZ = BIT(4), 70 EEPROM_SKU_CAP_BAND_52GHZ = BIT(5), 71 EEPROM_SKU_CAP_11N_ENABLE = BIT(6), 72 EEPROM_SKU_CAP_AMT_ENABLE = BIT(7), 73 EEPROM_SKU_CAP_IPAN_ENABLE = BIT(8) 74}; 75 76/* radio config bits (actual values from EEPROM definition) */ 77#define EEPROM_RF_CFG_TYPE_MSK(x) (x & 0x3) /* bits 0-1 */ 78#define EEPROM_RF_CFG_STEP_MSK(x) ((x >> 2) & 0x3) /* bits 2-3 */ 79#define EEPROM_RF_CFG_DASH_MSK(x) ((x >> 4) & 0x3) /* bits 4-5 */ 80#define EEPROM_RF_CFG_PNUM_MSK(x) ((x >> 6) & 0x3) /* bits 6-7 */ 81#define EEPROM_RF_CFG_TX_ANT_MSK(x) ((x >> 8) & 0xF) /* bits 8-11 */ 82#define EEPROM_RF_CFG_RX_ANT_MSK(x) ((x >> 12) & 0xF) /* bits 12-15 */ 83 84/* 85 * EEPROM bands 86 * These are the channel numbers from each band in the order 87 * that they are stored in the EEPROM band information. Note 88 * that EEPROM bands aren't the same as mac80211 bands, and 89 * there are even special "ht40 bands" in the EEPROM. 90 */ 91static const u8 iwl_eeprom_band_1[14] = { /* 2.4 GHz */ 92 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14 93}; 94 95static const u8 iwl_eeprom_band_2[] = { /* 4915-5080MHz */ 96 183, 184, 185, 187, 188, 189, 192, 196, 7, 8, 11, 12, 16 97}; 98 99static const u8 iwl_eeprom_band_3[] = { /* 5170-5320MHz */ 100 34, 36, 38, 40, 42, 44, 46, 48, 52, 56, 60, 64 101}; 102 103static const u8 iwl_eeprom_band_4[] = { /* 5500-5700MHz */ 104 100, 104, 108, 112, 116, 120, 124, 128, 132, 136, 140 105}; 106 107static const u8 iwl_eeprom_band_5[] = { /* 5725-5825MHz */ 108 145, 149, 153, 157, 161, 165 109}; 110 111static const u8 iwl_eeprom_band_6[] = { /* 2.4 ht40 channel */ 112 1, 2, 3, 4, 5, 6, 7 113}; 114 115static const u8 iwl_eeprom_band_7[] = { /* 5.2 ht40 channel */ 116 36, 44, 52, 60, 100, 108, 116, 124, 132, 149, 157 117}; 118 119#define IWL_NUM_CHANNELS (ARRAY_SIZE(iwl_eeprom_band_1) + \ 120 ARRAY_SIZE(iwl_eeprom_band_2) + \ 121 ARRAY_SIZE(iwl_eeprom_band_3) + \ 122 ARRAY_SIZE(iwl_eeprom_band_4) + \ 123 ARRAY_SIZE(iwl_eeprom_band_5)) 124 125/* rate data (static) */ 126static struct ieee80211_rate iwl_cfg80211_rates[] = { 127 { .bitrate = 1 * 10, .hw_value = 0, .hw_value_short = 0, }, 128 { .bitrate = 2 * 10, .hw_value = 1, .hw_value_short = 1, 129 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 130 { .bitrate = 5.5 * 10, .hw_value = 2, .hw_value_short = 2, 131 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 132 { .bitrate = 11 * 10, .hw_value = 3, .hw_value_short = 3, 133 .flags = IEEE80211_RATE_SHORT_PREAMBLE, }, 134 { .bitrate = 6 * 10, .hw_value = 4, .hw_value_short = 4, }, 135 { .bitrate = 9 * 10, .hw_value = 5, .hw_value_short = 5, }, 136 { .bitrate = 12 * 10, .hw_value = 6, .hw_value_short = 6, }, 137 { .bitrate = 18 * 10, .hw_value = 7, .hw_value_short = 7, }, 138 { .bitrate = 24 * 10, .hw_value = 8, .hw_value_short = 8, }, 139 { .bitrate = 36 * 10, .hw_value = 9, .hw_value_short = 9, }, 140 { .bitrate = 48 * 10, .hw_value = 10, .hw_value_short = 10, }, 141 { .bitrate = 54 * 10, .hw_value = 11, .hw_value_short = 11, }, 142}; 143#define RATES_24_OFFS 0 144#define N_RATES_24 ARRAY_SIZE(iwl_cfg80211_rates) 145#define RATES_52_OFFS 4 146#define N_RATES_52 (N_RATES_24 - RATES_52_OFFS) 147 148/* EEPROM reading functions */ 149 150static u16 iwl_eeprom_query16(const u8 *eeprom, size_t eeprom_size, int offset) 151{ 152 if (WARN_ON(offset + sizeof(u16) > eeprom_size)) 153 return 0; 154 return le16_to_cpup((const __le16 *)(eeprom + offset)); 155} 156 157static u32 eeprom_indirect_address(const u8 *eeprom, size_t eeprom_size, 158 u32 address) 159{ 160 u16 offset = 0; 161 162 if ((address & INDIRECT_ADDRESS) == 0) 163 return address; 164 165 switch (address & INDIRECT_TYPE_MSK) { 166 case INDIRECT_HOST: 167 offset = iwl_eeprom_query16(eeprom, eeprom_size, 168 EEPROM_LINK_HOST); 169 break; 170 case INDIRECT_GENERAL: 171 offset = iwl_eeprom_query16(eeprom, eeprom_size, 172 EEPROM_LINK_GENERAL); 173 break; 174 case INDIRECT_REGULATORY: 175 offset = iwl_eeprom_query16(eeprom, eeprom_size, 176 EEPROM_LINK_REGULATORY); 177 break; 178 case INDIRECT_TXP_LIMIT: 179 offset = iwl_eeprom_query16(eeprom, eeprom_size, 180 EEPROM_LINK_TXP_LIMIT); 181 break; 182 case INDIRECT_TXP_LIMIT_SIZE: 183 offset = iwl_eeprom_query16(eeprom, eeprom_size, 184 EEPROM_LINK_TXP_LIMIT_SIZE); 185 break; 186 case INDIRECT_CALIBRATION: 187 offset = iwl_eeprom_query16(eeprom, eeprom_size, 188 EEPROM_LINK_CALIBRATION); 189 break; 190 case INDIRECT_PROCESS_ADJST: 191 offset = iwl_eeprom_query16(eeprom, eeprom_size, 192 EEPROM_LINK_PROCESS_ADJST); 193 break; 194 case INDIRECT_OTHERS: 195 offset = iwl_eeprom_query16(eeprom, eeprom_size, 196 EEPROM_LINK_OTHERS); 197 break; 198 default: 199 WARN_ON(1); 200 break; 201 } 202 203 /* translate the offset from words to byte */ 204 return (address & ADDRESS_MSK) + (offset << 1); 205} 206 207static const void *iwl_eeprom_query_addr(const u8 *eeprom, size_t eeprom_size, 208 u32 offset) 209{ 210 u32 address = eeprom_indirect_address(eeprom, eeprom_size, offset); 211 212 if (WARN_ON(address >= eeprom_size)) 213 return NULL; 214 215 return &eeprom[address]; 216} 217 218static int iwl_eeprom_read_calib(const u8 *eeprom, size_t eeprom_size, 219 struct iwl_nvm_data *data) 220{ 221 const struct iwl_eeprom_calib_hdr *hdr; 222 223 hdr = iwl_eeprom_query_addr(eeprom, eeprom_size, EEPROM_CALIB_ALL); 224 if (!hdr) 225 return -ENODATA; 226 data->calib_version = hdr->version; 227 data->calib_voltage = hdr->voltage; 228 229 return 0; 230} 231 232/** 233 * enum iwl_eeprom_channel_flags - channel flags in EEPROM 234 * @EEPROM_CHANNEL_VALID: channel is usable for this SKU/geo 235 * @EEPROM_CHANNEL_IBSS: usable as an IBSS channel 236 * @EEPROM_CHANNEL_ACTIVE: active scanning allowed 237 * @EEPROM_CHANNEL_RADAR: radar detection required 238 * @EEPROM_CHANNEL_WIDE: 20 MHz channel okay (?) 239 * @EEPROM_CHANNEL_DFS: dynamic freq selection candidate 240 */ 241enum iwl_eeprom_channel_flags { 242 EEPROM_CHANNEL_VALID = BIT(0), 243 EEPROM_CHANNEL_IBSS = BIT(1), 244 EEPROM_CHANNEL_ACTIVE = BIT(3), 245 EEPROM_CHANNEL_RADAR = BIT(4), 246 EEPROM_CHANNEL_WIDE = BIT(5), 247 EEPROM_CHANNEL_DFS = BIT(7), 248}; 249 250/** 251 * struct iwl_eeprom_channel - EEPROM channel data 252 * @flags: %EEPROM_CHANNEL_* flags 253 * @max_power_avg: max power (in dBm) on this channel, at most 31 dBm 254 */ 255struct iwl_eeprom_channel { 256 u8 flags; 257 s8 max_power_avg; 258} __packed; 259 260enum iwl_eeprom_enhanced_txpwr_flags { 261 IWL_EEPROM_ENH_TXP_FL_VALID = BIT(0), 262 IWL_EEPROM_ENH_TXP_FL_BAND_52G = BIT(1), 263 IWL_EEPROM_ENH_TXP_FL_OFDM = BIT(2), 264 IWL_EEPROM_ENH_TXP_FL_40MHZ = BIT(3), 265 IWL_EEPROM_ENH_TXP_FL_HT_AP = BIT(4), 266 IWL_EEPROM_ENH_TXP_FL_RES1 = BIT(5), 267 IWL_EEPROM_ENH_TXP_FL_RES2 = BIT(6), 268 IWL_EEPROM_ENH_TXP_FL_COMMON_TYPE = BIT(7), 269}; 270 271/** 272 * struct iwl_eeprom_enhanced_txpwr - enhanced regulatory TX power limits 273 * @flags: entry flags 274 * @channel: channel number 275 * @chain_a_max: chain a max power in 1/2 dBm 276 * @chain_b_max: chain b max power in 1/2 dBm 277 * @chain_c_max: chain c max power in 1/2 dBm 278 * @delta_20_in_40: 20-in-40 deltas (hi/lo) 279 * @mimo2_max: mimo2 max power in 1/2 dBm 280 * @mimo3_max: mimo3 max power in 1/2 dBm 281 * 282 * This structure presents the enhanced regulatory tx power limit layout 283 * in an EEPROM image. 284 */ 285struct iwl_eeprom_enhanced_txpwr { 286 u8 flags; 287 u8 channel; 288 s8 chain_a_max; 289 s8 chain_b_max; 290 s8 chain_c_max; 291 u8 delta_20_in_40; 292 s8 mimo2_max; 293 s8 mimo3_max; 294} __packed; 295 296static s8 iwl_get_max_txpwr_half_dbm(const struct iwl_nvm_data *data, 297 const struct iwl_eeprom_enhanced_txpwr *txp) 298{ 299 s8 result = 0; /* (.5 dBm) */ 300 301 /* Take the highest tx power from any valid chains */ 302 if (data->valid_tx_ant & ANT_A && txp->chain_a_max > result) 303 result = txp->chain_a_max; 304 305 if (data->valid_tx_ant & ANT_B && txp->chain_b_max > result) 306 result = txp->chain_b_max; 307 308 if (data->valid_tx_ant & ANT_C && txp->chain_c_max > result) 309 result = txp->chain_c_max; 310 311 if ((data->valid_tx_ant == ANT_AB || 312 data->valid_tx_ant == ANT_BC || 313 data->valid_tx_ant == ANT_AC) && txp->mimo2_max > result) 314 result = txp->mimo2_max; 315 316 if (data->valid_tx_ant == ANT_ABC && txp->mimo3_max > result) 317 result = txp->mimo3_max; 318 319 return result; 320} 321 322#define EEPROM_TXP_OFFS (0x00 | INDIRECT_ADDRESS | INDIRECT_TXP_LIMIT) 323#define EEPROM_TXP_ENTRY_LEN sizeof(struct iwl_eeprom_enhanced_txpwr) 324#define EEPROM_TXP_SZ_OFFS (0x00 | INDIRECT_ADDRESS | INDIRECT_TXP_LIMIT_SIZE) 325 326#define TXP_CHECK_AND_PRINT(x) \ 327 ((txp->flags & IWL_EEPROM_ENH_TXP_FL_##x) ? # x " " : "") 328 329static void 330iwl_eeprom_enh_txp_read_element(struct iwl_nvm_data *data, 331 const struct iwl_eeprom_enhanced_txpwr *txp, 332 int n_channels, s8 max_txpower_avg) 333{ 334 int ch_idx; 335 enum nl80211_band band; 336 337 band = txp->flags & IWL_EEPROM_ENH_TXP_FL_BAND_52G ? 338 NL80211_BAND_5GHZ : NL80211_BAND_2GHZ; 339 340 for (ch_idx = 0; ch_idx < n_channels; ch_idx++) { 341 struct ieee80211_channel *chan = &data->channels[ch_idx]; 342 343 /* update matching channel or from common data only */ 344 if (txp->channel != 0 && chan->hw_value != txp->channel) 345 continue; 346 347 /* update matching band only */ 348 if (band != chan->band) 349 continue; 350 351 if (chan->max_power < max_txpower_avg && 352 !(txp->flags & IWL_EEPROM_ENH_TXP_FL_40MHZ)) 353 chan->max_power = max_txpower_avg; 354 } 355} 356 357static void iwl_eeprom_enhanced_txpower(struct device *dev, 358 struct iwl_nvm_data *data, 359 const u8 *eeprom, size_t eeprom_size, 360 int n_channels) 361{ 362 const struct iwl_eeprom_enhanced_txpwr *txp_array, *txp; 363 int idx, entries; 364 const __le16 *txp_len; 365 s8 max_txp_avg_halfdbm; 366 367 BUILD_BUG_ON(sizeof(struct iwl_eeprom_enhanced_txpwr) != 8); 368 369 /* the length is in 16-bit words, but we want entries */ 370 txp_len = iwl_eeprom_query_addr(eeprom, eeprom_size, EEPROM_TXP_SZ_OFFS); 371 entries = le16_to_cpup(txp_len) * 2 / EEPROM_TXP_ENTRY_LEN; 372 373 txp_array = iwl_eeprom_query_addr(eeprom, eeprom_size, EEPROM_TXP_OFFS); 374 375 for (idx = 0; idx < entries; idx++) { 376 txp = &txp_array[idx]; 377 /* skip invalid entries */ 378 if (!(txp->flags & IWL_EEPROM_ENH_TXP_FL_VALID)) 379 continue; 380 381 IWL_DEBUG_EEPROM(dev, "%s %d:\t %s%s%s%s%s%s%s%s (0x%02x)\n", 382 (txp->channel && (txp->flags & 383 IWL_EEPROM_ENH_TXP_FL_COMMON_TYPE)) ? 384 "Common " : (txp->channel) ? 385 "Channel" : "Common", 386 (txp->channel), 387 TXP_CHECK_AND_PRINT(VALID), 388 TXP_CHECK_AND_PRINT(BAND_52G), 389 TXP_CHECK_AND_PRINT(OFDM), 390 TXP_CHECK_AND_PRINT(40MHZ), 391 TXP_CHECK_AND_PRINT(HT_AP), 392 TXP_CHECK_AND_PRINT(RES1), 393 TXP_CHECK_AND_PRINT(RES2), 394 TXP_CHECK_AND_PRINT(COMMON_TYPE), 395 txp->flags); 396 IWL_DEBUG_EEPROM(dev, 397 "\t\t chain_A: %d chain_B: %d chain_C: %d\n", 398 txp->chain_a_max, txp->chain_b_max, 399 txp->chain_c_max); 400 IWL_DEBUG_EEPROM(dev, 401 "\t\t MIMO2: %d MIMO3: %d High 20_on_40: 0x%02x Low 20_on_40: 0x%02x\n", 402 txp->mimo2_max, txp->mimo3_max, 403 ((txp->delta_20_in_40 & 0xf0) >> 4), 404 (txp->delta_20_in_40 & 0x0f)); 405 406 max_txp_avg_halfdbm = iwl_get_max_txpwr_half_dbm(data, txp); 407 408 iwl_eeprom_enh_txp_read_element(data, txp, n_channels, 409 DIV_ROUND_UP(max_txp_avg_halfdbm, 2)); 410 411 if (max_txp_avg_halfdbm > data->max_tx_pwr_half_dbm) 412 data->max_tx_pwr_half_dbm = max_txp_avg_halfdbm; 413 } 414} 415 416static void iwl_init_band_reference(const struct iwl_rf_cfg *cfg, 417 const u8 *eeprom, size_t eeprom_size, 418 int eeprom_band, int *eeprom_ch_count, 419 const struct iwl_eeprom_channel **ch_info, 420 const u8 **eeprom_ch_array) 421{ 422 u32 offset = cfg->eeprom_params->regulatory_bands[eeprom_band - 1]; 423 424 offset |= INDIRECT_ADDRESS | INDIRECT_REGULATORY; 425 426 *ch_info = iwl_eeprom_query_addr(eeprom, eeprom_size, offset); 427 428 switch (eeprom_band) { 429 case 1: /* 2.4GHz band */ 430 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_1); 431 *eeprom_ch_array = iwl_eeprom_band_1; 432 break; 433 case 2: /* 4.9GHz band */ 434 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_2); 435 *eeprom_ch_array = iwl_eeprom_band_2; 436 break; 437 case 3: /* 5.2GHz band */ 438 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_3); 439 *eeprom_ch_array = iwl_eeprom_band_3; 440 break; 441 case 4: /* 5.5GHz band */ 442 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_4); 443 *eeprom_ch_array = iwl_eeprom_band_4; 444 break; 445 case 5: /* 5.7GHz band */ 446 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_5); 447 *eeprom_ch_array = iwl_eeprom_band_5; 448 break; 449 case 6: /* 2.4GHz ht40 channels */ 450 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_6); 451 *eeprom_ch_array = iwl_eeprom_band_6; 452 break; 453 case 7: /* 5 GHz ht40 channels */ 454 *eeprom_ch_count = ARRAY_SIZE(iwl_eeprom_band_7); 455 *eeprom_ch_array = iwl_eeprom_band_7; 456 break; 457 default: 458 *eeprom_ch_count = 0; 459 *eeprom_ch_array = NULL; 460 WARN_ON(1); 461 } 462} 463 464#define CHECK_AND_PRINT(x) \ 465 ((eeprom_ch->flags & EEPROM_CHANNEL_##x) ? # x " " : "") 466 467static void iwl_mod_ht40_chan_info(struct device *dev, 468 struct iwl_nvm_data *data, int n_channels, 469 enum nl80211_band band, u16 channel, 470 const struct iwl_eeprom_channel *eeprom_ch, 471 u8 clear_ht40_extension_channel) 472{ 473 struct ieee80211_channel *chan = NULL; 474 int i; 475 476 for (i = 0; i < n_channels; i++) { 477 if (data->channels[i].band != band) 478 continue; 479 if (data->channels[i].hw_value != channel) 480 continue; 481 chan = &data->channels[i]; 482 break; 483 } 484 485 if (!chan) 486 return; 487 488 IWL_DEBUG_EEPROM(dev, 489 "HT40 Ch. %d [%sGHz] %s%s%s%s%s(0x%02x %ddBm): Ad-Hoc %ssupported\n", 490 channel, 491 band == NL80211_BAND_5GHZ ? "5.2" : "2.4", 492 CHECK_AND_PRINT(IBSS), 493 CHECK_AND_PRINT(ACTIVE), 494 CHECK_AND_PRINT(RADAR), 495 CHECK_AND_PRINT(WIDE), 496 CHECK_AND_PRINT(DFS), 497 eeprom_ch->flags, 498 eeprom_ch->max_power_avg, 499 ((eeprom_ch->flags & EEPROM_CHANNEL_IBSS) && 500 !(eeprom_ch->flags & EEPROM_CHANNEL_RADAR)) ? "" 501 : "not "); 502 503 if (eeprom_ch->flags & EEPROM_CHANNEL_VALID) 504 chan->flags &= ~clear_ht40_extension_channel; 505} 506 507#define CHECK_AND_PRINT_I(x) \ 508 ((eeprom_ch_info[ch_idx].flags & EEPROM_CHANNEL_##x) ? # x " " : "") 509 510static int iwl_init_channel_map(struct device *dev, const struct iwl_rf_cfg *cfg, 511 struct iwl_nvm_data *data, 512 const u8 *eeprom, size_t eeprom_size) 513{ 514 int band, ch_idx; 515 const struct iwl_eeprom_channel *eeprom_ch_info; 516 const u8 *eeprom_ch_array; 517 int eeprom_ch_count; 518 int n_channels = 0; 519 520 /* 521 * Loop through the 5 EEPROM bands and add them to the parse list 522 */ 523 for (band = 1; band <= 5; band++) { 524 struct ieee80211_channel *channel; 525 526 iwl_init_band_reference(cfg, eeprom, eeprom_size, band, 527 &eeprom_ch_count, &eeprom_ch_info, 528 &eeprom_ch_array); 529 530 /* Loop through each band adding each of the channels */ 531 for (ch_idx = 0; ch_idx < eeprom_ch_count; ch_idx++) { 532 const struct iwl_eeprom_channel *eeprom_ch; 533 534 eeprom_ch = &eeprom_ch_info[ch_idx]; 535 536 if (!(eeprom_ch->flags & EEPROM_CHANNEL_VALID)) { 537 IWL_DEBUG_EEPROM(dev, 538 "Ch. %d Flags %x [%sGHz] - No traffic\n", 539 eeprom_ch_array[ch_idx], 540 eeprom_ch_info[ch_idx].flags, 541 (band != 1) ? "5.2" : "2.4"); 542 continue; 543 } 544 545 channel = &data->channels[n_channels]; 546 n_channels++; 547 548 channel->hw_value = eeprom_ch_array[ch_idx]; 549 channel->band = (band == 1) ? NL80211_BAND_2GHZ 550 : NL80211_BAND_5GHZ; 551 channel->center_freq = 552 ieee80211_channel_to_frequency( 553 channel->hw_value, channel->band); 554 555 /* set no-HT40, will enable as appropriate later */ 556 channel->flags = IEEE80211_CHAN_NO_HT40; 557 558 if (!(eeprom_ch->flags & EEPROM_CHANNEL_IBSS)) 559 channel->flags |= IEEE80211_CHAN_NO_IR; 560 561 if (!(eeprom_ch->flags & EEPROM_CHANNEL_ACTIVE)) 562 channel->flags |= IEEE80211_CHAN_NO_IR; 563 564 if (eeprom_ch->flags & EEPROM_CHANNEL_RADAR) 565 channel->flags |= IEEE80211_CHAN_RADAR; 566 567 /* Initialize regulatory-based run-time data */ 568 channel->max_power = 569 eeprom_ch_info[ch_idx].max_power_avg; 570 IWL_DEBUG_EEPROM(dev, 571 "Ch. %d [%sGHz] %s%s%s%s%s%s(0x%02x %ddBm): Ad-Hoc %ssupported\n", 572 channel->hw_value, 573 (band != 1) ? "5.2" : "2.4", 574 CHECK_AND_PRINT_I(VALID), 575 CHECK_AND_PRINT_I(IBSS), 576 CHECK_AND_PRINT_I(ACTIVE), 577 CHECK_AND_PRINT_I(RADAR), 578 CHECK_AND_PRINT_I(WIDE), 579 CHECK_AND_PRINT_I(DFS), 580 eeprom_ch_info[ch_idx].flags, 581 eeprom_ch_info[ch_idx].max_power_avg, 582 ((eeprom_ch_info[ch_idx].flags & 583 EEPROM_CHANNEL_IBSS) && 584 !(eeprom_ch_info[ch_idx].flags & 585 EEPROM_CHANNEL_RADAR)) 586 ? "" : "not "); 587 } 588 } 589 590 if (cfg->eeprom_params->enhanced_txpower) { 591 /* 592 * for newer device (6000 series and up) 593 * EEPROM contain enhanced tx power information 594 * driver need to process addition information 595 * to determine the max channel tx power limits 596 */ 597 iwl_eeprom_enhanced_txpower(dev, data, eeprom, eeprom_size, 598 n_channels); 599 } else { 600 /* All others use data from channel map */ 601 int i; 602 603 data->max_tx_pwr_half_dbm = -128; 604 605 for (i = 0; i < n_channels; i++) 606 data->max_tx_pwr_half_dbm = 607 max_t(s8, data->max_tx_pwr_half_dbm, 608 data->channels[i].max_power * 2); 609 } 610 611 /* Check if we do have HT40 channels */ 612 if (cfg->eeprom_params->regulatory_bands[5] == 613 EEPROM_REGULATORY_BAND_NO_HT40 && 614 cfg->eeprom_params->regulatory_bands[6] == 615 EEPROM_REGULATORY_BAND_NO_HT40) 616 return n_channels; 617 618 /* Two additional EEPROM bands for 2.4 and 5 GHz HT40 channels */ 619 for (band = 6; band <= 7; band++) { 620 enum nl80211_band ieeeband; 621 622 iwl_init_band_reference(cfg, eeprom, eeprom_size, band, 623 &eeprom_ch_count, &eeprom_ch_info, 624 &eeprom_ch_array); 625 626 /* EEPROM band 6 is 2.4, band 7 is 5 GHz */ 627 ieeeband = (band == 6) ? NL80211_BAND_2GHZ 628 : NL80211_BAND_5GHZ; 629 630 /* Loop through each band adding each of the channels */ 631 for (ch_idx = 0; ch_idx < eeprom_ch_count; ch_idx++) { 632 /* Set up driver's info for lower half */ 633 iwl_mod_ht40_chan_info(dev, data, n_channels, ieeeband, 634 eeprom_ch_array[ch_idx], 635 &eeprom_ch_info[ch_idx], 636 IEEE80211_CHAN_NO_HT40PLUS); 637 638 /* Set up driver's info for upper half */ 639 iwl_mod_ht40_chan_info(dev, data, n_channels, ieeeband, 640 eeprom_ch_array[ch_idx] + 4, 641 &eeprom_ch_info[ch_idx], 642 IEEE80211_CHAN_NO_HT40MINUS); 643 } 644 } 645 646 return n_channels; 647} 648/* 649 * EEPROM access time values: 650 * 651 * Driver initiates EEPROM read by writing byte address << 1 to CSR_EEPROM_REG. 652 * Driver then polls CSR_EEPROM_REG for CSR_EEPROM_REG_READ_VALID_MSK (0x1). 653 * When polling, wait 10 uSec between polling loops, up to a maximum 5000 uSec. 654 * Driver reads 16-bit value from bits 31-16 of CSR_EEPROM_REG. 655 */ 656#define IWL_EEPROM_ACCESS_TIMEOUT 5000 /* uSec */ 657 658/* 659 * The device's EEPROM semaphore prevents conflicts between driver and uCode 660 * when accessing the EEPROM; each access is a series of pulses to/from the 661 * EEPROM chip, not a single event, so even reads could conflict if they 662 * weren't arbitrated by the semaphore. 663 */ 664#define IWL_EEPROM_SEM_TIMEOUT 10 /* microseconds */ 665#define IWL_EEPROM_SEM_RETRY_LIMIT 1000 /* number of attempts (not time) */ 666 667 668static int iwl_eeprom_acquire_semaphore(struct iwl_trans *trans) 669{ 670 u16 count; 671 int ret; 672 673 for (count = 0; count < IWL_EEPROM_SEM_RETRY_LIMIT; count++) { 674 /* Request semaphore */ 675 iwl_set_bit(trans, CSR_HW_IF_CONFIG_REG, 676 CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM); 677 678 /* See if we got it */ 679 ret = iwl_poll_bits(trans, CSR_HW_IF_CONFIG_REG, 680 CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM, 681 IWL_EEPROM_SEM_TIMEOUT); 682 if (!ret) { 683 IWL_DEBUG_EEPROM(trans->dev, 684 "Acquired semaphore after %d tries.\n", 685 count+1); 686 return 0; 687 } 688 } 689 690 return ret; 691} 692 693static void iwl_eeprom_release_semaphore(struct iwl_trans *trans) 694{ 695 iwl_clear_bit(trans, CSR_HW_IF_CONFIG_REG, 696 CSR_HW_IF_CONFIG_REG_EEPROM_OWN_SEM); 697} 698 699static int iwl_eeprom_verify_signature(struct iwl_trans *trans, bool nvm_is_otp) 700{ 701 u32 gp = iwl_read32(trans, CSR_EEPROM_GP) & CSR_EEPROM_GP_VALID_MSK; 702 703 IWL_DEBUG_EEPROM(trans->dev, "EEPROM signature=0x%08x\n", gp); 704 705 switch (gp) { 706 case CSR_EEPROM_GP_BAD_SIG_EEP_GOOD_SIG_OTP: 707 if (!nvm_is_otp) { 708 IWL_ERR(trans, "EEPROM with bad signature: 0x%08x\n", 709 gp); 710 return -ENOENT; 711 } 712 return 0; 713 case CSR_EEPROM_GP_GOOD_SIG_EEP_LESS_THAN_4K: 714 case CSR_EEPROM_GP_GOOD_SIG_EEP_MORE_THAN_4K: 715 if (nvm_is_otp) { 716 IWL_ERR(trans, "OTP with bad signature: 0x%08x\n", gp); 717 return -ENOENT; 718 } 719 return 0; 720 case CSR_EEPROM_GP_BAD_SIGNATURE_BOTH_EEP_AND_OTP: 721 default: 722 IWL_ERR(trans, 723 "bad EEPROM/OTP signature, type=%s, EEPROM_GP=0x%08x\n", 724 nvm_is_otp ? "OTP" : "EEPROM", gp); 725 return -ENOENT; 726 } 727} 728 729/****************************************************************************** 730 * 731 * OTP related functions 732 * 733******************************************************************************/ 734 735static void iwl_set_otp_access_absolute(struct iwl_trans *trans) 736{ 737 iwl_read32(trans, CSR_OTP_GP_REG); 738 739 iwl_clear_bit(trans, CSR_OTP_GP_REG, 740 CSR_OTP_GP_REG_OTP_ACCESS_MODE); 741} 742 743static int iwl_nvm_is_otp(struct iwl_trans *trans) 744{ 745 u32 otpgp; 746 747 /* OTP only valid for CP/PP and after */ 748 switch (trans->info.hw_rev & CSR_HW_REV_TYPE_MSK) { 749 case CSR_HW_REV_TYPE_NONE: 750 IWL_ERR(trans, "Unknown hardware type\n"); 751 return -EIO; 752 case CSR_HW_REV_TYPE_5300: 753 case CSR_HW_REV_TYPE_5350: 754 case CSR_HW_REV_TYPE_5100: 755 case CSR_HW_REV_TYPE_5150: 756 return 0; 757 default: 758 otpgp = iwl_read32(trans, CSR_OTP_GP_REG); 759 if (otpgp & CSR_OTP_GP_REG_DEVICE_SELECT) 760 return 1; 761 return 0; 762 } 763} 764 765static int iwl_init_otp_access(struct iwl_trans *trans) 766{ 767 int ret; 768 769 ret = iwl_trans_activate_nic(trans); 770 if (ret) 771 return ret; 772 773 iwl_set_bits_prph(trans, APMG_PS_CTRL_REG, 774 APMG_PS_CTRL_VAL_RESET_REQ); 775 udelay(5); 776 iwl_clear_bits_prph(trans, APMG_PS_CTRL_REG, 777 APMG_PS_CTRL_VAL_RESET_REQ); 778 779 /* 780 * CSR auto clock gate disable bit - 781 * this is only applicable for HW with OTP shadow RAM 782 */ 783 if (trans->mac_cfg->base->shadow_ram_support) 784 iwl_set_bit(trans, CSR_DBG_LINK_PWR_MGMT_REG, 785 CSR_RESET_LINK_PWR_MGMT_DISABLED); 786 787 return 0; 788} 789 790static int iwl_read_otp_word(struct iwl_trans *trans, u16 addr, 791 __le16 *eeprom_data) 792{ 793 int ret = 0; 794 u32 r; 795 u32 otpgp; 796 797 iwl_write32(trans, CSR_EEPROM_REG, 798 CSR_EEPROM_REG_MSK_ADDR & (addr << 1)); 799 ret = iwl_poll_bits(trans, CSR_EEPROM_REG, 800 CSR_EEPROM_REG_READ_VALID_MSK, 801 IWL_EEPROM_ACCESS_TIMEOUT); 802 if (ret) { 803 IWL_ERR(trans, "Time out reading OTP[%d]\n", addr); 804 return ret; 805 } 806 r = iwl_read32(trans, CSR_EEPROM_REG); 807 /* check for ECC errors: */ 808 otpgp = iwl_read32(trans, CSR_OTP_GP_REG); 809 if (otpgp & CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK) { 810 /* stop in this case */ 811 /* set the uncorrectable OTP ECC bit for acknowledgment */ 812 iwl_set_bit(trans, CSR_OTP_GP_REG, 813 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK); 814 IWL_ERR(trans, "Uncorrectable OTP ECC error, abort OTP read\n"); 815 return -EINVAL; 816 } 817 if (otpgp & CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK) { 818 /* continue in this case */ 819 /* set the correctable OTP ECC bit for acknowledgment */ 820 iwl_set_bit(trans, CSR_OTP_GP_REG, 821 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK); 822 IWL_ERR(trans, "Correctable OTP ECC error, continue read\n"); 823 } 824 *eeprom_data = cpu_to_le16(r >> 16); 825 return 0; 826} 827 828/* 829 * iwl_is_otp_empty: check for empty OTP 830 */ 831static bool iwl_is_otp_empty(struct iwl_trans *trans) 832{ 833 u16 next_link_addr = 0; 834 __le16 link_value; 835 bool is_empty = false; 836 837 /* locate the beginning of OTP link list */ 838 if (!iwl_read_otp_word(trans, next_link_addr, &link_value)) { 839 if (!link_value) { 840 IWL_ERR(trans, "OTP is empty\n"); 841 is_empty = true; 842 } 843 } else { 844 IWL_ERR(trans, "Unable to read first block of OTP list.\n"); 845 is_empty = true; 846 } 847 848 return is_empty; 849} 850 851 852/* 853 * iwl_find_otp_image: find EEPROM image in OTP 854 * finding the OTP block that contains the EEPROM image. 855 * the last valid block on the link list (the block _before_ the last block) 856 * is the block we should read and used to configure the device. 857 * If all the available OTP blocks are full, the last block will be the block 858 * we should read and used to configure the device. 859 * only perform this operation if shadow RAM is disabled 860 */ 861static int iwl_find_otp_image(struct iwl_trans *trans, 862 u16 *validblockaddr) 863{ 864 u16 next_link_addr = 0, valid_addr; 865 __le16 link_value = 0; 866 int usedblocks = 0; 867 868 /* set addressing mode to absolute to traverse the link list */ 869 iwl_set_otp_access_absolute(trans); 870 871 /* checking for empty OTP or error */ 872 if (iwl_is_otp_empty(trans)) 873 return -EINVAL; 874 875 /* 876 * start traverse link list 877 * until reach the max number of OTP blocks 878 * different devices have different number of OTP blocks 879 */ 880 do { 881 /* save current valid block address 882 * check for more block on the link list 883 */ 884 valid_addr = next_link_addr; 885 next_link_addr = le16_to_cpu(link_value) * sizeof(u16); 886 IWL_DEBUG_EEPROM(trans->dev, "OTP blocks %d addr 0x%x\n", 887 usedblocks, next_link_addr); 888 if (iwl_read_otp_word(trans, next_link_addr, &link_value)) 889 return -EINVAL; 890 if (!link_value) { 891 /* 892 * reach the end of link list, return success and 893 * set address point to the starting address 894 * of the image 895 */ 896 *validblockaddr = valid_addr; 897 /* skip first 2 bytes (link list pointer) */ 898 *validblockaddr += 2; 899 return 0; 900 } 901 /* more in the link list, continue */ 902 usedblocks++; 903 } while (usedblocks <= trans->mac_cfg->base->max_ll_items); 904 905 /* OTP has no valid blocks */ 906 IWL_DEBUG_EEPROM(trans->dev, "OTP has no valid blocks\n"); 907 return -EINVAL; 908} 909 910/* 911 * iwl_read_eeprom - read EEPROM contents 912 * 913 * Load the EEPROM contents from adapter and return it 914 * and its size. 915 * 916 * NOTE: This routine uses the non-debug IO access functions. 917 */ 918int iwl_read_eeprom(struct iwl_trans *trans, u8 **eeprom, size_t *eeprom_size) 919{ 920 __le16 *e; 921 u32 gp = iwl_read32(trans, CSR_EEPROM_GP); 922 int sz; 923 int ret; 924 u16 addr; 925 u16 validblockaddr = 0; 926 u16 cache_addr = 0; 927 int nvm_is_otp; 928 929 if (!eeprom || !eeprom_size) 930 return -EINVAL; 931 932 nvm_is_otp = iwl_nvm_is_otp(trans); 933 if (nvm_is_otp < 0) 934 return nvm_is_otp; 935 936 sz = trans->mac_cfg->base->eeprom_size; 937 IWL_DEBUG_EEPROM(trans->dev, "NVM size = %d\n", sz); 938 939 e = kmalloc(sz, GFP_KERNEL); 940 if (!e) 941 return -ENOMEM; 942 943 ret = iwl_eeprom_verify_signature(trans, nvm_is_otp); 944 if (ret) { 945 IWL_ERR(trans, "EEPROM not found, EEPROM_GP=0x%08x\n", gp); 946 goto err_free; 947 } 948 949 /* Make sure driver (instead of uCode) is allowed to read EEPROM */ 950 ret = iwl_eeprom_acquire_semaphore(trans); 951 if (ret) { 952 IWL_ERR(trans, "Failed to acquire EEPROM semaphore.\n"); 953 goto err_free; 954 } 955 956 if (nvm_is_otp) { 957 ret = iwl_init_otp_access(trans); 958 if (ret) { 959 IWL_ERR(trans, "Failed to initialize OTP access.\n"); 960 goto err_unlock; 961 } 962 963 iwl_write32(trans, CSR_EEPROM_GP, 964 iwl_read32(trans, CSR_EEPROM_GP) & 965 ~CSR_EEPROM_GP_IF_OWNER_MSK); 966 967 iwl_set_bit(trans, CSR_OTP_GP_REG, 968 CSR_OTP_GP_REG_ECC_CORR_STATUS_MSK | 969 CSR_OTP_GP_REG_ECC_UNCORR_STATUS_MSK); 970 /* traversing the linked list if no shadow ram supported */ 971 if (!trans->mac_cfg->base->shadow_ram_support) { 972 ret = iwl_find_otp_image(trans, &validblockaddr); 973 if (ret) 974 goto err_unlock; 975 } 976 for (addr = validblockaddr; addr < validblockaddr + sz; 977 addr += sizeof(u16)) { 978 __le16 eeprom_data; 979 980 ret = iwl_read_otp_word(trans, addr, &eeprom_data); 981 if (ret) 982 goto err_unlock; 983 e[cache_addr / 2] = eeprom_data; 984 cache_addr += sizeof(u16); 985 } 986 } else { 987 /* eeprom is an array of 16bit values */ 988 for (addr = 0; addr < sz; addr += sizeof(u16)) { 989 u32 r; 990 991 iwl_write32(trans, CSR_EEPROM_REG, 992 CSR_EEPROM_REG_MSK_ADDR & (addr << 1)); 993 994 ret = iwl_poll_bits(trans, CSR_EEPROM_REG, 995 CSR_EEPROM_REG_READ_VALID_MSK, 996 IWL_EEPROM_ACCESS_TIMEOUT); 997 if (ret) { 998 IWL_ERR(trans, 999 "Time out reading EEPROM[%d]\n", addr); 1000 goto err_unlock; 1001 } 1002 r = iwl_read32(trans, CSR_EEPROM_REG); 1003 e[addr / 2] = cpu_to_le16(r >> 16); 1004 } 1005 } 1006 1007 IWL_DEBUG_EEPROM(trans->dev, "NVM Type: %s\n", 1008 nvm_is_otp ? "OTP" : "EEPROM"); 1009 1010 iwl_eeprom_release_semaphore(trans); 1011 1012 *eeprom_size = sz; 1013 *eeprom = (u8 *)e; 1014 return 0; 1015 1016 err_unlock: 1017 iwl_eeprom_release_semaphore(trans); 1018 err_free: 1019 kfree(e); 1020 1021 return ret; 1022} 1023 1024static void iwl_init_sbands(struct iwl_trans *trans, const struct iwl_rf_cfg *cfg, 1025 struct iwl_nvm_data *data, 1026 const u8 *eeprom, size_t eeprom_size) 1027{ 1028 struct device *dev = trans->dev; 1029 int n_channels = iwl_init_channel_map(dev, cfg, data, 1030 eeprom, eeprom_size); 1031 int n_used = 0; 1032 struct ieee80211_supported_band *sband; 1033 1034 sband = &data->bands[NL80211_BAND_2GHZ]; 1035 sband->band = NL80211_BAND_2GHZ; 1036 sband->bitrates = &iwl_cfg80211_rates[RATES_24_OFFS]; 1037 sband->n_bitrates = N_RATES_24; 1038 n_used += iwl_init_sband_channels(data, sband, n_channels, 1039 NL80211_BAND_2GHZ); 1040 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_2GHZ, 1041 data->valid_tx_ant, data->valid_rx_ant); 1042 1043 sband = &data->bands[NL80211_BAND_5GHZ]; 1044 sband->band = NL80211_BAND_5GHZ; 1045 sband->bitrates = &iwl_cfg80211_rates[RATES_52_OFFS]; 1046 sband->n_bitrates = N_RATES_52; 1047 n_used += iwl_init_sband_channels(data, sband, n_channels, 1048 NL80211_BAND_5GHZ); 1049 iwl_init_ht_hw_capab(trans, data, &sband->ht_cap, NL80211_BAND_5GHZ, 1050 data->valid_tx_ant, data->valid_rx_ant); 1051 1052 if (n_channels != n_used) 1053 IWL_ERR_DEV(dev, "EEPROM: used only %d of %d channels\n", 1054 n_used, n_channels); 1055} 1056 1057/* EEPROM data functions */ 1058struct iwl_nvm_data * 1059iwl_parse_eeprom_data(struct iwl_trans *trans, const struct iwl_rf_cfg *cfg, 1060 const u8 *eeprom, size_t eeprom_size) 1061{ 1062 struct iwl_nvm_data *data; 1063 struct device *dev = trans->dev; 1064 const void *tmp; 1065 u16 radio_cfg, sku; 1066 1067 if (WARN_ON(!cfg || !cfg->eeprom_params)) 1068 return NULL; 1069 1070 data = kzalloc(struct_size(data, channels, IWL_NUM_CHANNELS), 1071 GFP_KERNEL); 1072 if (!data) 1073 return NULL; 1074 1075 /* get MAC address(es) */ 1076 tmp = iwl_eeprom_query_addr(eeprom, eeprom_size, EEPROM_MAC_ADDRESS); 1077 if (!tmp) 1078 goto err_free; 1079 memcpy(data->hw_addr, tmp, ETH_ALEN); 1080 data->n_hw_addrs = iwl_eeprom_query16(eeprom, eeprom_size, 1081 EEPROM_NUM_MAC_ADDRESS); 1082 1083 if (iwl_eeprom_read_calib(eeprom, eeprom_size, data)) 1084 goto err_free; 1085 1086 tmp = iwl_eeprom_query_addr(eeprom, eeprom_size, EEPROM_XTAL); 1087 if (!tmp) 1088 goto err_free; 1089 memcpy(data->xtal_calib, tmp, sizeof(data->xtal_calib)); 1090 1091 tmp = iwl_eeprom_query_addr(eeprom, eeprom_size, 1092 EEPROM_RAW_TEMPERATURE); 1093 if (!tmp) 1094 goto err_free; 1095 data->raw_temperature = *(const __le16 *)tmp; 1096 1097 tmp = iwl_eeprom_query_addr(eeprom, eeprom_size, 1098 EEPROM_KELVIN_TEMPERATURE); 1099 if (!tmp) 1100 goto err_free; 1101 data->kelvin_temperature = *(const __le16 *)tmp; 1102 data->kelvin_voltage = *((const __le16 *)tmp + 1); 1103 1104 radio_cfg = 1105 iwl_eeprom_query16(eeprom, eeprom_size, EEPROM_RADIO_CONFIG); 1106 data->radio_cfg_dash = EEPROM_RF_CFG_DASH_MSK(radio_cfg); 1107 data->radio_cfg_pnum = EEPROM_RF_CFG_PNUM_MSK(radio_cfg); 1108 data->radio_cfg_step = EEPROM_RF_CFG_STEP_MSK(radio_cfg); 1109 data->radio_cfg_type = EEPROM_RF_CFG_TYPE_MSK(radio_cfg); 1110 data->valid_rx_ant = EEPROM_RF_CFG_RX_ANT_MSK(radio_cfg); 1111 data->valid_tx_ant = EEPROM_RF_CFG_TX_ANT_MSK(radio_cfg); 1112 1113 sku = iwl_eeprom_query16(eeprom, eeprom_size, 1114 EEPROM_SKU_CAP); 1115 data->sku_cap_11n_enable = sku & EEPROM_SKU_CAP_11N_ENABLE; 1116 data->sku_cap_amt_enable = sku & EEPROM_SKU_CAP_AMT_ENABLE; 1117 data->sku_cap_band_24ghz_enable = sku & EEPROM_SKU_CAP_BAND_24GHZ; 1118 data->sku_cap_band_52ghz_enable = sku & EEPROM_SKU_CAP_BAND_52GHZ; 1119 data->sku_cap_ipan_enable = sku & EEPROM_SKU_CAP_IPAN_ENABLE; 1120 if (iwlwifi_mod_params.disable_11n & IWL_DISABLE_HT_ALL) 1121 data->sku_cap_11n_enable = false; 1122 1123 data->nvm_version = iwl_eeprom_query16(eeprom, eeprom_size, 1124 EEPROM_VERSION); 1125 1126 /* check overrides (some devices have wrong EEPROM) */ 1127 if (cfg->valid_tx_ant) 1128 data->valid_tx_ant = cfg->valid_tx_ant; 1129 if (cfg->valid_rx_ant) 1130 data->valid_rx_ant = cfg->valid_rx_ant; 1131 1132 if (!data->valid_tx_ant || !data->valid_rx_ant) { 1133 IWL_ERR_DEV(dev, "invalid antennas (0x%x, 0x%x)\n", 1134 data->valid_tx_ant, data->valid_rx_ant); 1135 goto err_free; 1136 } 1137 1138 iwl_init_sbands(trans, cfg, data, eeprom, eeprom_size); 1139 1140 return data; 1141 err_free: 1142 kfree(data); 1143 return NULL; 1144}
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