sc.c

  1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
  2/*
  3 * Copyright (C) 2015-2017 Intel Deutschland GmbH
  4 * Copyright (C) 2018-2025 Intel Corporation
  5 */
  6#include <linux/module.h>
  7#include <linux/stringify.h>
  8#include "iwl-config.h"
  9#include "iwl-prph.h"
 10#include "fw/api/txq.h"
 11
 12/* Highest firmware core release supported */
 13#define IWL_SC_UCODE_CORE_MAX	101
 14
 15/* Lowest firmware API version supported */
 16#define IWL_SC_UCODE_API_MIN	100
 17
 18/* NVM versions */
 19#define IWL_SC_NVM_VERSION		0x0a1d
 20
 21/* Memory offsets and lengths */
 22#define IWL_SC_SMEM_OFFSET		0x400000
 23#define IWL_SC_SMEM_LEN			0xD0000
 24
 25#define IWL_SC_A_FM_B_FW_PRE		"iwlwifi-sc-a0-fm-b0"
 26#define IWL_SC_A_FM_C_FW_PRE		"iwlwifi-sc-a0-fm-c0"
 27#define IWL_SC_A_WH_A_FW_PRE		"iwlwifi-sc-a0-wh-a0"
 28#define IWL_SC2_A_FM_C_FW_PRE		"iwlwifi-sc2-a0-fm-c0"
 29#define IWL_SC2_A_WH_A_FW_PRE		"iwlwifi-sc2-a0-wh-a0"
 30
 31static const struct iwl_family_base_params iwl_sc_base = {
 32	.num_of_queues = 512,
 33	.max_tfd_queue_size = 65536,
 34	.shadow_ram_support = true,
 35	.led_compensation = 57,
 36	.wd_timeout = IWL_LONG_WD_TIMEOUT,
 37	.max_event_log_size = 512,
 38	.shadow_reg_enable = true,
 39	.pcie_l1_allowed = true,
 40	.smem_offset = IWL_SC_SMEM_OFFSET,
 41	.smem_len = IWL_SC_SMEM_LEN,
 42	.apmg_not_supported = true,
 43	.mac_addr_from_csr = 0x30,
 44	.d3_debug_data_base_addr = 0x401000,
 45	.d3_debug_data_length = 60 * 1024,
 46	.mon_smem_regs = {
 47		.write_ptr = {
 48			.addr = LDBG_M2S_BUF_WPTR,
 49			.mask = LDBG_M2S_BUF_WPTR_VAL_MSK,
 50		},
 51		.cycle_cnt = {
 52			.addr = LDBG_M2S_BUF_WRAP_CNT,
 53			.mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK,
 54		},
 55	},
 56	.min_txq_size = 128,
 57	.gp2_reg_addr = 0xd02c68,
 58	.min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT,
 59	.mon_dram_regs = {
 60		.write_ptr = {
 61			.addr = DBGC_CUR_DBGBUF_STATUS,
 62			.mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK,
 63		},
 64		.cycle_cnt = {
 65			.addr = DBGC_DBGBUF_WRAP_AROUND,
 66			.mask = 0xffffffff,
 67		},
 68		.cur_frag = {
 69			.addr = DBGC_CUR_DBGBUF_STATUS,
 70			.mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK,
 71		},
 72	},
 73	.mon_dbgi_regs = {
 74		.write_ptr = {
 75			.addr = DBGI_SRAM_FIFO_POINTERS,
 76			.mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK,
 77		},
 78	},
 79	.features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
 80	.ucode_api_max = ENCODE_CORE_AS_API(IWL_SC_UCODE_CORE_MAX),
 81	.ucode_api_min = IWL_SC_UCODE_API_MIN,
 82};
 83
 84const struct iwl_mac_cfg iwl_sc_mac_cfg = {
 85	.device_family = IWL_DEVICE_FAMILY_SC,
 86	.base = &iwl_sc_base,
 87	.mq_rx_supported = true,
 88	.gen2 = true,
 89	.integrated = true,
 90	.umac_prph_offset = 0x300000,
 91	.xtal_latency = 12000,
 92	.low_latency_xtal = true,
 93	.ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
 94};
 95
 96IWL_CORE_FW(IWL_SC_A_FM_B_FW_PRE, IWL_SC_UCODE_CORE_MAX);
 97IWL_CORE_FW(IWL_SC_A_FM_C_FW_PRE, IWL_SC_UCODE_CORE_MAX);
 98IWL_CORE_FW(IWL_SC_A_WH_A_FW_PRE, IWL_SC_UCODE_CORE_MAX);
 99IWL_CORE_FW(IWL_SC2_A_FM_C_FW_PRE, IWL_SC_UCODE_CORE_MAX);
100IWL_CORE_FW(IWL_SC2_A_WH_A_FW_PRE, IWL_SC_UCODE_CORE_MAX);