bz.c

  1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
  2/*
  3 * Copyright (C) 2015-2017 Intel Deutschland GmbH
  4 * Copyright (C) 2018-2025 Intel Corporation
  5 */
  6#include <linux/module.h>
  7#include <linux/stringify.h>
  8#include "iwl-config.h"
  9#include "iwl-prph.h"
 10#include "fw/api/txq.h"
 11
 12/* Highest firmware core release supported */
 13#define IWL_BZ_UCODE_CORE_MAX	101
 14
 15/* Lowest firmware API version supported */
 16#define IWL_BZ_UCODE_API_MIN	100
 17
 18/* Memory offsets and lengths */
 19#define IWL_BZ_SMEM_OFFSET		0x400000
 20#define IWL_BZ_SMEM_LEN			0xD0000
 21
 22#define IWL_BZ_A_FM_B_FW_PRE		"iwlwifi-bz-a0-fm-b0"
 23#define IWL_BZ_A_FM_C_FW_PRE		"iwlwifi-bz-a0-fm-c0"
 24#define IWL_BZ_A_FM4_B_FW_PRE		"iwlwifi-bz-a0-fm4-b0"
 25#define IWL_GL_B_FM_B_FW_PRE		"iwlwifi-gl-b0-fm-b0"
 26#define IWL_GL_C_FM_C_FW_PRE		"iwlwifi-gl-c0-fm-c0"
 27
 28static const struct iwl_family_base_params iwl_bz_base = {
 29	.num_of_queues = 512,
 30	.max_tfd_queue_size = 65536,
 31	.shadow_ram_support = true,
 32	.led_compensation = 57,
 33	.wd_timeout = IWL_LONG_WD_TIMEOUT,
 34	.max_event_log_size = 512,
 35	.shadow_reg_enable = true,
 36	.pcie_l1_allowed = true,
 37	.smem_offset = IWL_BZ_SMEM_OFFSET,
 38	.smem_len = IWL_BZ_SMEM_LEN,
 39	.apmg_not_supported = true,
 40	.mac_addr_from_csr = 0x30,
 41	.d3_debug_data_base_addr = 0x401000,
 42	.d3_debug_data_length = 60 * 1024,
 43	.mon_smem_regs = {
 44		.write_ptr = {
 45			.addr = LDBG_M2S_BUF_WPTR,
 46			.mask = LDBG_M2S_BUF_WPTR_VAL_MSK,
 47	},
 48		.cycle_cnt = {
 49			.addr = LDBG_M2S_BUF_WRAP_CNT,
 50			.mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK,
 51		},
 52	},
 53	.min_txq_size = 128,
 54	.gp2_reg_addr = 0xd02c68,
 55	.min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_EHT,
 56	.mon_dram_regs = {
 57		.write_ptr = {
 58			.addr = DBGC_CUR_DBGBUF_STATUS,
 59			.mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK,
 60		},
 61		.cycle_cnt = {
 62			.addr = DBGC_DBGBUF_WRAP_AROUND,
 63			.mask = 0xffffffff,
 64		},
 65		.cur_frag = {
 66			.addr = DBGC_CUR_DBGBUF_STATUS,
 67			.mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK,
 68		},
 69	},
 70	.mon_dbgi_regs = {
 71		.write_ptr = {
 72			.addr = DBGI_SRAM_FIFO_POINTERS,
 73			.mask = DBGI_SRAM_FIFO_POINTERS_WR_PTR_MSK,
 74		},
 75	},
 76	.features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
 77	.ucode_api_max = ENCODE_CORE_AS_API(IWL_BZ_UCODE_CORE_MAX),
 78	.ucode_api_min = IWL_BZ_UCODE_API_MIN,
 79};
 80
 81const struct iwl_mac_cfg iwl_bz_mac_cfg = {
 82	.device_family = IWL_DEVICE_FAMILY_BZ,
 83	.base = &iwl_bz_base,
 84	.mq_rx_supported = true,
 85	.gen2 = true,
 86	.integrated = true,
 87	.umac_prph_offset = 0x300000,
 88	.xtal_latency = 12000,
 89	.low_latency_xtal = true,
 90	.ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
 91};
 92EXPORT_SYMBOL_IF_IWLWIFI_KUNIT(iwl_bz_mac_cfg);
 93
 94const struct iwl_mac_cfg iwl_gl_mac_cfg = {
 95	.device_family = IWL_DEVICE_FAMILY_BZ,
 96	.base = &iwl_bz_base,
 97	.mq_rx_supported = true,
 98	.gen2 = true,
 99	.umac_prph_offset = 0x300000,
100	.xtal_latency = 12000,
101	.low_latency_xtal = true,
102};
103
104IWL_CORE_FW(IWL_BZ_A_FM_B_FW_PRE, IWL_BZ_UCODE_CORE_MAX);
105IWL_CORE_FW(IWL_BZ_A_FM_C_FW_PRE, IWL_BZ_UCODE_CORE_MAX);
106IWL_CORE_FW(IWL_BZ_A_FM4_B_FW_PRE, IWL_BZ_UCODE_CORE_MAX);
107IWL_CORE_FW(IWL_GL_B_FM_B_FW_PRE, IWL_BZ_UCODE_CORE_MAX);
108IWL_CORE_FW(IWL_GL_C_FM_C_FW_PRE, IWL_BZ_UCODE_CORE_MAX);