ax210.c

  1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
  2/*
  3 * Copyright (C) 2015-2017 Intel Deutschland GmbH
  4 * Copyright (C) 2018-2025 Intel Corporation
  5 */
  6#include <linux/module.h>
  7#include <linux/stringify.h>
  8#include "iwl-config.h"
  9#include "iwl-prph.h"
 10#include "fw/api/txq.h"
 11
 12/* Highest firmware API version supported */
 13#define IWL_AX210_UCODE_API_MAX	89
 14
 15/* Lowest firmware API version supported */
 16#define IWL_AX210_UCODE_API_MIN	89
 17
 18/* Memory offsets and lengths */
 19#define IWL_AX210_SMEM_OFFSET		0x400000
 20#define IWL_AX210_SMEM_LEN		0xD0000
 21
 22static const struct iwl_family_base_params iwl_ax210_base = {
 23	.num_of_queues = 512,
 24	.max_tfd_queue_size = 65536,
 25	.shadow_ram_support = true,
 26	.led_compensation = 57,
 27	.wd_timeout = IWL_LONG_WD_TIMEOUT,
 28	.max_event_log_size = 512,
 29	.shadow_reg_enable = true,
 30	.pcie_l1_allowed = true,
 31	.smem_offset = IWL_AX210_SMEM_OFFSET,
 32	.smem_len = IWL_AX210_SMEM_LEN,
 33	.features = IWL_TX_CSUM_NETIF_FLAGS | NETIF_F_RXCSUM,
 34	.apmg_not_supported = true,
 35	.mac_addr_from_csr = 0x380,
 36	.d3_debug_data_base_addr = 0x401000,
 37	.d3_debug_data_length = 60 * 1024,
 38	.mon_smem_regs = {
 39		.write_ptr = {
 40			.addr = LDBG_M2S_BUF_WPTR,
 41			.mask = LDBG_M2S_BUF_WPTR_VAL_MSK,
 42		},
 43		.cycle_cnt = {
 44			.addr = LDBG_M2S_BUF_WRAP_CNT,
 45			.mask = LDBG_M2S_BUF_WRAP_CNT_VAL_MSK,
 46		},
 47	},
 48	.min_txq_size = 128,
 49	.gp2_reg_addr = 0xd02c68,
 50	.min_ba_txq_size = IWL_DEFAULT_QUEUE_SIZE_HE,
 51	.mon_dram_regs = {
 52		.write_ptr = {
 53			.addr = DBGC_CUR_DBGBUF_STATUS,
 54			.mask = DBGC_CUR_DBGBUF_STATUS_OFFSET_MSK,
 55		},
 56		.cycle_cnt = {
 57			.addr = DBGC_DBGBUF_WRAP_AROUND,
 58			.mask = 0xffffffff,
 59		},
 60		.cur_frag = {
 61			.addr = DBGC_CUR_DBGBUF_STATUS,
 62			.mask = DBGC_CUR_DBGBUF_STATUS_IDX_MSK,
 63		},
 64	},
 65	.ucode_api_min = IWL_AX210_UCODE_API_MIN,
 66	.ucode_api_max = IWL_AX210_UCODE_API_MAX,
 67};
 68
 69const struct iwl_mac_cfg iwl_ty_mac_cfg = {
 70	.mq_rx_supported = true,
 71	.gen2 = true,
 72	.device_family = IWL_DEVICE_FAMILY_AX210,
 73	.base = &iwl_ax210_base,
 74	.umac_prph_offset = 0x300000,
 75	/* TODO: the following values need to be checked */
 76	.xtal_latency = 500,
 77};
 78
 79const struct iwl_mac_cfg iwl_so_mac_cfg = {
 80	.mq_rx_supported = true,
 81	.gen2 = true,
 82	.device_family = IWL_DEVICE_FAMILY_AX210,
 83	.base = &iwl_ax210_base,
 84	.umac_prph_offset = 0x300000,
 85	.integrated = true,
 86	/* TODO: the following values need to be checked */
 87	.xtal_latency = 500,
 88	.ltr_delay = IWL_CFG_TRANS_LTR_DELAY_200US,
 89};
 90
 91const struct iwl_mac_cfg iwl_so_long_latency_mac_cfg = {
 92	.mq_rx_supported = true,
 93	.gen2 = true,
 94	.device_family = IWL_DEVICE_FAMILY_AX210,
 95	.base = &iwl_ax210_base,
 96	.umac_prph_offset = 0x300000,
 97	.integrated = true,
 98	.low_latency_xtal = true,
 99	.xtal_latency = 12000,
100	.ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
101};
102
103const struct iwl_mac_cfg iwl_so_long_latency_imr_mac_cfg = {
104	.mq_rx_supported = true,
105	.gen2 = true,
106	.device_family = IWL_DEVICE_FAMILY_AX210,
107	.base = &iwl_ax210_base,
108	.umac_prph_offset = 0x300000,
109	.integrated = true,
110	.low_latency_xtal = true,
111	.xtal_latency = 12000,
112	.ltr_delay = IWL_CFG_TRANS_LTR_DELAY_2500US,
113	.imr_enabled = true,
114};
115
116const struct iwl_mac_cfg iwl_ma_mac_cfg = {
117	.device_family = IWL_DEVICE_FAMILY_AX210,
118	.base = &iwl_ax210_base,
119	.mq_rx_supported = true,
120	.gen2 = true,
121	.integrated = true,
122	.umac_prph_offset = 0x300000
123};