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4965-mac.c
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linux-6.19.14/drivers/net/wireless/intel/iwlegacy/4965-mac.c
1// SPDX-License-Identifier: GPL-2.0-only 2/****************************************************************************** 3 * 4 * Copyright(c) 2003 - 2011 Intel Corporation. All rights reserved. 5 * 6 * Portions of this file are derived from the ipw3945 project, as well 7 * as portions of the ieee80211 subsystem header files. 8 * 9 * Contact Information: 10 * Intel Linux Wireless <ilw@linux.intel.com> 11 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497 12 * 13 *****************************************************************************/ 14 15#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 16 17#include <linux/kernel.h> 18#include <linux/module.h> 19#include <linux/init.h> 20#include <linux/pci.h> 21#include <linux/slab.h> 22#include <linux/dma-mapping.h> 23#include <linux/delay.h> 24#include <linux/sched.h> 25#include <linux/skbuff.h> 26#include <linux/netdevice.h> 27#include <linux/firmware.h> 28#include <linux/etherdevice.h> 29#include <linux/if_arp.h> 30#include <linux/units.h> 31 32#include <net/mac80211.h> 33 34#include <asm/div64.h> 35 36#define DRV_NAME "iwl4965" 37 38#include "common.h" 39#include "4965.h" 40 41/****************************************************************************** 42 * 43 * module boiler plate 44 * 45 ******************************************************************************/ 46 47/* 48 * module name, copyright, version, etc. 49 */ 50#define DRV_DESCRIPTION "Intel(R) Wireless WiFi 4965 driver for Linux" 51 52#ifdef CONFIG_IWLEGACY_DEBUG 53#define VD "d" 54#else 55#define VD 56#endif 57 58#define DRV_VERSION IWLWIFI_VERSION VD 59 60MODULE_DESCRIPTION(DRV_DESCRIPTION); 61MODULE_VERSION(DRV_VERSION); 62MODULE_AUTHOR(DRV_COPYRIGHT " " DRV_AUTHOR); 63MODULE_LICENSE("GPL"); 64MODULE_ALIAS("iwl4965"); 65 66void 67il4965_check_abort_status(struct il_priv *il, u8 frame_count, u32 status) 68{ 69 if (frame_count == 1 && status == TX_STATUS_FAIL_RFKILL_FLUSH) { 70 IL_ERR("Tx flush command to flush out all frames\n"); 71 if (!test_bit(S_EXIT_PENDING, &il->status)) 72 queue_work(il->workqueue, &il->tx_flush); 73 } 74} 75 76/* 77 * EEPROM 78 */ 79struct il_mod_params il4965_mod_params = { 80 .restart_fw = 1, 81 /* the rest are 0 by default */ 82}; 83 84void 85il4965_rx_queue_reset(struct il_priv *il, struct il_rx_queue *rxq) 86{ 87 unsigned long flags; 88 int i; 89 spin_lock_irqsave(&rxq->lock, flags); 90 INIT_LIST_HEAD(&rxq->rx_free); 91 INIT_LIST_HEAD(&rxq->rx_used); 92 /* Fill the rx_used queue with _all_ of the Rx buffers */ 93 for (i = 0; i < RX_FREE_BUFFERS + RX_QUEUE_SIZE; i++) { 94 /* In the reset function, these buffers may have been allocated 95 * to an SKB, so we need to unmap and free potential storage */ 96 if (rxq->pool[i].page != NULL) { 97 dma_unmap_page(&il->pci_dev->dev, 98 rxq->pool[i].page_dma, 99 PAGE_SIZE << il->hw_params.rx_page_order, 100 DMA_FROM_DEVICE); 101 __il_free_pages(il, rxq->pool[i].page); 102 rxq->pool[i].page = NULL; 103 } 104 list_add_tail(&rxq->pool[i].list, &rxq->rx_used); 105 } 106 107 for (i = 0; i < RX_QUEUE_SIZE; i++) 108 rxq->queue[i] = NULL; 109 110 /* Set us so that we have processed and used all buffers, but have 111 * not restocked the Rx queue with fresh buffers */ 112 rxq->read = rxq->write = 0; 113 rxq->write_actual = 0; 114 rxq->free_count = 0; 115 spin_unlock_irqrestore(&rxq->lock, flags); 116} 117 118int 119il4965_rx_init(struct il_priv *il, struct il_rx_queue *rxq) 120{ 121 u32 rb_size; 122 const u32 rfdnlog = RX_QUEUE_SIZE_LOG; /* 256 RBDs */ 123 u32 rb_timeout = 0; 124 125 if (il->cfg->mod_params->amsdu_size_8K) 126 rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_8K; 127 else 128 rb_size = FH49_RCSR_RX_CONFIG_REG_VAL_RB_SIZE_4K; 129 130 /* Stop Rx DMA */ 131 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0); 132 133 /* Reset driver's Rx queue write idx */ 134 il_wr(il, FH49_RSCSR_CHNL0_RBDCB_WPTR_REG, 0); 135 136 /* Tell device where to find RBD circular buffer in DRAM */ 137 il_wr(il, FH49_RSCSR_CHNL0_RBDCB_BASE_REG, (u32) (rxq->bd_dma >> 8)); 138 139 /* Tell device where in DRAM to update its Rx status */ 140 il_wr(il, FH49_RSCSR_CHNL0_STTS_WPTR_REG, rxq->rb_stts_dma >> 4); 141 142 /* Enable Rx DMA 143 * Direct rx interrupts to hosts 144 * Rx buffer size 4 or 8k 145 * RB timeout 0x10 146 * 256 RBDs 147 */ 148 il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 149 FH49_RCSR_RX_CONFIG_CHNL_EN_ENABLE_VAL | 150 FH49_RCSR_CHNL0_RX_CONFIG_IRQ_DEST_INT_HOST_VAL | 151 FH49_RCSR_CHNL0_RX_CONFIG_SINGLE_FRAME_MSK | 152 rb_size | 153 (rb_timeout << FH49_RCSR_RX_CONFIG_REG_IRQ_RBTH_POS) | 154 (rfdnlog << FH49_RCSR_RX_CONFIG_RBDCB_SIZE_POS)); 155 156 /* Set interrupt coalescing timer to default (2048 usecs) */ 157 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_TIMEOUT_DEF); 158 159 return 0; 160} 161 162static void 163il4965_set_pwr_vmain(struct il_priv *il) 164{ 165/* 166 * (for documentation purposes) 167 * to set power to V_AUX, do: 168 169 if (pci_pme_capable(il->pci_dev, PCI_D3cold)) 170 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG, 171 APMG_PS_CTRL_VAL_PWR_SRC_VAUX, 172 ~APMG_PS_CTRL_MSK_PWR_SRC); 173 */ 174 175 il_set_bits_mask_prph(il, APMG_PS_CTRL_REG, 176 APMG_PS_CTRL_VAL_PWR_SRC_VMAIN, 177 ~APMG_PS_CTRL_MSK_PWR_SRC); 178} 179 180int 181il4965_hw_nic_init(struct il_priv *il) 182{ 183 unsigned long flags; 184 struct il_rx_queue *rxq = &il->rxq; 185 int ret; 186 187 spin_lock_irqsave(&il->lock, flags); 188 il_apm_init(il); 189 /* Set interrupt coalescing calibration timer to default (512 usecs) */ 190 il_write8(il, CSR_INT_COALESCING, IL_HOST_INT_CALIB_TIMEOUT_DEF); 191 spin_unlock_irqrestore(&il->lock, flags); 192 193 il4965_set_pwr_vmain(il); 194 il4965_nic_config(il); 195 196 /* Allocate the RX queue, or reset if it is already allocated */ 197 if (!rxq->bd) { 198 ret = il_rx_queue_alloc(il); 199 if (ret) { 200 IL_ERR("Unable to initialize Rx queue\n"); 201 return -ENOMEM; 202 } 203 } else 204 il4965_rx_queue_reset(il, rxq); 205 206 il4965_rx_replenish(il); 207 208 il4965_rx_init(il, rxq); 209 210 spin_lock_irqsave(&il->lock, flags); 211 212 rxq->need_update = 1; 213 il_rx_queue_update_write_ptr(il, rxq); 214 215 spin_unlock_irqrestore(&il->lock, flags); 216 217 /* Allocate or reset and init all Tx and Command queues */ 218 if (!il->txq) { 219 ret = il4965_txq_ctx_alloc(il); 220 if (ret) 221 return ret; 222 } else 223 il4965_txq_ctx_reset(il); 224 225 set_bit(S_INIT, &il->status); 226 227 return 0; 228} 229 230/* 231 * il4965_dma_addr2rbd_ptr - convert a DMA address to a uCode read buffer ptr 232 */ 233static inline __le32 234il4965_dma_addr2rbd_ptr(struct il_priv *il, dma_addr_t dma_addr) 235{ 236 return cpu_to_le32((u32) (dma_addr >> 8)); 237} 238 239/* 240 * il4965_rx_queue_restock - refill RX queue from pre-allocated pool 241 * 242 * If there are slots in the RX queue that need to be restocked, 243 * and we have free pre-allocated buffers, fill the ranks as much 244 * as we can, pulling from rx_free. 245 * 246 * This moves the 'write' idx forward to catch up with 'processed', and 247 * also updates the memory address in the firmware to reference the new 248 * target buffer. 249 */ 250void 251il4965_rx_queue_restock(struct il_priv *il) 252{ 253 struct il_rx_queue *rxq = &il->rxq; 254 struct list_head *element; 255 struct il_rx_buf *rxb; 256 unsigned long flags; 257 258 spin_lock_irqsave(&rxq->lock, flags); 259 while (il_rx_queue_space(rxq) > 0 && rxq->free_count) { 260 /* The overwritten rxb must be a used one */ 261 rxb = rxq->queue[rxq->write]; 262 BUG_ON(rxb && rxb->page); 263 264 /* Get next free Rx buffer, remove from free list */ 265 element = rxq->rx_free.next; 266 rxb = list_entry(element, struct il_rx_buf, list); 267 list_del(element); 268 269 /* Point to Rx buffer via next RBD in circular buffer */ 270 rxq->bd[rxq->write] = 271 il4965_dma_addr2rbd_ptr(il, rxb->page_dma); 272 rxq->queue[rxq->write] = rxb; 273 rxq->write = (rxq->write + 1) & RX_QUEUE_MASK; 274 rxq->free_count--; 275 } 276 spin_unlock_irqrestore(&rxq->lock, flags); 277 /* If the pre-allocated buffer pool is dropping low, schedule to 278 * refill it */ 279 if (rxq->free_count <= RX_LOW_WATERMARK) 280 queue_work(il->workqueue, &il->rx_replenish); 281 282 /* If we've added more space for the firmware to place data, tell it. 283 * Increment device's write pointer in multiples of 8. */ 284 if (rxq->write_actual != (rxq->write & ~0x7)) { 285 spin_lock_irqsave(&rxq->lock, flags); 286 rxq->need_update = 1; 287 spin_unlock_irqrestore(&rxq->lock, flags); 288 il_rx_queue_update_write_ptr(il, rxq); 289 } 290} 291 292/* 293 * il4965_rx_replenish - Move all used packet from rx_used to rx_free 294 * 295 * When moving to rx_free an SKB is allocated for the slot. 296 * 297 * Also restock the Rx queue via il_rx_queue_restock. 298 * This is called as a scheduled work item (except for during initialization) 299 */ 300static void 301il4965_rx_allocate(struct il_priv *il, gfp_t priority) 302{ 303 struct il_rx_queue *rxq = &il->rxq; 304 struct list_head *element; 305 struct il_rx_buf *rxb; 306 struct page *page; 307 dma_addr_t page_dma; 308 unsigned long flags; 309 gfp_t gfp_mask = priority; 310 311 while (1) { 312 spin_lock_irqsave(&rxq->lock, flags); 313 if (list_empty(&rxq->rx_used)) { 314 spin_unlock_irqrestore(&rxq->lock, flags); 315 return; 316 } 317 spin_unlock_irqrestore(&rxq->lock, flags); 318 319 if (rxq->free_count > RX_LOW_WATERMARK) 320 gfp_mask |= __GFP_NOWARN; 321 322 if (il->hw_params.rx_page_order > 0) 323 gfp_mask |= __GFP_COMP; 324 325 /* Alloc a new receive buffer */ 326 page = alloc_pages(gfp_mask, il->hw_params.rx_page_order); 327 if (!page) { 328 if (net_ratelimit()) 329 D_INFO("alloc_pages failed, " "order: %d\n", 330 il->hw_params.rx_page_order); 331 332 if (rxq->free_count <= RX_LOW_WATERMARK && 333 net_ratelimit()) 334 IL_ERR("Failed to alloc_pages with %s. " 335 "Only %u free buffers remaining.\n", 336 priority == 337 GFP_ATOMIC ? "GFP_ATOMIC" : "GFP_KERNEL", 338 rxq->free_count); 339 /* We don't reschedule replenish work here -- we will 340 * call the restock method and if it still needs 341 * more buffers it will schedule replenish */ 342 return; 343 } 344 345 /* Get physical address of the RB */ 346 page_dma = dma_map_page(&il->pci_dev->dev, page, 0, 347 PAGE_SIZE << il->hw_params.rx_page_order, 348 DMA_FROM_DEVICE); 349 if (unlikely(dma_mapping_error(&il->pci_dev->dev, page_dma))) { 350 __free_pages(page, il->hw_params.rx_page_order); 351 break; 352 } 353 354 spin_lock_irqsave(&rxq->lock, flags); 355 356 if (list_empty(&rxq->rx_used)) { 357 spin_unlock_irqrestore(&rxq->lock, flags); 358 dma_unmap_page(&il->pci_dev->dev, page_dma, 359 PAGE_SIZE << il->hw_params.rx_page_order, 360 DMA_FROM_DEVICE); 361 __free_pages(page, il->hw_params.rx_page_order); 362 return; 363 } 364 365 element = rxq->rx_used.next; 366 rxb = list_entry(element, struct il_rx_buf, list); 367 list_del(element); 368 369 BUG_ON(rxb->page); 370 371 rxb->page = page; 372 rxb->page_dma = page_dma; 373 list_add_tail(&rxb->list, &rxq->rx_free); 374 rxq->free_count++; 375 il->alloc_rxb_page++; 376 377 spin_unlock_irqrestore(&rxq->lock, flags); 378 } 379} 380 381void 382il4965_rx_replenish(struct il_priv *il) 383{ 384 unsigned long flags; 385 386 il4965_rx_allocate(il, GFP_KERNEL); 387 388 spin_lock_irqsave(&il->lock, flags); 389 il4965_rx_queue_restock(il); 390 spin_unlock_irqrestore(&il->lock, flags); 391} 392 393void 394il4965_rx_replenish_now(struct il_priv *il) 395{ 396 il4965_rx_allocate(il, GFP_ATOMIC); 397 398 il4965_rx_queue_restock(il); 399} 400 401/* Assumes that the skb field of the buffers in 'pool' is kept accurate. 402 * If an SKB has been detached, the POOL needs to have its SKB set to NULL 403 * This free routine walks the list of POOL entries and if SKB is set to 404 * non NULL it is unmapped and freed 405 */ 406void 407il4965_rx_queue_free(struct il_priv *il, struct il_rx_queue *rxq) 408{ 409 int i; 410 for (i = 0; i < RX_QUEUE_SIZE + RX_FREE_BUFFERS; i++) { 411 if (rxq->pool[i].page != NULL) { 412 dma_unmap_page(&il->pci_dev->dev, 413 rxq->pool[i].page_dma, 414 PAGE_SIZE << il->hw_params.rx_page_order, 415 DMA_FROM_DEVICE); 416 __il_free_pages(il, rxq->pool[i].page); 417 rxq->pool[i].page = NULL; 418 } 419 } 420 421 dma_free_coherent(&il->pci_dev->dev, 4 * RX_QUEUE_SIZE, rxq->bd, 422 rxq->bd_dma); 423 dma_free_coherent(&il->pci_dev->dev, sizeof(struct il_rb_status), 424 rxq->rb_stts, rxq->rb_stts_dma); 425 rxq->bd = NULL; 426 rxq->rb_stts = NULL; 427} 428 429int 430il4965_rxq_stop(struct il_priv *il) 431{ 432 int ret; 433 434 _il_wr(il, FH49_MEM_RCSR_CHNL0_CONFIG_REG, 0); 435 ret = _il_poll_bit(il, FH49_MEM_RSSR_RX_STATUS_REG, 436 FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 437 FH49_RSSR_CHNL0_RX_STATUS_CHNL_IDLE, 438 1000); 439 if (ret < 0) 440 IL_ERR("Can't stop Rx DMA.\n"); 441 442 return 0; 443} 444 445int 446il4965_hwrate_to_mac80211_idx(u32 rate_n_flags, enum nl80211_band band) 447{ 448 int idx = 0; 449 int band_offset = 0; 450 451 /* HT rate format: mac80211 wants an MCS number, which is just LSB */ 452 if (rate_n_flags & RATE_MCS_HT_MSK) { 453 idx = (rate_n_flags & 0xff); 454 return idx; 455 /* Legacy rate format, search for match in table */ 456 } else { 457 if (band == NL80211_BAND_5GHZ) 458 band_offset = IL_FIRST_OFDM_RATE; 459 for (idx = band_offset; idx < RATE_COUNT_LEGACY; idx++) 460 if (il_rates[idx].plcp == (rate_n_flags & 0xFF)) 461 return idx - band_offset; 462 } 463 464 return -1; 465} 466 467static int 468il4965_calc_rssi(struct il_priv *il, struct il_rx_phy_res *rx_resp) 469{ 470 /* data from PHY/DSP regarding signal strength, etc., 471 * contents are always there, not configurable by host. */ 472 struct il4965_rx_non_cfg_phy *ncphy = 473 (struct il4965_rx_non_cfg_phy *)rx_resp->non_cfg_phy_buf; 474 u32 agc = 475 (le16_to_cpu(ncphy->agc_info) & IL49_AGC_DB_MASK) >> 476 IL49_AGC_DB_POS; 477 478 u32 valid_antennae = 479 (le16_to_cpu(rx_resp->phy_flags) & IL49_RX_PHY_FLAGS_ANTENNAE_MASK) 480 >> IL49_RX_PHY_FLAGS_ANTENNAE_OFFSET; 481 u8 max_rssi = 0; 482 u32 i; 483 484 /* Find max rssi among 3 possible receivers. 485 * These values are measured by the digital signal processor (DSP). 486 * They should stay fairly constant even as the signal strength varies, 487 * if the radio's automatic gain control (AGC) is working right. 488 * AGC value (see below) will provide the "interesting" info. */ 489 for (i = 0; i < 3; i++) 490 if (valid_antennae & (1 << i)) 491 max_rssi = max(ncphy->rssi_info[i << 1], max_rssi); 492 493 D_STATS("Rssi In A %d B %d C %d Max %d AGC dB %d\n", 494 ncphy->rssi_info[0], ncphy->rssi_info[2], ncphy->rssi_info[4], 495 max_rssi, agc); 496 497 /* dBm = max_rssi dB - agc dB - constant. 498 * Higher AGC (higher radio gain) means lower signal. */ 499 return max_rssi - agc - IL4965_RSSI_OFFSET; 500} 501 502static u32 503il4965_translate_rx_status(struct il_priv *il, u32 decrypt_in) 504{ 505 u32 decrypt_out = 0; 506 507 if ((decrypt_in & RX_RES_STATUS_STATION_FOUND) == 508 RX_RES_STATUS_STATION_FOUND) 509 decrypt_out |= 510 (RX_RES_STATUS_STATION_FOUND | 511 RX_RES_STATUS_NO_STATION_INFO_MISMATCH); 512 513 decrypt_out |= (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK); 514 515 /* packet was not encrypted */ 516 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) == 517 RX_RES_STATUS_SEC_TYPE_NONE) 518 return decrypt_out; 519 520 /* packet was encrypted with unknown alg */ 521 if ((decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) == 522 RX_RES_STATUS_SEC_TYPE_ERR) 523 return decrypt_out; 524 525 /* decryption was not done in HW */ 526 if ((decrypt_in & RX_MPDU_RES_STATUS_DEC_DONE_MSK) != 527 RX_MPDU_RES_STATUS_DEC_DONE_MSK) 528 return decrypt_out; 529 530 switch (decrypt_in & RX_RES_STATUS_SEC_TYPE_MSK) { 531 532 case RX_RES_STATUS_SEC_TYPE_CCMP: 533 /* alg is CCM: check MIC only */ 534 if (!(decrypt_in & RX_MPDU_RES_STATUS_MIC_OK)) 535 /* Bad MIC */ 536 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC; 537 else 538 decrypt_out |= RX_RES_STATUS_DECRYPT_OK; 539 540 break; 541 542 case RX_RES_STATUS_SEC_TYPE_TKIP: 543 if (!(decrypt_in & RX_MPDU_RES_STATUS_TTAK_OK)) { 544 /* Bad TTAK */ 545 decrypt_out |= RX_RES_STATUS_BAD_KEY_TTAK; 546 break; 547 } 548 fallthrough; /* if TTAK OK */ 549 default: 550 if (!(decrypt_in & RX_MPDU_RES_STATUS_ICV_OK)) 551 decrypt_out |= RX_RES_STATUS_BAD_ICV_MIC; 552 else 553 decrypt_out |= RX_RES_STATUS_DECRYPT_OK; 554 break; 555 } 556 557 D_RX("decrypt_in:0x%x decrypt_out = 0x%x\n", decrypt_in, decrypt_out); 558 559 return decrypt_out; 560} 561 562#define SMALL_PACKET_SIZE 256 563 564static void 565il4965_pass_packet_to_mac80211(struct il_priv *il, struct ieee80211_hdr *hdr, 566 u32 len, u32 ampdu_status, struct il_rx_buf *rxb, 567 struct ieee80211_rx_status *stats) 568{ 569 struct sk_buff *skb; 570 __le16 fc = hdr->frame_control; 571 572 /* We only process data packets if the interface is open */ 573 if (unlikely(!il->is_open)) { 574 D_DROP("Dropping packet while interface is not open.\n"); 575 return; 576 } 577 578 if (unlikely(test_bit(IL_STOP_REASON_PASSIVE, &il->stop_reason))) { 579 il_wake_queues_by_reason(il, IL_STOP_REASON_PASSIVE); 580 D_INFO("Woke queues - frame received on passive channel\n"); 581 } 582 583 /* In case of HW accelerated crypto and bad decryption, drop */ 584 if (!il->cfg->mod_params->sw_crypto && 585 il_set_decrypted_flag(il, hdr, ampdu_status, stats)) 586 return; 587 588 skb = dev_alloc_skb(SMALL_PACKET_SIZE); 589 if (!skb) { 590 IL_ERR("dev_alloc_skb failed\n"); 591 return; 592 } 593 594 if (len <= SMALL_PACKET_SIZE) { 595 skb_put_data(skb, hdr, len); 596 } else { 597 skb_add_rx_frag(skb, 0, rxb->page, (void *)hdr - rxb_addr(rxb), 598 len, PAGE_SIZE << il->hw_params.rx_page_order); 599 il->alloc_rxb_page--; 600 rxb->page = NULL; 601 } 602 603 il_update_stats(il, false, fc, len); 604 memcpy(IEEE80211_SKB_RXCB(skb), stats, sizeof(*stats)); 605 606 ieee80211_rx(il->hw, skb); 607} 608 609/* Called for N_RX (legacy ABG frames), or 610 * N_RX_MPDU (HT high-throughput N frames). */ 611static void 612il4965_hdl_rx(struct il_priv *il, struct il_rx_buf *rxb) 613{ 614 struct ieee80211_hdr *header; 615 struct ieee80211_rx_status rx_status = {}; 616 struct il_rx_pkt *pkt = rxb_addr(rxb); 617 struct il_rx_phy_res *phy_res; 618 __le32 rx_pkt_status; 619 struct il_rx_mpdu_res_start *amsdu; 620 u32 len; 621 u32 ampdu_status; 622 u32 rate_n_flags; 623 624 /** 625 * N_RX and N_RX_MPDU are handled differently. 626 * N_RX: physical layer info is in this buffer 627 * N_RX_MPDU: physical layer info was sent in separate 628 * command and cached in il->last_phy_res 629 * 630 * Here we set up local variables depending on which command is 631 * received. 632 */ 633 if (pkt->hdr.cmd == N_RX) { 634 phy_res = (struct il_rx_phy_res *)pkt->u.raw; 635 header = 636 (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*phy_res) + 637 phy_res->cfg_phy_cnt); 638 639 len = le16_to_cpu(phy_res->byte_count); 640 rx_pkt_status = 641 *(__le32 *) (pkt->u.raw + sizeof(*phy_res) + 642 phy_res->cfg_phy_cnt + len); 643 ampdu_status = le32_to_cpu(rx_pkt_status); 644 } else { 645 if (!il->_4965.last_phy_res_valid) { 646 IL_ERR("MPDU frame without cached PHY data\n"); 647 return; 648 } 649 phy_res = &il->_4965.last_phy_res; 650 amsdu = (struct il_rx_mpdu_res_start *)pkt->u.raw; 651 header = (struct ieee80211_hdr *)(pkt->u.raw + sizeof(*amsdu)); 652 len = le16_to_cpu(amsdu->byte_count); 653 rx_pkt_status = *(__le32 *) (pkt->u.raw + sizeof(*amsdu) + len); 654 ampdu_status = 655 il4965_translate_rx_status(il, le32_to_cpu(rx_pkt_status)); 656 } 657 658 if ((unlikely(phy_res->cfg_phy_cnt > 20))) { 659 D_DROP("dsp size out of range [0,20]: %d\n", 660 phy_res->cfg_phy_cnt); 661 return; 662 } 663 664 if (!(rx_pkt_status & RX_RES_STATUS_NO_CRC32_ERROR) || 665 !(rx_pkt_status & RX_RES_STATUS_NO_RXE_OVERFLOW)) { 666 D_RX("Bad CRC or FIFO: 0x%08X.\n", le32_to_cpu(rx_pkt_status)); 667 return; 668 } 669 670 /* This will be used in several places later */ 671 rate_n_flags = le32_to_cpu(phy_res->rate_n_flags); 672 673 /* rx_status carries information about the packet to mac80211 */ 674 rx_status.mactime = le64_to_cpu(phy_res->timestamp); 675 rx_status.band = 676 (phy_res-> 677 phy_flags & RX_RES_PHY_FLAGS_BAND_24_MSK) ? NL80211_BAND_2GHZ : 678 NL80211_BAND_5GHZ; 679 rx_status.freq = 680 ieee80211_channel_to_frequency(le16_to_cpu(phy_res->channel), 681 rx_status.band); 682 rx_status.rate_idx = 683 il4965_hwrate_to_mac80211_idx(rate_n_flags, rx_status.band); 684 rx_status.flag = 0; 685 686 /* TSF isn't reliable. In order to allow smooth user experience, 687 * this W/A doesn't propagate it to the mac80211 */ 688 /*rx_status.flag |= RX_FLAG_MACTIME_START; */ 689 690 il->ucode_beacon_time = le32_to_cpu(phy_res->beacon_time_stamp); 691 692 /* Find max signal strength (dBm) among 3 antenna/receiver chains */ 693 rx_status.signal = il4965_calc_rssi(il, phy_res); 694 695 D_STATS("Rssi %d, TSF %llu\n", rx_status.signal, 696 (unsigned long long)rx_status.mactime); 697 698 /* 699 * "antenna number" 700 * 701 * It seems that the antenna field in the phy flags value 702 * is actually a bit field. This is undefined by radiotap, 703 * it wants an actual antenna number but I always get "7" 704 * for most legacy frames I receive indicating that the 705 * same frame was received on all three RX chains. 706 * 707 * I think this field should be removed in favor of a 708 * new 802.11n radiotap field "RX chains" that is defined 709 * as a bitmask. 710 */ 711 rx_status.antenna = 712 (le16_to_cpu(phy_res->phy_flags) & RX_RES_PHY_FLAGS_ANTENNA_MSK) >> 713 RX_RES_PHY_FLAGS_ANTENNA_POS; 714 715 /* set the preamble flag if appropriate */ 716 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_SHORT_PREAMBLE_MSK) 717 rx_status.enc_flags |= RX_ENC_FLAG_SHORTPRE; 718 719 /* Set up the HT phy flags */ 720 if (rate_n_flags & RATE_MCS_HT_MSK) 721 rx_status.encoding = RX_ENC_HT; 722 if (rate_n_flags & RATE_MCS_HT40_MSK) 723 rx_status.bw = RATE_INFO_BW_40; 724 else 725 rx_status.bw = RATE_INFO_BW_20; 726 if (rate_n_flags & RATE_MCS_SGI_MSK) 727 rx_status.enc_flags |= RX_ENC_FLAG_SHORT_GI; 728 729 if (phy_res->phy_flags & RX_RES_PHY_FLAGS_AGG_MSK) { 730 /* We know which subframes of an A-MPDU belong 731 * together since we get a single PHY response 732 * from the firmware for all of them. 733 */ 734 735 rx_status.flag |= RX_FLAG_AMPDU_DETAILS; 736 rx_status.ampdu_reference = il->_4965.ampdu_ref; 737 } 738 739 il4965_pass_packet_to_mac80211(il, header, len, ampdu_status, rxb, 740 &rx_status); 741} 742 743/* Cache phy data (Rx signal strength, etc) for HT frame (N_RX_PHY). 744 * This will be used later in il_hdl_rx() for N_RX_MPDU. */ 745static void 746il4965_hdl_rx_phy(struct il_priv *il, struct il_rx_buf *rxb) 747{ 748 struct il_rx_pkt *pkt = rxb_addr(rxb); 749 il->_4965.last_phy_res_valid = true; 750 il->_4965.ampdu_ref++; 751 memcpy(&il->_4965.last_phy_res, pkt->u.raw, 752 sizeof(struct il_rx_phy_res)); 753} 754 755static int 756il4965_get_channels_for_scan(struct il_priv *il, struct ieee80211_vif *vif, 757 enum nl80211_band band, u8 is_active, 758 u8 n_probes, struct il_scan_channel *scan_ch) 759{ 760 struct ieee80211_channel *chan; 761 const struct ieee80211_supported_band *sband; 762 const struct il_channel_info *ch_info; 763 u16 passive_dwell = 0; 764 u16 active_dwell = 0; 765 int added, i; 766 u16 channel; 767 768 sband = il_get_hw_mode(il, band); 769 if (!sband) 770 return 0; 771 772 active_dwell = il_get_active_dwell_time(il, band, n_probes); 773 passive_dwell = il_get_passive_dwell_time(il, band, vif); 774 775 if (passive_dwell <= active_dwell) 776 passive_dwell = active_dwell + 1; 777 778 for (i = 0, added = 0; i < il->scan_request->n_channels; i++) { 779 chan = il->scan_request->channels[i]; 780 781 if (chan->band != band) 782 continue; 783 784 channel = chan->hw_value; 785 scan_ch->channel = cpu_to_le16(channel); 786 787 ch_info = il_get_channel_info(il, band, channel); 788 if (!il_is_channel_valid(ch_info)) { 789 D_SCAN("Channel %d is INVALID for this band.\n", 790 channel); 791 continue; 792 } 793 794 if (!is_active || il_is_channel_passive(ch_info) || 795 (chan->flags & IEEE80211_CHAN_NO_IR)) 796 scan_ch->type = SCAN_CHANNEL_TYPE_PASSIVE; 797 else 798 scan_ch->type = SCAN_CHANNEL_TYPE_ACTIVE; 799 800 if (n_probes) 801 scan_ch->type |= IL_SCAN_PROBE_MASK(n_probes); 802 803 scan_ch->active_dwell = cpu_to_le16(active_dwell); 804 scan_ch->passive_dwell = cpu_to_le16(passive_dwell); 805 806 /* Set txpower levels to defaults */ 807 scan_ch->dsp_atten = 110; 808 809 /* NOTE: if we were doing 6Mb OFDM for scans we'd use 810 * power level: 811 * scan_ch->tx_gain = ((1 << 5) | (2 << 3)) | 3; 812 */ 813 if (band == NL80211_BAND_5GHZ) 814 scan_ch->tx_gain = ((1 << 5) | (3 << 3)) | 3; 815 else 816 scan_ch->tx_gain = ((1 << 5) | (5 << 3)); 817 818 D_SCAN("Scanning ch=%d prob=0x%X [%s %d]\n", channel, 819 le32_to_cpu(scan_ch->type), 820 (scan_ch-> 821 type & SCAN_CHANNEL_TYPE_ACTIVE) ? "ACTIVE" : "PASSIVE", 822 (scan_ch-> 823 type & SCAN_CHANNEL_TYPE_ACTIVE) ? active_dwell : 824 passive_dwell); 825 826 scan_ch++; 827 added++; 828 } 829 830 D_SCAN("total channels to scan %d\n", added); 831 return added; 832} 833 834static void 835il4965_toggle_tx_ant(struct il_priv *il, u8 *ant, u8 valid) 836{ 837 int i; 838 u8 ind = *ant; 839 840 for (i = 0; i < RATE_ANT_NUM - 1; i++) { 841 ind = (ind + 1) < RATE_ANT_NUM ? ind + 1 : 0; 842 if (valid & BIT(ind)) { 843 *ant = ind; 844 return; 845 } 846 } 847} 848 849int 850il4965_request_scan(struct il_priv *il, struct ieee80211_vif *vif) 851{ 852 struct il_host_cmd cmd = { 853 .id = C_SCAN, 854 .len = sizeof(struct il_scan_cmd), 855 .flags = CMD_SIZE_HUGE, 856 }; 857 struct il_scan_cmd *scan; 858 u32 rate_flags = 0; 859 u16 cmd_len; 860 u16 rx_chain = 0; 861 enum nl80211_band band; 862 u8 n_probes = 0; 863 u8 rx_ant = il->hw_params.valid_rx_ant; 864 u8 rate; 865 bool is_active = false; 866 int chan_mod; 867 u8 active_chains; 868 u8 scan_tx_antennas = il->hw_params.valid_tx_ant; 869 int ret; 870 871 lockdep_assert_held(&il->mutex); 872 873 if (!il->scan_cmd) { 874 il->scan_cmd = 875 kmalloc(sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE, 876 GFP_KERNEL); 877 if (!il->scan_cmd) { 878 D_SCAN("fail to allocate memory for scan\n"); 879 return -ENOMEM; 880 } 881 } 882 scan = il->scan_cmd; 883 memset(scan, 0, sizeof(struct il_scan_cmd) + IL_MAX_SCAN_SIZE); 884 885 scan->quiet_plcp_th = IL_PLCP_QUIET_THRESH; 886 scan->quiet_time = IL_ACTIVE_QUIET_TIME; 887 888 if (il_is_any_associated(il)) { 889 u16 interval; 890 u32 extra; 891 u32 suspend_time = 100; 892 u32 scan_suspend_time = 100; 893 894 D_INFO("Scanning while associated...\n"); 895 interval = vif->bss_conf.beacon_int; 896 897 scan->suspend_time = 0; 898 scan->max_out_time = cpu_to_le32(200 * 1024); 899 if (!interval) 900 interval = suspend_time; 901 902 extra = (suspend_time / interval) << 22; 903 scan_suspend_time = 904 (extra | ((suspend_time % interval) * 1024)); 905 scan->suspend_time = cpu_to_le32(scan_suspend_time); 906 D_SCAN("suspend_time 0x%X beacon interval %d\n", 907 scan_suspend_time, interval); 908 } 909 910 if (il->scan_request->n_ssids) { 911 int i, p = 0; 912 D_SCAN("Kicking off active scan\n"); 913 for (i = 0; i < il->scan_request->n_ssids; i++) { 914 /* always does wildcard anyway */ 915 if (!il->scan_request->ssids[i].ssid_len) 916 continue; 917 scan->direct_scan[p].id = WLAN_EID_SSID; 918 scan->direct_scan[p].len = 919 il->scan_request->ssids[i].ssid_len; 920 memcpy(scan->direct_scan[p].ssid, 921 il->scan_request->ssids[i].ssid, 922 il->scan_request->ssids[i].ssid_len); 923 n_probes++; 924 p++; 925 } 926 is_active = true; 927 } else 928 D_SCAN("Start passive scan.\n"); 929 930 scan->tx_cmd.tx_flags = TX_CMD_FLG_SEQ_CTL_MSK; 931 scan->tx_cmd.sta_id = il->hw_params.bcast_id; 932 scan->tx_cmd.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; 933 934 switch (il->scan_band) { 935 case NL80211_BAND_2GHZ: 936 scan->flags = RXON_FLG_BAND_24G_MSK | RXON_FLG_AUTO_DETECT_MSK; 937 chan_mod = 938 le32_to_cpu(il->active.flags & RXON_FLG_CHANNEL_MODE_MSK) >> 939 RXON_FLG_CHANNEL_MODE_POS; 940 if (chan_mod == CHANNEL_MODE_PURE_40) { 941 rate = RATE_6M_PLCP; 942 } else { 943 rate = RATE_1M_PLCP; 944 rate_flags = RATE_MCS_CCK_MSK; 945 } 946 break; 947 case NL80211_BAND_5GHZ: 948 rate = RATE_6M_PLCP; 949 break; 950 default: 951 IL_WARN("Invalid scan band\n"); 952 return -EIO; 953 } 954 955 /* 956 * If active scanning is requested but a certain channel is 957 * marked passive, we can do active scanning if we detect 958 * transmissions. 959 * 960 * There is an issue with some firmware versions that triggers 961 * a sysassert on a "good CRC threshold" of zero (== disabled), 962 * on a radar channel even though this means that we should NOT 963 * send probes. 964 * 965 * The "good CRC threshold" is the number of frames that we 966 * need to receive during our dwell time on a channel before 967 * sending out probes -- setting this to a huge value will 968 * mean we never reach it, but at the same time work around 969 * the aforementioned issue. Thus use IL_GOOD_CRC_TH_NEVER 970 * here instead of IL_GOOD_CRC_TH_DISABLED. 971 */ 972 scan->good_CRC_th = 973 is_active ? IL_GOOD_CRC_TH_DEFAULT : IL_GOOD_CRC_TH_NEVER; 974 975 band = il->scan_band; 976 977 if (il->cfg->scan_rx_antennas[band]) 978 rx_ant = il->cfg->scan_rx_antennas[band]; 979 980 il4965_toggle_tx_ant(il, &il->scan_tx_ant[band], scan_tx_antennas); 981 rate_flags |= BIT(il->scan_tx_ant[band]) << RATE_MCS_ANT_POS; 982 scan->tx_cmd.rate_n_flags = cpu_to_le32(rate | rate_flags); 983 984 /* In power save mode use one chain, otherwise use all chains */ 985 if (test_bit(S_POWER_PMI, &il->status)) { 986 /* rx_ant has been set to all valid chains previously */ 987 active_chains = 988 rx_ant & ((u8) (il->chain_noise_data.active_chains)); 989 if (!active_chains) 990 active_chains = rx_ant; 991 992 D_SCAN("chain_noise_data.active_chains: %u\n", 993 il->chain_noise_data.active_chains); 994 995 rx_ant = il4965_first_antenna(active_chains); 996 } 997 998 /* MIMO is not used here, but value is required */ 999 rx_chain |= il->hw_params.valid_rx_ant << RXON_RX_CHAIN_VALID_POS; 1000 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_MIMO_SEL_POS; 1001 rx_chain |= rx_ant << RXON_RX_CHAIN_FORCE_SEL_POS; 1002 rx_chain |= 0x1 << RXON_RX_CHAIN_DRIVER_FORCE_POS; 1003 scan->rx_chain = cpu_to_le16(rx_chain); 1004 1005 cmd_len = 1006 il_fill_probe_req(il, (struct ieee80211_mgmt *)scan->data, 1007 vif->addr, il->scan_request->ie, 1008 il->scan_request->ie_len, 1009 IL_MAX_SCAN_SIZE - sizeof(*scan)); 1010 scan->tx_cmd.len = cpu_to_le16(cmd_len); 1011 1012 scan->filter_flags |= 1013 (RXON_FILTER_ACCEPT_GRP_MSK | RXON_FILTER_BCON_AWARE_MSK); 1014 1015 scan->channel_count = 1016 il4965_get_channels_for_scan(il, vif, band, is_active, n_probes, 1017 (void *)&scan->data[cmd_len]); 1018 if (scan->channel_count == 0) { 1019 D_SCAN("channel count %d\n", scan->channel_count); 1020 return -EIO; 1021 } 1022 1023 cmd.len += 1024 le16_to_cpu(scan->tx_cmd.len) + 1025 scan->channel_count * sizeof(struct il_scan_channel); 1026 cmd.data = scan; 1027 scan->len = cpu_to_le16(cmd.len); 1028 1029 set_bit(S_SCAN_HW, &il->status); 1030 1031 ret = il_send_cmd_sync(il, &cmd); 1032 if (ret) 1033 clear_bit(S_SCAN_HW, &il->status); 1034 1035 return ret; 1036} 1037 1038int 1039il4965_manage_ibss_station(struct il_priv *il, struct ieee80211_vif *vif, 1040 bool add) 1041{ 1042 struct il_vif_priv *vif_priv = (void *)vif->drv_priv; 1043 1044 if (add) 1045 return il4965_add_bssid_station(il, vif->bss_conf.bssid, 1046 &vif_priv->ibss_bssid_sta_id); 1047 return il_remove_station(il, vif_priv->ibss_bssid_sta_id, 1048 vif->bss_conf.bssid); 1049} 1050 1051void 1052il4965_free_tfds_in_queue(struct il_priv *il, int sta_id, int tid, int freed) 1053{ 1054 lockdep_assert_held(&il->sta_lock); 1055 1056 if (il->stations[sta_id].tid[tid].tfds_in_queue >= freed) 1057 il->stations[sta_id].tid[tid].tfds_in_queue -= freed; 1058 else { 1059 D_TX("free more than tfds_in_queue (%u:%d)\n", 1060 il->stations[sta_id].tid[tid].tfds_in_queue, freed); 1061 il->stations[sta_id].tid[tid].tfds_in_queue = 0; 1062 } 1063} 1064 1065#define IL_TX_QUEUE_MSK 0xfffff 1066 1067static bool 1068il4965_is_single_rx_stream(struct il_priv *il) 1069{ 1070 return il->current_ht_config.smps == IEEE80211_SMPS_STATIC || 1071 il->current_ht_config.single_chain_sufficient; 1072} 1073 1074#define IL_NUM_RX_CHAINS_MULTIPLE 3 1075#define IL_NUM_RX_CHAINS_SINGLE 2 1076#define IL_NUM_IDLE_CHAINS_DUAL 2 1077#define IL_NUM_IDLE_CHAINS_SINGLE 1 1078 1079/* 1080 * Determine how many receiver/antenna chains to use. 1081 * 1082 * More provides better reception via diversity. Fewer saves power 1083 * at the expense of throughput, but only when not in powersave to 1084 * start with. 1085 * 1086 * MIMO (dual stream) requires at least 2, but works better with 3. 1087 * This does not determine *which* chains to use, just how many. 1088 */ 1089static int 1090il4965_get_active_rx_chain_count(struct il_priv *il) 1091{ 1092 /* # of Rx chains to use when expecting MIMO. */ 1093 if (il4965_is_single_rx_stream(il)) 1094 return IL_NUM_RX_CHAINS_SINGLE; 1095 else 1096 return IL_NUM_RX_CHAINS_MULTIPLE; 1097} 1098 1099/* 1100 * When we are in power saving mode, unless device support spatial 1101 * multiplexing power save, use the active count for rx chain count. 1102 */ 1103static int 1104il4965_get_idle_rx_chain_count(struct il_priv *il, int active_cnt) 1105{ 1106 /* # Rx chains when idling, depending on SMPS mode */ 1107 switch (il->current_ht_config.smps) { 1108 case IEEE80211_SMPS_STATIC: 1109 case IEEE80211_SMPS_DYNAMIC: 1110 return IL_NUM_IDLE_CHAINS_SINGLE; 1111 case IEEE80211_SMPS_OFF: 1112 return active_cnt; 1113 default: 1114 WARN(1, "invalid SMPS mode %d", il->current_ht_config.smps); 1115 return active_cnt; 1116 } 1117} 1118 1119/* up to 4 chains */ 1120static u8 1121il4965_count_chain_bitmap(u32 chain_bitmap) 1122{ 1123 u8 res; 1124 res = (chain_bitmap & BIT(0)) >> 0; 1125 res += (chain_bitmap & BIT(1)) >> 1; 1126 res += (chain_bitmap & BIT(2)) >> 2; 1127 res += (chain_bitmap & BIT(3)) >> 3; 1128 return res; 1129} 1130 1131/* 1132 * il4965_set_rxon_chain - Set up Rx chain usage in "staging" RXON image 1133 * 1134 * Selects how many and which Rx receivers/antennas/chains to use. 1135 * This should not be used for scan command ... it puts data in wrong place. 1136 */ 1137void 1138il4965_set_rxon_chain(struct il_priv *il) 1139{ 1140 bool is_single = il4965_is_single_rx_stream(il); 1141 bool is_cam = !test_bit(S_POWER_PMI, &il->status); 1142 u8 idle_rx_cnt, active_rx_cnt, valid_rx_cnt; 1143 u32 active_chains; 1144 u16 rx_chain; 1145 1146 /* Tell uCode which antennas are actually connected. 1147 * Before first association, we assume all antennas are connected. 1148 * Just after first association, il4965_chain_noise_calibration() 1149 * checks which antennas actually *are* connected. */ 1150 if (il->chain_noise_data.active_chains) 1151 active_chains = il->chain_noise_data.active_chains; 1152 else 1153 active_chains = il->hw_params.valid_rx_ant; 1154 1155 rx_chain = active_chains << RXON_RX_CHAIN_VALID_POS; 1156 1157 /* How many receivers should we use? */ 1158 active_rx_cnt = il4965_get_active_rx_chain_count(il); 1159 idle_rx_cnt = il4965_get_idle_rx_chain_count(il, active_rx_cnt); 1160 1161 /* correct rx chain count according hw settings 1162 * and chain noise calibration 1163 */ 1164 valid_rx_cnt = il4965_count_chain_bitmap(active_chains); 1165 if (valid_rx_cnt < active_rx_cnt) 1166 active_rx_cnt = valid_rx_cnt; 1167 1168 if (valid_rx_cnt < idle_rx_cnt) 1169 idle_rx_cnt = valid_rx_cnt; 1170 1171 rx_chain |= active_rx_cnt << RXON_RX_CHAIN_MIMO_CNT_POS; 1172 rx_chain |= idle_rx_cnt << RXON_RX_CHAIN_CNT_POS; 1173 1174 il->staging.rx_chain = cpu_to_le16(rx_chain); 1175 1176 if (!is_single && active_rx_cnt >= IL_NUM_RX_CHAINS_SINGLE && is_cam) 1177 il->staging.rx_chain |= RXON_RX_CHAIN_MIMO_FORCE_MSK; 1178 else 1179 il->staging.rx_chain &= ~RXON_RX_CHAIN_MIMO_FORCE_MSK; 1180 1181 D_ASSOC("rx_chain=0x%X active=%d idle=%d\n", il->staging.rx_chain, 1182 active_rx_cnt, idle_rx_cnt); 1183 1184 WARN_ON(active_rx_cnt == 0 || idle_rx_cnt == 0 || 1185 active_rx_cnt < idle_rx_cnt); 1186} 1187 1188static const char * 1189il4965_get_fh_string(int cmd) 1190{ 1191 switch (cmd) { 1192 IL_CMD(FH49_RSCSR_CHNL0_STTS_WPTR_REG); 1193 IL_CMD(FH49_RSCSR_CHNL0_RBDCB_BASE_REG); 1194 IL_CMD(FH49_RSCSR_CHNL0_WPTR); 1195 IL_CMD(FH49_MEM_RCSR_CHNL0_CONFIG_REG); 1196 IL_CMD(FH49_MEM_RSSR_SHARED_CTRL_REG); 1197 IL_CMD(FH49_MEM_RSSR_RX_STATUS_REG); 1198 IL_CMD(FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV); 1199 IL_CMD(FH49_TSSR_TX_STATUS_REG); 1200 IL_CMD(FH49_TSSR_TX_ERROR_REG); 1201 default: 1202 return "UNKNOWN"; 1203 } 1204} 1205 1206int 1207il4965_dump_fh(struct il_priv *il, char **buf, bool display) 1208{ 1209 int i; 1210#ifdef CONFIG_IWLEGACY_DEBUG 1211 int pos = 0; 1212 size_t bufsz = 0; 1213#endif 1214 static const u32 fh_tbl[] = { 1215 FH49_RSCSR_CHNL0_STTS_WPTR_REG, 1216 FH49_RSCSR_CHNL0_RBDCB_BASE_REG, 1217 FH49_RSCSR_CHNL0_WPTR, 1218 FH49_MEM_RCSR_CHNL0_CONFIG_REG, 1219 FH49_MEM_RSSR_SHARED_CTRL_REG, 1220 FH49_MEM_RSSR_RX_STATUS_REG, 1221 FH49_MEM_RSSR_RX_ENABLE_ERR_IRQ2DRV, 1222 FH49_TSSR_TX_STATUS_REG, 1223 FH49_TSSR_TX_ERROR_REG 1224 }; 1225#ifdef CONFIG_IWLEGACY_DEBUG 1226 if (display) { 1227 bufsz = ARRAY_SIZE(fh_tbl) * 48 + 40; 1228 *buf = kmalloc(bufsz, GFP_KERNEL); 1229 if (!*buf) 1230 return -ENOMEM; 1231 pos += 1232 scnprintf(*buf + pos, bufsz - pos, "FH register values:\n"); 1233 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { 1234 pos += 1235 scnprintf(*buf + pos, bufsz - pos, 1236 " %34s: 0X%08x\n", 1237 il4965_get_fh_string(fh_tbl[i]), 1238 il_rd(il, fh_tbl[i])); 1239 } 1240 return pos; 1241 } 1242#endif 1243 IL_ERR("FH register values:\n"); 1244 for (i = 0; i < ARRAY_SIZE(fh_tbl); i++) { 1245 IL_ERR(" %34s: 0X%08x\n", il4965_get_fh_string(fh_tbl[i]), 1246 il_rd(il, fh_tbl[i])); 1247 } 1248 return 0; 1249} 1250 1251static void 1252il4965_hdl_missed_beacon(struct il_priv *il, struct il_rx_buf *rxb) 1253{ 1254 struct il_rx_pkt *pkt = rxb_addr(rxb); 1255 struct il_missed_beacon_notif *missed_beacon; 1256 1257 missed_beacon = &pkt->u.missed_beacon; 1258 if (le32_to_cpu(missed_beacon->consecutive_missed_beacons) > 1259 il->missed_beacon_threshold) { 1260 D_CALIB("missed bcn cnsq %d totl %d rcd %d expctd %d\n", 1261 le32_to_cpu(missed_beacon->consecutive_missed_beacons), 1262 le32_to_cpu(missed_beacon->total_missed_becons), 1263 le32_to_cpu(missed_beacon->num_recvd_beacons), 1264 le32_to_cpu(missed_beacon->num_expected_beacons)); 1265 if (!test_bit(S_SCANNING, &il->status)) 1266 il4965_init_sensitivity(il); 1267 } 1268} 1269 1270/* Calculate noise level, based on measurements during network silence just 1271 * before arriving beacon. This measurement can be done only if we know 1272 * exactly when to expect beacons, therefore only when we're associated. */ 1273static void 1274il4965_rx_calc_noise(struct il_priv *il) 1275{ 1276 struct stats_rx_non_phy *rx_info; 1277 int num_active_rx = 0; 1278 int total_silence = 0; 1279 int bcn_silence_a, bcn_silence_b, bcn_silence_c; 1280 int last_rx_noise; 1281 1282 rx_info = &(il->_4965.stats.rx.general); 1283 bcn_silence_a = 1284 le32_to_cpu(rx_info->beacon_silence_rssi_a) & IN_BAND_FILTER; 1285 bcn_silence_b = 1286 le32_to_cpu(rx_info->beacon_silence_rssi_b) & IN_BAND_FILTER; 1287 bcn_silence_c = 1288 le32_to_cpu(rx_info->beacon_silence_rssi_c) & IN_BAND_FILTER; 1289 1290 if (bcn_silence_a) { 1291 total_silence += bcn_silence_a; 1292 num_active_rx++; 1293 } 1294 if (bcn_silence_b) { 1295 total_silence += bcn_silence_b; 1296 num_active_rx++; 1297 } 1298 if (bcn_silence_c) { 1299 total_silence += bcn_silence_c; 1300 num_active_rx++; 1301 } 1302 1303 /* Average among active antennas */ 1304 if (num_active_rx) 1305 last_rx_noise = (total_silence / num_active_rx) - 107; 1306 else 1307 last_rx_noise = IL_NOISE_MEAS_NOT_AVAILABLE; 1308 1309 D_CALIB("inband silence a %u, b %u, c %u, dBm %d\n", bcn_silence_a, 1310 bcn_silence_b, bcn_silence_c, last_rx_noise); 1311} 1312 1313#ifdef CONFIG_IWLEGACY_DEBUGFS 1314/* 1315 * based on the assumption of all stats counter are in DWORD 1316 * FIXME: This function is for debugging, do not deal with 1317 * the case of counters roll-over. 1318 */ 1319static void 1320il4965_accumulative_stats(struct il_priv *il, __le32 * stats) 1321{ 1322 int i, size; 1323 __le32 *prev_stats; 1324 u32 *accum_stats; 1325 u32 *delta, *max_delta; 1326 struct stats_general_common *general, *accum_general; 1327 1328 prev_stats = (__le32 *) &il->_4965.stats; 1329 accum_stats = (u32 *) &il->_4965.accum_stats; 1330 size = sizeof(struct il_notif_stats); 1331 general = &il->_4965.stats.general.common; 1332 accum_general = &il->_4965.accum_stats.general.common; 1333 delta = (u32 *) &il->_4965.delta_stats; 1334 max_delta = (u32 *) &il->_4965.max_delta; 1335 1336 for (i = sizeof(__le32); i < size; 1337 i += 1338 sizeof(__le32), stats++, prev_stats++, delta++, max_delta++, 1339 accum_stats++) { 1340 if (le32_to_cpu(*stats) > le32_to_cpu(*prev_stats)) { 1341 *delta = 1342 (le32_to_cpu(*stats) - le32_to_cpu(*prev_stats)); 1343 *accum_stats += *delta; 1344 if (*delta > *max_delta) 1345 *max_delta = *delta; 1346 } 1347 } 1348 1349 /* reset accumulative stats for "no-counter" type stats */ 1350 accum_general->temperature = general->temperature; 1351 accum_general->ttl_timestamp = general->ttl_timestamp; 1352} 1353#endif 1354 1355static void 1356il4965_hdl_stats(struct il_priv *il, struct il_rx_buf *rxb) 1357{ 1358 const int recalib_seconds = 60; 1359 bool change; 1360 struct il_rx_pkt *pkt = rxb_addr(rxb); 1361 1362 D_RX("Statistics notification received (%d vs %d).\n", 1363 (int)sizeof(struct il_notif_stats), 1364 le32_to_cpu(pkt->len_n_flags) & IL_RX_FRAME_SIZE_MSK); 1365 1366 change = 1367 ((il->_4965.stats.general.common.temperature != 1368 pkt->u.stats.general.common.temperature) || 1369 ((il->_4965.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK) != 1370 (pkt->u.stats.flag & STATS_REPLY_FLG_HT40_MODE_MSK))); 1371#ifdef CONFIG_IWLEGACY_DEBUGFS 1372 il4965_accumulative_stats(il, (__le32 *) &pkt->u.stats); 1373#endif 1374 1375 /* TODO: reading some of stats is unneeded */ 1376 memcpy(&il->_4965.stats, &pkt->u.stats, sizeof(il->_4965.stats)); 1377 1378 set_bit(S_STATS, &il->status); 1379 1380 /* 1381 * Reschedule the stats timer to occur in recalib_seconds to ensure 1382 * we get a thermal update even if the uCode doesn't give us one 1383 */ 1384 mod_timer(&il->stats_periodic, 1385 jiffies + secs_to_jiffies(recalib_seconds)); 1386 1387 if (unlikely(!test_bit(S_SCANNING, &il->status)) && 1388 (pkt->hdr.cmd == N_STATS)) { 1389 il4965_rx_calc_noise(il); 1390 queue_work(il->workqueue, &il->run_time_calib_work); 1391 } 1392 1393 if (change) 1394 il4965_temperature_calib(il); 1395} 1396 1397static void 1398il4965_hdl_c_stats(struct il_priv *il, struct il_rx_buf *rxb) 1399{ 1400 struct il_rx_pkt *pkt = rxb_addr(rxb); 1401 1402 if (le32_to_cpu(pkt->u.stats.flag) & UCODE_STATS_CLEAR_MSK) { 1403#ifdef CONFIG_IWLEGACY_DEBUGFS 1404 memset(&il->_4965.accum_stats, 0, 1405 sizeof(struct il_notif_stats)); 1406 memset(&il->_4965.delta_stats, 0, 1407 sizeof(struct il_notif_stats)); 1408 memset(&il->_4965.max_delta, 0, sizeof(struct il_notif_stats)); 1409#endif 1410 D_RX("Statistics have been cleared\n"); 1411 } 1412 il4965_hdl_stats(il, rxb); 1413} 1414 1415 1416/* 1417 * mac80211 queues, ACs, hardware queues, FIFOs. 1418 * 1419 * Cf. https://wireless.wiki.kernel.org/en/developers/Documentation/mac80211/queues 1420 * 1421 * Mac80211 uses the following numbers, which we get as from it 1422 * by way of skb_get_queue_mapping(skb): 1423 * 1424 * VO 0 1425 * VI 1 1426 * BE 2 1427 * BK 3 1428 * 1429 * 1430 * Regular (not A-MPDU) frames are put into hardware queues corresponding 1431 * to the FIFOs, see comments in iwl-prph.h. Aggregated frames get their 1432 * own queue per aggregation session (RA/TID combination), such queues are 1433 * set up to map into FIFOs too, for which we need an AC->FIFO mapping. In 1434 * order to map frames to the right queue, we also need an AC->hw queue 1435 * mapping. This is implemented here. 1436 * 1437 * Due to the way hw queues are set up (by the hw specific modules like 1438 * 4965.c), the AC->hw queue mapping is the identity 1439 * mapping. 1440 */ 1441 1442static const u8 tid_to_ac[] = { 1443 IEEE80211_AC_BE, 1444 IEEE80211_AC_BK, 1445 IEEE80211_AC_BK, 1446 IEEE80211_AC_BE, 1447 IEEE80211_AC_VI, 1448 IEEE80211_AC_VI, 1449 IEEE80211_AC_VO, 1450 IEEE80211_AC_VO 1451}; 1452 1453static inline int 1454il4965_get_ac_from_tid(u16 tid) 1455{ 1456 if (likely(tid < ARRAY_SIZE(tid_to_ac))) 1457 return tid_to_ac[tid]; 1458 1459 /* no support for TIDs 8-15 yet */ 1460 return -EINVAL; 1461} 1462 1463static inline int 1464il4965_get_fifo_from_tid(u16 tid) 1465{ 1466 static const u8 ac_to_fifo[] = { 1467 IL_TX_FIFO_VO, 1468 IL_TX_FIFO_VI, 1469 IL_TX_FIFO_BE, 1470 IL_TX_FIFO_BK, 1471 }; 1472 1473 if (likely(tid < ARRAY_SIZE(tid_to_ac))) 1474 return ac_to_fifo[tid_to_ac[tid]]; 1475 1476 /* no support for TIDs 8-15 yet */ 1477 return -EINVAL; 1478} 1479 1480/* 1481 * handle build C_TX command notification. 1482 */ 1483static void 1484il4965_tx_cmd_build_basic(struct il_priv *il, struct sk_buff *skb, 1485 struct il_tx_cmd *tx_cmd, 1486 struct ieee80211_tx_info *info, 1487 struct ieee80211_hdr *hdr, u8 std_id) 1488{ 1489 __le16 fc = hdr->frame_control; 1490 __le32 tx_flags = tx_cmd->tx_flags; 1491 1492 tx_cmd->stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; 1493 if (!(info->flags & IEEE80211_TX_CTL_NO_ACK)) { 1494 tx_flags |= TX_CMD_FLG_ACK_MSK; 1495 if (ieee80211_is_mgmt(fc)) 1496 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; 1497 if (ieee80211_is_probe_resp(fc) && 1498 !(le16_to_cpu(hdr->seq_ctrl) & 0xf)) 1499 tx_flags |= TX_CMD_FLG_TSF_MSK; 1500 } else { 1501 tx_flags &= (~TX_CMD_FLG_ACK_MSK); 1502 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; 1503 } 1504 1505 if (ieee80211_is_back_req(fc)) 1506 tx_flags |= TX_CMD_FLG_ACK_MSK | TX_CMD_FLG_IMM_BA_RSP_MASK; 1507 1508 tx_cmd->sta_id = std_id; 1509 if (ieee80211_has_morefrags(fc)) 1510 tx_flags |= TX_CMD_FLG_MORE_FRAG_MSK; 1511 1512 if (ieee80211_is_data_qos(fc)) { 1513 u8 *qc = ieee80211_get_qos_ctl(hdr); 1514 tx_cmd->tid_tspec = qc[0] & 0xf; 1515 tx_flags &= ~TX_CMD_FLG_SEQ_CTL_MSK; 1516 } else { 1517 tx_flags |= TX_CMD_FLG_SEQ_CTL_MSK; 1518 } 1519 1520 il_tx_cmd_protection(il, info, fc, &tx_flags); 1521 1522 tx_flags &= ~(TX_CMD_FLG_ANT_SEL_MSK); 1523 if (ieee80211_is_mgmt(fc)) { 1524 if (ieee80211_is_assoc_req(fc) || ieee80211_is_reassoc_req(fc)) 1525 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(3); 1526 else 1527 tx_cmd->timeout.pm_frame_timeout = cpu_to_le16(2); 1528 } else { 1529 tx_cmd->timeout.pm_frame_timeout = 0; 1530 } 1531 1532 tx_cmd->driver_txop = 0; 1533 tx_cmd->tx_flags = tx_flags; 1534 tx_cmd->next_frame_len = 0; 1535} 1536 1537static void 1538il4965_tx_cmd_build_rate(struct il_priv *il, 1539 struct il_tx_cmd *tx_cmd, 1540 struct ieee80211_tx_info *info, 1541 struct ieee80211_sta *sta, 1542 __le16 fc) 1543{ 1544 const u8 rts_retry_limit = 60; 1545 u32 rate_flags; 1546 int rate_idx; 1547 u8 data_retry_limit; 1548 u8 rate_plcp; 1549 1550 /* Set retry limit on DATA packets and Probe Responses */ 1551 if (ieee80211_is_probe_resp(fc)) 1552 data_retry_limit = 3; 1553 else 1554 data_retry_limit = IL4965_DEFAULT_TX_RETRY; 1555 tx_cmd->data_retry_limit = data_retry_limit; 1556 /* Set retry limit on RTS packets */ 1557 tx_cmd->rts_retry_limit = min(data_retry_limit, rts_retry_limit); 1558 1559 /* DATA packets will use the uCode station table for rate/antenna 1560 * selection */ 1561 if (ieee80211_is_data(fc)) { 1562 tx_cmd->initial_rate_idx = 0; 1563 tx_cmd->tx_flags |= TX_CMD_FLG_STA_RATE_MSK; 1564 return; 1565 } 1566 1567 /** 1568 * If the current TX rate stored in mac80211 has the MCS bit set, it's 1569 * not really a TX rate. Thus, we use the lowest supported rate for 1570 * this band. Also use the lowest supported rate if the stored rate 1571 * idx is invalid. 1572 */ 1573 rate_idx = info->control.rates[0].idx; 1574 if ((info->control.rates[0].flags & IEEE80211_TX_RC_MCS) || rate_idx < 0 1575 || rate_idx > RATE_COUNT_LEGACY) 1576 rate_idx = rate_lowest_index(&il->bands[info->band], sta); 1577 /* For 5 GHZ band, remap mac80211 rate indices into driver indices */ 1578 if (info->band == NL80211_BAND_5GHZ) { 1579 rate_idx += IL_FIRST_OFDM_RATE; 1580 if (rate_idx > IL_LAST_OFDM_RATE) 1581 rate_idx = IL_LAST_OFDM_RATE; 1582 } 1583 /* Get PLCP rate for tx_cmd->rate_n_flags */ 1584 rate_plcp = il_rates[rate_idx].plcp; 1585 /* Zero out flags for this packet */ 1586 rate_flags = 0; 1587 1588 /* Set CCK flag as needed */ 1589 if (rate_idx >= IL_FIRST_CCK_RATE && rate_idx <= IL_LAST_CCK_RATE) 1590 rate_flags |= RATE_MCS_CCK_MSK; 1591 1592 /* Set up antennas */ 1593 il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant); 1594 rate_flags |= BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS; 1595 1596 /* Set the rate in the TX cmd */ 1597 tx_cmd->rate_n_flags = cpu_to_le32(rate_plcp | rate_flags); 1598} 1599 1600static void 1601il4965_tx_cmd_build_hwcrypto(struct il_priv *il, struct ieee80211_tx_info *info, 1602 struct il_tx_cmd *tx_cmd, struct sk_buff *skb_frag, 1603 int sta_id) 1604{ 1605 struct ieee80211_key_conf *keyconf = info->control.hw_key; 1606 1607 switch (keyconf->cipher) { 1608 case WLAN_CIPHER_SUITE_CCMP: 1609 tx_cmd->sec_ctl = TX_CMD_SEC_CCM; 1610 memcpy(tx_cmd->key, keyconf->key, keyconf->keylen); 1611 if (info->flags & IEEE80211_TX_CTL_AMPDU) 1612 tx_cmd->tx_flags |= TX_CMD_FLG_AGG_CCMP_MSK; 1613 D_TX("tx_cmd with AES hwcrypto\n"); 1614 break; 1615 1616 case WLAN_CIPHER_SUITE_TKIP: 1617 tx_cmd->sec_ctl = TX_CMD_SEC_TKIP; 1618 ieee80211_get_tkip_p2k(keyconf, skb_frag, tx_cmd->key); 1619 D_TX("tx_cmd with tkip hwcrypto\n"); 1620 break; 1621 1622 case WLAN_CIPHER_SUITE_WEP104: 1623 tx_cmd->sec_ctl |= TX_CMD_SEC_KEY128; 1624 fallthrough; 1625 case WLAN_CIPHER_SUITE_WEP40: 1626 tx_cmd->sec_ctl |= 1627 (TX_CMD_SEC_WEP | (keyconf->keyidx & TX_CMD_SEC_MSK) << 1628 TX_CMD_SEC_SHIFT); 1629 1630 memcpy(&tx_cmd->key[3], keyconf->key, keyconf->keylen); 1631 1632 D_TX("Configuring packet for WEP encryption " "with key %d\n", 1633 keyconf->keyidx); 1634 break; 1635 1636 default: 1637 IL_ERR("Unknown encode cipher %x\n", keyconf->cipher); 1638 break; 1639 } 1640} 1641 1642/* 1643 * start C_TX command process 1644 */ 1645int 1646il4965_tx_skb(struct il_priv *il, 1647 struct ieee80211_sta *sta, 1648 struct sk_buff *skb) 1649{ 1650 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 1651 struct ieee80211_tx_info *info = IEEE80211_SKB_CB(skb); 1652 struct il_station_priv *sta_priv = NULL; 1653 struct il_tx_queue *txq; 1654 struct il_queue *q; 1655 struct il_device_cmd *out_cmd; 1656 struct il_cmd_meta *out_meta; 1657 struct il_tx_cmd *tx_cmd; 1658 int txq_id; 1659 dma_addr_t phys_addr; 1660 dma_addr_t txcmd_phys; 1661 dma_addr_t scratch_phys; 1662 u16 len, firstlen, secondlen; 1663 u16 seq_number = 0; 1664 __le16 fc; 1665 u8 hdr_len; 1666 u8 sta_id; 1667 u8 wait_write_ptr = 0; 1668 u8 tid = 0; 1669 u8 *qc = NULL; 1670 unsigned long flags; 1671 bool is_agg = false; 1672 1673 spin_lock_irqsave(&il->lock, flags); 1674 if (il_is_rfkill(il)) { 1675 D_DROP("Dropping - RF KILL\n"); 1676 goto drop_unlock; 1677 } 1678 1679 fc = hdr->frame_control; 1680 1681#ifdef CONFIG_IWLEGACY_DEBUG 1682 if (ieee80211_is_auth(fc)) 1683 D_TX("Sending AUTH frame\n"); 1684 else if (ieee80211_is_assoc_req(fc)) 1685 D_TX("Sending ASSOC frame\n"); 1686 else if (ieee80211_is_reassoc_req(fc)) 1687 D_TX("Sending REASSOC frame\n"); 1688#endif 1689 1690 hdr_len = ieee80211_hdrlen(fc); 1691 1692 /* For management frames use broadcast id to do not break aggregation */ 1693 if (!ieee80211_is_data(fc)) 1694 sta_id = il->hw_params.bcast_id; 1695 else { 1696 /* Find idx into station table for destination station */ 1697 sta_id = il_sta_id_or_broadcast(il, sta); 1698 1699 if (sta_id == IL_INVALID_STATION) { 1700 D_DROP("Dropping - INVALID STATION: %pM\n", hdr->addr1); 1701 goto drop_unlock; 1702 } 1703 } 1704 1705 D_TX("station Id %d\n", sta_id); 1706 1707 if (sta) 1708 sta_priv = (void *)sta->drv_priv; 1709 1710 if (sta_priv && sta_priv->asleep && 1711 (info->flags & IEEE80211_TX_CTL_NO_PS_BUFFER)) { 1712 /* 1713 * This sends an asynchronous command to the device, 1714 * but we can rely on it being processed before the 1715 * next frame is processed -- and the next frame to 1716 * this station is the one that will consume this 1717 * counter. 1718 * For now set the counter to just 1 since we do not 1719 * support uAPSD yet. 1720 */ 1721 il4965_sta_modify_sleep_tx_count(il, sta_id, 1); 1722 } 1723 1724 /* FIXME: remove me ? */ 1725 WARN_ON_ONCE(info->flags & IEEE80211_TX_CTL_SEND_AFTER_DTIM); 1726 1727 /* Access category (AC) is also the queue number */ 1728 txq_id = skb_get_queue_mapping(skb); 1729 1730 /* irqs already disabled/saved above when locking il->lock */ 1731 spin_lock(&il->sta_lock); 1732 1733 if (ieee80211_is_data_qos(fc)) { 1734 qc = ieee80211_get_qos_ctl(hdr); 1735 tid = qc[0] & IEEE80211_QOS_CTL_TID_MASK; 1736 if (WARN_ON_ONCE(tid >= MAX_TID_COUNT)) { 1737 spin_unlock(&il->sta_lock); 1738 goto drop_unlock; 1739 } 1740 seq_number = il->stations[sta_id].tid[tid].seq_number; 1741 seq_number &= IEEE80211_SCTL_SEQ; 1742 hdr->seq_ctrl = 1743 hdr->seq_ctrl & cpu_to_le16(IEEE80211_SCTL_FRAG); 1744 hdr->seq_ctrl |= cpu_to_le16(seq_number); 1745 seq_number += 0x10; 1746 /* aggregation is on for this <sta,tid> */ 1747 if (info->flags & IEEE80211_TX_CTL_AMPDU && 1748 il->stations[sta_id].tid[tid].agg.state == IL_AGG_ON) { 1749 txq_id = il->stations[sta_id].tid[tid].agg.txq_id; 1750 is_agg = true; 1751 } 1752 } 1753 1754 txq = &il->txq[txq_id]; 1755 q = &txq->q; 1756 1757 if (unlikely(il_queue_space(q) < q->high_mark)) { 1758 spin_unlock(&il->sta_lock); 1759 goto drop_unlock; 1760 } 1761 1762 if (ieee80211_is_data_qos(fc)) { 1763 il->stations[sta_id].tid[tid].tfds_in_queue++; 1764 if (!ieee80211_has_morefrags(fc)) 1765 il->stations[sta_id].tid[tid].seq_number = seq_number; 1766 } 1767 1768 spin_unlock(&il->sta_lock); 1769 1770 txq->skbs[q->write_ptr] = skb; 1771 1772 /* Set up first empty entry in queue's array of Tx/cmd buffers */ 1773 out_cmd = txq->cmd[q->write_ptr]; 1774 out_meta = &txq->meta[q->write_ptr]; 1775 tx_cmd = container_of(&out_cmd->cmd.tx, struct il_tx_cmd, __hdr); 1776 memset(&out_cmd->hdr, 0, sizeof(out_cmd->hdr)); 1777 memset(tx_cmd, 0, sizeof(struct il_tx_cmd)); 1778 1779 /* 1780 * Set up the Tx-command (not MAC!) header. 1781 * Store the chosen Tx queue and TFD idx within the sequence field; 1782 * after Tx, uCode's Tx response will return this value so driver can 1783 * locate the frame within the tx queue and do post-tx processing. 1784 */ 1785 out_cmd->hdr.cmd = C_TX; 1786 out_cmd->hdr.sequence = 1787 cpu_to_le16((u16) 1788 (QUEUE_TO_SEQ(txq_id) | IDX_TO_SEQ(q->write_ptr))); 1789 1790 /* Copy MAC header from skb into command buffer */ 1791 memcpy(tx_cmd->hdr, hdr, hdr_len); 1792 1793 /* Total # bytes to be transmitted */ 1794 tx_cmd->len = cpu_to_le16((u16) skb->len); 1795 1796 if (info->control.hw_key) 1797 il4965_tx_cmd_build_hwcrypto(il, info, tx_cmd, skb, sta_id); 1798 1799 /* TODO need this for burst mode later on */ 1800 il4965_tx_cmd_build_basic(il, skb, tx_cmd, info, hdr, sta_id); 1801 1802 il4965_tx_cmd_build_rate(il, tx_cmd, info, sta, fc); 1803 1804 /* 1805 * Use the first empty entry in this queue's command buffer array 1806 * to contain the Tx command and MAC header concatenated together 1807 * (payload data will be in another buffer). 1808 * Size of this varies, due to varying MAC header length. 1809 * If end is not dword aligned, we'll have 2 extra bytes at the end 1810 * of the MAC header (device reads on dword boundaries). 1811 * We'll tell device about this padding later. 1812 */ 1813 len = sizeof(struct il_tx_cmd) + sizeof(struct il_cmd_header) + hdr_len; 1814 firstlen = (len + 3) & ~3; 1815 1816 /* Tell NIC about any 2-byte padding after MAC header */ 1817 if (firstlen != len) 1818 tx_cmd->tx_flags |= TX_CMD_FLG_MH_PAD_MSK; 1819 1820 /* Physical address of this Tx command's header (not MAC header!), 1821 * within command buffer array. */ 1822 txcmd_phys = dma_map_single(&il->pci_dev->dev, &out_cmd->hdr, firstlen, 1823 DMA_BIDIRECTIONAL); 1824 if (unlikely(dma_mapping_error(&il->pci_dev->dev, txcmd_phys))) 1825 goto drop_unlock; 1826 1827 /* Set up TFD's 2nd entry to point directly to remainder of skb, 1828 * if any (802.11 null frames have no payload). */ 1829 secondlen = skb->len - hdr_len; 1830 if (secondlen > 0) { 1831 phys_addr = dma_map_single(&il->pci_dev->dev, skb->data + hdr_len, 1832 secondlen, DMA_TO_DEVICE); 1833 if (unlikely(dma_mapping_error(&il->pci_dev->dev, phys_addr))) 1834 goto drop_unlock; 1835 } 1836 1837 /* Add buffer containing Tx command and MAC(!) header to TFD's 1838 * first entry */ 1839 il->ops->txq_attach_buf_to_tfd(il, txq, txcmd_phys, firstlen, 1, 0); 1840 dma_unmap_addr_set(out_meta, mapping, txcmd_phys); 1841 dma_unmap_len_set(out_meta, len, firstlen); 1842 if (secondlen) 1843 il->ops->txq_attach_buf_to_tfd(il, txq, phys_addr, secondlen, 1844 0, 0); 1845 1846 if (!ieee80211_has_morefrags(hdr->frame_control)) { 1847 txq->need_update = 1; 1848 } else { 1849 wait_write_ptr = 1; 1850 txq->need_update = 0; 1851 } 1852 1853 scratch_phys = 1854 txcmd_phys + sizeof(struct il_cmd_header) + 1855 offsetof(struct il_tx_cmd, scratch); 1856 1857 /* take back ownership of DMA buffer to enable update */ 1858 dma_sync_single_for_cpu(&il->pci_dev->dev, txcmd_phys, firstlen, 1859 DMA_BIDIRECTIONAL); 1860 tx_cmd->dram_lsb_ptr = cpu_to_le32(scratch_phys); 1861 tx_cmd->dram_msb_ptr = il_get_dma_hi_addr(scratch_phys); 1862 1863 il_update_stats(il, true, fc, skb->len); 1864 1865 D_TX("sequence nr = 0X%x\n", le16_to_cpu(out_cmd->hdr.sequence)); 1866 D_TX("tx_flags = 0X%x\n", le32_to_cpu(tx_cmd->tx_flags)); 1867 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd, sizeof(*tx_cmd)); 1868 il_print_hex_dump(il, IL_DL_TX, (u8 *) tx_cmd->hdr, hdr_len); 1869 1870 /* Set up entry for this TFD in Tx byte-count array */ 1871 if (info->flags & IEEE80211_TX_CTL_AMPDU) 1872 il->ops->txq_update_byte_cnt_tbl(il, txq, le16_to_cpu(tx_cmd->len)); 1873 1874 dma_sync_single_for_device(&il->pci_dev->dev, txcmd_phys, firstlen, 1875 DMA_BIDIRECTIONAL); 1876 1877 /* Tell device the write idx *just past* this latest filled TFD */ 1878 q->write_ptr = il_queue_inc_wrap(q->write_ptr, q->n_bd); 1879 il_txq_update_write_ptr(il, txq); 1880 spin_unlock_irqrestore(&il->lock, flags); 1881 1882 /* 1883 * At this point the frame is "transmitted" successfully 1884 * and we will get a TX status notification eventually, 1885 * regardless of the value of ret. "ret" only indicates 1886 * whether or not we should update the write pointer. 1887 */ 1888 1889 /* 1890 * Avoid atomic ops if it isn't an associated client. 1891 * Also, if this is a packet for aggregation, don't 1892 * increase the counter because the ucode will stop 1893 * aggregation queues when their respective station 1894 * goes to sleep. 1895 */ 1896 if (sta_priv && sta_priv->client && !is_agg) 1897 atomic_inc(&sta_priv->pending_frames); 1898 1899 if (il_queue_space(q) < q->high_mark && il->mac80211_registered) { 1900 if (wait_write_ptr) { 1901 spin_lock_irqsave(&il->lock, flags); 1902 txq->need_update = 1; 1903 il_txq_update_write_ptr(il, txq); 1904 spin_unlock_irqrestore(&il->lock, flags); 1905 } else { 1906 il_stop_queue(il, txq); 1907 } 1908 } 1909 1910 return 0; 1911 1912drop_unlock: 1913 spin_unlock_irqrestore(&il->lock, flags); 1914 return -1; 1915} 1916 1917static inline int 1918il4965_alloc_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr, size_t size) 1919{ 1920 ptr->addr = dma_alloc_coherent(&il->pci_dev->dev, size, &ptr->dma, 1921 GFP_KERNEL); 1922 if (!ptr->addr) 1923 return -ENOMEM; 1924 ptr->size = size; 1925 return 0; 1926} 1927 1928static inline void 1929il4965_free_dma_ptr(struct il_priv *il, struct il_dma_ptr *ptr) 1930{ 1931 if (unlikely(!ptr->addr)) 1932 return; 1933 1934 dma_free_coherent(&il->pci_dev->dev, ptr->size, ptr->addr, ptr->dma); 1935 memset(ptr, 0, sizeof(*ptr)); 1936} 1937 1938/* 1939 * il4965_hw_txq_ctx_free - Free TXQ Context 1940 * 1941 * Destroy all TX DMA queues and structures 1942 */ 1943void 1944il4965_hw_txq_ctx_free(struct il_priv *il) 1945{ 1946 int txq_id; 1947 1948 /* Tx queues */ 1949 if (il->txq) { 1950 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) 1951 if (txq_id == il->cmd_queue) 1952 il_cmd_queue_free(il); 1953 else 1954 il_tx_queue_free(il, txq_id); 1955 } 1956 il4965_free_dma_ptr(il, &il->kw); 1957 1958 il4965_free_dma_ptr(il, &il->scd_bc_tbls); 1959 1960 /* free tx queue structure */ 1961 il_free_txq_mem(il); 1962} 1963 1964/* 1965 * il4965_txq_ctx_alloc - allocate TX queue context 1966 * Allocate all Tx DMA structures and initialize them 1967 */ 1968int 1969il4965_txq_ctx_alloc(struct il_priv *il) 1970{ 1971 int ret, txq_id; 1972 unsigned long flags; 1973 1974 /* Free all tx/cmd queues and keep-warm buffer */ 1975 il4965_hw_txq_ctx_free(il); 1976 1977 ret = 1978 il4965_alloc_dma_ptr(il, &il->scd_bc_tbls, 1979 il->hw_params.scd_bc_tbls_size); 1980 if (ret) { 1981 IL_ERR("Scheduler BC Table allocation failed\n"); 1982 goto error_bc_tbls; 1983 } 1984 /* Alloc keep-warm buffer */ 1985 ret = il4965_alloc_dma_ptr(il, &il->kw, IL_KW_SIZE); 1986 if (ret) { 1987 IL_ERR("Keep Warm allocation failed\n"); 1988 goto error_kw; 1989 } 1990 1991 /* allocate tx queue structure */ 1992 ret = il_alloc_txq_mem(il); 1993 if (ret) 1994 goto error; 1995 1996 spin_lock_irqsave(&il->lock, flags); 1997 1998 /* Turn off all Tx DMA fifos */ 1999 il4965_txq_set_sched(il, 0); 2000 2001 /* Tell NIC where to find the "keep warm" buffer */ 2002 il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4); 2003 2004 spin_unlock_irqrestore(&il->lock, flags); 2005 2006 /* Alloc and init all Tx queues, including the command queue (#4/#9) */ 2007 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) { 2008 ret = il_tx_queue_init(il, txq_id); 2009 if (ret) { 2010 IL_ERR("Tx %d queue init failed\n", txq_id); 2011 goto error; 2012 } 2013 } 2014 2015 return ret; 2016 2017error: 2018 il4965_hw_txq_ctx_free(il); 2019 il4965_free_dma_ptr(il, &il->kw); 2020error_kw: 2021 il4965_free_dma_ptr(il, &il->scd_bc_tbls); 2022error_bc_tbls: 2023 return ret; 2024} 2025 2026void 2027il4965_txq_ctx_reset(struct il_priv *il) 2028{ 2029 int txq_id; 2030 unsigned long flags; 2031 2032 spin_lock_irqsave(&il->lock, flags); 2033 2034 /* Turn off all Tx DMA fifos */ 2035 il4965_txq_set_sched(il, 0); 2036 /* Tell NIC where to find the "keep warm" buffer */ 2037 il_wr(il, FH49_KW_MEM_ADDR_REG, il->kw.dma >> 4); 2038 2039 spin_unlock_irqrestore(&il->lock, flags); 2040 2041 /* Alloc and init all Tx queues, including the command queue (#4) */ 2042 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) 2043 il_tx_queue_reset(il, txq_id); 2044} 2045 2046static void 2047il4965_txq_ctx_unmap(struct il_priv *il) 2048{ 2049 int txq_id; 2050 2051 if (!il->txq) 2052 return; 2053 2054 /* Unmap DMA from host system and free skb's */ 2055 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) 2056 if (txq_id == il->cmd_queue) 2057 il_cmd_queue_unmap(il); 2058 else 2059 il_tx_queue_unmap(il, txq_id); 2060} 2061 2062/* 2063 * il4965_txq_ctx_stop - Stop all Tx DMA channels 2064 */ 2065void 2066il4965_txq_ctx_stop(struct il_priv *il) 2067{ 2068 int ch, ret; 2069 2070 _il_wr_prph(il, IL49_SCD_TXFACT, 0); 2071 2072 /* Stop each Tx DMA channel, and wait for it to be idle */ 2073 for (ch = 0; ch < il->hw_params.dma_chnl_num; ch++) { 2074 _il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(ch), 0x0); 2075 ret = 2076 _il_poll_bit(il, FH49_TSSR_TX_STATUS_REG, 2077 FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 2078 FH49_TSSR_TX_STATUS_REG_MSK_CHNL_IDLE(ch), 2079 1000); 2080 if (ret < 0) 2081 IL_ERR("Timeout stopping DMA channel %d [0x%08x]", 2082 ch, _il_rd(il, FH49_TSSR_TX_STATUS_REG)); 2083 } 2084} 2085 2086/* 2087 * Find first available (lowest unused) Tx Queue, mark it "active". 2088 * Called only when finding queue for aggregation. 2089 * Should never return anything < 7, because they should already 2090 * be in use as EDCA AC (0-3), Command (4), reserved (5, 6) 2091 */ 2092static int 2093il4965_txq_ctx_activate_free(struct il_priv *il) 2094{ 2095 int txq_id; 2096 2097 for (txq_id = 0; txq_id < il->hw_params.max_txq_num; txq_id++) 2098 if (!test_and_set_bit(txq_id, &il->txq_ctx_active_msk)) 2099 return txq_id; 2100 return -1; 2101} 2102 2103/* 2104 * il4965_tx_queue_stop_scheduler - Stop queue, but keep configuration 2105 */ 2106static void 2107il4965_tx_queue_stop_scheduler(struct il_priv *il, u16 txq_id) 2108{ 2109 /* Simply stop the queue, but don't change any configuration; 2110 * the SCD_ACT_EN bit is the write-enable mask for the ACTIVE bit. */ 2111 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id), 2112 (0 << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) | 2113 (1 << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACT_EN)); 2114} 2115 2116/* 2117 * il4965_tx_queue_set_q2ratid - Map unique receiver/tid combination to a queue 2118 */ 2119static int 2120il4965_tx_queue_set_q2ratid(struct il_priv *il, u16 ra_tid, u16 txq_id) 2121{ 2122 u32 tbl_dw_addr; 2123 u32 tbl_dw; 2124 u16 scd_q2ratid; 2125 2126 scd_q2ratid = ra_tid & IL_SCD_QUEUE_RA_TID_MAP_RATID_MSK; 2127 2128 tbl_dw_addr = 2129 il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(txq_id); 2130 2131 tbl_dw = il_read_targ_mem(il, tbl_dw_addr); 2132 2133 if (txq_id & 0x1) 2134 tbl_dw = (scd_q2ratid << 16) | (tbl_dw & 0x0000FFFF); 2135 else 2136 tbl_dw = scd_q2ratid | (tbl_dw & 0xFFFF0000); 2137 2138 il_write_targ_mem(il, tbl_dw_addr, tbl_dw); 2139 2140 return 0; 2141} 2142 2143/* 2144 * il4965_tx_queue_agg_enable - Set up & enable aggregation for selected queue 2145 * 2146 * NOTE: txq_id must be greater than IL49_FIRST_AMPDU_QUEUE, 2147 * i.e. it must be one of the higher queues used for aggregation 2148 */ 2149static int 2150il4965_txq_agg_enable(struct il_priv *il, int txq_id, int tx_fifo, int sta_id, 2151 int tid, u16 ssn_idx) 2152{ 2153 unsigned long flags; 2154 u16 ra_tid; 2155 int ret; 2156 2157 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) || 2158 (IL49_FIRST_AMPDU_QUEUE + 2159 il->cfg->num_of_ampdu_queues <= txq_id)) { 2160 IL_WARN("queue number out of range: %d, must be %d to %d\n", 2161 txq_id, IL49_FIRST_AMPDU_QUEUE, 2162 IL49_FIRST_AMPDU_QUEUE + 2163 il->cfg->num_of_ampdu_queues - 1); 2164 return -EINVAL; 2165 } 2166 2167 ra_tid = BUILD_RAxTID(sta_id, tid); 2168 2169 /* Modify device's station table to Tx this TID */ 2170 ret = il4965_sta_tx_modify_enable_tid(il, sta_id, tid); 2171 if (ret) 2172 return ret; 2173 2174 spin_lock_irqsave(&il->lock, flags); 2175 2176 /* Stop this Tx queue before configuring it */ 2177 il4965_tx_queue_stop_scheduler(il, txq_id); 2178 2179 /* Map receiver-address / traffic-ID to this queue */ 2180 il4965_tx_queue_set_q2ratid(il, ra_tid, txq_id); 2181 2182 /* Set this queue as a chain-building queue */ 2183 il_set_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id)); 2184 2185 /* Place first TFD at idx corresponding to start sequence number. 2186 * Assumes that ssn_idx is valid (!= 0xFFF) */ 2187 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 2188 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 2189 il4965_set_wr_ptrs(il, txq_id, ssn_idx); 2190 2191 /* Set up Tx win size and frame limit for this queue */ 2192 il_write_targ_mem(il, 2193 il->scd_base_addr + 2194 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id), 2195 (SCD_WIN_SIZE << IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) 2196 & IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK); 2197 2198 il_write_targ_mem(il, 2199 il->scd_base_addr + 2200 IL49_SCD_CONTEXT_QUEUE_OFFSET(txq_id) + sizeof(u32), 2201 (SCD_FRAME_LIMIT << 2202 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 2203 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK); 2204 2205 il_set_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id)); 2206 2207 /* Set up Status area in SRAM, map to Tx DMA/FIFO, activate the queue */ 2208 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 1); 2209 2210 spin_unlock_irqrestore(&il->lock, flags); 2211 2212 return 0; 2213} 2214 2215int 2216il4965_tx_agg_start(struct il_priv *il, struct ieee80211_vif *vif, 2217 struct ieee80211_sta *sta, u16 tid, u16 * ssn) 2218{ 2219 int sta_id; 2220 int tx_fifo; 2221 int txq_id; 2222 int ret; 2223 unsigned long flags; 2224 struct il_tid_data *tid_data; 2225 2226 /* FIXME: warning if tx fifo not found ? */ 2227 tx_fifo = il4965_get_fifo_from_tid(tid); 2228 if (unlikely(tx_fifo < 0)) 2229 return tx_fifo; 2230 2231 D_HT("%s on ra = %pM tid = %d\n", __func__, sta->addr, tid); 2232 2233 sta_id = il_sta_id(sta); 2234 if (sta_id == IL_INVALID_STATION) { 2235 IL_ERR("Start AGG on invalid station\n"); 2236 return -ENXIO; 2237 } 2238 if (unlikely(tid >= MAX_TID_COUNT)) 2239 return -EINVAL; 2240 2241 if (il->stations[sta_id].tid[tid].agg.state != IL_AGG_OFF) { 2242 IL_ERR("Start AGG when state is not IL_AGG_OFF !\n"); 2243 return -ENXIO; 2244 } 2245 2246 txq_id = il4965_txq_ctx_activate_free(il); 2247 if (txq_id == -1) { 2248 IL_ERR("No free aggregation queue available\n"); 2249 return -ENXIO; 2250 } 2251 2252 spin_lock_irqsave(&il->sta_lock, flags); 2253 tid_data = &il->stations[sta_id].tid[tid]; 2254 *ssn = IEEE80211_SEQ_TO_SN(tid_data->seq_number); 2255 tid_data->agg.txq_id = txq_id; 2256 il_set_swq_id(&il->txq[txq_id], il4965_get_ac_from_tid(tid), txq_id); 2257 spin_unlock_irqrestore(&il->sta_lock, flags); 2258 2259 ret = il4965_txq_agg_enable(il, txq_id, tx_fifo, sta_id, tid, *ssn); 2260 if (ret) 2261 return ret; 2262 2263 spin_lock_irqsave(&il->sta_lock, flags); 2264 tid_data = &il->stations[sta_id].tid[tid]; 2265 if (tid_data->tfds_in_queue == 0) { 2266 D_HT("HW queue is empty\n"); 2267 tid_data->agg.state = IL_AGG_ON; 2268 ret = IEEE80211_AMPDU_TX_START_IMMEDIATE; 2269 } else { 2270 D_HT("HW queue is NOT empty: %d packets in HW queue\n", 2271 tid_data->tfds_in_queue); 2272 tid_data->agg.state = IL_EMPTYING_HW_QUEUE_ADDBA; 2273 } 2274 spin_unlock_irqrestore(&il->sta_lock, flags); 2275 return ret; 2276} 2277 2278/* 2279 * txq_id must be greater than IL49_FIRST_AMPDU_QUEUE 2280 * il->lock must be held by the caller 2281 */ 2282static int 2283il4965_txq_agg_disable(struct il_priv *il, u16 txq_id, u16 ssn_idx, u8 tx_fifo) 2284{ 2285 if ((IL49_FIRST_AMPDU_QUEUE > txq_id) || 2286 (IL49_FIRST_AMPDU_QUEUE + 2287 il->cfg->num_of_ampdu_queues <= txq_id)) { 2288 IL_WARN("queue number out of range: %d, must be %d to %d\n", 2289 txq_id, IL49_FIRST_AMPDU_QUEUE, 2290 IL49_FIRST_AMPDU_QUEUE + 2291 il->cfg->num_of_ampdu_queues - 1); 2292 return -EINVAL; 2293 } 2294 2295 il4965_tx_queue_stop_scheduler(il, txq_id); 2296 2297 il_clear_bits_prph(il, IL49_SCD_QUEUECHAIN_SEL, (1 << txq_id)); 2298 2299 il->txq[txq_id].q.read_ptr = (ssn_idx & 0xff); 2300 il->txq[txq_id].q.write_ptr = (ssn_idx & 0xff); 2301 /* supposes that ssn_idx is valid (!= 0xFFF) */ 2302 il4965_set_wr_ptrs(il, txq_id, ssn_idx); 2303 2304 il_clear_bits_prph(il, IL49_SCD_INTERRUPT_MASK, (1 << txq_id)); 2305 il_txq_ctx_deactivate(il, txq_id); 2306 il4965_tx_queue_set_status(il, &il->txq[txq_id], tx_fifo, 0); 2307 2308 return 0; 2309} 2310 2311int 2312il4965_tx_agg_stop(struct il_priv *il, struct ieee80211_vif *vif, 2313 struct ieee80211_sta *sta, u16 tid) 2314{ 2315 int tx_fifo_id, txq_id, sta_id, ssn; 2316 struct il_tid_data *tid_data; 2317 int write_ptr, read_ptr; 2318 unsigned long flags; 2319 2320 /* FIXME: warning if tx_fifo_id not found ? */ 2321 tx_fifo_id = il4965_get_fifo_from_tid(tid); 2322 if (unlikely(tx_fifo_id < 0)) 2323 return tx_fifo_id; 2324 2325 sta_id = il_sta_id(sta); 2326 2327 if (sta_id == IL_INVALID_STATION) { 2328 IL_ERR("Invalid station for AGG tid %d\n", tid); 2329 return -ENXIO; 2330 } 2331 2332 spin_lock_irqsave(&il->sta_lock, flags); 2333 2334 tid_data = &il->stations[sta_id].tid[tid]; 2335 ssn = (tid_data->seq_number & IEEE80211_SCTL_SEQ) >> 4; 2336 txq_id = tid_data->agg.txq_id; 2337 2338 switch (il->stations[sta_id].tid[tid].agg.state) { 2339 case IL_EMPTYING_HW_QUEUE_ADDBA: 2340 /* 2341 * This can happen if the peer stops aggregation 2342 * again before we've had a chance to drain the 2343 * queue we selected previously, i.e. before the 2344 * session was really started completely. 2345 */ 2346 D_HT("AGG stop before setup done\n"); 2347 goto turn_off; 2348 case IL_AGG_ON: 2349 break; 2350 default: 2351 IL_WARN("Stopping AGG while state not ON or starting\n"); 2352 } 2353 2354 write_ptr = il->txq[txq_id].q.write_ptr; 2355 read_ptr = il->txq[txq_id].q.read_ptr; 2356 2357 /* The queue is not empty */ 2358 if (write_ptr != read_ptr) { 2359 D_HT("Stopping a non empty AGG HW QUEUE\n"); 2360 il->stations[sta_id].tid[tid].agg.state = 2361 IL_EMPTYING_HW_QUEUE_DELBA; 2362 spin_unlock_irqrestore(&il->sta_lock, flags); 2363 return 0; 2364 } 2365 2366 D_HT("HW queue is empty\n"); 2367turn_off: 2368 il->stations[sta_id].tid[tid].agg.state = IL_AGG_OFF; 2369 2370 /* do not restore/save irqs */ 2371 spin_unlock(&il->sta_lock); 2372 spin_lock(&il->lock); 2373 2374 /* 2375 * the only reason this call can fail is queue number out of range, 2376 * which can happen if uCode is reloaded and all the station 2377 * information are lost. if it is outside the range, there is no need 2378 * to deactivate the uCode queue, just return "success" to allow 2379 * mac80211 to clean up it own data. 2380 */ 2381 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo_id); 2382 spin_unlock_irqrestore(&il->lock, flags); 2383 2384 ieee80211_stop_tx_ba_cb_irqsafe(vif, sta->addr, tid); 2385 2386 return 0; 2387} 2388 2389int 2390il4965_txq_check_empty(struct il_priv *il, int sta_id, u8 tid, int txq_id) 2391{ 2392 struct il_queue *q = &il->txq[txq_id].q; 2393 u8 *addr = il->stations[sta_id].sta.sta.addr; 2394 struct il_tid_data *tid_data = &il->stations[sta_id].tid[tid]; 2395 2396 lockdep_assert_held(&il->sta_lock); 2397 2398 switch (il->stations[sta_id].tid[tid].agg.state) { 2399 case IL_EMPTYING_HW_QUEUE_DELBA: 2400 /* We are reclaiming the last packet of the */ 2401 /* aggregated HW queue */ 2402 if (txq_id == tid_data->agg.txq_id && 2403 q->read_ptr == q->write_ptr) { 2404 u16 ssn = IEEE80211_SEQ_TO_SN(tid_data->seq_number); 2405 int tx_fifo = il4965_get_fifo_from_tid(tid); 2406 D_HT("HW queue empty: continue DELBA flow\n"); 2407 il4965_txq_agg_disable(il, txq_id, ssn, tx_fifo); 2408 tid_data->agg.state = IL_AGG_OFF; 2409 ieee80211_stop_tx_ba_cb_irqsafe(il->vif, addr, tid); 2410 } 2411 break; 2412 case IL_EMPTYING_HW_QUEUE_ADDBA: 2413 /* We are reclaiming the last packet of the queue */ 2414 if (tid_data->tfds_in_queue == 0) { 2415 D_HT("HW queue empty: continue ADDBA flow\n"); 2416 tid_data->agg.state = IL_AGG_ON; 2417 ieee80211_start_tx_ba_cb_irqsafe(il->vif, addr, tid); 2418 } 2419 break; 2420 } 2421 2422 return 0; 2423} 2424 2425static void 2426il4965_non_agg_tx_status(struct il_priv *il, const u8 *addr1) 2427{ 2428 struct ieee80211_sta *sta; 2429 struct il_station_priv *sta_priv; 2430 2431 rcu_read_lock(); 2432 sta = ieee80211_find_sta(il->vif, addr1); 2433 if (sta) { 2434 sta_priv = (void *)sta->drv_priv; 2435 /* avoid atomic ops if this isn't a client */ 2436 if (sta_priv->client && 2437 atomic_dec_return(&sta_priv->pending_frames) == 0) 2438 ieee80211_sta_block_awake(il->hw, sta, false); 2439 } 2440 rcu_read_unlock(); 2441} 2442 2443static void 2444il4965_tx_status(struct il_priv *il, struct sk_buff *skb, bool is_agg) 2445{ 2446 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data; 2447 2448 if (!is_agg) 2449 il4965_non_agg_tx_status(il, hdr->addr1); 2450 2451 ieee80211_tx_status_irqsafe(il->hw, skb); 2452} 2453 2454int 2455il4965_tx_queue_reclaim(struct il_priv *il, int txq_id, int idx) 2456{ 2457 struct il_tx_queue *txq = &il->txq[txq_id]; 2458 struct il_queue *q = &txq->q; 2459 int nfreed = 0; 2460 struct ieee80211_hdr *hdr; 2461 struct sk_buff *skb; 2462 2463 if (idx >= q->n_bd || il_queue_used(q, idx) == 0) { 2464 IL_ERR("Read idx for DMA queue txq id (%d), idx %d, " 2465 "is out of range [0-%d] %d %d.\n", txq_id, idx, q->n_bd, 2466 q->write_ptr, q->read_ptr); 2467 return 0; 2468 } 2469 2470 for (idx = il_queue_inc_wrap(idx, q->n_bd); q->read_ptr != idx; 2471 q->read_ptr = il_queue_inc_wrap(q->read_ptr, q->n_bd)) { 2472 2473 skb = txq->skbs[txq->q.read_ptr]; 2474 2475 if (WARN_ON_ONCE(skb == NULL)) 2476 continue; 2477 2478 hdr = (struct ieee80211_hdr *) skb->data; 2479 if (ieee80211_is_data_qos(hdr->frame_control)) 2480 nfreed++; 2481 2482 il4965_tx_status(il, skb, txq_id >= IL4965_FIRST_AMPDU_QUEUE); 2483 2484 txq->skbs[txq->q.read_ptr] = NULL; 2485 il->ops->txq_free_tfd(il, txq); 2486 } 2487 return nfreed; 2488} 2489 2490/* 2491 * il4965_tx_status_reply_compressed_ba - Update tx status from block-ack 2492 * 2493 * Go through block-ack's bitmap of ACK'd frames, update driver's record of 2494 * ACK vs. not. This gets sent to mac80211, then to rate scaling algo. 2495 */ 2496static int 2497il4965_tx_status_reply_compressed_ba(struct il_priv *il, struct il_ht_agg *agg, 2498 struct il_compressed_ba_resp *ba_resp) 2499{ 2500 int i, sh, ack; 2501 u16 seq_ctl = le16_to_cpu(ba_resp->seq_ctl); 2502 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow); 2503 int successes = 0; 2504 struct ieee80211_tx_info *info; 2505 u64 bitmap, sent_bitmap; 2506 2507 if (unlikely(!agg->wait_for_ba)) { 2508 if (unlikely(ba_resp->bitmap)) 2509 IL_ERR("Received BA when not expected\n"); 2510 return -EINVAL; 2511 } 2512 2513 /* Mark that the expected block-ack response arrived */ 2514 agg->wait_for_ba = 0; 2515 D_TX_REPLY("BA %d %d\n", agg->start_idx, ba_resp->seq_ctl); 2516 2517 /* Calculate shift to align block-ack bits with our Tx win bits */ 2518 sh = agg->start_idx - SEQ_TO_IDX(seq_ctl >> 4); 2519 if (sh < 0) /* tbw something is wrong with indices */ 2520 sh += 0x100; 2521 2522 if (agg->frame_count > (64 - sh)) { 2523 D_TX_REPLY("more frames than bitmap size"); 2524 return -1; 2525 } 2526 2527 /* don't use 64-bit values for now */ 2528 bitmap = le64_to_cpu(ba_resp->bitmap) >> sh; 2529 2530 /* check for success or failure according to the 2531 * transmitted bitmap and block-ack bitmap */ 2532 sent_bitmap = bitmap & agg->bitmap; 2533 2534 /* For each frame attempted in aggregation, 2535 * update driver's record of tx frame's status. */ 2536 i = 0; 2537 while (sent_bitmap) { 2538 ack = sent_bitmap & 1ULL; 2539 successes += ack; 2540 D_TX_REPLY("%s ON i=%d idx=%d raw=%d\n", ack ? "ACK" : "NACK", 2541 i, (agg->start_idx + i) & 0xff, agg->start_idx + i); 2542 sent_bitmap >>= 1; 2543 ++i; 2544 } 2545 2546 D_TX_REPLY("Bitmap %llx\n", (unsigned long long)bitmap); 2547 2548 info = IEEE80211_SKB_CB(il->txq[scd_flow].skbs[agg->start_idx]); 2549 memset(&info->status, 0, sizeof(info->status)); 2550 info->flags |= IEEE80211_TX_STAT_ACK; 2551 info->flags |= IEEE80211_TX_STAT_AMPDU; 2552 info->status.ampdu_ack_len = successes; 2553 info->status.ampdu_len = agg->frame_count; 2554 il4965_hwrate_to_tx_control(il, agg->rate_n_flags, info); 2555 2556 return 0; 2557} 2558 2559static inline bool 2560il4965_is_tx_success(u32 status) 2561{ 2562 status &= TX_STATUS_MSK; 2563 return (status == TX_STATUS_SUCCESS || status == TX_STATUS_DIRECT_DONE); 2564} 2565 2566static u8 2567il4965_find_station(struct il_priv *il, const u8 *addr) 2568{ 2569 int i; 2570 int start = 0; 2571 int ret = IL_INVALID_STATION; 2572 unsigned long flags; 2573 2574 if (il->iw_mode == NL80211_IFTYPE_ADHOC) 2575 start = IL_STA_ID; 2576 2577 if (is_broadcast_ether_addr(addr)) 2578 return il->hw_params.bcast_id; 2579 2580 spin_lock_irqsave(&il->sta_lock, flags); 2581 for (i = start; i < il->hw_params.max_stations; i++) 2582 if (il->stations[i].used && 2583 ether_addr_equal(il->stations[i].sta.sta.addr, addr)) { 2584 ret = i; 2585 goto out; 2586 } 2587 2588 D_ASSOC("can not find STA %pM total %d\n", addr, il->num_stations); 2589 2590out: 2591 /* 2592 * It may be possible that more commands interacting with stations 2593 * arrive before we completed processing the adding of 2594 * station 2595 */ 2596 if (ret != IL_INVALID_STATION && 2597 (!(il->stations[ret].used & IL_STA_UCODE_ACTIVE) || 2598 (il->stations[ret].used & IL_STA_UCODE_INPROGRESS))) { 2599 IL_ERR("Requested station info for sta %d before ready.\n", 2600 ret); 2601 ret = IL_INVALID_STATION; 2602 } 2603 spin_unlock_irqrestore(&il->sta_lock, flags); 2604 return ret; 2605} 2606 2607static int 2608il4965_get_ra_sta_id(struct il_priv *il, struct ieee80211_hdr *hdr) 2609{ 2610 if (il->iw_mode == NL80211_IFTYPE_STATION) 2611 return IL_AP_ID; 2612 else { 2613 u8 *da = ieee80211_get_DA(hdr); 2614 2615 return il4965_find_station(il, da); 2616 } 2617} 2618 2619static inline u32 2620il4965_get_scd_ssn(struct il4965_tx_resp *tx_resp) 2621{ 2622 return le32_to_cpup(&tx_resp->u.status + 2623 tx_resp->frame_count) & IEEE80211_MAX_SN; 2624} 2625 2626static inline u32 2627il4965_tx_status_to_mac80211(u32 status) 2628{ 2629 status &= TX_STATUS_MSK; 2630 2631 switch (status) { 2632 case TX_STATUS_SUCCESS: 2633 case TX_STATUS_DIRECT_DONE: 2634 return IEEE80211_TX_STAT_ACK; 2635 case TX_STATUS_FAIL_DEST_PS: 2636 return IEEE80211_TX_STAT_TX_FILTERED; 2637 default: 2638 return 0; 2639 } 2640} 2641 2642/* 2643 * il4965_tx_status_reply_tx - Handle Tx response for frames in aggregation queue 2644 */ 2645static int 2646il4965_tx_status_reply_tx(struct il_priv *il, struct il_ht_agg *agg, 2647 struct il4965_tx_resp *tx_resp, int txq_id, 2648 u16 start_idx) 2649{ 2650 u16 status; 2651 struct agg_tx_status *frame_status = tx_resp->u.agg_status; 2652 struct ieee80211_tx_info *info = NULL; 2653 struct ieee80211_hdr *hdr = NULL; 2654 u32 rate_n_flags = le32_to_cpu(tx_resp->rate_n_flags); 2655 int i, sh, idx; 2656 u16 seq; 2657 if (agg->wait_for_ba) 2658 D_TX_REPLY("got tx response w/o block-ack\n"); 2659 2660 agg->frame_count = tx_resp->frame_count; 2661 agg->start_idx = start_idx; 2662 agg->rate_n_flags = rate_n_flags; 2663 agg->bitmap = 0; 2664 2665 /* num frames attempted by Tx command */ 2666 if (agg->frame_count == 1) { 2667 /* Only one frame was attempted; no block-ack will arrive */ 2668 status = le16_to_cpu(frame_status[0].status); 2669 idx = start_idx; 2670 2671 D_TX_REPLY("FrameCnt = %d, StartIdx=%d idx=%d\n", 2672 agg->frame_count, agg->start_idx, idx); 2673 2674 info = IEEE80211_SKB_CB(il->txq[txq_id].skbs[idx]); 2675 info->status.rates[0].count = tx_resp->failure_frame + 1; 2676 info->flags &= ~IEEE80211_TX_CTL_AMPDU; 2677 info->flags |= il4965_tx_status_to_mac80211(status); 2678 il4965_hwrate_to_tx_control(il, rate_n_flags, info); 2679 2680 D_TX_REPLY("1 Frame 0x%x failure :%d\n", status & 0xff, 2681 tx_resp->failure_frame); 2682 D_TX_REPLY("Rate Info rate_n_flags=%x\n", rate_n_flags); 2683 2684 agg->wait_for_ba = 0; 2685 } else { 2686 /* Two or more frames were attempted; expect block-ack */ 2687 u64 bitmap = 0; 2688 int start = agg->start_idx; 2689 struct sk_buff *skb; 2690 2691 /* Construct bit-map of pending frames within Tx win */ 2692 for (i = 0; i < agg->frame_count; i++) { 2693 u16 sc; 2694 status = le16_to_cpu(frame_status[i].status); 2695 seq = le16_to_cpu(frame_status[i].sequence); 2696 idx = SEQ_TO_IDX(seq); 2697 txq_id = SEQ_TO_QUEUE(seq); 2698 2699 if (status & 2700 (AGG_TX_STATE_FEW_BYTES_MSK | 2701 AGG_TX_STATE_ABORT_MSK)) 2702 continue; 2703 2704 D_TX_REPLY("FrameCnt = %d, txq_id=%d idx=%d\n", 2705 agg->frame_count, txq_id, idx); 2706 2707 skb = il->txq[txq_id].skbs[idx]; 2708 if (WARN_ON_ONCE(skb == NULL)) 2709 return -1; 2710 hdr = (struct ieee80211_hdr *) skb->data; 2711 2712 sc = le16_to_cpu(hdr->seq_ctrl); 2713 if (idx != (IEEE80211_SEQ_TO_SN(sc) & 0xff)) { 2714 IL_ERR("BUG_ON idx doesn't match seq control" 2715 " idx=%d, seq_idx=%d, seq=%d\n", idx, 2716 IEEE80211_SEQ_TO_SN(sc), hdr->seq_ctrl); 2717 return -1; 2718 } 2719 2720 D_TX_REPLY("AGG Frame i=%d idx %d seq=%d\n", i, idx, 2721 IEEE80211_SEQ_TO_SN(sc)); 2722 2723 sh = idx - start; 2724 if (sh > 64) { 2725 sh = (start - idx) + 0xff; 2726 bitmap = bitmap << sh; 2727 sh = 0; 2728 start = idx; 2729 } else if (sh < -64) 2730 sh = 0xff - (start - idx); 2731 else if (sh < 0) { 2732 sh = start - idx; 2733 start = idx; 2734 bitmap = bitmap << sh; 2735 sh = 0; 2736 } 2737 bitmap |= 1ULL << sh; 2738 D_TX_REPLY("start=%d bitmap=0x%llx\n", start, 2739 (unsigned long long)bitmap); 2740 } 2741 2742 agg->bitmap = bitmap; 2743 agg->start_idx = start; 2744 D_TX_REPLY("Frames %d start_idx=%d bitmap=0x%llx\n", 2745 agg->frame_count, agg->start_idx, 2746 (unsigned long long)agg->bitmap); 2747 2748 if (bitmap) 2749 agg->wait_for_ba = 1; 2750 } 2751 return 0; 2752} 2753 2754/* 2755 * il4965_hdl_tx - Handle standard (non-aggregation) Tx response 2756 */ 2757static void 2758il4965_hdl_tx(struct il_priv *il, struct il_rx_buf *rxb) 2759{ 2760 struct il_rx_pkt *pkt = rxb_addr(rxb); 2761 u16 sequence = le16_to_cpu(pkt->hdr.sequence); 2762 int txq_id = SEQ_TO_QUEUE(sequence); 2763 int idx = SEQ_TO_IDX(sequence); 2764 struct il_tx_queue *txq = &il->txq[txq_id]; 2765 struct sk_buff *skb; 2766 struct ieee80211_hdr *hdr; 2767 struct ieee80211_tx_info *info; 2768 struct il4965_tx_resp *tx_resp = (void *)&pkt->u.raw[0]; 2769 u32 status = le32_to_cpu(tx_resp->u.status); 2770 int tid; 2771 int sta_id; 2772 int freed; 2773 u8 *qc = NULL; 2774 unsigned long flags; 2775 2776 if (idx >= txq->q.n_bd || il_queue_used(&txq->q, idx) == 0) { 2777 IL_ERR("Read idx for DMA queue txq_id (%d) idx %d " 2778 "is out of range [0-%d] %d %d\n", txq_id, idx, 2779 txq->q.n_bd, txq->q.write_ptr, txq->q.read_ptr); 2780 return; 2781 } 2782 2783 txq->time_stamp = jiffies; 2784 2785 skb = txq->skbs[txq->q.read_ptr]; 2786 info = IEEE80211_SKB_CB(skb); 2787 memset(&info->status, 0, sizeof(info->status)); 2788 2789 hdr = (struct ieee80211_hdr *) skb->data; 2790 if (ieee80211_is_data_qos(hdr->frame_control)) { 2791 qc = ieee80211_get_qos_ctl(hdr); 2792 tid = qc[0] & 0xf; 2793 } 2794 2795 sta_id = il4965_get_ra_sta_id(il, hdr); 2796 if (txq->sched_retry && unlikely(sta_id == IL_INVALID_STATION)) { 2797 IL_ERR("Station not known\n"); 2798 return; 2799 } 2800 2801 /* 2802 * Firmware will not transmit frame on passive channel, if it not yet 2803 * received some valid frame on that channel. When this error happen 2804 * we have to wait until firmware will unblock itself i.e. when we 2805 * note received beacon or other frame. We unblock queues in 2806 * il4965_pass_packet_to_mac80211 or in il_mac_bss_info_changed. 2807 */ 2808 if (unlikely((status & TX_STATUS_MSK) == TX_STATUS_FAIL_PASSIVE_NO_RX) && 2809 il->iw_mode == NL80211_IFTYPE_STATION) { 2810 il_stop_queues_by_reason(il, IL_STOP_REASON_PASSIVE); 2811 D_INFO("Stopped queues - RX waiting on passive channel\n"); 2812 } 2813 2814 spin_lock_irqsave(&il->sta_lock, flags); 2815 if (txq->sched_retry) { 2816 const u32 scd_ssn = il4965_get_scd_ssn(tx_resp); 2817 struct il_ht_agg *agg; 2818 2819 if (WARN_ON(!qc)) 2820 goto out; 2821 2822 agg = &il->stations[sta_id].tid[tid].agg; 2823 2824 il4965_tx_status_reply_tx(il, agg, tx_resp, txq_id, idx); 2825 2826 /* check if BAR is needed */ 2827 if (tx_resp->frame_count == 1 && 2828 !il4965_is_tx_success(status)) 2829 info->flags |= IEEE80211_TX_STAT_AMPDU_NO_BACK; 2830 2831 if (txq->q.read_ptr != (scd_ssn & 0xff)) { 2832 idx = il_queue_dec_wrap(scd_ssn & 0xff, txq->q.n_bd); 2833 D_TX_REPLY("Retry scheduler reclaim scd_ssn " 2834 "%d idx %d\n", scd_ssn, idx); 2835 freed = il4965_tx_queue_reclaim(il, txq_id, idx); 2836 il4965_free_tfds_in_queue(il, sta_id, tid, freed); 2837 2838 if (il->mac80211_registered && 2839 il_queue_space(&txq->q) > txq->q.low_mark && 2840 agg->state != IL_EMPTYING_HW_QUEUE_DELBA) 2841 il_wake_queue(il, txq); 2842 } 2843 } else { 2844 info->status.rates[0].count = tx_resp->failure_frame + 1; 2845 info->flags |= il4965_tx_status_to_mac80211(status); 2846 il4965_hwrate_to_tx_control(il, 2847 le32_to_cpu(tx_resp->rate_n_flags), 2848 info); 2849 2850 D_TX_REPLY("TXQ %d status %s (0x%08x) " 2851 "rate_n_flags 0x%x retries %d\n", txq_id, 2852 il4965_get_tx_fail_reason(status), status, 2853 le32_to_cpu(tx_resp->rate_n_flags), 2854 tx_resp->failure_frame); 2855 2856 freed = il4965_tx_queue_reclaim(il, txq_id, idx); 2857 if (qc && likely(sta_id != IL_INVALID_STATION)) 2858 il4965_free_tfds_in_queue(il, sta_id, tid, freed); 2859 else if (sta_id == IL_INVALID_STATION) 2860 D_TX_REPLY("Station not known\n"); 2861 2862 if (il->mac80211_registered && 2863 il_queue_space(&txq->q) > txq->q.low_mark) 2864 il_wake_queue(il, txq); 2865 } 2866out: 2867 if (qc && likely(sta_id != IL_INVALID_STATION)) 2868 il4965_txq_check_empty(il, sta_id, tid, txq_id); 2869 2870 il4965_check_abort_status(il, tx_resp->frame_count, status); 2871 2872 spin_unlock_irqrestore(&il->sta_lock, flags); 2873} 2874 2875/* 2876 * translate ucode response to mac80211 tx status control values 2877 */ 2878void 2879il4965_hwrate_to_tx_control(struct il_priv *il, u32 rate_n_flags, 2880 struct ieee80211_tx_info *info) 2881{ 2882 struct ieee80211_tx_rate *r = &info->status.rates[0]; 2883 2884 info->status.antenna = 2885 ((rate_n_flags & RATE_MCS_ANT_ABC_MSK) >> RATE_MCS_ANT_POS); 2886 if (rate_n_flags & RATE_MCS_HT_MSK) 2887 r->flags |= IEEE80211_TX_RC_MCS; 2888 if (rate_n_flags & RATE_MCS_GF_MSK) 2889 r->flags |= IEEE80211_TX_RC_GREEN_FIELD; 2890 if (rate_n_flags & RATE_MCS_HT40_MSK) 2891 r->flags |= IEEE80211_TX_RC_40_MHZ_WIDTH; 2892 if (rate_n_flags & RATE_MCS_DUP_MSK) 2893 r->flags |= IEEE80211_TX_RC_DUP_DATA; 2894 if (rate_n_flags & RATE_MCS_SGI_MSK) 2895 r->flags |= IEEE80211_TX_RC_SHORT_GI; 2896 r->idx = il4965_hwrate_to_mac80211_idx(rate_n_flags, info->band); 2897} 2898 2899/* 2900 * il4965_hdl_compressed_ba - Handler for N_COMPRESSED_BA 2901 * 2902 * Handles block-acknowledge notification from device, which reports success 2903 * of frames sent via aggregation. 2904 */ 2905static void 2906il4965_hdl_compressed_ba(struct il_priv *il, struct il_rx_buf *rxb) 2907{ 2908 struct il_rx_pkt *pkt = rxb_addr(rxb); 2909 struct il_compressed_ba_resp *ba_resp = &pkt->u.compressed_ba; 2910 struct il_tx_queue *txq = NULL; 2911 struct il_ht_agg *agg; 2912 int idx; 2913 int sta_id; 2914 int tid; 2915 unsigned long flags; 2916 2917 /* "flow" corresponds to Tx queue */ 2918 u16 scd_flow = le16_to_cpu(ba_resp->scd_flow); 2919 2920 /* "ssn" is start of block-ack Tx win, corresponds to idx 2921 * (in Tx queue's circular buffer) of first TFD/frame in win */ 2922 u16 ba_resp_scd_ssn = le16_to_cpu(ba_resp->scd_ssn); 2923 2924 if (scd_flow >= il->hw_params.max_txq_num) { 2925 IL_ERR("BUG_ON scd_flow is bigger than number of queues\n"); 2926 return; 2927 } 2928 2929 txq = &il->txq[scd_flow]; 2930 sta_id = ba_resp->sta_id; 2931 tid = ba_resp->tid; 2932 agg = &il->stations[sta_id].tid[tid].agg; 2933 if (unlikely(agg->txq_id != scd_flow)) { 2934 /* 2935 * FIXME: this is a uCode bug which need to be addressed, 2936 * log the information and return for now! 2937 * since it is possible happen very often and in order 2938 * not to fill the syslog, don't enable the logging by default 2939 */ 2940 D_TX_REPLY("BA scd_flow %d does not match txq_id %d\n", 2941 scd_flow, agg->txq_id); 2942 return; 2943 } 2944 2945 /* Find idx just before block-ack win */ 2946 idx = il_queue_dec_wrap(ba_resp_scd_ssn & 0xff, txq->q.n_bd); 2947 2948 spin_lock_irqsave(&il->sta_lock, flags); 2949 2950 D_TX_REPLY("N_COMPRESSED_BA [%d] Received from %pM, " "sta_id = %d\n", 2951 agg->wait_for_ba, (u8 *) &ba_resp->sta_addr_lo32, 2952 ba_resp->sta_id); 2953 D_TX_REPLY("TID = %d, SeqCtl = %d, bitmap = 0x%llx," "scd_flow = " 2954 "%d, scd_ssn = %d\n", ba_resp->tid, ba_resp->seq_ctl, 2955 (unsigned long long)le64_to_cpu(ba_resp->bitmap), 2956 ba_resp->scd_flow, ba_resp->scd_ssn); 2957 D_TX_REPLY("DAT start_idx = %d, bitmap = 0x%llx\n", agg->start_idx, 2958 (unsigned long long)agg->bitmap); 2959 2960 /* Update driver's record of ACK vs. not for each frame in win */ 2961 il4965_tx_status_reply_compressed_ba(il, agg, ba_resp); 2962 2963 /* Release all TFDs before the SSN, i.e. all TFDs in front of 2964 * block-ack win (we assume that they've been successfully 2965 * transmitted ... if not, it's too late anyway). */ 2966 if (txq->q.read_ptr != (ba_resp_scd_ssn & 0xff)) { 2967 /* calculate mac80211 ampdu sw queue to wake */ 2968 int freed = il4965_tx_queue_reclaim(il, scd_flow, idx); 2969 il4965_free_tfds_in_queue(il, sta_id, tid, freed); 2970 2971 if (il_queue_space(&txq->q) > txq->q.low_mark && 2972 il->mac80211_registered && 2973 agg->state != IL_EMPTYING_HW_QUEUE_DELBA) 2974 il_wake_queue(il, txq); 2975 2976 il4965_txq_check_empty(il, sta_id, tid, scd_flow); 2977 } 2978 2979 spin_unlock_irqrestore(&il->sta_lock, flags); 2980} 2981 2982#ifdef CONFIG_IWLEGACY_DEBUG 2983const char * 2984il4965_get_tx_fail_reason(u32 status) 2985{ 2986#define TX_STATUS_FAIL(x) case TX_STATUS_FAIL_ ## x: return #x 2987#define TX_STATUS_POSTPONE(x) case TX_STATUS_POSTPONE_ ## x: return #x 2988 2989 switch (status & TX_STATUS_MSK) { 2990 case TX_STATUS_SUCCESS: 2991 return "SUCCESS"; 2992 TX_STATUS_POSTPONE(DELAY); 2993 TX_STATUS_POSTPONE(FEW_BYTES); 2994 TX_STATUS_POSTPONE(QUIET_PERIOD); 2995 TX_STATUS_POSTPONE(CALC_TTAK); 2996 TX_STATUS_FAIL(INTERNAL_CROSSED_RETRY); 2997 TX_STATUS_FAIL(SHORT_LIMIT); 2998 TX_STATUS_FAIL(LONG_LIMIT); 2999 TX_STATUS_FAIL(FIFO_UNDERRUN); 3000 TX_STATUS_FAIL(DRAIN_FLOW); 3001 TX_STATUS_FAIL(RFKILL_FLUSH); 3002 TX_STATUS_FAIL(LIFE_EXPIRE); 3003 TX_STATUS_FAIL(DEST_PS); 3004 TX_STATUS_FAIL(HOST_ABORTED); 3005 TX_STATUS_FAIL(BT_RETRY); 3006 TX_STATUS_FAIL(STA_INVALID); 3007 TX_STATUS_FAIL(FRAG_DROPPED); 3008 TX_STATUS_FAIL(TID_DISABLE); 3009 TX_STATUS_FAIL(FIFO_FLUSHED); 3010 TX_STATUS_FAIL(INSUFFICIENT_CF_POLL); 3011 TX_STATUS_FAIL(PASSIVE_NO_RX); 3012 TX_STATUS_FAIL(NO_BEACON_ON_RADAR); 3013 } 3014 3015 return "UNKNOWN"; 3016 3017#undef TX_STATUS_FAIL 3018#undef TX_STATUS_POSTPONE 3019} 3020#endif /* CONFIG_IWLEGACY_DEBUG */ 3021 3022static struct il_link_quality_cmd * 3023il4965_sta_alloc_lq(struct il_priv *il, u8 sta_id) 3024{ 3025 int i, r; 3026 struct il_link_quality_cmd *link_cmd; 3027 u32 rate_flags = 0; 3028 __le32 rate_n_flags; 3029 3030 link_cmd = kzalloc(sizeof(struct il_link_quality_cmd), GFP_KERNEL); 3031 if (!link_cmd) { 3032 IL_ERR("Unable to allocate memory for LQ cmd.\n"); 3033 return NULL; 3034 } 3035 /* Set up the rate scaling to start at selected rate, fall back 3036 * all the way down to 1M in IEEE order, and then spin on 1M */ 3037 if (il->band == NL80211_BAND_5GHZ) 3038 r = RATE_6M_IDX; 3039 else 3040 r = RATE_1M_IDX; 3041 3042 if (r >= IL_FIRST_CCK_RATE && r <= IL_LAST_CCK_RATE) 3043 rate_flags |= RATE_MCS_CCK_MSK; 3044 3045 rate_flags |= 3046 il4965_first_antenna(il->hw_params. 3047 valid_tx_ant) << RATE_MCS_ANT_POS; 3048 rate_n_flags = cpu_to_le32(il_rates[r].plcp | rate_flags); 3049 for (i = 0; i < LINK_QUAL_MAX_RETRY_NUM; i++) 3050 link_cmd->rs_table[i].rate_n_flags = rate_n_flags; 3051 3052 link_cmd->general_params.single_stream_ant_msk = 3053 il4965_first_antenna(il->hw_params.valid_tx_ant); 3054 3055 link_cmd->general_params.dual_stream_ant_msk = 3056 il->hw_params.valid_tx_ant & ~il4965_first_antenna(il->hw_params. 3057 valid_tx_ant); 3058 if (!link_cmd->general_params.dual_stream_ant_msk) { 3059 link_cmd->general_params.dual_stream_ant_msk = ANT_AB; 3060 } else if (il4965_num_of_ant(il->hw_params.valid_tx_ant) == 2) { 3061 link_cmd->general_params.dual_stream_ant_msk = 3062 il->hw_params.valid_tx_ant; 3063 } 3064 3065 link_cmd->agg_params.agg_dis_start_th = LINK_QUAL_AGG_DISABLE_START_DEF; 3066 link_cmd->agg_params.agg_time_limit = 3067 cpu_to_le16(LINK_QUAL_AGG_TIME_LIMIT_DEF); 3068 3069 link_cmd->sta_id = sta_id; 3070 3071 return link_cmd; 3072} 3073 3074/* 3075 * il4965_add_bssid_station - Add the special IBSS BSSID station 3076 * 3077 * Function sleeps. 3078 */ 3079int 3080il4965_add_bssid_station(struct il_priv *il, const u8 *addr, u8 *sta_id_r) 3081{ 3082 int ret; 3083 u8 sta_id; 3084 struct il_link_quality_cmd *link_cmd; 3085 unsigned long flags; 3086 3087 if (sta_id_r) 3088 *sta_id_r = IL_INVALID_STATION; 3089 3090 ret = il_add_station_common(il, addr, 0, NULL, &sta_id); 3091 if (ret) { 3092 IL_ERR("Unable to add station %pM\n", addr); 3093 return ret; 3094 } 3095 3096 if (sta_id_r) 3097 *sta_id_r = sta_id; 3098 3099 spin_lock_irqsave(&il->sta_lock, flags); 3100 il->stations[sta_id].used |= IL_STA_LOCAL; 3101 spin_unlock_irqrestore(&il->sta_lock, flags); 3102 3103 /* Set up default rate scaling table in device's station table */ 3104 link_cmd = il4965_sta_alloc_lq(il, sta_id); 3105 if (!link_cmd) { 3106 IL_ERR("Unable to initialize rate scaling for station %pM.\n", 3107 addr); 3108 return -ENOMEM; 3109 } 3110 3111 ret = il_send_lq_cmd(il, link_cmd, CMD_SYNC, true); 3112 if (ret) 3113 IL_ERR("Link quality command failed (%d)\n", ret); 3114 3115 spin_lock_irqsave(&il->sta_lock, flags); 3116 il->stations[sta_id].lq = link_cmd; 3117 spin_unlock_irqrestore(&il->sta_lock, flags); 3118 3119 return 0; 3120} 3121 3122static int 3123il4965_static_wepkey_cmd(struct il_priv *il, bool send_if_empty) 3124{ 3125 int i; 3126 u8 buff[sizeof(struct il_wep_cmd) + 3127 sizeof(struct il_wep_key) * WEP_KEYS_MAX]; 3128 struct il_wep_cmd *wep_cmd = (struct il_wep_cmd *)buff; 3129 size_t cmd_size = sizeof(struct il_wep_cmd); 3130 struct il_host_cmd cmd = { 3131 .id = C_WEPKEY, 3132 .data = wep_cmd, 3133 .flags = CMD_SYNC, 3134 }; 3135 bool not_empty = false; 3136 3137 might_sleep(); 3138 3139 memset(wep_cmd, 0, 3140 cmd_size + (sizeof(struct il_wep_key) * WEP_KEYS_MAX)); 3141 3142 for (i = 0; i < WEP_KEYS_MAX; i++) { 3143 u8 key_size = il->_4965.wep_keys[i].key_size; 3144 3145 wep_cmd->key[i].key_idx = i; 3146 if (key_size) { 3147 wep_cmd->key[i].key_offset = i; 3148 not_empty = true; 3149 } else 3150 wep_cmd->key[i].key_offset = WEP_INVALID_OFFSET; 3151 3152 wep_cmd->key[i].key_size = key_size; 3153 memcpy(&wep_cmd->key[i].key[3], il->_4965.wep_keys[i].key, key_size); 3154 } 3155 3156 wep_cmd->global_key_type = WEP_KEY_WEP_TYPE; 3157 wep_cmd->num_keys = WEP_KEYS_MAX; 3158 3159 cmd_size += sizeof(struct il_wep_key) * WEP_KEYS_MAX; 3160 cmd.len = cmd_size; 3161 3162 if (not_empty || send_if_empty) 3163 return il_send_cmd(il, &cmd); 3164 else 3165 return 0; 3166} 3167 3168int 3169il4965_restore_default_wep_keys(struct il_priv *il) 3170{ 3171 lockdep_assert_held(&il->mutex); 3172 3173 return il4965_static_wepkey_cmd(il, false); 3174} 3175 3176int 3177il4965_remove_default_wep_key(struct il_priv *il, 3178 struct ieee80211_key_conf *keyconf) 3179{ 3180 int ret; 3181 int idx = keyconf->keyidx; 3182 3183 lockdep_assert_held(&il->mutex); 3184 3185 D_WEP("Removing default WEP key: idx=%d\n", idx); 3186 3187 memset(&il->_4965.wep_keys[idx], 0, sizeof(struct il_wep_key)); 3188 if (il_is_rfkill(il)) { 3189 D_WEP("Not sending C_WEPKEY command due to RFKILL.\n"); 3190 /* but keys in device are clear anyway so return success */ 3191 return 0; 3192 } 3193 ret = il4965_static_wepkey_cmd(il, 1); 3194 D_WEP("Remove default WEP key: idx=%d ret=%d\n", idx, ret); 3195 3196 return ret; 3197} 3198 3199int 3200il4965_set_default_wep_key(struct il_priv *il, 3201 struct ieee80211_key_conf *keyconf) 3202{ 3203 int ret; 3204 int len = keyconf->keylen; 3205 int idx = keyconf->keyidx; 3206 3207 lockdep_assert_held(&il->mutex); 3208 3209 if (len != WEP_KEY_LEN_128 && len != WEP_KEY_LEN_64) { 3210 D_WEP("Bad WEP key length %d\n", keyconf->keylen); 3211 return -EINVAL; 3212 } 3213 3214 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV; 3215 keyconf->hw_key_idx = HW_KEY_DEFAULT; 3216 il->stations[IL_AP_ID].keyinfo.cipher = keyconf->cipher; 3217 3218 il->_4965.wep_keys[idx].key_size = len; 3219 memcpy(&il->_4965.wep_keys[idx].key, &keyconf->key, len); 3220 3221 ret = il4965_static_wepkey_cmd(il, false); 3222 3223 D_WEP("Set default WEP key: len=%d idx=%d ret=%d\n", len, idx, ret); 3224 return ret; 3225} 3226 3227static int 3228il4965_set_wep_dynamic_key_info(struct il_priv *il, 3229 struct ieee80211_key_conf *keyconf, u8 sta_id) 3230{ 3231 unsigned long flags; 3232 __le16 key_flags = 0; 3233 struct il_addsta_cmd sta_cmd; 3234 3235 lockdep_assert_held(&il->mutex); 3236 3237 keyconf->flags &= ~IEEE80211_KEY_FLAG_GENERATE_IV; 3238 3239 key_flags |= (STA_KEY_FLG_WEP | STA_KEY_FLG_MAP_KEY_MSK); 3240 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); 3241 key_flags &= ~STA_KEY_FLG_INVALID; 3242 3243 if (keyconf->keylen == WEP_KEY_LEN_128) 3244 key_flags |= STA_KEY_FLG_KEY_SIZE_MSK; 3245 3246 if (sta_id == il->hw_params.bcast_id) 3247 key_flags |= STA_KEY_MULTICAST_MSK; 3248 3249 spin_lock_irqsave(&il->sta_lock, flags); 3250 3251 il->stations[sta_id].keyinfo.cipher = keyconf->cipher; 3252 il->stations[sta_id].keyinfo.keylen = keyconf->keylen; 3253 il->stations[sta_id].keyinfo.keyidx = keyconf->keyidx; 3254 3255 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen); 3256 3257 memcpy(&il->stations[sta_id].sta.key.key[3], keyconf->key, 3258 keyconf->keylen); 3259 3260 if ((il->stations[sta_id].sta.key. 3261 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC) 3262 il->stations[sta_id].sta.key.key_offset = 3263 il_get_free_ucode_key_idx(il); 3264 /* else, we are overriding an existing key => no need to allocated room 3265 * in uCode. */ 3266 3267 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET, 3268 "no space for a new key"); 3269 3270 il->stations[sta_id].sta.key.key_flags = key_flags; 3271 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; 3272 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 3273 3274 memcpy(&sta_cmd, &il->stations[sta_id].sta, 3275 sizeof(struct il_addsta_cmd)); 3276 spin_unlock_irqrestore(&il->sta_lock, flags); 3277 3278 return il_send_add_sta(il, &sta_cmd, CMD_SYNC); 3279} 3280 3281static int 3282il4965_set_ccmp_dynamic_key_info(struct il_priv *il, 3283 struct ieee80211_key_conf *keyconf, u8 sta_id) 3284{ 3285 unsigned long flags; 3286 __le16 key_flags = 0; 3287 struct il_addsta_cmd sta_cmd; 3288 3289 lockdep_assert_held(&il->mutex); 3290 3291 key_flags |= (STA_KEY_FLG_CCMP | STA_KEY_FLG_MAP_KEY_MSK); 3292 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); 3293 key_flags &= ~STA_KEY_FLG_INVALID; 3294 3295 if (sta_id == il->hw_params.bcast_id) 3296 key_flags |= STA_KEY_MULTICAST_MSK; 3297 3298 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 3299 3300 spin_lock_irqsave(&il->sta_lock, flags); 3301 il->stations[sta_id].keyinfo.cipher = keyconf->cipher; 3302 il->stations[sta_id].keyinfo.keylen = keyconf->keylen; 3303 3304 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, keyconf->keylen); 3305 3306 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, keyconf->keylen); 3307 3308 if ((il->stations[sta_id].sta.key. 3309 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC) 3310 il->stations[sta_id].sta.key.key_offset = 3311 il_get_free_ucode_key_idx(il); 3312 /* else, we are overriding an existing key => no need to allocated room 3313 * in uCode. */ 3314 3315 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET, 3316 "no space for a new key"); 3317 3318 il->stations[sta_id].sta.key.key_flags = key_flags; 3319 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; 3320 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 3321 3322 memcpy(&sta_cmd, &il->stations[sta_id].sta, 3323 sizeof(struct il_addsta_cmd)); 3324 spin_unlock_irqrestore(&il->sta_lock, flags); 3325 3326 return il_send_add_sta(il, &sta_cmd, CMD_SYNC); 3327} 3328 3329static int 3330il4965_set_tkip_dynamic_key_info(struct il_priv *il, 3331 struct ieee80211_key_conf *keyconf, u8 sta_id) 3332{ 3333 unsigned long flags; 3334 __le16 key_flags = 0; 3335 3336 key_flags |= (STA_KEY_FLG_TKIP | STA_KEY_FLG_MAP_KEY_MSK); 3337 key_flags |= cpu_to_le16(keyconf->keyidx << STA_KEY_FLG_KEYID_POS); 3338 key_flags &= ~STA_KEY_FLG_INVALID; 3339 3340 if (sta_id == il->hw_params.bcast_id) 3341 key_flags |= STA_KEY_MULTICAST_MSK; 3342 3343 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_IV; 3344 keyconf->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC; 3345 3346 spin_lock_irqsave(&il->sta_lock, flags); 3347 3348 il->stations[sta_id].keyinfo.cipher = keyconf->cipher; 3349 il->stations[sta_id].keyinfo.keylen = 16; 3350 3351 if ((il->stations[sta_id].sta.key. 3352 key_flags & STA_KEY_FLG_ENCRYPT_MSK) == STA_KEY_FLG_NO_ENC) 3353 il->stations[sta_id].sta.key.key_offset = 3354 il_get_free_ucode_key_idx(il); 3355 /* else, we are overriding an existing key => no need to allocated room 3356 * in uCode. */ 3357 3358 WARN(il->stations[sta_id].sta.key.key_offset == WEP_INVALID_OFFSET, 3359 "no space for a new key"); 3360 3361 il->stations[sta_id].sta.key.key_flags = key_flags; 3362 3363 /* This copy is acutally not needed: we get the key with each TX */ 3364 memcpy(il->stations[sta_id].keyinfo.key, keyconf->key, 16); 3365 3366 memcpy(il->stations[sta_id].sta.key.key, keyconf->key, 16); 3367 3368 spin_unlock_irqrestore(&il->sta_lock, flags); 3369 3370 return 0; 3371} 3372 3373void 3374il4965_update_tkip_key(struct il_priv *il, struct ieee80211_key_conf *keyconf, 3375 struct ieee80211_sta *sta, u32 iv32, u16 *phase1key) 3376{ 3377 u8 sta_id; 3378 unsigned long flags; 3379 int i; 3380 3381 if (il_scan_cancel(il)) { 3382 /* cancel scan failed, just live w/ bad key and rely 3383 briefly on SW decryption */ 3384 return; 3385 } 3386 3387 sta_id = il_sta_id_or_broadcast(il, sta); 3388 if (sta_id == IL_INVALID_STATION) 3389 return; 3390 3391 spin_lock_irqsave(&il->sta_lock, flags); 3392 3393 il->stations[sta_id].sta.key.tkip_rx_tsc_byte2 = (u8) iv32; 3394 3395 for (i = 0; i < 5; i++) 3396 il->stations[sta_id].sta.key.tkip_rx_ttak[i] = 3397 cpu_to_le16(phase1key[i]); 3398 3399 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; 3400 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 3401 3402 il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC); 3403 3404 spin_unlock_irqrestore(&il->sta_lock, flags); 3405} 3406 3407int 3408il4965_remove_dynamic_key(struct il_priv *il, 3409 struct ieee80211_key_conf *keyconf, u8 sta_id) 3410{ 3411 unsigned long flags; 3412 u16 key_flags; 3413 u8 keyidx; 3414 struct il_addsta_cmd sta_cmd; 3415 3416 lockdep_assert_held(&il->mutex); 3417 3418 il->_4965.key_mapping_keys--; 3419 3420 spin_lock_irqsave(&il->sta_lock, flags); 3421 key_flags = le16_to_cpu(il->stations[sta_id].sta.key.key_flags); 3422 keyidx = (key_flags >> STA_KEY_FLG_KEYID_POS) & 0x3; 3423 3424 D_WEP("Remove dynamic key: idx=%d sta=%d\n", keyconf->keyidx, sta_id); 3425 3426 if (keyconf->keyidx != keyidx) { 3427 /* We need to remove a key with idx different that the one 3428 * in the uCode. This means that the key we need to remove has 3429 * been replaced by another one with different idx. 3430 * Don't do anything and return ok 3431 */ 3432 spin_unlock_irqrestore(&il->sta_lock, flags); 3433 return 0; 3434 } 3435 3436 if (il->stations[sta_id].sta.key.key_flags & STA_KEY_FLG_INVALID) { 3437 IL_WARN("Removing wrong key %d 0x%x\n", keyconf->keyidx, 3438 key_flags); 3439 spin_unlock_irqrestore(&il->sta_lock, flags); 3440 return 0; 3441 } 3442 3443 if (!test_and_clear_bit 3444 (il->stations[sta_id].sta.key.key_offset, &il->ucode_key_table)) 3445 IL_ERR("idx %d not used in uCode key table.\n", 3446 il->stations[sta_id].sta.key.key_offset); 3447 memset(&il->stations[sta_id].keyinfo, 0, sizeof(struct il_hw_key)); 3448 memset(&il->stations[sta_id].sta.key, 0, sizeof(struct il4965_keyinfo)); 3449 il->stations[sta_id].sta.key.key_flags = 3450 STA_KEY_FLG_NO_ENC | STA_KEY_FLG_INVALID; 3451 il->stations[sta_id].sta.key.key_offset = keyconf->hw_key_idx; 3452 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_KEY_MASK; 3453 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 3454 3455 if (il_is_rfkill(il)) { 3456 D_WEP 3457 ("Not sending C_ADD_STA command because RFKILL enabled.\n"); 3458 spin_unlock_irqrestore(&il->sta_lock, flags); 3459 return 0; 3460 } 3461 memcpy(&sta_cmd, &il->stations[sta_id].sta, 3462 sizeof(struct il_addsta_cmd)); 3463 spin_unlock_irqrestore(&il->sta_lock, flags); 3464 3465 return il_send_add_sta(il, &sta_cmd, CMD_SYNC); 3466} 3467 3468int 3469il4965_set_dynamic_key(struct il_priv *il, struct ieee80211_key_conf *keyconf, 3470 u8 sta_id) 3471{ 3472 int ret; 3473 3474 lockdep_assert_held(&il->mutex); 3475 3476 il->_4965.key_mapping_keys++; 3477 keyconf->hw_key_idx = HW_KEY_DYNAMIC; 3478 3479 switch (keyconf->cipher) { 3480 case WLAN_CIPHER_SUITE_CCMP: 3481 ret = 3482 il4965_set_ccmp_dynamic_key_info(il, keyconf, sta_id); 3483 break; 3484 case WLAN_CIPHER_SUITE_TKIP: 3485 ret = 3486 il4965_set_tkip_dynamic_key_info(il, keyconf, sta_id); 3487 break; 3488 case WLAN_CIPHER_SUITE_WEP40: 3489 case WLAN_CIPHER_SUITE_WEP104: 3490 ret = il4965_set_wep_dynamic_key_info(il, keyconf, sta_id); 3491 break; 3492 default: 3493 IL_ERR("Unknown alg: %s cipher = %x\n", __func__, 3494 keyconf->cipher); 3495 ret = -EINVAL; 3496 } 3497 3498 D_WEP("Set dynamic key: cipher=%x len=%d idx=%d sta=%d ret=%d\n", 3499 keyconf->cipher, keyconf->keylen, keyconf->keyidx, sta_id, ret); 3500 3501 return ret; 3502} 3503 3504/* 3505 * il4965_alloc_bcast_station - add broadcast station into driver's station table. 3506 * 3507 * This adds the broadcast station into the driver's station table 3508 * and marks it driver active, so that it will be restored to the 3509 * device at the next best time. 3510 */ 3511int 3512il4965_alloc_bcast_station(struct il_priv *il) 3513{ 3514 struct il_link_quality_cmd *link_cmd; 3515 unsigned long flags; 3516 u8 sta_id; 3517 3518 spin_lock_irqsave(&il->sta_lock, flags); 3519 sta_id = il_prep_station(il, il_bcast_addr, false, NULL); 3520 if (sta_id == IL_INVALID_STATION) { 3521 IL_ERR("Unable to prepare broadcast station\n"); 3522 spin_unlock_irqrestore(&il->sta_lock, flags); 3523 3524 return -EINVAL; 3525 } 3526 3527 il->stations[sta_id].used |= IL_STA_DRIVER_ACTIVE; 3528 il->stations[sta_id].used |= IL_STA_BCAST; 3529 spin_unlock_irqrestore(&il->sta_lock, flags); 3530 3531 link_cmd = il4965_sta_alloc_lq(il, sta_id); 3532 if (!link_cmd) { 3533 IL_ERR 3534 ("Unable to initialize rate scaling for bcast station.\n"); 3535 return -ENOMEM; 3536 } 3537 3538 spin_lock_irqsave(&il->sta_lock, flags); 3539 il->stations[sta_id].lq = link_cmd; 3540 spin_unlock_irqrestore(&il->sta_lock, flags); 3541 3542 return 0; 3543} 3544 3545/* 3546 * il4965_update_bcast_station - update broadcast station's LQ command 3547 * 3548 * Only used by iwl4965. Placed here to have all bcast station management 3549 * code together. 3550 */ 3551static int 3552il4965_update_bcast_station(struct il_priv *il) 3553{ 3554 unsigned long flags; 3555 struct il_link_quality_cmd *link_cmd; 3556 u8 sta_id = il->hw_params.bcast_id; 3557 3558 link_cmd = il4965_sta_alloc_lq(il, sta_id); 3559 if (!link_cmd) { 3560 IL_ERR("Unable to initialize rate scaling for bcast sta.\n"); 3561 return -ENOMEM; 3562 } 3563 3564 spin_lock_irqsave(&il->sta_lock, flags); 3565 if (il->stations[sta_id].lq) 3566 kfree(il->stations[sta_id].lq); 3567 else 3568 D_INFO("Bcast sta rate scaling has not been initialized.\n"); 3569 il->stations[sta_id].lq = link_cmd; 3570 spin_unlock_irqrestore(&il->sta_lock, flags); 3571 3572 return 0; 3573} 3574 3575int 3576il4965_update_bcast_stations(struct il_priv *il) 3577{ 3578 return il4965_update_bcast_station(il); 3579} 3580 3581/* 3582 * il4965_sta_tx_modify_enable_tid - Enable Tx for this TID in station table 3583 */ 3584int 3585il4965_sta_tx_modify_enable_tid(struct il_priv *il, int sta_id, int tid) 3586{ 3587 unsigned long flags; 3588 struct il_addsta_cmd sta_cmd; 3589 3590 lockdep_assert_held(&il->mutex); 3591 3592 /* Remove "disable" flag, to enable Tx for this TID */ 3593 spin_lock_irqsave(&il->sta_lock, flags); 3594 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_TID_DISABLE_TX; 3595 il->stations[sta_id].sta.tid_disable_tx &= cpu_to_le16(~(1 << tid)); 3596 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 3597 memcpy(&sta_cmd, &il->stations[sta_id].sta, 3598 sizeof(struct il_addsta_cmd)); 3599 spin_unlock_irqrestore(&il->sta_lock, flags); 3600 3601 return il_send_add_sta(il, &sta_cmd, CMD_SYNC); 3602} 3603 3604int 3605il4965_sta_rx_agg_start(struct il_priv *il, struct ieee80211_sta *sta, int tid, 3606 u16 ssn) 3607{ 3608 unsigned long flags; 3609 int sta_id; 3610 struct il_addsta_cmd sta_cmd; 3611 3612 lockdep_assert_held(&il->mutex); 3613 3614 sta_id = il_sta_id(sta); 3615 if (sta_id == IL_INVALID_STATION) 3616 return -ENXIO; 3617 3618 spin_lock_irqsave(&il->sta_lock, flags); 3619 il->stations[sta_id].sta.station_flags_msk = 0; 3620 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_ADDBA_TID_MSK; 3621 il->stations[sta_id].sta.add_immediate_ba_tid = (u8) tid; 3622 il->stations[sta_id].sta.add_immediate_ba_ssn = cpu_to_le16(ssn); 3623 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 3624 memcpy(&sta_cmd, &il->stations[sta_id].sta, 3625 sizeof(struct il_addsta_cmd)); 3626 spin_unlock_irqrestore(&il->sta_lock, flags); 3627 3628 return il_send_add_sta(il, &sta_cmd, CMD_SYNC); 3629} 3630 3631int 3632il4965_sta_rx_agg_stop(struct il_priv *il, struct ieee80211_sta *sta, int tid) 3633{ 3634 unsigned long flags; 3635 int sta_id; 3636 struct il_addsta_cmd sta_cmd; 3637 3638 lockdep_assert_held(&il->mutex); 3639 3640 sta_id = il_sta_id(sta); 3641 if (sta_id == IL_INVALID_STATION) { 3642 IL_ERR("Invalid station for AGG tid %d\n", tid); 3643 return -ENXIO; 3644 } 3645 3646 spin_lock_irqsave(&il->sta_lock, flags); 3647 il->stations[sta_id].sta.station_flags_msk = 0; 3648 il->stations[sta_id].sta.sta.modify_mask = STA_MODIFY_DELBA_TID_MSK; 3649 il->stations[sta_id].sta.remove_immediate_ba_tid = (u8) tid; 3650 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 3651 memcpy(&sta_cmd, &il->stations[sta_id].sta, 3652 sizeof(struct il_addsta_cmd)); 3653 spin_unlock_irqrestore(&il->sta_lock, flags); 3654 3655 return il_send_add_sta(il, &sta_cmd, CMD_SYNC); 3656} 3657 3658void 3659il4965_sta_modify_sleep_tx_count(struct il_priv *il, int sta_id, int cnt) 3660{ 3661 unsigned long flags; 3662 3663 spin_lock_irqsave(&il->sta_lock, flags); 3664 il->stations[sta_id].sta.station_flags |= STA_FLG_PWR_SAVE_MSK; 3665 il->stations[sta_id].sta.station_flags_msk = STA_FLG_PWR_SAVE_MSK; 3666 il->stations[sta_id].sta.sta.modify_mask = 3667 STA_MODIFY_SLEEP_TX_COUNT_MSK; 3668 il->stations[sta_id].sta.sleep_tx_count = cpu_to_le16(cnt); 3669 il->stations[sta_id].sta.mode = STA_CONTROL_MODIFY_MSK; 3670 il_send_add_sta(il, &il->stations[sta_id].sta, CMD_ASYNC); 3671 spin_unlock_irqrestore(&il->sta_lock, flags); 3672 3673} 3674 3675void 3676il4965_update_chain_flags(struct il_priv *il) 3677{ 3678 if (il->ops->set_rxon_chain) { 3679 il->ops->set_rxon_chain(il); 3680 if (il->active.rx_chain != il->staging.rx_chain) 3681 il_commit_rxon(il); 3682 } 3683} 3684 3685static void 3686il4965_clear_free_frames(struct il_priv *il) 3687{ 3688 struct list_head *element; 3689 3690 D_INFO("%d frames on pre-allocated heap on clear.\n", il->frames_count); 3691 3692 while (!list_empty(&il->free_frames)) { 3693 element = il->free_frames.next; 3694 list_del(element); 3695 kfree(list_entry(element, struct il_frame, list)); 3696 il->frames_count--; 3697 } 3698 3699 if (il->frames_count) { 3700 IL_WARN("%d frames still in use. Did we lose one?\n", 3701 il->frames_count); 3702 il->frames_count = 0; 3703 } 3704} 3705 3706static struct il_frame * 3707il4965_get_free_frame(struct il_priv *il) 3708{ 3709 struct il_frame *frame; 3710 struct list_head *element; 3711 if (list_empty(&il->free_frames)) { 3712 frame = kzalloc(sizeof(*frame), GFP_KERNEL); 3713 if (!frame) { 3714 IL_ERR("Could not allocate frame!\n"); 3715 return NULL; 3716 } 3717 3718 il->frames_count++; 3719 return frame; 3720 } 3721 3722 element = il->free_frames.next; 3723 list_del(element); 3724 return list_entry(element, struct il_frame, list); 3725} 3726 3727static void 3728il4965_free_frame(struct il_priv *il, struct il_frame *frame) 3729{ 3730 memset(frame, 0, sizeof(*frame)); 3731 list_add(&frame->list, &il->free_frames); 3732} 3733 3734static u32 3735il4965_fill_beacon_frame(struct il_priv *il, struct ieee80211_hdr *hdr, 3736 int left) 3737{ 3738 lockdep_assert_held(&il->mutex); 3739 3740 if (!il->beacon_skb) 3741 return 0; 3742 3743 if (il->beacon_skb->len > left) 3744 return 0; 3745 3746 memcpy(hdr, il->beacon_skb->data, il->beacon_skb->len); 3747 3748 return il->beacon_skb->len; 3749} 3750 3751/* Parse the beacon frame to find the TIM element and set tim_idx & tim_size */ 3752static void 3753il4965_set_beacon_tim(struct il_priv *il, 3754 struct il_tx_beacon_cmd *tx_beacon_cmd, u8 * beacon, 3755 u32 frame_size) 3756{ 3757 u16 tim_idx; 3758 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)beacon; 3759 3760 /* 3761 * The idx is relative to frame start but we start looking at the 3762 * variable-length part of the beacon. 3763 */ 3764 tim_idx = mgmt->u.beacon.variable - beacon; 3765 3766 /* Parse variable-length elements of beacon to find WLAN_EID_TIM */ 3767 while ((tim_idx < (frame_size - 2)) && 3768 (beacon[tim_idx] != WLAN_EID_TIM)) 3769 tim_idx += beacon[tim_idx + 1] + 2; 3770 3771 /* If TIM field was found, set variables */ 3772 if ((tim_idx < (frame_size - 1)) && (beacon[tim_idx] == WLAN_EID_TIM)) { 3773 tx_beacon_cmd->tim_idx = cpu_to_le16(tim_idx); 3774 tx_beacon_cmd->tim_size = beacon[tim_idx + 1]; 3775 } else 3776 IL_WARN("Unable to find TIM Element in beacon\n"); 3777} 3778 3779static unsigned int 3780il4965_hw_get_beacon_cmd(struct il_priv *il, struct il_frame *frame) 3781{ 3782 struct il_tx_beacon_cmd *tx_beacon_cmd; 3783 u32 frame_size; 3784 u32 rate_flags; 3785 u32 rate; 3786 /* 3787 * We have to set up the TX command, the TX Beacon command, and the 3788 * beacon contents. 3789 */ 3790 3791 lockdep_assert_held(&il->mutex); 3792 3793 if (!il->beacon_enabled) { 3794 IL_ERR("Trying to build beacon without beaconing enabled\n"); 3795 return 0; 3796 } 3797 3798 /* Initialize memory */ 3799 tx_beacon_cmd = &frame->u.beacon; 3800 memset(tx_beacon_cmd, 0, sizeof(*tx_beacon_cmd)); 3801 3802 /* Set up TX beacon contents */ 3803 frame_size = 3804 il4965_fill_beacon_frame(il, tx_beacon_cmd->frame, 3805 sizeof(frame->u) - sizeof(*tx_beacon_cmd)); 3806 if (WARN_ON_ONCE(frame_size > MAX_MPDU_SIZE)) 3807 return 0; 3808 if (!frame_size) 3809 return 0; 3810 3811 /* Set up TX command fields */ 3812 tx_beacon_cmd->tx.len = cpu_to_le16((u16) frame_size); 3813 tx_beacon_cmd->tx.sta_id = il->hw_params.bcast_id; 3814 tx_beacon_cmd->tx.stop_time.life_time = TX_CMD_LIFE_TIME_INFINITE; 3815 tx_beacon_cmd->tx.tx_flags = 3816 TX_CMD_FLG_SEQ_CTL_MSK | TX_CMD_FLG_TSF_MSK | 3817 TX_CMD_FLG_STA_RATE_MSK; 3818 3819 /* Set up TX beacon command fields */ 3820 il4965_set_beacon_tim(il, tx_beacon_cmd, (u8 *) tx_beacon_cmd->frame, 3821 frame_size); 3822 3823 /* Set up packet rate and flags */ 3824 rate = il_get_lowest_plcp(il); 3825 il4965_toggle_tx_ant(il, &il->mgmt_tx_ant, il->hw_params.valid_tx_ant); 3826 rate_flags = BIT(il->mgmt_tx_ant) << RATE_MCS_ANT_POS; 3827 if ((rate >= IL_FIRST_CCK_RATE) && (rate <= IL_LAST_CCK_RATE)) 3828 rate_flags |= RATE_MCS_CCK_MSK; 3829 tx_beacon_cmd->tx.rate_n_flags = cpu_to_le32(rate | rate_flags); 3830 3831 return sizeof(*tx_beacon_cmd) + frame_size; 3832} 3833 3834int 3835il4965_send_beacon_cmd(struct il_priv *il) 3836{ 3837 struct il_frame *frame; 3838 unsigned int frame_size; 3839 int rc; 3840 3841 frame = il4965_get_free_frame(il); 3842 if (!frame) { 3843 IL_ERR("Could not obtain free frame buffer for beacon " 3844 "command.\n"); 3845 return -ENOMEM; 3846 } 3847 3848 frame_size = il4965_hw_get_beacon_cmd(il, frame); 3849 if (!frame_size) { 3850 IL_ERR("Error configuring the beacon command\n"); 3851 il4965_free_frame(il, frame); 3852 return -EINVAL; 3853 } 3854 3855 rc = il_send_cmd_pdu(il, C_TX_BEACON, frame_size, &frame->u.cmd[0]); 3856 3857 il4965_free_frame(il, frame); 3858 3859 return rc; 3860} 3861 3862static inline dma_addr_t 3863il4965_tfd_tb_get_addr(struct il_tfd *tfd, u8 idx) 3864{ 3865 struct il_tfd_tb *tb = &tfd->tbs[idx]; 3866 3867 dma_addr_t addr = get_unaligned_le32(&tb->lo); 3868 if (sizeof(dma_addr_t) > sizeof(u32)) 3869 addr |= 3870 ((dma_addr_t) (le16_to_cpu(tb->hi_n_len) & 0xF) << 16) << 3871 16; 3872 3873 return addr; 3874} 3875 3876static inline u16 3877il4965_tfd_tb_get_len(struct il_tfd *tfd, u8 idx) 3878{ 3879 struct il_tfd_tb *tb = &tfd->tbs[idx]; 3880 3881 return le16_to_cpu(tb->hi_n_len) >> 4; 3882} 3883 3884static inline void 3885il4965_tfd_set_tb(struct il_tfd *tfd, u8 idx, dma_addr_t addr, u16 len) 3886{ 3887 struct il_tfd_tb *tb = &tfd->tbs[idx]; 3888 u16 hi_n_len = len << 4; 3889 3890 put_unaligned_le32(addr, &tb->lo); 3891 if (sizeof(dma_addr_t) > sizeof(u32)) 3892 hi_n_len |= ((addr >> 16) >> 16) & 0xF; 3893 3894 tb->hi_n_len = cpu_to_le16(hi_n_len); 3895 3896 tfd->num_tbs = idx + 1; 3897} 3898 3899static inline u8 3900il4965_tfd_get_num_tbs(struct il_tfd *tfd) 3901{ 3902 return tfd->num_tbs & 0x1f; 3903} 3904 3905/* 3906 * il4965_hw_txq_free_tfd - Free all chunks referenced by TFD [txq->q.read_ptr] 3907 * 3908 * Does NOT advance any TFD circular buffer read/write idxes 3909 * Does NOT free the TFD itself (which is within circular buffer) 3910 */ 3911void 3912il4965_hw_txq_free_tfd(struct il_priv *il, struct il_tx_queue *txq) 3913{ 3914 struct il_tfd *tfd_tmp = (struct il_tfd *)txq->tfds; 3915 struct il_tfd *tfd; 3916 struct pci_dev *dev = il->pci_dev; 3917 int idx = txq->q.read_ptr; 3918 int i; 3919 int num_tbs; 3920 3921 tfd = &tfd_tmp[idx]; 3922 3923 /* Sanity check on number of chunks */ 3924 num_tbs = il4965_tfd_get_num_tbs(tfd); 3925 3926 if (num_tbs >= IL_NUM_OF_TBS) { 3927 IL_ERR("Too many chunks: %i\n", num_tbs); 3928 /* @todo issue fatal error, it is quite serious situation */ 3929 return; 3930 } 3931 3932 /* Unmap tx_cmd */ 3933 if (num_tbs) 3934 dma_unmap_single(&dev->dev, 3935 dma_unmap_addr(&txq->meta[idx], mapping), 3936 dma_unmap_len(&txq->meta[idx], len), 3937 DMA_BIDIRECTIONAL); 3938 3939 /* Unmap chunks, if any. */ 3940 for (i = 1; i < num_tbs; i++) 3941 dma_unmap_single(&dev->dev, il4965_tfd_tb_get_addr(tfd, i), 3942 il4965_tfd_tb_get_len(tfd, i), DMA_TO_DEVICE); 3943 3944 /* free SKB */ 3945 if (txq->skbs) { 3946 struct sk_buff *skb = txq->skbs[txq->q.read_ptr]; 3947 3948 /* can be called from irqs-disabled context */ 3949 if (skb) { 3950 dev_kfree_skb_any(skb); 3951 txq->skbs[txq->q.read_ptr] = NULL; 3952 } 3953 } 3954} 3955 3956int 3957il4965_hw_txq_attach_buf_to_tfd(struct il_priv *il, struct il_tx_queue *txq, 3958 dma_addr_t addr, u16 len, u8 reset, u8 pad) 3959{ 3960 struct il_queue *q; 3961 struct il_tfd *tfd, *tfd_tmp; 3962 u32 num_tbs; 3963 3964 q = &txq->q; 3965 tfd_tmp = (struct il_tfd *)txq->tfds; 3966 tfd = &tfd_tmp[q->write_ptr]; 3967 3968 if (reset) 3969 memset(tfd, 0, sizeof(*tfd)); 3970 3971 num_tbs = il4965_tfd_get_num_tbs(tfd); 3972 3973 /* Each TFD can point to a maximum 20 Tx buffers */ 3974 if (num_tbs >= IL_NUM_OF_TBS) { 3975 IL_ERR("Error can not send more than %d chunks\n", 3976 IL_NUM_OF_TBS); 3977 return -EINVAL; 3978 } 3979 3980 BUG_ON(addr & ~DMA_BIT_MASK(36)); 3981 if (unlikely(addr & ~IL_TX_DMA_MASK)) 3982 IL_ERR("Unaligned address = %llx\n", (unsigned long long)addr); 3983 3984 il4965_tfd_set_tb(tfd, num_tbs, addr, len); 3985 3986 return 0; 3987} 3988 3989/* 3990 * Tell nic where to find circular buffer of Tx Frame Descriptors for 3991 * given Tx queue, and enable the DMA channel used for that queue. 3992 * 3993 * 4965 supports up to 16 Tx queues in DRAM, mapped to up to 8 Tx DMA 3994 * channels supported in hardware. 3995 */ 3996int 3997il4965_hw_tx_queue_init(struct il_priv *il, struct il_tx_queue *txq) 3998{ 3999 int txq_id = txq->q.id; 4000 4001 /* Circular buffer (TFD queue in DRAM) physical base address */ 4002 il_wr(il, FH49_MEM_CBBC_QUEUE(txq_id), txq->q.dma_addr >> 8); 4003 4004 return 0; 4005} 4006 4007/****************************************************************************** 4008 * 4009 * Generic RX handler implementations 4010 * 4011 ******************************************************************************/ 4012static void 4013il4965_hdl_alive(struct il_priv *il, struct il_rx_buf *rxb) 4014{ 4015 struct il_rx_pkt *pkt = rxb_addr(rxb); 4016 struct il_alive_resp *palive; 4017 struct delayed_work *pwork; 4018 4019 palive = &pkt->u.alive_frame; 4020 4021 D_INFO("Alive ucode status 0x%08X revision " "0x%01X 0x%01X\n", 4022 palive->is_valid, palive->ver_type, palive->ver_subtype); 4023 4024 if (palive->ver_subtype == INITIALIZE_SUBTYPE) { 4025 D_INFO("Initialization Alive received.\n"); 4026 memcpy(&il->card_alive_init, &pkt->u.raw, 4027 sizeof(struct il_init_alive_resp)); 4028 pwork = &il->init_alive_start; 4029 } else { 4030 D_INFO("Runtime Alive received.\n"); 4031 memcpy(&il->card_alive, &pkt->u.alive_frame, 4032 sizeof(struct il_alive_resp)); 4033 pwork = &il->alive_start; 4034 } 4035 4036 /* We delay the ALIVE response by 5ms to 4037 * give the HW RF Kill time to activate... */ 4038 if (palive->is_valid == UCODE_VALID_OK) 4039 queue_delayed_work(il->workqueue, pwork, msecs_to_jiffies(5)); 4040 else 4041 IL_WARN("uCode did not respond OK.\n"); 4042} 4043 4044/* 4045 * il4965_bg_stats_periodic - Timer callback to queue stats 4046 * 4047 * This callback is provided in order to send a stats request. 4048 * 4049 * This timer function is continually reset to execute within 4050 * 60 seconds since the last N_STATS was received. We need to 4051 * ensure we receive the stats in order to update the temperature 4052 * used for calibrating the TXPOWER. 4053 */ 4054static void 4055il4965_bg_stats_periodic(struct timer_list *t) 4056{ 4057 struct il_priv *il = timer_container_of(il, t, stats_periodic); 4058 4059 if (test_bit(S_EXIT_PENDING, &il->status)) 4060 return; 4061 4062 /* dont send host command if rf-kill is on */ 4063 if (!il_is_ready_rf(il)) 4064 return; 4065 4066 il_send_stats_request(il, CMD_ASYNC, false); 4067} 4068 4069static void 4070il4965_hdl_beacon(struct il_priv *il, struct il_rx_buf *rxb) 4071{ 4072 struct il_rx_pkt *pkt = rxb_addr(rxb); 4073 struct il4965_beacon_notif *beacon = 4074 (struct il4965_beacon_notif *)pkt->u.raw; 4075#ifdef CONFIG_IWLEGACY_DEBUG 4076 u8 rate = il4965_hw_get_rate(beacon->beacon_notify_hdr.rate_n_flags); 4077 4078 D_RX("beacon status %x retries %d iss %d tsf:0x%.8x%.8x rate %d\n", 4079 le32_to_cpu(beacon->beacon_notify_hdr.u.status) & TX_STATUS_MSK, 4080 beacon->beacon_notify_hdr.failure_frame, 4081 le32_to_cpu(beacon->ibss_mgr_status), 4082 le32_to_cpu(beacon->high_tsf), le32_to_cpu(beacon->low_tsf), rate); 4083#endif 4084 il->ibss_manager = le32_to_cpu(beacon->ibss_mgr_status); 4085} 4086 4087static void 4088il4965_perform_ct_kill_task(struct il_priv *il) 4089{ 4090 unsigned long flags; 4091 4092 D_POWER("Stop all queues\n"); 4093 4094 if (il->mac80211_registered) 4095 ieee80211_stop_queues(il->hw); 4096 4097 _il_wr(il, CSR_UCODE_DRV_GP1_SET, 4098 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); 4099 _il_rd(il, CSR_UCODE_DRV_GP1); 4100 4101 spin_lock_irqsave(&il->reg_lock, flags); 4102 if (likely(_il_grab_nic_access(il))) 4103 _il_release_nic_access(il); 4104 spin_unlock_irqrestore(&il->reg_lock, flags); 4105} 4106 4107/* Handle notification from uCode that card's power state is changing 4108 * due to software, hardware, or critical temperature RFKILL */ 4109static void 4110il4965_hdl_card_state(struct il_priv *il, struct il_rx_buf *rxb) 4111{ 4112 struct il_rx_pkt *pkt = rxb_addr(rxb); 4113 u32 flags = le32_to_cpu(pkt->u.card_state_notif.flags); 4114 unsigned long status = il->status; 4115 4116 D_RF_KILL("Card state received: HW:%s SW:%s CT:%s\n", 4117 (flags & HW_CARD_DISABLED) ? "Kill" : "On", 4118 (flags & SW_CARD_DISABLED) ? "Kill" : "On", 4119 (flags & CT_CARD_DISABLED) ? "Reached" : "Not reached"); 4120 4121 if (flags & (SW_CARD_DISABLED | HW_CARD_DISABLED | CT_CARD_DISABLED)) { 4122 4123 _il_wr(il, CSR_UCODE_DRV_GP1_SET, 4124 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 4125 4126 il_wr(il, HBUS_TARG_MBX_C, HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); 4127 4128 if (!(flags & RXON_CARD_DISABLED)) { 4129 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, 4130 CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 4131 il_wr(il, HBUS_TARG_MBX_C, 4132 HBUS_TARG_MBX_C_REG_BIT_CMD_BLOCKED); 4133 } 4134 } 4135 4136 if (flags & CT_CARD_DISABLED) 4137 il4965_perform_ct_kill_task(il); 4138 4139 if (flags & HW_CARD_DISABLED) 4140 set_bit(S_RFKILL, &il->status); 4141 else 4142 clear_bit(S_RFKILL, &il->status); 4143 4144 if (!(flags & RXON_CARD_DISABLED)) 4145 il_scan_cancel(il); 4146 4147 if ((test_bit(S_RFKILL, &status) != 4148 test_bit(S_RFKILL, &il->status))) 4149 wiphy_rfkill_set_hw_state(il->hw->wiphy, 4150 test_bit(S_RFKILL, &il->status)); 4151 else 4152 wake_up(&il->wait_command_queue); 4153} 4154 4155/* 4156 * il4965_setup_handlers - Initialize Rx handler callbacks 4157 * 4158 * Setup the RX handlers for each of the reply types sent from the uCode 4159 * to the host. 4160 * 4161 * This function chains into the hardware specific files for them to setup 4162 * any hardware specific handlers as well. 4163 */ 4164static void 4165il4965_setup_handlers(struct il_priv *il) 4166{ 4167 il->handlers[N_ALIVE] = il4965_hdl_alive; 4168 il->handlers[N_ERROR] = il_hdl_error; 4169 il->handlers[N_CHANNEL_SWITCH] = il_hdl_csa; 4170 il->handlers[N_SPECTRUM_MEASUREMENT] = il_hdl_spectrum_measurement; 4171 il->handlers[N_PM_SLEEP] = il_hdl_pm_sleep; 4172 il->handlers[N_PM_DEBUG_STATS] = il_hdl_pm_debug_stats; 4173 il->handlers[N_BEACON] = il4965_hdl_beacon; 4174 4175 /* 4176 * The same handler is used for both the REPLY to a discrete 4177 * stats request from the host as well as for the periodic 4178 * stats notifications (after received beacons) from the uCode. 4179 */ 4180 il->handlers[C_STATS] = il4965_hdl_c_stats; 4181 il->handlers[N_STATS] = il4965_hdl_stats; 4182 4183 il_setup_rx_scan_handlers(il); 4184 4185 /* status change handler */ 4186 il->handlers[N_CARD_STATE] = il4965_hdl_card_state; 4187 4188 il->handlers[N_MISSED_BEACONS] = il4965_hdl_missed_beacon; 4189 /* Rx handlers */ 4190 il->handlers[N_RX_PHY] = il4965_hdl_rx_phy; 4191 il->handlers[N_RX_MPDU] = il4965_hdl_rx; 4192 il->handlers[N_RX] = il4965_hdl_rx; 4193 /* block ack */ 4194 il->handlers[N_COMPRESSED_BA] = il4965_hdl_compressed_ba; 4195 /* Tx response */ 4196 il->handlers[C_TX] = il4965_hdl_tx; 4197} 4198 4199/* 4200 * il4965_rx_handle - Main entry function for receiving responses from uCode 4201 * 4202 * Uses the il->handlers callback function array to invoke 4203 * the appropriate handlers, including command responses, 4204 * frame-received notifications, and other notifications. 4205 */ 4206void 4207il4965_rx_handle(struct il_priv *il) 4208{ 4209 struct il_rx_buf *rxb; 4210 struct il_rx_pkt *pkt; 4211 struct il_rx_queue *rxq = &il->rxq; 4212 u32 r, i; 4213 int reclaim; 4214 unsigned long flags; 4215 u8 fill_rx = 0; 4216 u32 count = 8; 4217 int total_empty; 4218 4219 /* uCode's read idx (stored in shared DRAM) indicates the last Rx 4220 * buffer that the driver may process (last buffer filled by ucode). */ 4221 r = le16_to_cpu(rxq->rb_stts->closed_rb_num) & 0x0FFF; 4222 i = rxq->read; 4223 4224 /* Rx interrupt, but nothing sent from uCode */ 4225 if (i == r) 4226 D_RX("r = %d, i = %d\n", r, i); 4227 4228 /* calculate total frames need to be restock after handling RX */ 4229 total_empty = r - rxq->write_actual; 4230 if (total_empty < 0) 4231 total_empty += RX_QUEUE_SIZE; 4232 4233 if (total_empty > (RX_QUEUE_SIZE / 2)) 4234 fill_rx = 1; 4235 4236 while (i != r) { 4237 rxb = rxq->queue[i]; 4238 4239 /* If an RXB doesn't have a Rx queue slot associated with it, 4240 * then a bug has been introduced in the queue refilling 4241 * routines -- catch it here */ 4242 BUG_ON(rxb == NULL); 4243 4244 rxq->queue[i] = NULL; 4245 4246 dma_unmap_page(&il->pci_dev->dev, rxb->page_dma, 4247 PAGE_SIZE << il->hw_params.rx_page_order, 4248 DMA_FROM_DEVICE); 4249 pkt = rxb_addr(rxb); 4250 reclaim = il_need_reclaim(il, pkt); 4251 4252 /* Based on type of command response or notification, 4253 * handle those that need handling via function in 4254 * handlers table. See il4965_setup_handlers() */ 4255 if (il->handlers[pkt->hdr.cmd]) { 4256 D_RX("r = %d, i = %d, %s, 0x%02x\n", r, i, 4257 il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); 4258 il->isr_stats.handlers[pkt->hdr.cmd]++; 4259 il->handlers[pkt->hdr.cmd] (il, rxb); 4260 } else { 4261 /* No handling needed */ 4262 D_RX("r %d i %d No handler needed for %s, 0x%02x\n", r, 4263 i, il_get_cmd_string(pkt->hdr.cmd), pkt->hdr.cmd); 4264 } 4265 4266 /* 4267 * XXX: After here, we should always check rxb->page 4268 * against NULL before touching it or its virtual 4269 * memory (pkt). Because some handler might have 4270 * already taken or freed the pages. 4271 */ 4272 4273 if (reclaim) { 4274 /* Invoke any callbacks, transfer the buffer to caller, 4275 * and fire off the (possibly) blocking il_send_cmd() 4276 * as we reclaim the driver command queue */ 4277 if (rxb->page) 4278 il_tx_cmd_complete(il, rxb); 4279 else 4280 IL_WARN("Claim null rxb?\n"); 4281 } 4282 4283 /* Reuse the page if possible. For notification packets and 4284 * SKBs that fail to Rx correctly, add them back into the 4285 * rx_free list for reuse later. */ 4286 spin_lock_irqsave(&rxq->lock, flags); 4287 if (rxb->page != NULL) { 4288 rxb->page_dma = 4289 dma_map_page(&il->pci_dev->dev, rxb->page, 0, 4290 PAGE_SIZE << il->hw_params.rx_page_order, 4291 DMA_FROM_DEVICE); 4292 4293 if (unlikely(dma_mapping_error(&il->pci_dev->dev, 4294 rxb->page_dma))) { 4295 __il_free_pages(il, rxb->page); 4296 rxb->page = NULL; 4297 list_add_tail(&rxb->list, &rxq->rx_used); 4298 } else { 4299 list_add_tail(&rxb->list, &rxq->rx_free); 4300 rxq->free_count++; 4301 } 4302 } else 4303 list_add_tail(&rxb->list, &rxq->rx_used); 4304 4305 spin_unlock_irqrestore(&rxq->lock, flags); 4306 4307 i = (i + 1) & RX_QUEUE_MASK; 4308 /* If there are a lot of unused frames, 4309 * restock the Rx queue so ucode wont assert. */ 4310 if (fill_rx) { 4311 count++; 4312 if (count >= 8) { 4313 rxq->read = i; 4314 il4965_rx_replenish_now(il); 4315 count = 0; 4316 } 4317 } 4318 } 4319 4320 /* Backtrack one entry */ 4321 rxq->read = i; 4322 if (fill_rx) 4323 il4965_rx_replenish_now(il); 4324 else 4325 il4965_rx_queue_restock(il); 4326} 4327 4328/* call this function to flush any scheduled tasklet */ 4329static inline void 4330il4965_synchronize_irq(struct il_priv *il) 4331{ 4332 /* wait to make sure we flush pending tasklet */ 4333 synchronize_irq(il->pci_dev->irq); 4334 tasklet_kill(&il->irq_tasklet); 4335} 4336 4337static void 4338il4965_irq_tasklet(struct tasklet_struct *t) 4339{ 4340 struct il_priv *il = from_tasklet(il, t, irq_tasklet); 4341 u32 inta, handled = 0; 4342 u32 inta_fh; 4343 unsigned long flags; 4344 u32 i; 4345#ifdef CONFIG_IWLEGACY_DEBUG 4346 u32 inta_mask; 4347#endif 4348 4349 spin_lock_irqsave(&il->lock, flags); 4350 4351 /* Ack/clear/reset pending uCode interrupts. 4352 * Note: Some bits in CSR_INT are "OR" of bits in CSR_FH_INT_STATUS, 4353 * and will clear only when CSR_FH_INT_STATUS gets cleared. */ 4354 inta = _il_rd(il, CSR_INT); 4355 _il_wr(il, CSR_INT, inta); 4356 4357 /* Ack/clear/reset pending flow-handler (DMA) interrupts. 4358 * Any new interrupts that happen after this, either while we're 4359 * in this tasklet, or later, will show up in next ISR/tasklet. */ 4360 inta_fh = _il_rd(il, CSR_FH_INT_STATUS); 4361 _il_wr(il, CSR_FH_INT_STATUS, inta_fh); 4362 4363#ifdef CONFIG_IWLEGACY_DEBUG 4364 if (il_get_debug_level(il) & IL_DL_ISR) { 4365 /* just for debug */ 4366 inta_mask = _il_rd(il, CSR_INT_MASK); 4367 D_ISR("inta 0x%08x, enabled 0x%08x, fh 0x%08x\n", inta, 4368 inta_mask, inta_fh); 4369 } 4370#endif 4371 4372 spin_unlock_irqrestore(&il->lock, flags); 4373 4374 /* Since CSR_INT and CSR_FH_INT_STATUS reads and clears are not 4375 * atomic, make sure that inta covers all the interrupts that 4376 * we've discovered, even if FH interrupt came in just after 4377 * reading CSR_INT. */ 4378 if (inta_fh & CSR49_FH_INT_RX_MASK) 4379 inta |= CSR_INT_BIT_FH_RX; 4380 if (inta_fh & CSR49_FH_INT_TX_MASK) 4381 inta |= CSR_INT_BIT_FH_TX; 4382 4383 /* Now service all interrupt bits discovered above. */ 4384 if (inta & CSR_INT_BIT_HW_ERR) { 4385 IL_ERR("Hardware error detected. Restarting.\n"); 4386 4387 /* Tell the device to stop sending interrupts */ 4388 il_disable_interrupts(il); 4389 4390 il->isr_stats.hw++; 4391 il_irq_handle_error(il); 4392 4393 handled |= CSR_INT_BIT_HW_ERR; 4394 4395 return; 4396 } 4397#ifdef CONFIG_IWLEGACY_DEBUG 4398 if (il_get_debug_level(il) & (IL_DL_ISR)) { 4399 /* NIC fires this, but we don't use it, redundant with WAKEUP */ 4400 if (inta & CSR_INT_BIT_SCD) { 4401 D_ISR("Scheduler finished to transmit " 4402 "the frame/frames.\n"); 4403 il->isr_stats.sch++; 4404 } 4405 4406 /* Alive notification via Rx interrupt will do the real work */ 4407 if (inta & CSR_INT_BIT_ALIVE) { 4408 D_ISR("Alive interrupt\n"); 4409 il->isr_stats.alive++; 4410 } 4411 } 4412#endif 4413 /* Safely ignore these bits for debug checks below */ 4414 inta &= ~(CSR_INT_BIT_SCD | CSR_INT_BIT_ALIVE); 4415 4416 /* HW RF KILL switch toggled */ 4417 if (inta & CSR_INT_BIT_RF_KILL) { 4418 int hw_rf_kill = 0; 4419 4420 if (!(_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW)) 4421 hw_rf_kill = 1; 4422 4423 IL_WARN("RF_KILL bit toggled to %s.\n", 4424 hw_rf_kill ? "disable radio" : "enable radio"); 4425 4426 il->isr_stats.rfkill++; 4427 4428 /* driver only loads ucode once setting the interface up. 4429 * the driver allows loading the ucode even if the radio 4430 * is killed. Hence update the killswitch state here. The 4431 * rfkill handler will care about restarting if needed. 4432 */ 4433 if (hw_rf_kill) { 4434 set_bit(S_RFKILL, &il->status); 4435 } else { 4436 clear_bit(S_RFKILL, &il->status); 4437 il_force_reset(il, true); 4438 } 4439 wiphy_rfkill_set_hw_state(il->hw->wiphy, hw_rf_kill); 4440 4441 handled |= CSR_INT_BIT_RF_KILL; 4442 } 4443 4444 /* Chip got too hot and stopped itself */ 4445 if (inta & CSR_INT_BIT_CT_KILL) { 4446 IL_ERR("Microcode CT kill error detected.\n"); 4447 il->isr_stats.ctkill++; 4448 handled |= CSR_INT_BIT_CT_KILL; 4449 } 4450 4451 /* Error detected by uCode */ 4452 if (inta & CSR_INT_BIT_SW_ERR) { 4453 IL_ERR("Microcode SW error detected. " " Restarting 0x%X.\n", 4454 inta); 4455 il->isr_stats.sw++; 4456 il_irq_handle_error(il); 4457 handled |= CSR_INT_BIT_SW_ERR; 4458 } 4459 4460 /* 4461 * uCode wakes up after power-down sleep. 4462 * Tell device about any new tx or host commands enqueued, 4463 * and about any Rx buffers made available while asleep. 4464 */ 4465 if (inta & CSR_INT_BIT_WAKEUP) { 4466 D_ISR("Wakeup interrupt\n"); 4467 il_rx_queue_update_write_ptr(il, &il->rxq); 4468 for (i = 0; i < il->hw_params.max_txq_num; i++) 4469 il_txq_update_write_ptr(il, &il->txq[i]); 4470 il->isr_stats.wakeup++; 4471 handled |= CSR_INT_BIT_WAKEUP; 4472 } 4473 4474 /* All uCode command responses, including Tx command responses, 4475 * Rx "responses" (frame-received notification), and other 4476 * notifications from uCode come through here*/ 4477 if (inta & (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX)) { 4478 il4965_rx_handle(il); 4479 il->isr_stats.rx++; 4480 handled |= (CSR_INT_BIT_FH_RX | CSR_INT_BIT_SW_RX); 4481 } 4482 4483 /* This "Tx" DMA channel is used only for loading uCode */ 4484 if (inta & CSR_INT_BIT_FH_TX) { 4485 D_ISR("uCode load interrupt\n"); 4486 il->isr_stats.tx++; 4487 handled |= CSR_INT_BIT_FH_TX; 4488 /* Wake up uCode load routine, now that load is complete */ 4489 il->ucode_write_complete = 1; 4490 wake_up(&il->wait_command_queue); 4491 } 4492 4493 if (inta & ~handled) { 4494 IL_ERR("Unhandled INTA bits 0x%08x\n", inta & ~handled); 4495 il->isr_stats.unhandled++; 4496 } 4497 4498 if (inta & ~(il->inta_mask)) { 4499 IL_WARN("Disabled INTA bits 0x%08x were pending\n", 4500 inta & ~il->inta_mask); 4501 IL_WARN(" with FH49_INT = 0x%08x\n", inta_fh); 4502 } 4503 4504 /* Re-enable all interrupts */ 4505 /* only Re-enable if disabled by irq */ 4506 if (test_bit(S_INT_ENABLED, &il->status)) 4507 il_enable_interrupts(il); 4508 /* Re-enable RF_KILL if it occurred */ 4509 else if (handled & CSR_INT_BIT_RF_KILL) 4510 il_enable_rfkill_int(il); 4511 4512#ifdef CONFIG_IWLEGACY_DEBUG 4513 if (il_get_debug_level(il) & (IL_DL_ISR)) { 4514 inta = _il_rd(il, CSR_INT); 4515 inta_mask = _il_rd(il, CSR_INT_MASK); 4516 inta_fh = _il_rd(il, CSR_FH_INT_STATUS); 4517 D_ISR("End inta 0x%08x, enabled 0x%08x, fh 0x%08x, " 4518 "flags 0x%08lx\n", inta, inta_mask, inta_fh, flags); 4519 } 4520#endif 4521} 4522 4523/***************************************************************************** 4524 * 4525 * sysfs attributes 4526 * 4527 *****************************************************************************/ 4528 4529#ifdef CONFIG_IWLEGACY_DEBUG 4530 4531/* 4532 * The following adds a new attribute to the sysfs representation 4533 * of this device driver (i.e. a new file in /sys/class/net/wlan0/device/) 4534 * used for controlling the debug level. 4535 * 4536 * See the level definitions in iwl for details. 4537 * 4538 * The debug_level being managed using sysfs below is a per device debug 4539 * level that is used instead of the global debug level if it (the per 4540 * device debug level) is set. 4541 */ 4542static ssize_t 4543il4965_show_debug_level(struct device *d, struct device_attribute *attr, 4544 char *buf) 4545{ 4546 struct il_priv *il = dev_get_drvdata(d); 4547 return sprintf(buf, "0x%08X\n", il_get_debug_level(il)); 4548} 4549 4550static ssize_t 4551il4965_store_debug_level(struct device *d, struct device_attribute *attr, 4552 const char *buf, size_t count) 4553{ 4554 struct il_priv *il = dev_get_drvdata(d); 4555 unsigned long val; 4556 int ret; 4557 4558 ret = kstrtoul(buf, 0, &val); 4559 if (ret) 4560 IL_ERR("%s is not in hex or decimal form.\n", buf); 4561 else 4562 il->debug_level = val; 4563 4564 return strnlen(buf, count); 4565} 4566 4567static DEVICE_ATTR(debug_level, 0644, il4965_show_debug_level, 4568 il4965_store_debug_level); 4569 4570#endif /* CONFIG_IWLEGACY_DEBUG */ 4571 4572static ssize_t 4573il4965_show_temperature(struct device *d, struct device_attribute *attr, 4574 char *buf) 4575{ 4576 struct il_priv *il = dev_get_drvdata(d); 4577 4578 if (!il_is_alive(il)) 4579 return -EAGAIN; 4580 4581 return sprintf(buf, "%d\n", il->temperature); 4582} 4583 4584static DEVICE_ATTR(temperature, 0444, il4965_show_temperature, NULL); 4585 4586static ssize_t 4587il4965_show_tx_power(struct device *d, struct device_attribute *attr, char *buf) 4588{ 4589 struct il_priv *il = dev_get_drvdata(d); 4590 4591 if (!il_is_ready_rf(il)) 4592 return sprintf(buf, "off\n"); 4593 else 4594 return sprintf(buf, "%d\n", il->tx_power_user_lmt); 4595} 4596 4597static ssize_t 4598il4965_store_tx_power(struct device *d, struct device_attribute *attr, 4599 const char *buf, size_t count) 4600{ 4601 struct il_priv *il = dev_get_drvdata(d); 4602 unsigned long val; 4603 int ret; 4604 4605 ret = kstrtoul(buf, 10, &val); 4606 if (ret) 4607 IL_INFO("%s is not in decimal form.\n", buf); 4608 else { 4609 mutex_lock(&il->mutex); 4610 ret = il_set_tx_power(il, val, false); 4611 mutex_unlock(&il->mutex); 4612 if (ret) 4613 IL_ERR("failed setting tx power (0x%08x).\n", ret); 4614 else 4615 ret = count; 4616 } 4617 return ret; 4618} 4619 4620static DEVICE_ATTR(tx_power, 0644, il4965_show_tx_power, 4621 il4965_store_tx_power); 4622 4623static struct attribute *il_sysfs_entries[] = { 4624 &dev_attr_temperature.attr, 4625 &dev_attr_tx_power.attr, 4626#ifdef CONFIG_IWLEGACY_DEBUG 4627 &dev_attr_debug_level.attr, 4628#endif 4629 NULL 4630}; 4631 4632static const struct attribute_group il_attribute_group = { 4633 .name = NULL, /* put in device directory */ 4634 .attrs = il_sysfs_entries, 4635}; 4636 4637/****************************************************************************** 4638 * 4639 * uCode download functions 4640 * 4641 ******************************************************************************/ 4642 4643static void 4644il4965_dealloc_ucode_pci(struct il_priv *il) 4645{ 4646 il_free_fw_desc(il->pci_dev, &il->ucode_code); 4647 il_free_fw_desc(il->pci_dev, &il->ucode_data); 4648 il_free_fw_desc(il->pci_dev, &il->ucode_data_backup); 4649 il_free_fw_desc(il->pci_dev, &il->ucode_init); 4650 il_free_fw_desc(il->pci_dev, &il->ucode_init_data); 4651 il_free_fw_desc(il->pci_dev, &il->ucode_boot); 4652} 4653 4654static void 4655il4965_nic_start(struct il_priv *il) 4656{ 4657 /* Remove all resets to allow NIC to operate */ 4658 _il_wr(il, CSR_RESET, 0); 4659} 4660 4661static void il4965_ucode_callback(const struct firmware *ucode_raw, 4662 void *context); 4663static int il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length); 4664 4665static int __must_check 4666il4965_request_firmware(struct il_priv *il, bool first) 4667{ 4668 const char *name_pre = il->cfg->fw_name_pre; 4669 char tag[8]; 4670 4671 if (first) { 4672 il->fw_idx = il->cfg->ucode_api_max; 4673 sprintf(tag, "%d", il->fw_idx); 4674 } else { 4675 il->fw_idx--; 4676 sprintf(tag, "%d", il->fw_idx); 4677 } 4678 4679 if (il->fw_idx < il->cfg->ucode_api_min) { 4680 IL_ERR("no suitable firmware found!\n"); 4681 return -ENOENT; 4682 } 4683 4684 sprintf(il->firmware_name, "%s%s%s", name_pre, tag, ".ucode"); 4685 4686 D_INFO("attempting to load firmware '%s'\n", il->firmware_name); 4687 4688 return request_firmware_nowait(THIS_MODULE, 1, il->firmware_name, 4689 &il->pci_dev->dev, GFP_KERNEL, il, 4690 il4965_ucode_callback); 4691} 4692 4693struct il4965_firmware_pieces { 4694 const void *inst, *data, *init, *init_data, *boot; 4695 size_t inst_size, data_size, init_size, init_data_size, boot_size; 4696}; 4697 4698static int 4699il4965_load_firmware(struct il_priv *il, const struct firmware *ucode_raw, 4700 struct il4965_firmware_pieces *pieces) 4701{ 4702 struct il_ucode_header *ucode = (void *)ucode_raw->data; 4703 u32 api_ver, hdr_size; 4704 const u8 *src; 4705 4706 il->ucode_ver = le32_to_cpu(ucode->ver); 4707 api_ver = IL_UCODE_API(il->ucode_ver); 4708 4709 switch (api_ver) { 4710 default: 4711 case 0: 4712 case 1: 4713 case 2: 4714 hdr_size = 24; 4715 if (ucode_raw->size < hdr_size) { 4716 IL_ERR("File size too small!\n"); 4717 return -EINVAL; 4718 } 4719 pieces->inst_size = le32_to_cpu(ucode->v1.inst_size); 4720 pieces->data_size = le32_to_cpu(ucode->v1.data_size); 4721 pieces->init_size = le32_to_cpu(ucode->v1.init_size); 4722 pieces->init_data_size = le32_to_cpu(ucode->v1.init_data_size); 4723 pieces->boot_size = le32_to_cpu(ucode->v1.boot_size); 4724 src = ucode->v1.data; 4725 break; 4726 } 4727 4728 /* Verify size of file vs. image size info in file's header */ 4729 if (ucode_raw->size != 4730 hdr_size + pieces->inst_size + pieces->data_size + 4731 pieces->init_size + pieces->init_data_size + pieces->boot_size) { 4732 4733 IL_ERR("uCode file size %d does not match expected size\n", 4734 (int)ucode_raw->size); 4735 return -EINVAL; 4736 } 4737 4738 pieces->inst = src; 4739 src += pieces->inst_size; 4740 pieces->data = src; 4741 src += pieces->data_size; 4742 pieces->init = src; 4743 src += pieces->init_size; 4744 pieces->init_data = src; 4745 src += pieces->init_data_size; 4746 pieces->boot = src; 4747 src += pieces->boot_size; 4748 4749 return 0; 4750} 4751 4752/* 4753 * il4965_ucode_callback - callback when firmware was loaded 4754 * 4755 * If loaded successfully, copies the firmware into buffers 4756 * for the card to fetch (via DMA). 4757 */ 4758static void 4759il4965_ucode_callback(const struct firmware *ucode_raw, void *context) 4760{ 4761 struct il_priv *il = context; 4762 int err; 4763 struct il4965_firmware_pieces pieces; 4764 const unsigned int api_max = il->cfg->ucode_api_max; 4765 const unsigned int api_min = il->cfg->ucode_api_min; 4766 u32 api_ver; 4767 4768 u32 max_probe_length = 200; 4769 u32 standard_phy_calibration_size = 4770 IL_DEFAULT_STANDARD_PHY_CALIBRATE_TBL_SIZE; 4771 4772 memset(&pieces, 0, sizeof(pieces)); 4773 4774 if (!ucode_raw) { 4775 if (il->fw_idx <= il->cfg->ucode_api_max) 4776 IL_ERR("request for firmware file '%s' failed.\n", 4777 il->firmware_name); 4778 goto try_again; 4779 } 4780 4781 D_INFO("Loaded firmware file '%s' (%zd bytes).\n", il->firmware_name, 4782 ucode_raw->size); 4783 4784 /* Make sure that we got at least the API version number */ 4785 if (ucode_raw->size < 4) { 4786 IL_ERR("File size way too small!\n"); 4787 goto try_again; 4788 } 4789 4790 /* Data from ucode file: header followed by uCode images */ 4791 err = il4965_load_firmware(il, ucode_raw, &pieces); 4792 4793 if (err) 4794 goto try_again; 4795 4796 api_ver = IL_UCODE_API(il->ucode_ver); 4797 4798 /* 4799 * api_ver should match the api version forming part of the 4800 * firmware filename ... but we don't check for that and only rely 4801 * on the API version read from firmware header from here on forward 4802 */ 4803 if (api_ver < api_min || api_ver > api_max) { 4804 IL_ERR("Driver unable to support your firmware API. " 4805 "Driver supports v%u, firmware is v%u.\n", api_max, 4806 api_ver); 4807 goto try_again; 4808 } 4809 4810 if (api_ver != api_max) 4811 IL_ERR("Firmware has old API version. Expected v%u, " 4812 "got v%u. New firmware can be obtained " 4813 "from http://www.intellinuxwireless.org.\n", api_max, 4814 api_ver); 4815 4816 IL_INFO("loaded firmware version %u.%u.%u.%u\n", 4817 IL_UCODE_MAJOR(il->ucode_ver), IL_UCODE_MINOR(il->ucode_ver), 4818 IL_UCODE_API(il->ucode_ver), IL_UCODE_SERIAL(il->ucode_ver)); 4819 4820 snprintf(il->hw->wiphy->fw_version, sizeof(il->hw->wiphy->fw_version), 4821 "%u.%u.%u.%u", IL_UCODE_MAJOR(il->ucode_ver), 4822 IL_UCODE_MINOR(il->ucode_ver), IL_UCODE_API(il->ucode_ver), 4823 IL_UCODE_SERIAL(il->ucode_ver)); 4824 4825 /* 4826 * For any of the failures below (before allocating pci memory) 4827 * we will try to load a version with a smaller API -- maybe the 4828 * user just got a corrupted version of the latest API. 4829 */ 4830 4831 D_INFO("f/w package hdr ucode version raw = 0x%x\n", il->ucode_ver); 4832 D_INFO("f/w package hdr runtime inst size = %zd\n", pieces.inst_size); 4833 D_INFO("f/w package hdr runtime data size = %zd\n", pieces.data_size); 4834 D_INFO("f/w package hdr init inst size = %zd\n", pieces.init_size); 4835 D_INFO("f/w package hdr init data size = %zd\n", pieces.init_data_size); 4836 D_INFO("f/w package hdr boot inst size = %zd\n", pieces.boot_size); 4837 4838 /* Verify that uCode images will fit in card's SRAM */ 4839 if (pieces.inst_size > il->hw_params.max_inst_size) { 4840 IL_ERR("uCode instr len %zd too large to fit in\n", 4841 pieces.inst_size); 4842 goto try_again; 4843 } 4844 4845 if (pieces.data_size > il->hw_params.max_data_size) { 4846 IL_ERR("uCode data len %zd too large to fit in\n", 4847 pieces.data_size); 4848 goto try_again; 4849 } 4850 4851 if (pieces.init_size > il->hw_params.max_inst_size) { 4852 IL_ERR("uCode init instr len %zd too large to fit in\n", 4853 pieces.init_size); 4854 goto try_again; 4855 } 4856 4857 if (pieces.init_data_size > il->hw_params.max_data_size) { 4858 IL_ERR("uCode init data len %zd too large to fit in\n", 4859 pieces.init_data_size); 4860 goto try_again; 4861 } 4862 4863 if (pieces.boot_size > il->hw_params.max_bsm_size) { 4864 IL_ERR("uCode boot instr len %zd too large to fit in\n", 4865 pieces.boot_size); 4866 goto try_again; 4867 } 4868 4869 /* Allocate ucode buffers for card's bus-master loading ... */ 4870 4871 /* Runtime instructions and 2 copies of data: 4872 * 1) unmodified from disk 4873 * 2) backup cache for save/restore during power-downs */ 4874 il->ucode_code.len = pieces.inst_size; 4875 il_alloc_fw_desc(il->pci_dev, &il->ucode_code); 4876 4877 il->ucode_data.len = pieces.data_size; 4878 il_alloc_fw_desc(il->pci_dev, &il->ucode_data); 4879 4880 il->ucode_data_backup.len = pieces.data_size; 4881 il_alloc_fw_desc(il->pci_dev, &il->ucode_data_backup); 4882 4883 if (!il->ucode_code.v_addr || !il->ucode_data.v_addr || 4884 !il->ucode_data_backup.v_addr) 4885 goto err_pci_alloc; 4886 4887 /* Initialization instructions and data */ 4888 if (pieces.init_size && pieces.init_data_size) { 4889 il->ucode_init.len = pieces.init_size; 4890 il_alloc_fw_desc(il->pci_dev, &il->ucode_init); 4891 4892 il->ucode_init_data.len = pieces.init_data_size; 4893 il_alloc_fw_desc(il->pci_dev, &il->ucode_init_data); 4894 4895 if (!il->ucode_init.v_addr || !il->ucode_init_data.v_addr) 4896 goto err_pci_alloc; 4897 } 4898 4899 /* Bootstrap (instructions only, no data) */ 4900 if (pieces.boot_size) { 4901 il->ucode_boot.len = pieces.boot_size; 4902 il_alloc_fw_desc(il->pci_dev, &il->ucode_boot); 4903 4904 if (!il->ucode_boot.v_addr) 4905 goto err_pci_alloc; 4906 } 4907 4908 /* Now that we can no longer fail, copy information */ 4909 4910 il->sta_key_max_num = STA_KEY_MAX_NUM; 4911 4912 /* Copy images into buffers for card's bus-master reads ... */ 4913 4914 /* Runtime instructions (first block of data in file) */ 4915 D_INFO("Copying (but not loading) uCode instr len %zd\n", 4916 pieces.inst_size); 4917 memcpy(il->ucode_code.v_addr, pieces.inst, pieces.inst_size); 4918 4919 D_INFO("uCode instr buf vaddr = 0x%p, paddr = 0x%08x\n", 4920 il->ucode_code.v_addr, (u32) il->ucode_code.p_addr); 4921 4922 /* 4923 * Runtime data 4924 * NOTE: Copy into backup buffer will be done in il_up() 4925 */ 4926 D_INFO("Copying (but not loading) uCode data len %zd\n", 4927 pieces.data_size); 4928 memcpy(il->ucode_data.v_addr, pieces.data, pieces.data_size); 4929 memcpy(il->ucode_data_backup.v_addr, pieces.data, pieces.data_size); 4930 4931 /* Initialization instructions */ 4932 if (pieces.init_size) { 4933 D_INFO("Copying (but not loading) init instr len %zd\n", 4934 pieces.init_size); 4935 memcpy(il->ucode_init.v_addr, pieces.init, pieces.init_size); 4936 } 4937 4938 /* Initialization data */ 4939 if (pieces.init_data_size) { 4940 D_INFO("Copying (but not loading) init data len %zd\n", 4941 pieces.init_data_size); 4942 memcpy(il->ucode_init_data.v_addr, pieces.init_data, 4943 pieces.init_data_size); 4944 } 4945 4946 /* Bootstrap instructions */ 4947 D_INFO("Copying (but not loading) boot instr len %zd\n", 4948 pieces.boot_size); 4949 memcpy(il->ucode_boot.v_addr, pieces.boot, pieces.boot_size); 4950 4951 /* 4952 * figure out the offset of chain noise reset and gain commands 4953 * base on the size of standard phy calibration commands table size 4954 */ 4955 il->_4965.phy_calib_chain_noise_reset_cmd = 4956 standard_phy_calibration_size; 4957 il->_4965.phy_calib_chain_noise_gain_cmd = 4958 standard_phy_calibration_size + 1; 4959 4960 /************************************************** 4961 * This is still part of probe() in a sense... 4962 * 4963 * 9. Setup and register with mac80211 and debugfs 4964 **************************************************/ 4965 err = il4965_mac_setup_register(il, max_probe_length); 4966 if (err) 4967 goto out_unbind; 4968 4969 il_dbgfs_register(il, DRV_NAME); 4970 4971 err = sysfs_create_group(&il->pci_dev->dev.kobj, &il_attribute_group); 4972 if (err) { 4973 IL_ERR("failed to create sysfs device attributes\n"); 4974 goto out_unbind; 4975 } 4976 4977 /* We have our copies now, allow OS release its copies */ 4978 release_firmware(ucode_raw); 4979 complete(&il->_4965.firmware_loading_complete); 4980 return; 4981 4982try_again: 4983 /* try next, if any */ 4984 if (il4965_request_firmware(il, false)) 4985 goto out_unbind; 4986 release_firmware(ucode_raw); 4987 return; 4988 4989err_pci_alloc: 4990 IL_ERR("failed to allocate pci memory\n"); 4991 il4965_dealloc_ucode_pci(il); 4992out_unbind: 4993 complete(&il->_4965.firmware_loading_complete); 4994 device_release_driver(&il->pci_dev->dev); 4995 release_firmware(ucode_raw); 4996} 4997 4998static const char *const desc_lookup_text[] = { 4999 "OK", 5000 "FAIL", 5001 "BAD_PARAM", 5002 "BAD_CHECKSUM", 5003 "NMI_INTERRUPT_WDG", 5004 "SYSASSERT", 5005 "FATAL_ERROR", 5006 "BAD_COMMAND", 5007 "HW_ERROR_TUNE_LOCK", 5008 "HW_ERROR_TEMPERATURE", 5009 "ILLEGAL_CHAN_FREQ", 5010 "VCC_NOT_STBL", 5011 "FH49_ERROR", 5012 "NMI_INTERRUPT_HOST", 5013 "NMI_INTERRUPT_ACTION_PT", 5014 "NMI_INTERRUPT_UNKNOWN", 5015 "UCODE_VERSION_MISMATCH", 5016 "HW_ERROR_ABS_LOCK", 5017 "HW_ERROR_CAL_LOCK_FAIL", 5018 "NMI_INTERRUPT_INST_ACTION_PT", 5019 "NMI_INTERRUPT_DATA_ACTION_PT", 5020 "NMI_TRM_HW_ER", 5021 "NMI_INTERRUPT_TRM", 5022 "NMI_INTERRUPT_BREAK_POINT", 5023 "DEBUG_0", 5024 "DEBUG_1", 5025 "DEBUG_2", 5026 "DEBUG_3", 5027}; 5028 5029static struct { 5030 char *name; 5031 u8 num; 5032} advanced_lookup[] = { 5033 { 5034 "NMI_INTERRUPT_WDG", 0x34}, { 5035 "SYSASSERT", 0x35}, { 5036 "UCODE_VERSION_MISMATCH", 0x37}, { 5037 "BAD_COMMAND", 0x38}, { 5038 "NMI_INTERRUPT_DATA_ACTION_PT", 0x3C}, { 5039 "FATAL_ERROR", 0x3D}, { 5040 "NMI_TRM_HW_ERR", 0x46}, { 5041 "NMI_INTERRUPT_TRM", 0x4C}, { 5042 "NMI_INTERRUPT_BREAK_POINT", 0x54}, { 5043 "NMI_INTERRUPT_WDG_RXF_FULL", 0x5C}, { 5044 "NMI_INTERRUPT_WDG_NO_RBD_RXF_FULL", 0x64}, { 5045 "NMI_INTERRUPT_HOST", 0x66}, { 5046 "NMI_INTERRUPT_ACTION_PT", 0x7C}, { 5047 "NMI_INTERRUPT_UNKNOWN", 0x84}, { 5048 "NMI_INTERRUPT_INST_ACTION_PT", 0x86}, { 5049"ADVANCED_SYSASSERT", 0},}; 5050 5051static const char * 5052il4965_desc_lookup(u32 num) 5053{ 5054 int i; 5055 int max = ARRAY_SIZE(desc_lookup_text); 5056 5057 if (num < max) 5058 return desc_lookup_text[num]; 5059 5060 max = ARRAY_SIZE(advanced_lookup) - 1; 5061 for (i = 0; i < max; i++) { 5062 if (advanced_lookup[i].num == num) 5063 break; 5064 } 5065 return advanced_lookup[i].name; 5066} 5067 5068#define ERROR_START_OFFSET (1 * sizeof(u32)) 5069#define ERROR_ELEM_SIZE (7 * sizeof(u32)) 5070 5071void 5072il4965_dump_nic_error_log(struct il_priv *il) 5073{ 5074 u32 data2, line; 5075 u32 desc, time, count, base, data1; 5076 u32 blink1, blink2, ilink1, ilink2; 5077 u32 pc, hcmd; 5078 5079 if (il->ucode_type == UCODE_INIT) 5080 base = le32_to_cpu(il->card_alive_init.error_event_table_ptr); 5081 else 5082 base = le32_to_cpu(il->card_alive.error_event_table_ptr); 5083 5084 if (!il->ops->is_valid_rtc_data_addr(base)) { 5085 IL_ERR("Not valid error log pointer 0x%08X for %s uCode\n", 5086 base, (il->ucode_type == UCODE_INIT) ? "Init" : "RT"); 5087 return; 5088 } 5089 5090 count = il_read_targ_mem(il, base); 5091 5092 if (ERROR_START_OFFSET <= count * ERROR_ELEM_SIZE) { 5093 IL_ERR("Start IWL Error Log Dump:\n"); 5094 IL_ERR("Status: 0x%08lX, count: %d\n", il->status, count); 5095 } 5096 5097 desc = il_read_targ_mem(il, base + 1 * sizeof(u32)); 5098 il->isr_stats.err_code = desc; 5099 pc = il_read_targ_mem(il, base + 2 * sizeof(u32)); 5100 blink1 = il_read_targ_mem(il, base + 3 * sizeof(u32)); 5101 blink2 = il_read_targ_mem(il, base + 4 * sizeof(u32)); 5102 ilink1 = il_read_targ_mem(il, base + 5 * sizeof(u32)); 5103 ilink2 = il_read_targ_mem(il, base + 6 * sizeof(u32)); 5104 data1 = il_read_targ_mem(il, base + 7 * sizeof(u32)); 5105 data2 = il_read_targ_mem(il, base + 8 * sizeof(u32)); 5106 line = il_read_targ_mem(il, base + 9 * sizeof(u32)); 5107 time = il_read_targ_mem(il, base + 11 * sizeof(u32)); 5108 hcmd = il_read_targ_mem(il, base + 22 * sizeof(u32)); 5109 5110 IL_ERR("Desc Time " 5111 "data1 data2 line\n"); 5112 IL_ERR("%-28s (0x%04X) %010u 0x%08X 0x%08X %u\n", 5113 il4965_desc_lookup(desc), desc, time, data1, data2, line); 5114 IL_ERR("pc blink1 blink2 ilink1 ilink2 hcmd\n"); 5115 IL_ERR("0x%05X 0x%05X 0x%05X 0x%05X 0x%05X 0x%05X\n", pc, blink1, 5116 blink2, ilink1, ilink2, hcmd); 5117} 5118 5119static void 5120il4965_rf_kill_ct_config(struct il_priv *il) 5121{ 5122 struct il_ct_kill_config cmd; 5123 unsigned long flags; 5124 int ret = 0; 5125 5126 spin_lock_irqsave(&il->lock, flags); 5127 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, 5128 CSR_UCODE_DRV_GP1_REG_BIT_CT_KILL_EXIT); 5129 spin_unlock_irqrestore(&il->lock, flags); 5130 5131 cmd.critical_temperature_R = 5132 cpu_to_le32(il->hw_params.ct_kill_threshold); 5133 5134 ret = il_send_cmd_pdu(il, C_CT_KILL_CONFIG, sizeof(cmd), &cmd); 5135 if (ret) 5136 IL_ERR("C_CT_KILL_CONFIG failed\n"); 5137 else 5138 D_INFO("C_CT_KILL_CONFIG " "succeeded, " 5139 "critical temperature is %d\n", 5140 il->hw_params.ct_kill_threshold); 5141} 5142 5143static const s8 default_queue_to_tx_fifo[] = { 5144 IL_TX_FIFO_VO, 5145 IL_TX_FIFO_VI, 5146 IL_TX_FIFO_BE, 5147 IL_TX_FIFO_BK, 5148 IL49_CMD_FIFO_NUM, 5149 IL_TX_FIFO_UNUSED, 5150 IL_TX_FIFO_UNUSED, 5151}; 5152 5153#define IL_MASK(lo, hi) ((1 << (hi)) | ((1 << (hi)) - (1 << (lo)))) 5154 5155static int 5156il4965_alive_notify(struct il_priv *il) 5157{ 5158 u32 a; 5159 unsigned long flags; 5160 int i, chan; 5161 u32 reg_val; 5162 5163 spin_lock_irqsave(&il->lock, flags); 5164 5165 /* Clear 4965's internal Tx Scheduler data base */ 5166 il->scd_base_addr = il_rd_prph(il, IL49_SCD_SRAM_BASE_ADDR); 5167 a = il->scd_base_addr + IL49_SCD_CONTEXT_DATA_OFFSET; 5168 for (; a < il->scd_base_addr + IL49_SCD_TX_STTS_BITMAP_OFFSET; a += 4) 5169 il_write_targ_mem(il, a, 0); 5170 for (; a < il->scd_base_addr + IL49_SCD_TRANSLATE_TBL_OFFSET; a += 4) 5171 il_write_targ_mem(il, a, 0); 5172 for (; 5173 a < 5174 il->scd_base_addr + 5175 IL49_SCD_TRANSLATE_TBL_OFFSET_QUEUE(il->hw_params.max_txq_num); 5176 a += 4) 5177 il_write_targ_mem(il, a, 0); 5178 5179 /* Tel 4965 where to find Tx byte count tables */ 5180 il_wr_prph(il, IL49_SCD_DRAM_BASE_ADDR, il->scd_bc_tbls.dma >> 10); 5181 5182 /* Enable DMA channel */ 5183 for (chan = 0; chan < FH49_TCSR_CHNL_NUM; chan++) 5184 il_wr(il, FH49_TCSR_CHNL_TX_CONFIG_REG(chan), 5185 FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CHNL_ENABLE | 5186 FH49_TCSR_TX_CONFIG_REG_VAL_DMA_CREDIT_ENABLE); 5187 5188 /* Update FH chicken bits */ 5189 reg_val = il_rd(il, FH49_TX_CHICKEN_BITS_REG); 5190 il_wr(il, FH49_TX_CHICKEN_BITS_REG, 5191 reg_val | FH49_TX_CHICKEN_BITS_SCD_AUTO_RETRY_EN); 5192 5193 /* Disable chain mode for all queues */ 5194 il_wr_prph(il, IL49_SCD_QUEUECHAIN_SEL, 0); 5195 5196 /* Initialize each Tx queue (including the command queue) */ 5197 for (i = 0; i < il->hw_params.max_txq_num; i++) { 5198 5199 /* TFD circular buffer read/write idxes */ 5200 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(i), 0); 5201 il_wr(il, HBUS_TARG_WRPTR, 0 | (i << 8)); 5202 5203 /* Max Tx Window size for Scheduler-ACK mode */ 5204 il_write_targ_mem(il, 5205 il->scd_base_addr + 5206 IL49_SCD_CONTEXT_QUEUE_OFFSET(i), 5207 (SCD_WIN_SIZE << 5208 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_POS) & 5209 IL49_SCD_QUEUE_CTX_REG1_WIN_SIZE_MSK); 5210 5211 /* Frame limit */ 5212 il_write_targ_mem(il, 5213 il->scd_base_addr + 5214 IL49_SCD_CONTEXT_QUEUE_OFFSET(i) + 5215 sizeof(u32), 5216 (SCD_FRAME_LIMIT << 5217 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_POS) & 5218 IL49_SCD_QUEUE_CTX_REG2_FRAME_LIMIT_MSK); 5219 5220 } 5221 il_wr_prph(il, IL49_SCD_INTERRUPT_MASK, 5222 (1 << il->hw_params.max_txq_num) - 1); 5223 5224 /* Activate all Tx DMA/FIFO channels */ 5225 il4965_txq_set_sched(il, IL_MASK(0, 6)); 5226 5227 il4965_set_wr_ptrs(il, IL_DEFAULT_CMD_QUEUE_NUM, 0); 5228 5229 /* make sure all queue are not stopped */ 5230 memset(&il->queue_stopped[0], 0, sizeof(il->queue_stopped)); 5231 for (i = 0; i < 4; i++) 5232 atomic_set(&il->queue_stop_count[i], 0); 5233 5234 /* reset to 0 to enable all the queue first */ 5235 il->txq_ctx_active_msk = 0; 5236 /* Map each Tx/cmd queue to its corresponding fifo */ 5237 BUILD_BUG_ON(ARRAY_SIZE(default_queue_to_tx_fifo) != 7); 5238 5239 for (i = 0; i < ARRAY_SIZE(default_queue_to_tx_fifo); i++) { 5240 int ac = default_queue_to_tx_fifo[i]; 5241 5242 il_txq_ctx_activate(il, i); 5243 5244 if (ac == IL_TX_FIFO_UNUSED) 5245 continue; 5246 5247 il4965_tx_queue_set_status(il, &il->txq[i], ac, 0); 5248 } 5249 5250 spin_unlock_irqrestore(&il->lock, flags); 5251 5252 return 0; 5253} 5254 5255/* 5256 * il4965_alive_start - called after N_ALIVE notification received 5257 * from protocol/runtime uCode (initialization uCode's 5258 * Alive gets handled by il_init_alive_start()). 5259 */ 5260static void 5261il4965_alive_start(struct il_priv *il) 5262{ 5263 int ret = 0; 5264 5265 D_INFO("Runtime Alive received.\n"); 5266 5267 if (il->card_alive.is_valid != UCODE_VALID_OK) { 5268 /* We had an error bringing up the hardware, so take it 5269 * all the way back down so we can try again */ 5270 D_INFO("Alive failed.\n"); 5271 goto restart; 5272 } 5273 5274 /* Initialize uCode has loaded Runtime uCode ... verify inst image. 5275 * This is a paranoid check, because we would not have gotten the 5276 * "runtime" alive if code weren't properly loaded. */ 5277 if (il4965_verify_ucode(il)) { 5278 /* Runtime instruction load was bad; 5279 * take it all the way back down so we can try again */ 5280 D_INFO("Bad runtime uCode load.\n"); 5281 goto restart; 5282 } 5283 5284 ret = il4965_alive_notify(il); 5285 if (ret) { 5286 IL_WARN("Could not complete ALIVE transition [ntf]: %d\n", ret); 5287 goto restart; 5288 } 5289 5290 /* After the ALIVE response, we can send host commands to the uCode */ 5291 set_bit(S_ALIVE, &il->status); 5292 5293 /* Enable watchdog to monitor the driver tx queues */ 5294 il_setup_watchdog(il); 5295 5296 if (il_is_rfkill(il)) 5297 return; 5298 5299 ieee80211_wake_queues(il->hw); 5300 5301 il->active_rate = RATES_MASK; 5302 5303 il_power_update_mode(il, true); 5304 D_INFO("Updated power mode\n"); 5305 5306 if (il_is_associated(il)) { 5307 struct il_rxon_cmd *active_rxon = 5308 (struct il_rxon_cmd *)&il->active; 5309 /* apply any changes in staging */ 5310 il->staging.filter_flags |= RXON_FILTER_ASSOC_MSK; 5311 active_rxon->filter_flags &= ~RXON_FILTER_ASSOC_MSK; 5312 } else { 5313 /* Initialize our rx_config data */ 5314 il_connection_init_rx_config(il); 5315 5316 if (il->ops->set_rxon_chain) 5317 il->ops->set_rxon_chain(il); 5318 } 5319 5320 /* Configure bluetooth coexistence if enabled */ 5321 il_send_bt_config(il); 5322 5323 il4965_reset_run_time_calib(il); 5324 5325 set_bit(S_READY, &il->status); 5326 5327 /* Configure the adapter for unassociated operation */ 5328 il_commit_rxon(il); 5329 5330 /* At this point, the NIC is initialized and operational */ 5331 il4965_rf_kill_ct_config(il); 5332 5333 D_INFO("ALIVE processing complete.\n"); 5334 wake_up(&il->wait_command_queue); 5335 5336 return; 5337 5338restart: 5339 queue_work(il->workqueue, &il->restart); 5340} 5341 5342static void il4965_cancel_deferred_work(struct il_priv *il); 5343 5344static void 5345__il4965_down(struct il_priv *il) 5346{ 5347 unsigned long flags; 5348 int exit_pending; 5349 5350 D_INFO(DRV_NAME " is going down\n"); 5351 5352 il_scan_cancel_timeout(il, 200); 5353 5354 exit_pending = test_and_set_bit(S_EXIT_PENDING, &il->status); 5355 5356 /* Stop TX queues watchdog. We need to have S_EXIT_PENDING bit set 5357 * to prevent rearm timer */ 5358 timer_delete_sync(&il->watchdog); 5359 5360 il_clear_ucode_stations(il); 5361 5362 /* FIXME: race conditions ? */ 5363 spin_lock_irq(&il->sta_lock); 5364 /* 5365 * Remove all key information that is not stored as part 5366 * of station information since mac80211 may not have had 5367 * a chance to remove all the keys. When device is 5368 * reconfigured by mac80211 after an error all keys will 5369 * be reconfigured. 5370 */ 5371 memset(il->_4965.wep_keys, 0, sizeof(il->_4965.wep_keys)); 5372 il->_4965.key_mapping_keys = 0; 5373 spin_unlock_irq(&il->sta_lock); 5374 5375 il_dealloc_bcast_stations(il); 5376 il_clear_driver_stations(il); 5377 5378 /* Unblock any waiting calls */ 5379 wake_up_all(&il->wait_command_queue); 5380 5381 /* Wipe out the EXIT_PENDING status bit if we are not actually 5382 * exiting the module */ 5383 if (!exit_pending) 5384 clear_bit(S_EXIT_PENDING, &il->status); 5385 5386 /* stop and reset the on-board processor */ 5387 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); 5388 5389 /* tell the device to stop sending interrupts */ 5390 spin_lock_irqsave(&il->lock, flags); 5391 il_disable_interrupts(il); 5392 spin_unlock_irqrestore(&il->lock, flags); 5393 il4965_synchronize_irq(il); 5394 5395 if (il->mac80211_registered) 5396 ieee80211_stop_queues(il->hw); 5397 5398 /* If we have not previously called il_init() then 5399 * clear all bits but the RF Kill bit and return */ 5400 if (!il_is_init(il)) { 5401 il->status = 5402 test_bit(S_RFKILL, &il->status) << S_RFKILL | 5403 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED | 5404 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING; 5405 goto exit; 5406 } 5407 5408 /* ...otherwise clear out all the status bits but the RF Kill 5409 * bit and continue taking the NIC down. */ 5410 il->status &= 5411 test_bit(S_RFKILL, &il->status) << S_RFKILL | 5412 test_bit(S_GEO_CONFIGURED, &il->status) << S_GEO_CONFIGURED | 5413 test_bit(S_FW_ERROR, &il->status) << S_FW_ERROR | 5414 test_bit(S_EXIT_PENDING, &il->status) << S_EXIT_PENDING; 5415 5416 /* 5417 * We disabled and synchronized interrupt, and priv->mutex is taken, so 5418 * here is the only thread which will program device registers, but 5419 * still have lockdep assertions, so we are taking reg_lock. 5420 */ 5421 spin_lock_irq(&il->reg_lock); 5422 /* FIXME: il_grab_nic_access if rfkill is off ? */ 5423 5424 il4965_txq_ctx_stop(il); 5425 il4965_rxq_stop(il); 5426 /* Power-down device's busmaster DMA clocks */ 5427 _il_wr_prph(il, APMG_CLK_DIS_REG, APMG_CLK_VAL_DMA_CLK_RQT); 5428 udelay(5); 5429 /* Make sure (redundant) we've released our request to stay awake */ 5430 _il_clear_bit(il, CSR_GP_CNTRL, CSR_GP_CNTRL_REG_FLAG_MAC_ACCESS_REQ); 5431 /* Stop the device, and put it in low power state */ 5432 _il_apm_stop(il); 5433 5434 spin_unlock_irq(&il->reg_lock); 5435 5436 il4965_txq_ctx_unmap(il); 5437exit: 5438 memset(&il->card_alive, 0, sizeof(struct il_alive_resp)); 5439 5440 dev_kfree_skb(il->beacon_skb); 5441 il->beacon_skb = NULL; 5442 5443 /* clear out any free frames */ 5444 il4965_clear_free_frames(il); 5445} 5446 5447static void 5448il4965_down(struct il_priv *il) 5449{ 5450 mutex_lock(&il->mutex); 5451 __il4965_down(il); 5452 mutex_unlock(&il->mutex); 5453 5454 il4965_cancel_deferred_work(il); 5455} 5456 5457 5458static void 5459il4965_set_hw_ready(struct il_priv *il) 5460{ 5461 int ret; 5462 5463 il_set_bit(il, CSR_HW_IF_CONFIG_REG, 5464 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY); 5465 5466 /* See if we got it */ 5467 ret = _il_poll_bit(il, CSR_HW_IF_CONFIG_REG, 5468 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 5469 CSR_HW_IF_CONFIG_REG_BIT_NIC_READY, 5470 100); 5471 if (ret >= 0) 5472 il->hw_ready = true; 5473 5474 D_INFO("hardware %s ready\n", (il->hw_ready) ? "" : "not"); 5475} 5476 5477static void 5478il4965_prepare_card_hw(struct il_priv *il) 5479{ 5480 int ret; 5481 5482 il->hw_ready = false; 5483 5484 il4965_set_hw_ready(il); 5485 if (il->hw_ready) 5486 return; 5487 5488 /* If HW is not ready, prepare the conditions to check again */ 5489 il_set_bit(il, CSR_HW_IF_CONFIG_REG, CSR_HW_IF_CONFIG_REG_PREPARE); 5490 5491 ret = 5492 _il_poll_bit(il, CSR_HW_IF_CONFIG_REG, 5493 ~CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 5494 CSR_HW_IF_CONFIG_REG_BIT_NIC_PREPARE_DONE, 150000); 5495 5496 /* HW should be ready by now, check again. */ 5497 if (ret != -ETIMEDOUT) 5498 il4965_set_hw_ready(il); 5499} 5500 5501#define MAX_HW_RESTARTS 5 5502 5503static int 5504__il4965_up(struct il_priv *il) 5505{ 5506 int i; 5507 int ret; 5508 5509 if (test_bit(S_EXIT_PENDING, &il->status)) { 5510 IL_WARN("Exit pending; will not bring the NIC up\n"); 5511 return -EIO; 5512 } 5513 5514 if (!il->ucode_data_backup.v_addr || !il->ucode_data.v_addr) { 5515 IL_ERR("ucode not available for device bringup\n"); 5516 return -EIO; 5517 } 5518 5519 ret = il4965_alloc_bcast_station(il); 5520 if (ret) { 5521 il_dealloc_bcast_stations(il); 5522 return ret; 5523 } 5524 5525 il4965_prepare_card_hw(il); 5526 if (!il->hw_ready) { 5527 il_dealloc_bcast_stations(il); 5528 IL_ERR("HW not ready\n"); 5529 return -EIO; 5530 } 5531 5532 /* If platform's RF_KILL switch is NOT set to KILL */ 5533 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) 5534 clear_bit(S_RFKILL, &il->status); 5535 else { 5536 set_bit(S_RFKILL, &il->status); 5537 wiphy_rfkill_set_hw_state(il->hw->wiphy, true); 5538 5539 il_dealloc_bcast_stations(il); 5540 il_enable_rfkill_int(il); 5541 IL_WARN("Radio disabled by HW RF Kill switch\n"); 5542 return 0; 5543 } 5544 5545 _il_wr(il, CSR_INT, 0xFFFFFFFF); 5546 5547 /* must be initialised before il_hw_nic_init */ 5548 il->cmd_queue = IL_DEFAULT_CMD_QUEUE_NUM; 5549 5550 ret = il4965_hw_nic_init(il); 5551 if (ret) { 5552 IL_ERR("Unable to init nic\n"); 5553 il_dealloc_bcast_stations(il); 5554 return ret; 5555 } 5556 5557 /* make sure rfkill handshake bits are cleared */ 5558 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 5559 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_DRV_GP1_BIT_CMD_BLOCKED); 5560 5561 /* clear (again), then enable host interrupts */ 5562 _il_wr(il, CSR_INT, 0xFFFFFFFF); 5563 il_enable_interrupts(il); 5564 5565 /* really make sure rfkill handshake bits are cleared */ 5566 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 5567 _il_wr(il, CSR_UCODE_DRV_GP1_CLR, CSR_UCODE_SW_BIT_RFKILL); 5568 5569 /* Copy original ucode data image from disk into backup cache. 5570 * This will be used to initialize the on-board processor's 5571 * data SRAM for a clean start when the runtime program first loads. */ 5572 memcpy(il->ucode_data_backup.v_addr, il->ucode_data.v_addr, 5573 il->ucode_data.len); 5574 5575 for (i = 0; i < MAX_HW_RESTARTS; i++) { 5576 5577 /* load bootstrap state machine, 5578 * load bootstrap program into processor's memory, 5579 * prepare to load the "initialize" uCode */ 5580 ret = il->ops->load_ucode(il); 5581 5582 if (ret) { 5583 IL_ERR("Unable to set up bootstrap uCode: %d\n", ret); 5584 continue; 5585 } 5586 5587 /* start card; "initialize" will load runtime ucode */ 5588 il4965_nic_start(il); 5589 5590 D_INFO(DRV_NAME " is coming up\n"); 5591 5592 return 0; 5593 } 5594 5595 set_bit(S_EXIT_PENDING, &il->status); 5596 __il4965_down(il); 5597 clear_bit(S_EXIT_PENDING, &il->status); 5598 5599 /* tried to restart and config the device for as long as our 5600 * patience could withstand */ 5601 IL_ERR("Unable to initialize device after %d attempts.\n", i); 5602 return -EIO; 5603} 5604 5605/***************************************************************************** 5606 * 5607 * Workqueue callbacks 5608 * 5609 *****************************************************************************/ 5610 5611static void 5612il4965_bg_init_alive_start(struct work_struct *data) 5613{ 5614 struct il_priv *il = 5615 container_of(data, struct il_priv, init_alive_start.work); 5616 5617 mutex_lock(&il->mutex); 5618 if (test_bit(S_EXIT_PENDING, &il->status)) 5619 goto out; 5620 5621 il->ops->init_alive_start(il); 5622out: 5623 mutex_unlock(&il->mutex); 5624} 5625 5626static void 5627il4965_bg_alive_start(struct work_struct *data) 5628{ 5629 struct il_priv *il = 5630 container_of(data, struct il_priv, alive_start.work); 5631 5632 mutex_lock(&il->mutex); 5633 if (test_bit(S_EXIT_PENDING, &il->status)) 5634 goto out; 5635 5636 il4965_alive_start(il); 5637out: 5638 mutex_unlock(&il->mutex); 5639} 5640 5641static void 5642il4965_bg_run_time_calib_work(struct work_struct *work) 5643{ 5644 struct il_priv *il = container_of(work, struct il_priv, 5645 run_time_calib_work); 5646 5647 mutex_lock(&il->mutex); 5648 5649 if (test_bit(S_EXIT_PENDING, &il->status) || 5650 test_bit(S_SCANNING, &il->status)) { 5651 mutex_unlock(&il->mutex); 5652 return; 5653 } 5654 5655 if (il->start_calib) { 5656 il4965_chain_noise_calibration(il, (void *)&il->_4965.stats); 5657 il4965_sensitivity_calibration(il, (void *)&il->_4965.stats); 5658 } 5659 5660 mutex_unlock(&il->mutex); 5661} 5662 5663static void 5664il4965_bg_restart(struct work_struct *data) 5665{ 5666 struct il_priv *il = container_of(data, struct il_priv, restart); 5667 5668 if (test_bit(S_EXIT_PENDING, &il->status)) 5669 return; 5670 5671 if (test_and_clear_bit(S_FW_ERROR, &il->status)) { 5672 mutex_lock(&il->mutex); 5673 il->is_open = 0; 5674 5675 __il4965_down(il); 5676 5677 mutex_unlock(&il->mutex); 5678 il4965_cancel_deferred_work(il); 5679 ieee80211_restart_hw(il->hw); 5680 } else { 5681 il4965_down(il); 5682 5683 mutex_lock(&il->mutex); 5684 if (test_bit(S_EXIT_PENDING, &il->status)) { 5685 mutex_unlock(&il->mutex); 5686 return; 5687 } 5688 5689 __il4965_up(il); 5690 mutex_unlock(&il->mutex); 5691 } 5692} 5693 5694static void 5695il4965_bg_rx_replenish(struct work_struct *data) 5696{ 5697 struct il_priv *il = container_of(data, struct il_priv, rx_replenish); 5698 5699 if (test_bit(S_EXIT_PENDING, &il->status)) 5700 return; 5701 5702 mutex_lock(&il->mutex); 5703 il4965_rx_replenish(il); 5704 mutex_unlock(&il->mutex); 5705} 5706 5707/***************************************************************************** 5708 * 5709 * mac80211 entry point functions 5710 * 5711 *****************************************************************************/ 5712 5713#define UCODE_READY_TIMEOUT (4 * HZ) 5714 5715/* 5716 * Not a mac80211 entry point function, but it fits in with all the 5717 * other mac80211 functions grouped here. 5718 */ 5719static int 5720il4965_mac_setup_register(struct il_priv *il, u32 max_probe_length) 5721{ 5722 int ret; 5723 struct ieee80211_hw *hw = il->hw; 5724 5725 hw->rate_control_algorithm = "iwl-4965-rs"; 5726 5727 /* Tell mac80211 our characteristics */ 5728 ieee80211_hw_set(hw, SUPPORTS_DYNAMIC_PS); 5729 ieee80211_hw_set(hw, SUPPORTS_PS); 5730 ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS); 5731 ieee80211_hw_set(hw, SPECTRUM_MGMT); 5732 ieee80211_hw_set(hw, NEED_DTIM_BEFORE_ASSOC); 5733 ieee80211_hw_set(hw, SIGNAL_DBM); 5734 ieee80211_hw_set(hw, AMPDU_AGGREGATION); 5735 if (il->cfg->sku & IL_SKU_N) 5736 hw->wiphy->features |= NL80211_FEATURE_DYNAMIC_SMPS | 5737 NL80211_FEATURE_STATIC_SMPS; 5738 5739 hw->sta_data_size = sizeof(struct il_station_priv); 5740 hw->vif_data_size = sizeof(struct il_vif_priv); 5741 5742 hw->wiphy->interface_modes = 5743 BIT(NL80211_IFTYPE_STATION) | BIT(NL80211_IFTYPE_ADHOC); 5744 5745 hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN; 5746 hw->wiphy->regulatory_flags |= REGULATORY_CUSTOM_REG | 5747 REGULATORY_DISABLE_BEACON_HINTS; 5748 5749 /* 5750 * For now, disable PS by default because it affects 5751 * RX performance significantly. 5752 */ 5753 hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT; 5754 5755 hw->wiphy->max_scan_ssids = PROBE_OPTION_MAX; 5756 /* we create the 802.11 header and a zero-length SSID element */ 5757 hw->wiphy->max_scan_ie_len = max_probe_length - 24 - 2; 5758 5759 /* Default value; 4 EDCA QOS priorities */ 5760 hw->queues = 4; 5761 5762 hw->max_listen_interval = IL_CONN_MAX_LISTEN_INTERVAL; 5763 5764 if (il->bands[NL80211_BAND_2GHZ].n_channels) 5765 il->hw->wiphy->bands[NL80211_BAND_2GHZ] = 5766 &il->bands[NL80211_BAND_2GHZ]; 5767 if (il->bands[NL80211_BAND_5GHZ].n_channels) 5768 il->hw->wiphy->bands[NL80211_BAND_5GHZ] = 5769 &il->bands[NL80211_BAND_5GHZ]; 5770 5771 il_leds_init(il); 5772 5773 wiphy_ext_feature_set(il->hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST); 5774 5775 ret = ieee80211_register_hw(il->hw); 5776 if (ret) { 5777 IL_ERR("Failed to register hw (error %d)\n", ret); 5778 return ret; 5779 } 5780 il->mac80211_registered = 1; 5781 5782 return 0; 5783} 5784 5785int 5786il4965_mac_start(struct ieee80211_hw *hw) 5787{ 5788 struct il_priv *il = hw->priv; 5789 int ret; 5790 5791 D_MAC80211("enter\n"); 5792 5793 /* we should be verifying the device is ready to be opened */ 5794 mutex_lock(&il->mutex); 5795 ret = __il4965_up(il); 5796 mutex_unlock(&il->mutex); 5797 5798 if (ret) 5799 return ret; 5800 5801 if (il_is_rfkill(il)) 5802 goto out; 5803 5804 D_INFO("Start UP work done.\n"); 5805 5806 /* Wait for START_ALIVE from Run Time ucode. Otherwise callbacks from 5807 * mac80211 will not be run successfully. */ 5808 ret = wait_event_timeout(il->wait_command_queue, 5809 test_bit(S_READY, &il->status), 5810 UCODE_READY_TIMEOUT); 5811 if (!ret) { 5812 if (!test_bit(S_READY, &il->status)) { 5813 IL_ERR("START_ALIVE timeout after %dms.\n", 5814 jiffies_to_msecs(UCODE_READY_TIMEOUT)); 5815 return -ETIMEDOUT; 5816 } 5817 } 5818 5819 il4965_led_enable(il); 5820 5821out: 5822 il->is_open = 1; 5823 D_MAC80211("leave\n"); 5824 return 0; 5825} 5826 5827void 5828il4965_mac_stop(struct ieee80211_hw *hw, bool suspend) 5829{ 5830 struct il_priv *il = hw->priv; 5831 5832 D_MAC80211("enter\n"); 5833 5834 if (!il->is_open) 5835 return; 5836 5837 il->is_open = 0; 5838 5839 il4965_down(il); 5840 5841 flush_workqueue(il->workqueue); 5842 5843 /* User space software may expect getting rfkill changes 5844 * even if interface is down */ 5845 _il_wr(il, CSR_INT, 0xFFFFFFFF); 5846 il_enable_rfkill_int(il); 5847 5848 D_MAC80211("leave\n"); 5849} 5850 5851void 5852il4965_mac_tx(struct ieee80211_hw *hw, 5853 struct ieee80211_tx_control *control, 5854 struct sk_buff *skb) 5855{ 5856 struct il_priv *il = hw->priv; 5857 5858 D_MACDUMP("enter\n"); 5859 5860 D_TX("dev->xmit(%d bytes) at rate 0x%02x\n", skb->len, 5861 ieee80211_get_tx_rate(hw, IEEE80211_SKB_CB(skb))->bitrate); 5862 5863 if (il4965_tx_skb(il, control->sta, skb)) 5864 dev_kfree_skb_any(skb); 5865 5866 D_MACDUMP("leave\n"); 5867} 5868 5869void 5870il4965_mac_update_tkip_key(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 5871 struct ieee80211_key_conf *keyconf, 5872 struct ieee80211_sta *sta, u32 iv32, u16 * phase1key) 5873{ 5874 struct il_priv *il = hw->priv; 5875 5876 D_MAC80211("enter\n"); 5877 5878 il4965_update_tkip_key(il, keyconf, sta, iv32, phase1key); 5879 5880 D_MAC80211("leave\n"); 5881} 5882 5883int 5884il4965_mac_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd, 5885 struct ieee80211_vif *vif, struct ieee80211_sta *sta, 5886 struct ieee80211_key_conf *key) 5887{ 5888 struct il_priv *il = hw->priv; 5889 int ret; 5890 u8 sta_id; 5891 bool is_default_wep_key = false; 5892 5893 D_MAC80211("enter\n"); 5894 5895 if (il->cfg->mod_params->sw_crypto) { 5896 D_MAC80211("leave - hwcrypto disabled\n"); 5897 return -EOPNOTSUPP; 5898 } 5899 5900 /* 5901 * To support IBSS RSN, don't program group keys in IBSS, the 5902 * hardware will then not attempt to decrypt the frames. 5903 */ 5904 if (vif->type == NL80211_IFTYPE_ADHOC && 5905 !(key->flags & IEEE80211_KEY_FLAG_PAIRWISE)) { 5906 D_MAC80211("leave - ad-hoc group key\n"); 5907 return -EOPNOTSUPP; 5908 } 5909 5910 sta_id = il_sta_id_or_broadcast(il, sta); 5911 if (sta_id == IL_INVALID_STATION) 5912 return -EINVAL; 5913 5914 mutex_lock(&il->mutex); 5915 il_scan_cancel_timeout(il, 100); 5916 5917 /* 5918 * If we are getting WEP group key and we didn't receive any key mapping 5919 * so far, we are in legacy wep mode (group key only), otherwise we are 5920 * in 1X mode. 5921 * In legacy wep mode, we use another host command to the uCode. 5922 */ 5923 if ((key->cipher == WLAN_CIPHER_SUITE_WEP40 || 5924 key->cipher == WLAN_CIPHER_SUITE_WEP104) && !sta) { 5925 if (cmd == SET_KEY) 5926 is_default_wep_key = !il->_4965.key_mapping_keys; 5927 else 5928 is_default_wep_key = 5929 (key->hw_key_idx == HW_KEY_DEFAULT); 5930 } 5931 5932 switch (cmd) { 5933 case SET_KEY: 5934 if (is_default_wep_key) 5935 ret = il4965_set_default_wep_key(il, key); 5936 else 5937 ret = il4965_set_dynamic_key(il, key, sta_id); 5938 5939 D_MAC80211("enable hwcrypto key\n"); 5940 break; 5941 case DISABLE_KEY: 5942 if (is_default_wep_key) 5943 ret = il4965_remove_default_wep_key(il, key); 5944 else 5945 ret = il4965_remove_dynamic_key(il, key, sta_id); 5946 5947 D_MAC80211("disable hwcrypto key\n"); 5948 break; 5949 default: 5950 ret = -EINVAL; 5951 } 5952 5953 mutex_unlock(&il->mutex); 5954 D_MAC80211("leave\n"); 5955 5956 return ret; 5957} 5958 5959int 5960il4965_mac_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 5961 struct ieee80211_ampdu_params *params) 5962{ 5963 struct il_priv *il = hw->priv; 5964 int ret = -EINVAL; 5965 struct ieee80211_sta *sta = params->sta; 5966 enum ieee80211_ampdu_mlme_action action = params->action; 5967 u16 tid = params->tid; 5968 u16 *ssn = ¶ms->ssn; 5969 5970 D_HT("A-MPDU action on addr %pM tid %d\n", sta->addr, tid); 5971 5972 if (!(il->cfg->sku & IL_SKU_N)) 5973 return -EACCES; 5974 5975 mutex_lock(&il->mutex); 5976 5977 switch (action) { 5978 case IEEE80211_AMPDU_RX_START: 5979 D_HT("start Rx\n"); 5980 ret = il4965_sta_rx_agg_start(il, sta, tid, *ssn); 5981 break; 5982 case IEEE80211_AMPDU_RX_STOP: 5983 D_HT("stop Rx\n"); 5984 ret = il4965_sta_rx_agg_stop(il, sta, tid); 5985 if (test_bit(S_EXIT_PENDING, &il->status)) 5986 ret = 0; 5987 break; 5988 case IEEE80211_AMPDU_TX_START: 5989 D_HT("start Tx\n"); 5990 ret = il4965_tx_agg_start(il, vif, sta, tid, ssn); 5991 break; 5992 case IEEE80211_AMPDU_TX_STOP_CONT: 5993 case IEEE80211_AMPDU_TX_STOP_FLUSH: 5994 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT: 5995 D_HT("stop Tx\n"); 5996 ret = il4965_tx_agg_stop(il, vif, sta, tid); 5997 if (test_bit(S_EXIT_PENDING, &il->status)) 5998 ret = 0; 5999 break; 6000 case IEEE80211_AMPDU_TX_OPERATIONAL: 6001 ret = 0; 6002 break; 6003 } 6004 mutex_unlock(&il->mutex); 6005 6006 return ret; 6007} 6008 6009int 6010il4965_mac_sta_add(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 6011 struct ieee80211_sta *sta) 6012{ 6013 struct il_priv *il = hw->priv; 6014 struct il_station_priv *sta_priv = (void *)sta->drv_priv; 6015 bool is_ap = vif->type == NL80211_IFTYPE_STATION; 6016 int ret; 6017 u8 sta_id; 6018 6019 D_INFO("received request to add station %pM\n", sta->addr); 6020 mutex_lock(&il->mutex); 6021 D_INFO("proceeding to add station %pM\n", sta->addr); 6022 sta_priv->common.sta_id = IL_INVALID_STATION; 6023 6024 atomic_set(&sta_priv->pending_frames, 0); 6025 6026 ret = 6027 il_add_station_common(il, sta->addr, is_ap, sta, &sta_id); 6028 if (ret) { 6029 IL_ERR("Unable to add station %pM (%d)\n", sta->addr, ret); 6030 /* Should we return success if return code is EEXIST ? */ 6031 mutex_unlock(&il->mutex); 6032 return ret; 6033 } 6034 6035 sta_priv->common.sta_id = sta_id; 6036 6037 /* Initialize rate scaling */ 6038 D_INFO("Initializing rate scaling for station %pM\n", sta->addr); 6039 il4965_rs_rate_init(il, sta, sta_id); 6040 mutex_unlock(&il->mutex); 6041 6042 return 0; 6043} 6044 6045void 6046il4965_mac_channel_switch(struct ieee80211_hw *hw, struct ieee80211_vif *vif, 6047 struct ieee80211_channel_switch *ch_switch) 6048{ 6049 struct il_priv *il = hw->priv; 6050 const struct il_channel_info *ch_info; 6051 struct ieee80211_conf *conf = &hw->conf; 6052 struct ieee80211_channel *channel = ch_switch->chandef.chan; 6053 struct il_ht_config *ht_conf = &il->current_ht_config; 6054 u16 ch; 6055 6056 D_MAC80211("enter\n"); 6057 6058 mutex_lock(&il->mutex); 6059 6060 if (il_is_rfkill(il)) 6061 goto out; 6062 6063 if (test_bit(S_EXIT_PENDING, &il->status) || 6064 test_bit(S_SCANNING, &il->status) || 6065 test_bit(S_CHANNEL_SWITCH_PENDING, &il->status)) 6066 goto out; 6067 6068 if (!il_is_associated(il)) 6069 goto out; 6070 6071 if (!il->ops->set_channel_switch) 6072 goto out; 6073 6074 ch = channel->hw_value; 6075 if (le16_to_cpu(il->active.channel) == ch) 6076 goto out; 6077 6078 ch_info = il_get_channel_info(il, channel->band, ch); 6079 if (!il_is_channel_valid(ch_info)) { 6080 D_MAC80211("invalid channel\n"); 6081 goto out; 6082 } 6083 6084 spin_lock_irq(&il->lock); 6085 6086 il->current_ht_config.smps = conf->smps_mode; 6087 6088 /* Configure HT40 channels */ 6089 switch (cfg80211_get_chandef_type(&ch_switch->chandef)) { 6090 case NL80211_CHAN_NO_HT: 6091 case NL80211_CHAN_HT20: 6092 il->ht.is_40mhz = false; 6093 il->ht.extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_NONE; 6094 break; 6095 case NL80211_CHAN_HT40MINUS: 6096 il->ht.extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_BELOW; 6097 il->ht.is_40mhz = true; 6098 break; 6099 case NL80211_CHAN_HT40PLUS: 6100 il->ht.extension_chan_offset = IEEE80211_HT_PARAM_CHA_SEC_ABOVE; 6101 il->ht.is_40mhz = true; 6102 break; 6103 } 6104 6105 if ((le16_to_cpu(il->staging.channel) != ch)) 6106 il->staging.flags = 0; 6107 6108 il_set_rxon_channel(il, channel); 6109 il_set_rxon_ht(il, ht_conf); 6110 il_set_flags_for_band(il, channel->band, il->vif); 6111 6112 spin_unlock_irq(&il->lock); 6113 6114 il_set_rate(il); 6115 /* 6116 * at this point, staging_rxon has the 6117 * configuration for channel switch 6118 */ 6119 set_bit(S_CHANNEL_SWITCH_PENDING, &il->status); 6120 il->switch_channel = cpu_to_le16(ch); 6121 if (il->ops->set_channel_switch(il, ch_switch)) { 6122 clear_bit(S_CHANNEL_SWITCH_PENDING, &il->status); 6123 il->switch_channel = 0; 6124 ieee80211_chswitch_done(il->vif, false, 0); 6125 } 6126 6127out: 6128 mutex_unlock(&il->mutex); 6129 D_MAC80211("leave\n"); 6130} 6131 6132void 6133il4965_configure_filter(struct ieee80211_hw *hw, unsigned int changed_flags, 6134 unsigned int *total_flags, u64 multicast) 6135{ 6136 struct il_priv *il = hw->priv; 6137 __le32 filter_or = 0, filter_nand = 0; 6138 6139#define CHK(test, flag) do { \ 6140 if (*total_flags & (test)) \ 6141 filter_or |= (flag); \ 6142 else \ 6143 filter_nand |= (flag); \ 6144 } while (0) 6145 6146 D_MAC80211("Enter: changed: 0x%x, total: 0x%x\n", changed_flags, 6147 *total_flags); 6148 6149 CHK(FIF_OTHER_BSS, RXON_FILTER_PROMISC_MSK); 6150 /* Setting _just_ RXON_FILTER_CTL2HOST_MSK causes FH errors */ 6151 CHK(FIF_CONTROL, RXON_FILTER_CTL2HOST_MSK | RXON_FILTER_PROMISC_MSK); 6152 CHK(FIF_BCN_PRBRESP_PROMISC, RXON_FILTER_BCON_AWARE_MSK); 6153 6154#undef CHK 6155 6156 mutex_lock(&il->mutex); 6157 6158 il->staging.filter_flags &= ~filter_nand; 6159 il->staging.filter_flags |= filter_or; 6160 6161 /* 6162 * Not committing directly because hardware can perform a scan, 6163 * but we'll eventually commit the filter flags change anyway. 6164 */ 6165 6166 mutex_unlock(&il->mutex); 6167 6168 /* 6169 * Receiving all multicast frames is always enabled by the 6170 * default flags setup in il_connection_init_rx_config() 6171 * since we currently do not support programming multicast 6172 * filters into the device. 6173 */ 6174 *total_flags &= 6175 FIF_OTHER_BSS | FIF_ALLMULTI | 6176 FIF_BCN_PRBRESP_PROMISC | FIF_CONTROL; 6177} 6178 6179/***************************************************************************** 6180 * 6181 * driver setup and teardown 6182 * 6183 *****************************************************************************/ 6184 6185static void 6186il4965_bg_txpower_work(struct work_struct *work) 6187{ 6188 struct il_priv *il = container_of(work, struct il_priv, 6189 txpower_work); 6190 6191 mutex_lock(&il->mutex); 6192 6193 /* If a scan happened to start before we got here 6194 * then just return; the stats notification will 6195 * kick off another scheduled work to compensate for 6196 * any temperature delta we missed here. */ 6197 if (test_bit(S_EXIT_PENDING, &il->status) || 6198 test_bit(S_SCANNING, &il->status)) 6199 goto out; 6200 6201 /* Regardless of if we are associated, we must reconfigure the 6202 * TX power since frames can be sent on non-radar channels while 6203 * not associated */ 6204 il->ops->send_tx_power(il); 6205 6206 /* Update last_temperature to keep is_calib_needed from running 6207 * when it isn't needed... */ 6208 il->last_temperature = il->temperature; 6209out: 6210 mutex_unlock(&il->mutex); 6211} 6212 6213static int 6214il4965_setup_deferred_work(struct il_priv *il) 6215{ 6216 il->workqueue = create_singlethread_workqueue(DRV_NAME); 6217 if (!il->workqueue) 6218 return -ENOMEM; 6219 6220 init_waitqueue_head(&il->wait_command_queue); 6221 6222 INIT_WORK(&il->restart, il4965_bg_restart); 6223 INIT_WORK(&il->rx_replenish, il4965_bg_rx_replenish); 6224 INIT_WORK(&il->run_time_calib_work, il4965_bg_run_time_calib_work); 6225 INIT_DELAYED_WORK(&il->init_alive_start, il4965_bg_init_alive_start); 6226 INIT_DELAYED_WORK(&il->alive_start, il4965_bg_alive_start); 6227 6228 il_setup_scan_deferred_work(il); 6229 6230 INIT_WORK(&il->txpower_work, il4965_bg_txpower_work); 6231 6232 timer_setup(&il->stats_periodic, il4965_bg_stats_periodic, 0); 6233 6234 timer_setup(&il->watchdog, il_bg_watchdog, 0); 6235 6236 tasklet_setup(&il->irq_tasklet, il4965_irq_tasklet); 6237 6238 return 0; 6239} 6240 6241static void 6242il4965_cancel_deferred_work(struct il_priv *il) 6243{ 6244 cancel_work_sync(&il->txpower_work); 6245 cancel_delayed_work_sync(&il->init_alive_start); 6246 cancel_delayed_work(&il->alive_start); 6247 cancel_work_sync(&il->run_time_calib_work); 6248 6249 il_cancel_scan_deferred_work(il); 6250 6251 timer_delete_sync(&il->stats_periodic); 6252} 6253 6254static void 6255il4965_init_hw_rates(struct il_priv *il, struct ieee80211_rate *rates) 6256{ 6257 int i; 6258 6259 for (i = 0; i < RATE_COUNT_LEGACY; i++) { 6260 rates[i].bitrate = il_rates[i].ieee * 5; 6261 rates[i].hw_value = i; /* Rate scaling will work on idxes */ 6262 rates[i].hw_value_short = i; 6263 rates[i].flags = 0; 6264 if ((i >= IL_FIRST_CCK_RATE) && (i <= IL_LAST_CCK_RATE)) { 6265 /* 6266 * If CCK != 1M then set short preamble rate flag. 6267 */ 6268 rates[i].flags |= 6269 (il_rates[i].plcp == 6270 RATE_1M_PLCP) ? 0 : IEEE80211_RATE_SHORT_PREAMBLE; 6271 } 6272 } 6273} 6274 6275/* 6276 * Acquire il->lock before calling this function ! 6277 */ 6278void 6279il4965_set_wr_ptrs(struct il_priv *il, int txq_id, u32 idx) 6280{ 6281 il_wr(il, HBUS_TARG_WRPTR, (idx & 0xff) | (txq_id << 8)); 6282 il_wr_prph(il, IL49_SCD_QUEUE_RDPTR(txq_id), idx); 6283} 6284 6285void 6286il4965_tx_queue_set_status(struct il_priv *il, struct il_tx_queue *txq, 6287 int tx_fifo_id, int scd_retry) 6288{ 6289 int txq_id = txq->q.id; 6290 6291 /* Find out whether to activate Tx queue */ 6292 int active = test_bit(txq_id, &il->txq_ctx_active_msk) ? 1 : 0; 6293 6294 /* Set up and activate */ 6295 il_wr_prph(il, IL49_SCD_QUEUE_STATUS_BITS(txq_id), 6296 (active << IL49_SCD_QUEUE_STTS_REG_POS_ACTIVE) | 6297 (tx_fifo_id << IL49_SCD_QUEUE_STTS_REG_POS_TXF) | 6298 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_WSL) | 6299 (scd_retry << IL49_SCD_QUEUE_STTS_REG_POS_SCD_ACK) | 6300 IL49_SCD_QUEUE_STTS_REG_MSK); 6301 6302 txq->sched_retry = scd_retry; 6303 6304 D_INFO("%s %s Queue %d on AC %d\n", active ? "Activate" : "Deactivate", 6305 scd_retry ? "BA" : "AC", txq_id, tx_fifo_id); 6306} 6307 6308static const struct ieee80211_ops il4965_mac_ops = { 6309 .add_chanctx = ieee80211_emulate_add_chanctx, 6310 .remove_chanctx = ieee80211_emulate_remove_chanctx, 6311 .change_chanctx = ieee80211_emulate_change_chanctx, 6312 .switch_vif_chanctx = ieee80211_emulate_switch_vif_chanctx, 6313 .tx = il4965_mac_tx, 6314 .wake_tx_queue = ieee80211_handle_wake_tx_queue, 6315 .start = il4965_mac_start, 6316 .stop = il4965_mac_stop, 6317 .add_interface = il_mac_add_interface, 6318 .remove_interface = il_mac_remove_interface, 6319 .change_interface = il_mac_change_interface, 6320 .config = il_mac_config, 6321 .configure_filter = il4965_configure_filter, 6322 .set_key = il4965_mac_set_key, 6323 .update_tkip_key = il4965_mac_update_tkip_key, 6324 .conf_tx = il_mac_conf_tx, 6325 .reset_tsf = il_mac_reset_tsf, 6326 .bss_info_changed = il_mac_bss_info_changed, 6327 .ampdu_action = il4965_mac_ampdu_action, 6328 .hw_scan = il_mac_hw_scan, 6329 .sta_add = il4965_mac_sta_add, 6330 .sta_remove = il_mac_sta_remove, 6331 .channel_switch = il4965_mac_channel_switch, 6332 .tx_last_beacon = il_mac_tx_last_beacon, 6333 .flush = il_mac_flush, 6334}; 6335 6336static int 6337il4965_init_drv(struct il_priv *il) 6338{ 6339 int ret; 6340 6341 spin_lock_init(&il->sta_lock); 6342 spin_lock_init(&il->hcmd_lock); 6343 6344 INIT_LIST_HEAD(&il->free_frames); 6345 6346 mutex_init(&il->mutex); 6347 6348 il->ieee_channels = NULL; 6349 il->ieee_rates = NULL; 6350 il->band = NL80211_BAND_2GHZ; 6351 6352 il->iw_mode = NL80211_IFTYPE_STATION; 6353 il->current_ht_config.smps = IEEE80211_SMPS_STATIC; 6354 il->missed_beacon_threshold = IL_MISSED_BEACON_THRESHOLD_DEF; 6355 6356 /* initialize force reset */ 6357 il->force_reset.reset_duration = IL_DELAY_NEXT_FORCE_FW_RELOAD; 6358 6359 /* Choose which receivers/antennas to use */ 6360 if (il->ops->set_rxon_chain) 6361 il->ops->set_rxon_chain(il); 6362 6363 il_init_scan_params(il); 6364 6365 ret = il_init_channel_map(il); 6366 if (ret) { 6367 IL_ERR("initializing regulatory failed: %d\n", ret); 6368 goto err; 6369 } 6370 6371 ret = il_init_geos(il); 6372 if (ret) { 6373 IL_ERR("initializing geos failed: %d\n", ret); 6374 goto err_free_channel_map; 6375 } 6376 il4965_init_hw_rates(il, il->ieee_rates); 6377 6378 return 0; 6379 6380err_free_channel_map: 6381 il_free_channel_map(il); 6382err: 6383 return ret; 6384} 6385 6386static void 6387il4965_uninit_drv(struct il_priv *il) 6388{ 6389 il_free_geos(il); 6390 il_free_channel_map(il); 6391 kfree(il->scan_cmd); 6392} 6393 6394static void 6395il4965_hw_detect(struct il_priv *il) 6396{ 6397 il->hw_rev = _il_rd(il, CSR_HW_REV); 6398 il->hw_wa_rev = _il_rd(il, CSR_HW_REV_WA_REG); 6399 il->rev_id = il->pci_dev->revision; 6400 D_INFO("HW Revision ID = 0x%X\n", il->rev_id); 6401} 6402 6403static const struct il_sensitivity_ranges il4965_sensitivity = { 6404 .min_nrg_cck = 97, 6405 .max_nrg_cck = 0, /* not used, set to 0 */ 6406 6407 .auto_corr_min_ofdm = 85, 6408 .auto_corr_min_ofdm_mrc = 170, 6409 .auto_corr_min_ofdm_x1 = 105, 6410 .auto_corr_min_ofdm_mrc_x1 = 220, 6411 6412 .auto_corr_max_ofdm = 120, 6413 .auto_corr_max_ofdm_mrc = 210, 6414 .auto_corr_max_ofdm_x1 = 140, 6415 .auto_corr_max_ofdm_mrc_x1 = 270, 6416 6417 .auto_corr_min_cck = 125, 6418 .auto_corr_max_cck = 200, 6419 .auto_corr_min_cck_mrc = 200, 6420 .auto_corr_max_cck_mrc = 400, 6421 6422 .nrg_th_cck = 100, 6423 .nrg_th_ofdm = 100, 6424 6425 .barker_corr_th_min = 190, 6426 .barker_corr_th_min_mrc = 390, 6427 .nrg_th_cca = 62, 6428}; 6429 6430static void 6431il4965_set_hw_params(struct il_priv *il) 6432{ 6433 il->hw_params.bcast_id = IL4965_BROADCAST_ID; 6434 il->hw_params.max_rxq_size = RX_QUEUE_SIZE; 6435 il->hw_params.max_rxq_log = RX_QUEUE_SIZE_LOG; 6436 if (il->cfg->mod_params->amsdu_size_8K) 6437 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_8K); 6438 else 6439 il->hw_params.rx_page_order = get_order(IL_RX_BUF_SIZE_4K); 6440 6441 il->hw_params.max_beacon_itrvl = IL_MAX_UCODE_BEACON_INTERVAL; 6442 6443 if (il->cfg->mod_params->disable_11n) 6444 il->cfg->sku &= ~IL_SKU_N; 6445 6446 if (il->cfg->mod_params->num_of_queues >= IL_MIN_NUM_QUEUES && 6447 il->cfg->mod_params->num_of_queues <= IL49_NUM_QUEUES) 6448 il->cfg->num_of_queues = 6449 il->cfg->mod_params->num_of_queues; 6450 6451 il->hw_params.max_txq_num = il->cfg->num_of_queues; 6452 il->hw_params.dma_chnl_num = FH49_TCSR_CHNL_NUM; 6453 il->hw_params.scd_bc_tbls_size = 6454 il->cfg->num_of_queues * 6455 sizeof(struct il4965_scd_bc_tbl); 6456 6457 il->hw_params.tfd_size = sizeof(struct il_tfd); 6458 il->hw_params.max_stations = IL4965_STATION_COUNT; 6459 il->hw_params.max_data_size = IL49_RTC_DATA_SIZE; 6460 il->hw_params.max_inst_size = IL49_RTC_INST_SIZE; 6461 il->hw_params.max_bsm_size = BSM_SRAM_SIZE; 6462 il->hw_params.ht40_channel = BIT(NL80211_BAND_5GHZ); 6463 6464 il->hw_params.rx_wrt_ptr_reg = FH49_RSCSR_CHNL0_WPTR; 6465 6466 il->hw_params.tx_chains_num = il4965_num_of_ant(il->cfg->valid_tx_ant); 6467 il->hw_params.rx_chains_num = il4965_num_of_ant(il->cfg->valid_rx_ant); 6468 il->hw_params.valid_tx_ant = il->cfg->valid_tx_ant; 6469 il->hw_params.valid_rx_ant = il->cfg->valid_rx_ant; 6470 6471 il->hw_params.ct_kill_threshold = 6472 celsius_to_kelvin(CT_KILL_THRESHOLD_LEGACY); 6473 6474 il->hw_params.sens = &il4965_sensitivity; 6475 il->hw_params.beacon_time_tsf_bits = IL4965_EXT_BEACON_TIME_POS; 6476} 6477 6478static int 6479il4965_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent) 6480{ 6481 int err = 0; 6482 struct il_priv *il; 6483 struct ieee80211_hw *hw; 6484 struct il_cfg *cfg = (struct il_cfg *)(ent->driver_data); 6485 unsigned long flags; 6486 u16 pci_cmd; 6487 6488 /************************ 6489 * 1. Allocating HW data 6490 ************************/ 6491 6492 hw = ieee80211_alloc_hw(sizeof(struct il_priv), &il4965_mac_ops); 6493 if (!hw) { 6494 err = -ENOMEM; 6495 goto out; 6496 } 6497 il = hw->priv; 6498 il->hw = hw; 6499 SET_IEEE80211_DEV(hw, &pdev->dev); 6500 6501 D_INFO("*** LOAD DRIVER ***\n"); 6502 il->cfg = cfg; 6503 il->ops = &il4965_ops; 6504#ifdef CONFIG_IWLEGACY_DEBUGFS 6505 il->debugfs_ops = &il4965_debugfs_ops; 6506#endif 6507 il->pci_dev = pdev; 6508 il->inta_mask = CSR_INI_SET_MASK; 6509 6510 /************************** 6511 * 2. Initializing PCI bus 6512 **************************/ 6513 pci_disable_link_state(pdev, 6514 PCIE_LINK_STATE_L0S | PCIE_LINK_STATE_L1 | 6515 PCIE_LINK_STATE_CLKPM); 6516 6517 if (pci_enable_device(pdev)) { 6518 err = -ENODEV; 6519 goto out_ieee80211_free_hw; 6520 } 6521 6522 pci_set_master(pdev); 6523 6524 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(36)); 6525 if (err) { 6526 err = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 6527 /* both attempts failed: */ 6528 if (err) { 6529 IL_WARN("No suitable DMA available.\n"); 6530 goto out_pci_disable_device; 6531 } 6532 } 6533 6534 err = pci_request_regions(pdev, DRV_NAME); 6535 if (err) 6536 goto out_pci_disable_device; 6537 6538 pci_set_drvdata(pdev, il); 6539 6540 /*********************** 6541 * 3. Read REV register 6542 ***********************/ 6543 il->hw_base = pci_ioremap_bar(pdev, 0); 6544 if (!il->hw_base) { 6545 err = -ENODEV; 6546 goto out_pci_release_regions; 6547 } 6548 6549 D_INFO("pci_resource_len = 0x%08llx\n", 6550 (unsigned long long)pci_resource_len(pdev, 0)); 6551 D_INFO("pci_resource_base = %p\n", il->hw_base); 6552 6553 /* these spin locks will be used in apm_ops.init and EEPROM access 6554 * we should init now 6555 */ 6556 spin_lock_init(&il->reg_lock); 6557 spin_lock_init(&il->lock); 6558 6559 /* 6560 * stop and reset the on-board processor just in case it is in a 6561 * strange state ... like being left stranded by a primary kernel 6562 * and this is now the kdump kernel trying to start up 6563 */ 6564 _il_wr(il, CSR_RESET, CSR_RESET_REG_FLAG_NEVO_RESET); 6565 6566 il4965_hw_detect(il); 6567 IL_INFO("Detected %s, REV=0x%X\n", il->cfg->name, il->hw_rev); 6568 6569 /* We disable the RETRY_TIMEOUT register (0x41) to keep 6570 * PCI Tx retries from interfering with C3 CPU state */ 6571 pci_write_config_byte(pdev, PCI_CFG_RETRY_TIMEOUT, 0x00); 6572 6573 il4965_prepare_card_hw(il); 6574 if (!il->hw_ready) { 6575 IL_WARN("Failed, HW not ready\n"); 6576 err = -EIO; 6577 goto out_iounmap; 6578 } 6579 6580 /***************** 6581 * 4. Read EEPROM 6582 *****************/ 6583 /* Read the EEPROM */ 6584 err = il_eeprom_init(il); 6585 if (err) { 6586 IL_ERR("Unable to init EEPROM\n"); 6587 goto out_iounmap; 6588 } 6589 err = il4965_eeprom_check_version(il); 6590 if (err) 6591 goto out_free_eeprom; 6592 6593 /* extract MAC Address */ 6594 il4965_eeprom_get_mac(il, il->addresses[0].addr); 6595 D_INFO("MAC address: %pM\n", il->addresses[0].addr); 6596 il->hw->wiphy->addresses = il->addresses; 6597 il->hw->wiphy->n_addresses = 1; 6598 6599 /************************ 6600 * 5. Setup HW constants 6601 ************************/ 6602 il4965_set_hw_params(il); 6603 6604 /******************* 6605 * 6. Setup il 6606 *******************/ 6607 6608 err = il4965_init_drv(il); 6609 if (err) 6610 goto out_free_eeprom; 6611 /* At this point both hw and il are initialized. */ 6612 6613 /******************** 6614 * 7. Setup services 6615 ********************/ 6616 spin_lock_irqsave(&il->lock, flags); 6617 il_disable_interrupts(il); 6618 spin_unlock_irqrestore(&il->lock, flags); 6619 6620 pci_enable_msi(il->pci_dev); 6621 6622 err = request_irq(il->pci_dev->irq, il_isr, IRQF_SHARED, DRV_NAME, il); 6623 if (err) { 6624 IL_ERR("Error allocating IRQ %d\n", il->pci_dev->irq); 6625 goto out_disable_msi; 6626 } 6627 6628 err = il4965_setup_deferred_work(il); 6629 if (err) 6630 goto out_free_irq; 6631 6632 il4965_setup_handlers(il); 6633 6634 /********************************************* 6635 * 8. Enable interrupts and read RFKILL state 6636 *********************************************/ 6637 6638 /* enable rfkill interrupt: hw bug w/a */ 6639 pci_read_config_word(il->pci_dev, PCI_COMMAND, &pci_cmd); 6640 if (pci_cmd & PCI_COMMAND_INTX_DISABLE) { 6641 pci_cmd &= ~PCI_COMMAND_INTX_DISABLE; 6642 pci_write_config_word(il->pci_dev, PCI_COMMAND, pci_cmd); 6643 } 6644 6645 il_enable_rfkill_int(il); 6646 6647 /* If platform's RF_KILL switch is NOT set to KILL */ 6648 if (_il_rd(il, CSR_GP_CNTRL) & CSR_GP_CNTRL_REG_FLAG_HW_RF_KILL_SW) 6649 clear_bit(S_RFKILL, &il->status); 6650 else 6651 set_bit(S_RFKILL, &il->status); 6652 6653 wiphy_rfkill_set_hw_state(il->hw->wiphy, 6654 test_bit(S_RFKILL, &il->status)); 6655 6656 il_power_initialize(il); 6657 6658 init_completion(&il->_4965.firmware_loading_complete); 6659 6660 err = il4965_request_firmware(il, true); 6661 if (err) 6662 goto out_destroy_workqueue; 6663 6664 return 0; 6665 6666out_destroy_workqueue: 6667 destroy_workqueue(il->workqueue); 6668 il->workqueue = NULL; 6669out_free_irq: 6670 free_irq(il->pci_dev->irq, il); 6671out_disable_msi: 6672 pci_disable_msi(il->pci_dev); 6673 il4965_uninit_drv(il); 6674out_free_eeprom: 6675 il_eeprom_free(il); 6676out_iounmap: 6677 iounmap(il->hw_base); 6678out_pci_release_regions: 6679 pci_release_regions(pdev); 6680out_pci_disable_device: 6681 pci_disable_device(pdev); 6682out_ieee80211_free_hw: 6683 ieee80211_free_hw(il->hw); 6684out: 6685 return err; 6686} 6687 6688static void 6689il4965_pci_remove(struct pci_dev *pdev) 6690{ 6691 struct il_priv *il = pci_get_drvdata(pdev); 6692 unsigned long flags; 6693 6694 if (!il) 6695 return; 6696 6697 wait_for_completion(&il->_4965.firmware_loading_complete); 6698 6699 D_INFO("*** UNLOAD DRIVER ***\n"); 6700 6701 il_dbgfs_unregister(il); 6702 sysfs_remove_group(&pdev->dev.kobj, &il_attribute_group); 6703 6704 /* ieee80211_unregister_hw call wil cause il_mac_stop to 6705 * be called and il4965_down since we are removing the device 6706 * we need to set S_EXIT_PENDING bit. 6707 */ 6708 set_bit(S_EXIT_PENDING, &il->status); 6709 6710 il_leds_exit(il); 6711 6712 if (il->mac80211_registered) { 6713 ieee80211_unregister_hw(il->hw); 6714 il->mac80211_registered = 0; 6715 } else { 6716 il4965_down(il); 6717 } 6718 6719 /* 6720 * Make sure device is reset to low power before unloading driver. 6721 * This may be redundant with il4965_down(), but there are paths to 6722 * run il4965_down() without calling apm_ops.stop(), and there are 6723 * paths to avoid running il4965_down() at all before leaving driver. 6724 * This (inexpensive) call *makes sure* device is reset. 6725 */ 6726 il_apm_stop(il); 6727 6728 /* make sure we flush any pending irq or 6729 * tasklet for the driver 6730 */ 6731 spin_lock_irqsave(&il->lock, flags); 6732 il_disable_interrupts(il); 6733 spin_unlock_irqrestore(&il->lock, flags); 6734 6735 il4965_synchronize_irq(il); 6736 6737 il4965_dealloc_ucode_pci(il); 6738 6739 if (il->rxq.bd) 6740 il4965_rx_queue_free(il, &il->rxq); 6741 il4965_hw_txq_ctx_free(il); 6742 6743 il_eeprom_free(il); 6744 6745 /*netif_stop_queue(dev); */ 6746 6747 /* ieee80211_unregister_hw calls il_mac_stop, which flushes 6748 * il->workqueue... so we can't take down the workqueue 6749 * until now... */ 6750 destroy_workqueue(il->workqueue); 6751 il->workqueue = NULL; 6752 6753 free_irq(il->pci_dev->irq, il); 6754 pci_disable_msi(il->pci_dev); 6755 iounmap(il->hw_base); 6756 pci_release_regions(pdev); 6757 pci_disable_device(pdev); 6758 6759 il4965_uninit_drv(il); 6760 6761 dev_kfree_skb(il->beacon_skb); 6762 6763 ieee80211_free_hw(il->hw); 6764} 6765 6766/* 6767 * Activate/Deactivate Tx DMA/FIFO channels according tx fifos mask 6768 * must be called under il->lock and mac access 6769 */ 6770void 6771il4965_txq_set_sched(struct il_priv *il, u32 mask) 6772{ 6773 il_wr_prph(il, IL49_SCD_TXFACT, mask); 6774} 6775 6776/***************************************************************************** 6777 * 6778 * driver and module entry point 6779 * 6780 *****************************************************************************/ 6781 6782/* Hardware specific file defines the PCI IDs table for that hardware module */ 6783static const struct pci_device_id il4965_hw_card_ids[] = { 6784 {IL_PCI_DEVICE(0x4229, PCI_ANY_ID, il4965_cfg)}, 6785 {IL_PCI_DEVICE(0x4230, PCI_ANY_ID, il4965_cfg)}, 6786 {0} 6787}; 6788MODULE_DEVICE_TABLE(pci, il4965_hw_card_ids); 6789 6790static struct pci_driver il4965_driver = { 6791 .name = DRV_NAME, 6792 .id_table = il4965_hw_card_ids, 6793 .probe = il4965_pci_probe, 6794 .remove = il4965_pci_remove, 6795 .driver.pm = IL_LEGACY_PM_OPS, 6796}; 6797 6798static int __init 6799il4965_init(void) 6800{ 6801 6802 int ret; 6803 pr_info(DRV_DESCRIPTION ", " DRV_VERSION "\n"); 6804 pr_info(DRV_COPYRIGHT "\n"); 6805 6806 ret = il4965_rate_control_register(); 6807 if (ret) { 6808 pr_err("Unable to register rate control algorithm: %d\n", ret); 6809 return ret; 6810 } 6811 6812 ret = pci_register_driver(&il4965_driver); 6813 if (ret) { 6814 pr_err("Unable to initialize PCI module\n"); 6815 goto error_register; 6816 } 6817 6818 return ret; 6819 6820error_register: 6821 il4965_rate_control_unregister(); 6822 return ret; 6823} 6824 6825static void __exit 6826il4965_exit(void) 6827{ 6828 pci_unregister_driver(&il4965_driver); 6829 il4965_rate_control_unregister(); 6830} 6831 6832module_exit(il4965_exit); 6833module_init(il4965_init); 6834 6835#ifdef CONFIG_IWLEGACY_DEBUG 6836module_param_named(debug, il_debug_level, uint, 0644); 6837MODULE_PARM_DESC(debug, "debug output mask"); 6838#endif 6839 6840module_param_named(swcrypto, il4965_mod_params.sw_crypto, int, 0444); 6841MODULE_PARM_DESC(swcrypto, "using crypto in software (default 0 [hardware])"); 6842module_param_named(queues_num, il4965_mod_params.num_of_queues, int, 0444); 6843MODULE_PARM_DESC(queues_num, "number of hw queues."); 6844module_param_named(11n_disable, il4965_mod_params.disable_11n, int, 0444); 6845MODULE_PARM_DESC(11n_disable, "disable 11n functionality"); 6846module_param_named(amsdu_size_8K, il4965_mod_params.amsdu_size_8K, int, 0444); 6847MODULE_PARM_DESC(amsdu_size_8K, "enable 8K amsdu size (default 0 [disabled])"); 6848module_param_named(fw_restart, il4965_mod_params.restart_fw, int, 0444); 6849MODULE_PARM_DESC(fw_restart, "restart firmware in case of error");
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