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sdio.c
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linux-6.19.14/drivers/net/wireless/broadcom/brcm80211/brcmfmac/sdio.c
1// SPDX-License-Identifier: ISC 2/* 3 * Copyright (c) 2010 Broadcom Corporation 4 */ 5 6#include <linux/types.h> 7#include <linux/atomic.h> 8#include <linux/kernel.h> 9#include <linux/kthread.h> 10#include <linux/printk.h> 11#include <linux/pci_ids.h> 12#include <linux/netdevice.h> 13#include <linux/interrupt.h> 14#include <linux/sched/signal.h> 15#include <linux/mmc/sdio.h> 16#include <linux/mmc/sdio_ids.h> 17#include <linux/mmc/sdio_func.h> 18#include <linux/mmc/card.h> 19#include <linux/mmc/core.h> 20#include <linux/semaphore.h> 21#include <linux/firmware.h> 22#include <linux/module.h> 23#include <linux/bcma/bcma.h> 24#include <linux/debugfs.h> 25#include <linux/vmalloc.h> 26#include <linux/unaligned.h> 27#include <defs.h> 28#include <brcmu_wifi.h> 29#include <brcmu_utils.h> 30#include <brcm_hw_ids.h> 31#include <soc.h> 32#include "sdio.h" 33#include "chip.h" 34#include "firmware.h" 35#include "core.h" 36#include "common.h" 37#include "bcdc.h" 38 39#define DCMD_RESP_TIMEOUT msecs_to_jiffies(2500) 40#define CTL_DONE_TIMEOUT msecs_to_jiffies(2500) 41 42/* watermark expressed in number of words */ 43#define DEFAULT_F2_WATERMARK 0x8 44#define CY_4373_F2_WATERMARK 0x40 45#define CY_4373_F1_MESBUSYCTRL (CY_4373_F2_WATERMARK | SBSDIO_MESBUSYCTRL_ENAB) 46#define CY_43012_F2_WATERMARK 0x60 47#define CY_43012_MES_WATERMARK 0x50 48#define CY_43012_MESBUSYCTRL (CY_43012_MES_WATERMARK | \ 49 SBSDIO_MESBUSYCTRL_ENAB) 50#define CY_4339_F2_WATERMARK 48 51#define CY_4339_MES_WATERMARK 80 52#define CY_4339_MESBUSYCTRL (CY_4339_MES_WATERMARK | \ 53 SBSDIO_MESBUSYCTRL_ENAB) 54#define CY_43455_F2_WATERMARK 0x60 55#define CY_43455_MES_WATERMARK 0x50 56#define CY_43455_MESBUSYCTRL (CY_43455_MES_WATERMARK | \ 57 SBSDIO_MESBUSYCTRL_ENAB) 58#define CY_435X_F2_WATERMARK 0x40 59#define CY_435X_F1_MESBUSYCTRL (CY_435X_F2_WATERMARK | \ 60 SBSDIO_MESBUSYCTRL_ENAB) 61 62#ifdef DEBUG 63 64#define BRCMF_TRAP_INFO_SIZE 80 65 66#define CBUF_LEN (128) 67 68/* Device console log buffer state */ 69#define CONSOLE_BUFFER_MAX 2024 70 71struct rte_log_le { 72 __le32 buf; /* Can't be pointer on (64-bit) hosts */ 73 __le32 buf_size; 74 __le32 idx; 75 char *_buf_compat; /* Redundant pointer for backward compat. */ 76}; 77 78struct rte_console { 79 /* Virtual UART 80 * When there is no UART (e.g. Quickturn), 81 * the host should write a complete 82 * input line directly into cbuf and then write 83 * the length into vcons_in. 84 * This may also be used when there is a real UART 85 * (at risk of conflicting with 86 * the real UART). vcons_out is currently unused. 87 */ 88 uint vcons_in; 89 uint vcons_out; 90 91 /* Output (logging) buffer 92 * Console output is written to a ring buffer log_buf at index log_idx. 93 * The host may read the output when it sees log_idx advance. 94 * Output will be lost if the output wraps around faster than the host 95 * polls. 96 */ 97 struct rte_log_le log_le; 98 99 /* Console input line buffer 100 * Characters are read one at a time into cbuf 101 * until <CR> is received, then 102 * the buffer is processed as a command line. 103 * Also used for virtual UART. 104 */ 105 uint cbuf_idx; 106 char cbuf[CBUF_LEN]; 107}; 108 109#endif /* DEBUG */ 110#include <chipcommon.h> 111 112#include "bus.h" 113#include "debug.h" 114#include "tracepoint.h" 115 116#define TXQLEN 2048 /* bulk tx queue length */ 117#define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */ 118#define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */ 119#define PRIOMASK 7 120 121#define TXRETRIES 2 /* # of retries for tx frames */ 122 123#define BRCMF_RXBOUND 50 /* Default for max rx frames in 124 one scheduling */ 125 126#define BRCMF_TXBOUND 20 /* Default for max tx frames in 127 one scheduling */ 128 129#define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */ 130 131#define MEMBLOCK 2048 /* Block size used for downloading 132 of dongle image */ 133#define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold 134 biggest possible glom */ 135 136#define BRCMF_FIRSTREAD (1 << 6) 137 138/* SBSDIO_DEVICE_CTL */ 139 140/* 1: device will assert busy signal when receiving CMD53 */ 141#define SBSDIO_DEVCTL_SETBUSY 0x01 142/* 1: assertion of sdio interrupt is synchronous to the sdio clock */ 143#define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02 144/* 1: mask all interrupts to host except the chipActive (rev 8) */ 145#define SBSDIO_DEVCTL_CA_INT_ONLY 0x04 146/* 1: isolate internal sdio signals, put external pads in tri-state; requires 147 * sdio bus power cycle to clear (rev 9) */ 148#define SBSDIO_DEVCTL_PADS_ISO 0x08 149/* 1: enable F2 Watermark */ 150#define SBSDIO_DEVCTL_F2WM_ENAB 0x10 151/* Force SD->SB reset mapping (rev 11) */ 152#define SBSDIO_DEVCTL_SB_RST_CTL 0x30 153/* Determined by CoreControl bit */ 154#define SBSDIO_DEVCTL_RST_CORECTL 0x00 155/* Force backplane reset */ 156#define SBSDIO_DEVCTL_RST_BPRESET 0x10 157/* Force no backplane reset */ 158#define SBSDIO_DEVCTL_RST_NOBPRESET 0x20 159 160/* direct(mapped) cis space */ 161 162/* MAPPED common CIS address */ 163#define SBSDIO_CIS_BASE_COMMON 0x1000 164/* maximum bytes in one CIS */ 165#define SBSDIO_CIS_SIZE_LIMIT 0x200 166/* cis offset addr is < 17 bits */ 167#define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF 168 169/* manfid tuple length, include tuple, link bytes */ 170#define SBSDIO_CIS_MANFID_TUPLE_LEN 6 171 172#define SD_REG(field) \ 173 (offsetof(struct sdpcmd_regs, field)) 174 175/* SDIO function 1 register CHIPCLKCSR */ 176/* Force ALP request to backplane */ 177#define SBSDIO_FORCE_ALP 0x01 178/* Force HT request to backplane */ 179#define SBSDIO_FORCE_HT 0x02 180/* Force ILP request to backplane */ 181#define SBSDIO_FORCE_ILP 0x04 182/* Make ALP ready (power up xtal) */ 183#define SBSDIO_ALP_AVAIL_REQ 0x08 184/* Make HT ready (power up PLL) */ 185#define SBSDIO_HT_AVAIL_REQ 0x10 186/* Squelch clock requests from HW */ 187#define SBSDIO_FORCE_HW_CLKREQ_OFF 0x20 188/* Status: ALP is ready */ 189#define SBSDIO_ALP_AVAIL 0x40 190/* Status: HT is ready */ 191#define SBSDIO_HT_AVAIL 0x80 192#define SBSDIO_CSR_MASK 0x1F 193#define SBSDIO_AVBITS (SBSDIO_HT_AVAIL | SBSDIO_ALP_AVAIL) 194#define SBSDIO_ALPAV(regval) ((regval) & SBSDIO_AVBITS) 195#define SBSDIO_HTAV(regval) (((regval) & SBSDIO_AVBITS) == SBSDIO_AVBITS) 196#define SBSDIO_ALPONLY(regval) (SBSDIO_ALPAV(regval) && !SBSDIO_HTAV(regval)) 197#define SBSDIO_CLKAV(regval, alponly) \ 198 (SBSDIO_ALPAV(regval) && (alponly ? 1 : SBSDIO_HTAV(regval))) 199 200/* intstatus */ 201#define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */ 202#define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */ 203#define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */ 204#define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */ 205#define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */ 206#define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */ 207#define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */ 208#define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */ 209#define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */ 210#define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */ 211#define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */ 212#define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */ 213#define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */ 214#define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */ 215#define I_PC (1 << 10) /* descriptor error */ 216#define I_PD (1 << 11) /* data error */ 217#define I_DE (1 << 12) /* Descriptor protocol Error */ 218#define I_RU (1 << 13) /* Receive descriptor Underflow */ 219#define I_RO (1 << 14) /* Receive fifo Overflow */ 220#define I_XU (1 << 15) /* Transmit fifo Underflow */ 221#define I_RI (1 << 16) /* Receive Interrupt */ 222#define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */ 223#define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */ 224#define I_XI (1 << 24) /* Transmit Interrupt */ 225#define I_RF_TERM (1 << 25) /* Read Frame Terminate */ 226#define I_WF_TERM (1 << 26) /* Write Frame Terminate */ 227#define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */ 228#define I_SBINT (1 << 28) /* sbintstatus Interrupt */ 229#define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */ 230#define I_SRESET (1 << 30) /* CCCR RES interrupt */ 231#define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */ 232#define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU) 233#define I_DMA (I_RI | I_XI | I_ERRORS) 234 235/* corecontrol */ 236#define CC_CISRDY (1 << 0) /* CIS Ready */ 237#define CC_BPRESEN (1 << 1) /* CCCR RES signal */ 238#define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */ 239#define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */ 240#define CC_XMTDATAAVAIL_MODE (1 << 4) 241#define CC_XMTDATAAVAIL_CTRL (1 << 5) 242 243/* SDA_FRAMECTRL */ 244#define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */ 245#define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */ 246#define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */ 247#define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */ 248 249/* 250 * Software allocation of To SB Mailbox resources 251 */ 252 253/* tosbmailbox bits corresponding to intstatus bits */ 254#define SMB_NAK (1 << 0) /* Frame NAK */ 255#define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */ 256#define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */ 257#define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */ 258 259/* tosbmailboxdata */ 260#define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */ 261 262/* 263 * Software allocation of To Host Mailbox resources 264 */ 265 266/* intstatus bits */ 267#define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */ 268#define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */ 269#define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */ 270#define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */ 271 272/* tohostmailboxdata */ 273#define HMB_DATA_NAKHANDLED 0x0001 /* retransmit NAK'd frame */ 274#define HMB_DATA_DEVREADY 0x0002 /* talk to host after enable */ 275#define HMB_DATA_FC 0x0004 /* per prio flowcontrol update flag */ 276#define HMB_DATA_FWREADY 0x0008 /* fw ready for protocol activity */ 277#define HMB_DATA_FWHALT 0x0010 /* firmware halted */ 278 279#define HMB_DATA_FCDATA_MASK 0xff000000 280#define HMB_DATA_FCDATA_SHIFT 24 281 282#define HMB_DATA_VERSION_MASK 0x00ff0000 283#define HMB_DATA_VERSION_SHIFT 16 284 285/* 286 * Software-defined protocol header 287 */ 288 289/* Current protocol version */ 290#define SDPCM_PROT_VERSION 4 291 292/* 293 * Shared structure between dongle and the host. 294 * The structure contains pointers to trap or assert information. 295 */ 296#define SDPCM_SHARED_VERSION 0x0003 297#define SDPCM_SHARED_VERSION_MASK 0x00FF 298#define SDPCM_SHARED_ASSERT_BUILT 0x0100 299#define SDPCM_SHARED_ASSERT 0x0200 300#define SDPCM_SHARED_TRAP 0x0400 301 302/* Space for header read, limit for data packets */ 303#define MAX_HDR_READ (1 << 6) 304#define MAX_RX_DATASZ 2048 305 306/* Bump up limit on waiting for HT to account for first startup; 307 * if the image is doing a CRC calculation before programming the PMU 308 * for HT availability, it could take a couple hundred ms more, so 309 * max out at a 1 second (1000000us). 310 */ 311#undef PMU_MAX_TRANSITION_DLY 312#define PMU_MAX_TRANSITION_DLY 1000000 313 314/* Value for ChipClockCSR during initial setup */ 315#define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \ 316 SBSDIO_ALP_AVAIL_REQ) 317 318/* Flags for SDH calls */ 319#define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED) 320 321#define BRCMF_IDLE_ACTIVE 0 /* Do not request any SD clock change 322 * when idle 323 */ 324#define BRCMF_IDLE_INTERVAL 1 325 326#define KSO_WAIT_US 50 327#define MAX_KSO_ATTEMPTS (PMU_MAX_TRANSITION_DLY/KSO_WAIT_US) 328#define BRCMF_SDIO_MAX_ACCESS_ERRORS 5 329 330#ifdef DEBUG 331/* Device console log buffer state */ 332struct brcmf_console { 333 uint count; /* Poll interval msec counter */ 334 uint log_addr; /* Log struct address (fixed) */ 335 struct rte_log_le log_le; /* Log struct (host copy) */ 336 uint bufsize; /* Size of log buffer */ 337 u8 *buf; /* Log buffer (host copy) */ 338 uint last; /* Last buffer read index */ 339}; 340 341struct brcmf_trap_info { 342 __le32 type; 343 __le32 epc; 344 __le32 cpsr; 345 __le32 spsr; 346 __le32 r0; /* a1 */ 347 __le32 r1; /* a2 */ 348 __le32 r2; /* a3 */ 349 __le32 r3; /* a4 */ 350 __le32 r4; /* v1 */ 351 __le32 r5; /* v2 */ 352 __le32 r6; /* v3 */ 353 __le32 r7; /* v4 */ 354 __le32 r8; /* v5 */ 355 __le32 r9; /* sb/v6 */ 356 __le32 r10; /* sl/v7 */ 357 __le32 r11; /* fp/v8 */ 358 __le32 r12; /* ip */ 359 __le32 r13; /* sp */ 360 __le32 r14; /* lr */ 361 __le32 pc; /* r15 */ 362}; 363#endif /* DEBUG */ 364 365struct sdpcm_shared { 366 u32 flags; 367 u32 trap_addr; 368 u32 assert_exp_addr; 369 u32 assert_file_addr; 370 u32 assert_line; 371 u32 console_addr; /* Address of struct rte_console */ 372 u32 msgtrace_addr; 373 u8 tag[32]; 374 u32 brpt_addr; 375}; 376 377struct sdpcm_shared_le { 378 __le32 flags; 379 __le32 trap_addr; 380 __le32 assert_exp_addr; 381 __le32 assert_file_addr; 382 __le32 assert_line; 383 __le32 console_addr; /* Address of struct rte_console */ 384 __le32 msgtrace_addr; 385 u8 tag[32]; 386 __le32 brpt_addr; 387}; 388 389/* dongle SDIO bus specific header info */ 390struct brcmf_sdio_hdrinfo { 391 u8 seq_num; 392 u8 channel; 393 u16 len; 394 u16 len_left; 395 u16 len_nxtfrm; 396 u8 dat_offset; 397 bool lastfrm; 398 u16 tail_pad; 399}; 400 401/* 402 * hold counter variables 403 */ 404struct brcmf_sdio_count { 405 uint intrcount; /* Count of device interrupt callbacks */ 406 uint lastintrs; /* Count as of last watchdog timer */ 407 uint pollcnt; /* Count of active polls */ 408 uint regfails; /* Count of R_REG failures */ 409 uint tx_sderrs; /* Count of tx attempts with sd errors */ 410 uint fcqueued; /* Tx packets that got queued */ 411 uint rxrtx; /* Count of rtx requests (NAK to dongle) */ 412 uint rx_toolong; /* Receive frames too long to receive */ 413 uint rxc_errors; /* SDIO errors when reading control frames */ 414 uint rx_hdrfail; /* SDIO errors on header reads */ 415 uint rx_badhdr; /* Bad received headers (roosync?) */ 416 uint rx_badseq; /* Mismatched rx sequence number */ 417 uint fc_rcvd; /* Number of flow-control events received */ 418 uint fc_xoff; /* Number which turned on flow-control */ 419 uint fc_xon; /* Number which turned off flow-control */ 420 uint rxglomfail; /* Failed deglom attempts */ 421 uint rxglomframes; /* Number of glom frames (superframes) */ 422 uint rxglompkts; /* Number of packets from glom frames */ 423 uint f2rxhdrs; /* Number of header reads */ 424 uint f2rxdata; /* Number of frame data reads */ 425 uint f2txdata; /* Number of f2 frame writes */ 426 uint f1regdata; /* Number of f1 register accesses */ 427 uint tickcnt; /* Number of watchdog been schedule */ 428 ulong tx_ctlerrs; /* Err of sending ctrl frames */ 429 ulong tx_ctlpkts; /* Ctrl frames sent to dongle */ 430 ulong rx_ctlerrs; /* Err of processing rx ctrl frames */ 431 ulong rx_ctlpkts; /* Ctrl frames processed from dongle */ 432 ulong rx_readahead_cnt; /* packets where header read-ahead was used */ 433}; 434 435/* misc chip info needed by some of the routines */ 436/* Private data for SDIO bus interaction */ 437struct brcmf_sdio { 438 struct brcmf_sdio_dev *sdiodev; /* sdio device handler */ 439 struct brcmf_chip *ci; /* Chip info struct */ 440 struct brcmf_core *sdio_core; /* sdio core info struct */ 441 442 u32 hostintmask; /* Copy of Host Interrupt Mask */ 443 atomic_t intstatus; /* Intstatus bits (events) pending */ 444 atomic_t fcstate; /* State of dongle flow-control */ 445 446 uint blocksize; /* Block size of SDIO transfers */ 447 uint roundup; /* Max roundup limit */ 448 449 struct pktq txq; /* Queue length used for flow-control */ 450 u8 flowcontrol; /* per prio flow control bitmask */ 451 u8 tx_seq; /* Transmit sequence number (next) */ 452 u8 tx_max; /* Maximum transmit sequence allowed */ 453 454 u8 *hdrbuf; /* buffer for handling rx frame */ 455 u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */ 456 u8 rx_seq; /* Receive sequence number (expected) */ 457 struct brcmf_sdio_hdrinfo cur_read; 458 /* info of current read frame */ 459 bool rxskip; /* Skip receive (awaiting NAK ACK) */ 460 bool rxpending; /* Data frame pending in dongle */ 461 462 uint rxbound; /* Rx frames to read before resched */ 463 uint txbound; /* Tx frames to send before resched */ 464 uint txminmax; 465 466 struct sk_buff *glomd; /* Packet containing glomming descriptor */ 467 struct sk_buff_head glom; /* Packet list for glommed superframe */ 468 469 u8 *rxbuf; /* Buffer for receiving control packets */ 470 uint rxblen; /* Allocated length of rxbuf */ 471 u8 *rxctl; /* Aligned pointer into rxbuf */ 472 u8 *rxctl_orig; /* pointer for freeing rxctl */ 473 uint rxlen; /* Length of valid data in buffer */ 474 spinlock_t rxctl_lock; /* protection lock for ctrl frame resources */ 475 476 u8 sdpcm_ver; /* Bus protocol reported by dongle */ 477 478 bool intr; /* Use interrupts */ 479 bool poll; /* Use polling */ 480 atomic_t ipend; /* Device interrupt is pending */ 481 uint spurious; /* Count of spurious interrupts */ 482 uint pollrate; /* Ticks between device polls */ 483 uint polltick; /* Tick counter */ 484 485#ifdef DEBUG 486 uint console_interval; 487 struct brcmf_console console; /* Console output polling support */ 488 uint console_addr; /* Console address from shared struct */ 489#endif /* DEBUG */ 490 491 uint clkstate; /* State of sd and backplane clock(s) */ 492 s32 idletime; /* Control for activity timeout */ 493 s32 idlecount; /* Activity timeout counter */ 494 s32 idleclock; /* How to set bus driver when idle */ 495 bool rxflow_mode; /* Rx flow control mode */ 496 bool rxflow; /* Is rx flow control on */ 497 bool alp_only; /* Don't use HT clock (ALP only) */ 498 499 u8 *ctrl_frame_buf; 500 u16 ctrl_frame_len; 501 bool ctrl_frame_stat; 502 int ctrl_frame_err; 503 504 spinlock_t txq_lock; /* protect bus->txq */ 505 wait_queue_head_t ctrl_wait; 506 wait_queue_head_t dcmd_resp_wait; 507 508 struct timer_list timer; 509 struct completion watchdog_wait; 510 struct task_struct *watchdog_tsk; 511 bool wd_active; 512 513 struct workqueue_struct *brcmf_wq; 514 struct work_struct datawork; 515 bool dpc_triggered; 516 bool dpc_running; 517 518 bool txoff; /* Transmit flow-controlled */ 519 struct brcmf_sdio_count sdcnt; 520 bool sr_enabled; /* SaveRestore enabled */ 521 bool sleeping; 522 523 u8 tx_hdrlen; /* sdio bus header length for tx packet */ 524 bool txglom; /* host tx glomming enable flag */ 525 u16 head_align; /* buffer pointer alignment */ 526 u16 sgentry_align; /* scatter-gather buffer alignment */ 527}; 528 529/* clkstate */ 530#define CLK_NONE 0 531#define CLK_SDONLY 1 532#define CLK_PENDING 2 533#define CLK_AVAIL 3 534 535#ifdef DEBUG 536static int qcount[NUMPRIO]; 537#endif /* DEBUG */ 538 539#define DEFAULT_SDIO_DRIVE_STRENGTH 6 /* in milliamps */ 540 541#define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL) 542 543/* Limit on rounding up frames */ 544static const uint max_roundup = 512; 545 546#ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT 547#define ALIGNMENT 8 548#else 549#define ALIGNMENT 4 550#endif 551 552enum brcmf_sdio_frmtype { 553 BRCMF_SDIO_FT_NORMAL, 554 BRCMF_SDIO_FT_SUPER, 555 BRCMF_SDIO_FT_SUB, 556}; 557 558#define SDIOD_DRVSTR_KEY(chip, pmu) (((unsigned int)(chip) << 16) | (pmu)) 559 560/* SDIO Pad drive strength to select value mappings */ 561struct sdiod_drive_str { 562 u8 strength; /* Pad Drive Strength in mA */ 563 u8 sel; /* Chip-specific select value */ 564}; 565 566/* SDIO Drive Strength to sel value table for PMU Rev 11 (1.8V) */ 567static const struct sdiod_drive_str sdiod_drvstr_tab1_1v8[] = { 568 {32, 0x6}, 569 {26, 0x7}, 570 {22, 0x4}, 571 {16, 0x5}, 572 {12, 0x2}, 573 {8, 0x3}, 574 {4, 0x0}, 575 {0, 0x1} 576}; 577 578/* SDIO Drive Strength to sel value table for PMU Rev 13 (1.8v) */ 579static const struct sdiod_drive_str sdiod_drive_strength_tab5_1v8[] = { 580 {6, 0x7}, 581 {5, 0x6}, 582 {4, 0x5}, 583 {3, 0x4}, 584 {2, 0x2}, 585 {1, 0x1}, 586 {0, 0x0} 587}; 588 589/* SDIO Drive Strength to sel value table for PMU Rev 17 (1.8v) */ 590static const struct sdiod_drive_str sdiod_drvstr_tab6_1v8[] = { 591 {3, 0x3}, 592 {2, 0x2}, 593 {1, 0x1}, 594 {0, 0x0} }; 595 596/* SDIO Drive Strength to sel value table for 43143 PMU Rev 17 (3.3V) */ 597static const struct sdiod_drive_str sdiod_drvstr_tab2_3v3[] = { 598 {16, 0x7}, 599 {12, 0x5}, 600 {8, 0x3}, 601 {4, 0x1} 602}; 603 604BRCMF_FW_DEF(43143, "brcmfmac43143-sdio"); 605BRCMF_FW_DEF(43241B0, "brcmfmac43241b0-sdio"); 606BRCMF_FW_DEF(43241B4, "brcmfmac43241b4-sdio"); 607BRCMF_FW_DEF(43241B5, "brcmfmac43241b5-sdio"); 608BRCMF_FW_DEF(4329, "brcmfmac4329-sdio"); 609BRCMF_FW_DEF(4330, "brcmfmac4330-sdio"); 610BRCMF_FW_DEF(4334, "brcmfmac4334-sdio"); 611BRCMF_FW_DEF(43340, "brcmfmac43340-sdio"); 612BRCMF_FW_DEF(4335, "brcmfmac4335-sdio"); 613BRCMF_FW_DEF(43362, "brcmfmac43362-sdio"); 614BRCMF_FW_DEF(4339, "brcmfmac4339-sdio"); 615BRCMF_FW_DEF(43430A0, "brcmfmac43430a0-sdio"); 616/* Note the names are not postfixed with a1 for backward compatibility */ 617BRCMF_FW_CLM_DEF(43430A1, "brcmfmac43430-sdio"); 618BRCMF_FW_DEF(43430B0, "brcmfmac43430b0-sdio"); 619BRCMF_FW_CLM_DEF(43439, "brcmfmac43439-sdio"); 620BRCMF_FW_CLM_DEF(43455, "brcmfmac43455-sdio"); 621BRCMF_FW_DEF(43456, "brcmfmac43456-sdio"); 622BRCMF_FW_CLM_DEF(4354, "brcmfmac4354-sdio"); 623BRCMF_FW_CLM_DEF(4356, "brcmfmac4356-sdio"); 624BRCMF_FW_DEF(4359, "brcmfmac4359-sdio"); 625BRCMF_FW_CLM_DEF(4373, "brcmfmac4373-sdio"); 626BRCMF_FW_CLM_DEF(43012, "brcmfmac43012-sdio"); 627BRCMF_FW_CLM_DEF(43752, "brcmfmac43752-sdio"); 628 629/* firmware config files */ 630MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-sdio.*.txt"); 631 632/* per-board firmware binaries */ 633MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-sdio.*.bin"); 634 635static const struct brcmf_firmware_mapping brcmf_sdio_fwnames[] = { 636 BRCMF_FW_ENTRY(BRCM_CC_43143_CHIP_ID, 0xFFFFFFFF, 43143), 637 BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0x0000001F, 43241B0), 638 BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0x00000020, 43241B4), 639 BRCMF_FW_ENTRY(BRCM_CC_43241_CHIP_ID, 0xFFFFFFC0, 43241B5), 640 BRCMF_FW_ENTRY(BRCM_CC_4329_CHIP_ID, 0xFFFFFFFF, 4329), 641 BRCMF_FW_ENTRY(BRCM_CC_4330_CHIP_ID, 0xFFFFFFFF, 4330), 642 BRCMF_FW_ENTRY(BRCM_CC_4334_CHIP_ID, 0xFFFFFFFF, 4334), 643 BRCMF_FW_ENTRY(BRCM_CC_43340_CHIP_ID, 0xFFFFFFFF, 43340), 644 BRCMF_FW_ENTRY(BRCM_CC_43341_CHIP_ID, 0xFFFFFFFF, 43340), 645 BRCMF_FW_ENTRY(BRCM_CC_4335_CHIP_ID, 0xFFFFFFFF, 4335), 646 BRCMF_FW_ENTRY(BRCM_CC_43362_CHIP_ID, 0xFFFFFFFE, 43362), 647 BRCMF_FW_ENTRY(BRCM_CC_4339_CHIP_ID, 0xFFFFFFFF, 4339), 648 BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0x00000001, 43430A0), 649 BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0x00000002, 43430A1), 650 BRCMF_FW_ENTRY(BRCM_CC_43430_CHIP_ID, 0xFFFFFFFC, 43430B0), 651 BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0x00000200, 43456), 652 BRCMF_FW_ENTRY(BRCM_CC_4345_CHIP_ID, 0xFFFFFDC0, 43455), 653 BRCMF_FW_ENTRY(BRCM_CC_43454_CHIP_ID, 0x00000040, 43455), 654 BRCMF_FW_ENTRY(BRCM_CC_4354_CHIP_ID, 0xFFFFFFFF, 4354), 655 BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356), 656 BRCMF_FW_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFFFF, 4359), 657 BRCMF_FW_ENTRY(BRCM_CC_43751_CHIP_ID, 0xFFFFFFFF, 43752), 658 BRCMF_FW_ENTRY(BRCM_CC_43752_CHIP_ID, 0xFFFFFFFF, 43752), 659 BRCMF_FW_ENTRY(CY_CC_4373_CHIP_ID, 0xFFFFFFFF, 4373), 660 BRCMF_FW_ENTRY(CY_CC_43012_CHIP_ID, 0xFFFFFFFF, 43012), 661 BRCMF_FW_ENTRY(CY_CC_43439_CHIP_ID, 0xFFFFFFFF, 43439), 662}; 663 664#define TXCTL_CREDITS 2 665 666static void pkt_align(struct sk_buff *p, int len, int align) 667{ 668 uint datalign; 669 datalign = (unsigned long)(p->data); 670 datalign = roundup(datalign, (align)) - datalign; 671 if (datalign) 672 skb_pull(p, datalign); 673 __skb_trim(p, len); 674} 675 676/* To check if there's window offered */ 677static bool data_ok(struct brcmf_sdio *bus) 678{ 679 u8 tx_rsv = 0; 680 681 /* Reserve TXCTL_CREDITS credits for txctl when it is ready to send */ 682 if (bus->ctrl_frame_stat) 683 tx_rsv = TXCTL_CREDITS; 684 685 return (bus->tx_max - bus->tx_seq - tx_rsv) != 0 && 686 ((bus->tx_max - bus->tx_seq - tx_rsv) & 0x80) == 0; 687 688} 689 690/* To check if there's window offered */ 691static bool txctl_ok(struct brcmf_sdio *bus) 692{ 693 return (bus->tx_max - bus->tx_seq) != 0 && 694 ((bus->tx_max - bus->tx_seq) & 0x80) == 0; 695} 696 697static int 698brcmf_sdio_kso_control(struct brcmf_sdio *bus, bool on) 699{ 700 u8 wr_val = 0, rd_val, cmp_val, bmask; 701 int err = 0; 702 int err_cnt = 0; 703 int try_cnt = 0; 704 705 brcmf_dbg(TRACE, "Enter: on=%d\n", on); 706 707 sdio_retune_crc_disable(bus->sdiodev->func1); 708 709 /* Cannot re-tune if device is asleep; defer till we're awake */ 710 if (on) 711 sdio_retune_hold_now(bus->sdiodev->func1); 712 713 wr_val = (on << SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); 714 /* 1st KSO write goes to AOS wake up core if device is asleep */ 715 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, wr_val, &err); 716 717 /* In case of 43012 chip, the chip could go down immediately after 718 * KSO bit is cleared. So the further reads of KSO register could 719 * fail. Thereby just bailing out immediately after clearing KSO 720 * bit, to avoid polling of KSO bit. 721 */ 722 if (!on && bus->ci->chip == CY_CC_43012_CHIP_ID) 723 return err; 724 725 if (on) { 726 /* device WAKEUP through KSO: 727 * write bit 0 & read back until 728 * both bits 0 (kso bit) & 1 (dev on status) are set 729 */ 730 cmp_val = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK | 731 SBSDIO_FUNC1_SLEEPCSR_DEVON_MASK; 732 bmask = cmp_val; 733 usleep_range(2000, 3000); 734 } else { 735 /* Put device to sleep, turn off KSO */ 736 cmp_val = 0; 737 /* only check for bit0, bit1(dev on status) may not 738 * get cleared right away 739 */ 740 bmask = SBSDIO_FUNC1_SLEEPCSR_KSO_MASK; 741 } 742 743 do { 744 /* reliable KSO bit set/clr: 745 * the sdiod sleep write access is synced to PMU 32khz clk 746 * just one write attempt may fail, 747 * read it back until it matches written value 748 */ 749 rd_val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, 750 &err); 751 if (!err) { 752 if ((rd_val & bmask) == cmp_val) 753 break; 754 err_cnt = 0; 755 } 756 /* bail out upon subsequent access errors */ 757 if (err && (err_cnt++ > BRCMF_SDIO_MAX_ACCESS_ERRORS)) 758 break; 759 760 udelay(KSO_WAIT_US); 761 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, wr_val, 762 &err); 763 764 } while (try_cnt++ < MAX_KSO_ATTEMPTS); 765 766 if (try_cnt > 2) 767 brcmf_dbg(SDIO, "try_cnt=%d rd_val=0x%x err=%d\n", try_cnt, 768 rd_val, err); 769 770 if (try_cnt > MAX_KSO_ATTEMPTS) 771 brcmf_err("max tries: rd_val=0x%x err=%d\n", rd_val, err); 772 773 if (on) 774 sdio_retune_release(bus->sdiodev->func1); 775 776 sdio_retune_crc_enable(bus->sdiodev->func1); 777 778 return err; 779} 780 781#define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE) 782 783/* Turn backplane clock on or off */ 784static int brcmf_sdio_htclk(struct brcmf_sdio *bus, bool on, bool pendok) 785{ 786 int err; 787 u8 clkctl, clkreq, devctl; 788 unsigned long timeout; 789 790 brcmf_dbg(SDIO, "Enter\n"); 791 792 clkctl = 0; 793 794 if (bus->sr_enabled) { 795 bus->clkstate = (on ? CLK_AVAIL : CLK_SDONLY); 796 return 0; 797 } 798 799 if (on) { 800 /* Request HT Avail */ 801 clkreq = 802 bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ; 803 804 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 805 clkreq, &err); 806 if (err) { 807 brcmf_err("HT Avail request error: %d\n", err); 808 return -EBADE; 809 } 810 811 /* Check current status */ 812 clkctl = brcmf_sdiod_readb(bus->sdiodev, 813 SBSDIO_FUNC1_CHIPCLKCSR, &err); 814 if (err) { 815 brcmf_err("HT Avail read error: %d\n", err); 816 return -EBADE; 817 } 818 819 /* Go to pending and await interrupt if appropriate */ 820 if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) { 821 /* Allow only clock-available interrupt */ 822 devctl = brcmf_sdiod_readb(bus->sdiodev, 823 SBSDIO_DEVICE_CTL, &err); 824 if (err) { 825 brcmf_err("Devctl error setting CA: %d\n", err); 826 return -EBADE; 827 } 828 829 devctl |= SBSDIO_DEVCTL_CA_INT_ONLY; 830 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL, 831 devctl, &err); 832 brcmf_dbg(SDIO, "CLKCTL: set PENDING\n"); 833 bus->clkstate = CLK_PENDING; 834 835 return 0; 836 } else if (bus->clkstate == CLK_PENDING) { 837 /* Cancel CA-only interrupt filter */ 838 devctl = brcmf_sdiod_readb(bus->sdiodev, 839 SBSDIO_DEVICE_CTL, &err); 840 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; 841 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL, 842 devctl, &err); 843 } 844 845 /* Otherwise, wait here (polling) for HT Avail */ 846 timeout = jiffies + 847 msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000); 848 while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { 849 clkctl = brcmf_sdiod_readb(bus->sdiodev, 850 SBSDIO_FUNC1_CHIPCLKCSR, 851 &err); 852 if (time_after(jiffies, timeout)) 853 break; 854 else 855 usleep_range(5000, 10000); 856 } 857 if (err) { 858 brcmf_err("HT Avail request error: %d\n", err); 859 return -EBADE; 860 } 861 if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) { 862 brcmf_err("HT Avail timeout (%d): clkctl 0x%02x\n", 863 PMU_MAX_TRANSITION_DLY, clkctl); 864 return -EBADE; 865 } 866 867 /* Mark clock available */ 868 bus->clkstate = CLK_AVAIL; 869 brcmf_dbg(SDIO, "CLKCTL: turned ON\n"); 870 871#if defined(DEBUG) 872 if (!bus->alp_only) { 873 if (SBSDIO_ALPONLY(clkctl)) 874 brcmf_err("HT Clock should be on\n"); 875 } 876#endif /* defined (DEBUG) */ 877 878 } else { 879 clkreq = 0; 880 881 if (bus->clkstate == CLK_PENDING) { 882 /* Cancel CA-only interrupt filter */ 883 devctl = brcmf_sdiod_readb(bus->sdiodev, 884 SBSDIO_DEVICE_CTL, &err); 885 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; 886 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_DEVICE_CTL, 887 devctl, &err); 888 } 889 890 bus->clkstate = CLK_SDONLY; 891 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 892 clkreq, &err); 893 brcmf_dbg(SDIO, "CLKCTL: turned OFF\n"); 894 if (err) { 895 brcmf_err("Failed access turning clock off: %d\n", 896 err); 897 return -EBADE; 898 } 899 } 900 return 0; 901} 902 903/* Change idle/active SD state */ 904static int brcmf_sdio_sdclk(struct brcmf_sdio *bus, bool on) 905{ 906 brcmf_dbg(SDIO, "Enter\n"); 907 908 if (on) 909 bus->clkstate = CLK_SDONLY; 910 else 911 bus->clkstate = CLK_NONE; 912 913 return 0; 914} 915 916/* Transition SD and backplane clock readiness */ 917static int brcmf_sdio_clkctl(struct brcmf_sdio *bus, uint target, bool pendok) 918{ 919#ifdef DEBUG 920 uint oldstate = bus->clkstate; 921#endif /* DEBUG */ 922 923 brcmf_dbg(SDIO, "Enter\n"); 924 925 /* Early exit if we're already there */ 926 if (bus->clkstate == target) 927 return 0; 928 929 switch (target) { 930 case CLK_AVAIL: 931 /* Make sure SD clock is available */ 932 if (bus->clkstate == CLK_NONE) 933 brcmf_sdio_sdclk(bus, true); 934 /* Now request HT Avail on the backplane */ 935 brcmf_sdio_htclk(bus, true, pendok); 936 break; 937 938 case CLK_SDONLY: 939 /* Remove HT request, or bring up SD clock */ 940 if (bus->clkstate == CLK_NONE) 941 brcmf_sdio_sdclk(bus, true); 942 else if (bus->clkstate == CLK_AVAIL) 943 brcmf_sdio_htclk(bus, false, false); 944 else 945 brcmf_err("request for %d -> %d\n", 946 bus->clkstate, target); 947 break; 948 949 case CLK_NONE: 950 /* Make sure to remove HT request */ 951 if (bus->clkstate == CLK_AVAIL) 952 brcmf_sdio_htclk(bus, false, false); 953 /* Now remove the SD clock */ 954 brcmf_sdio_sdclk(bus, false); 955 break; 956 } 957#ifdef DEBUG 958 brcmf_dbg(SDIO, "%d -> %d\n", oldstate, bus->clkstate); 959#endif /* DEBUG */ 960 961 return 0; 962} 963 964static int 965brcmf_sdio_bus_sleep(struct brcmf_sdio *bus, bool sleep, bool pendok) 966{ 967 int err = 0; 968 u8 clkcsr; 969 970 brcmf_dbg(SDIO, "Enter: request %s currently %s\n", 971 (sleep ? "SLEEP" : "WAKE"), 972 (bus->sleeping ? "SLEEP" : "WAKE")); 973 974 /* If SR is enabled control bus state with KSO */ 975 if (bus->sr_enabled) { 976 /* Done if we're already in the requested state */ 977 if (sleep == bus->sleeping) 978 goto end; 979 980 /* Going to sleep */ 981 if (sleep) { 982 clkcsr = brcmf_sdiod_readb(bus->sdiodev, 983 SBSDIO_FUNC1_CHIPCLKCSR, 984 &err); 985 if ((clkcsr & SBSDIO_CSR_MASK) == 0) { 986 brcmf_dbg(SDIO, "no clock, set ALP\n"); 987 brcmf_sdiod_writeb(bus->sdiodev, 988 SBSDIO_FUNC1_CHIPCLKCSR, 989 SBSDIO_ALP_AVAIL_REQ, &err); 990 } 991 err = brcmf_sdio_kso_control(bus, false); 992 } else { 993 err = brcmf_sdio_kso_control(bus, true); 994 } 995 if (err) { 996 brcmf_err("error while changing bus sleep state %d\n", 997 err); 998 goto done; 999 } 1000 } 1001 1002end: 1003 /* control clocks */ 1004 if (sleep) { 1005 if (!bus->sr_enabled) 1006 brcmf_sdio_clkctl(bus, CLK_NONE, pendok); 1007 } else { 1008 brcmf_sdio_clkctl(bus, CLK_AVAIL, pendok); 1009 brcmf_sdio_wd_timer(bus, true); 1010 } 1011 bus->sleeping = sleep; 1012 brcmf_dbg(SDIO, "new state %s\n", 1013 (sleep ? "SLEEP" : "WAKE")); 1014done: 1015 brcmf_dbg(SDIO, "Exit: err=%d\n", err); 1016 return err; 1017 1018} 1019 1020#ifdef DEBUG 1021static inline bool brcmf_sdio_valid_shared_address(u32 addr) 1022{ 1023 return !(addr == 0 || ((~addr >> 16) & 0xffff) == (addr & 0xffff)); 1024} 1025 1026static int brcmf_sdio_readshared(struct brcmf_sdio *bus, 1027 struct sdpcm_shared *sh) 1028{ 1029 u32 addr = 0; 1030 int rv; 1031 u32 shaddr = 0; 1032 struct sdpcm_shared_le sh_le; 1033 __le32 addr_le; 1034 1035 sdio_claim_host(bus->sdiodev->func1); 1036 brcmf_sdio_bus_sleep(bus, false, false); 1037 1038 /* 1039 * Read last word in socram to determine 1040 * address of sdpcm_shared structure 1041 */ 1042 shaddr = bus->ci->rambase + bus->ci->ramsize - 4; 1043 if (!bus->ci->rambase && brcmf_chip_sr_capable(bus->ci)) 1044 shaddr -= bus->ci->srsize; 1045 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, shaddr, 1046 (u8 *)&addr_le, 4); 1047 if (rv < 0) 1048 goto fail; 1049 1050 /* 1051 * Check if addr is valid. 1052 * NVRAM length at the end of memory should have been overwritten. 1053 */ 1054 addr = le32_to_cpu(addr_le); 1055 if (!brcmf_sdio_valid_shared_address(addr)) { 1056 brcmf_err("invalid sdpcm_shared address 0x%08X\n", addr); 1057 rv = -EINVAL; 1058 goto fail; 1059 } 1060 1061 brcmf_dbg(INFO, "sdpcm_shared address 0x%08X\n", addr); 1062 1063 /* Read hndrte_shared structure */ 1064 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&sh_le, 1065 sizeof(struct sdpcm_shared_le)); 1066 if (rv < 0) 1067 goto fail; 1068 1069 sdio_release_host(bus->sdiodev->func1); 1070 1071 /* Endianness */ 1072 sh->flags = le32_to_cpu(sh_le.flags); 1073 sh->trap_addr = le32_to_cpu(sh_le.trap_addr); 1074 sh->assert_exp_addr = le32_to_cpu(sh_le.assert_exp_addr); 1075 sh->assert_file_addr = le32_to_cpu(sh_le.assert_file_addr); 1076 sh->assert_line = le32_to_cpu(sh_le.assert_line); 1077 sh->console_addr = le32_to_cpu(sh_le.console_addr); 1078 sh->msgtrace_addr = le32_to_cpu(sh_le.msgtrace_addr); 1079 1080 if ((sh->flags & SDPCM_SHARED_VERSION_MASK) > SDPCM_SHARED_VERSION) { 1081 brcmf_err("sdpcm shared version unsupported: dhd %d dongle %d\n", 1082 SDPCM_SHARED_VERSION, 1083 sh->flags & SDPCM_SHARED_VERSION_MASK); 1084 return -EPROTO; 1085 } 1086 return 0; 1087 1088fail: 1089 brcmf_err("unable to obtain sdpcm_shared info: rv=%d (addr=0x%x)\n", 1090 rv, addr); 1091 sdio_release_host(bus->sdiodev->func1); 1092 return rv; 1093} 1094 1095static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus) 1096{ 1097 struct sdpcm_shared sh; 1098 1099 if (brcmf_sdio_readshared(bus, &sh) == 0) 1100 bus->console_addr = sh.console_addr; 1101} 1102#else 1103static void brcmf_sdio_get_console_addr(struct brcmf_sdio *bus) 1104{ 1105} 1106#endif /* DEBUG */ 1107 1108static u32 brcmf_sdio_hostmail(struct brcmf_sdio *bus) 1109{ 1110 struct brcmf_sdio_dev *sdiod = bus->sdiodev; 1111 struct brcmf_core *core = bus->sdio_core; 1112 u32 intstatus = 0; 1113 u32 hmb_data; 1114 u8 fcbits; 1115 int ret; 1116 1117 brcmf_dbg(SDIO, "Enter\n"); 1118 1119 /* Read mailbox data and ack that we did so */ 1120 hmb_data = brcmf_sdiod_readl(sdiod, 1121 core->base + SD_REG(tohostmailboxdata), 1122 &ret); 1123 1124 if (!ret) 1125 brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailbox), 1126 SMB_INT_ACK, &ret); 1127 1128 bus->sdcnt.f1regdata += 2; 1129 1130 /* dongle indicates the firmware has halted/crashed */ 1131 if (hmb_data & HMB_DATA_FWHALT) { 1132 brcmf_dbg(SDIO, "mailbox indicates firmware halted\n"); 1133 brcmf_fw_crashed(&sdiod->func1->dev); 1134 } 1135 1136 /* Dongle recomposed rx frames, accept them again */ 1137 if (hmb_data & HMB_DATA_NAKHANDLED) { 1138 brcmf_dbg(SDIO, "Dongle reports NAK handled, expect rtx of %d\n", 1139 bus->rx_seq); 1140 if (!bus->rxskip) 1141 brcmf_err("unexpected NAKHANDLED!\n"); 1142 1143 bus->rxskip = false; 1144 intstatus |= I_HMB_FRAME_IND; 1145 } 1146 1147 /* 1148 * DEVREADY does not occur with gSPI. 1149 */ 1150 if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) { 1151 bus->sdpcm_ver = 1152 (hmb_data & HMB_DATA_VERSION_MASK) >> 1153 HMB_DATA_VERSION_SHIFT; 1154 if (bus->sdpcm_ver != SDPCM_PROT_VERSION) 1155 brcmf_err("Version mismatch, dongle reports %d, " 1156 "expecting %d\n", 1157 bus->sdpcm_ver, SDPCM_PROT_VERSION); 1158 else 1159 brcmf_dbg(SDIO, "Dongle ready, protocol version %d\n", 1160 bus->sdpcm_ver); 1161 1162 /* 1163 * Retrieve console state address now that firmware should have 1164 * updated it. 1165 */ 1166 brcmf_sdio_get_console_addr(bus); 1167 } 1168 1169 /* 1170 * Flow Control has been moved into the RX headers and this out of band 1171 * method isn't used any more. 1172 * remaining backward compatible with older dongles. 1173 */ 1174 if (hmb_data & HMB_DATA_FC) { 1175 fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >> 1176 HMB_DATA_FCDATA_SHIFT; 1177 1178 if (fcbits & ~bus->flowcontrol) 1179 bus->sdcnt.fc_xoff++; 1180 1181 if (bus->flowcontrol & ~fcbits) 1182 bus->sdcnt.fc_xon++; 1183 1184 bus->sdcnt.fc_rcvd++; 1185 bus->flowcontrol = fcbits; 1186 } 1187 1188 /* Shouldn't be any others */ 1189 if (hmb_data & ~(HMB_DATA_DEVREADY | 1190 HMB_DATA_NAKHANDLED | 1191 HMB_DATA_FC | 1192 HMB_DATA_FWREADY | 1193 HMB_DATA_FWHALT | 1194 HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK)) 1195 brcmf_err("Unknown mailbox data content: 0x%02x\n", 1196 hmb_data); 1197 1198 return intstatus; 1199} 1200 1201static void brcmf_sdio_rxfail(struct brcmf_sdio *bus, bool abort, bool rtx) 1202{ 1203 struct brcmf_sdio_dev *sdiod = bus->sdiodev; 1204 struct brcmf_core *core = bus->sdio_core; 1205 uint retries = 0; 1206 u16 lastrbc; 1207 u8 hi, lo; 1208 int err; 1209 1210 brcmf_err("%sterminate frame%s\n", 1211 abort ? "abort command, " : "", 1212 rtx ? ", send NAK" : ""); 1213 1214 if (abort) 1215 brcmf_sdiod_abort(bus->sdiodev, bus->sdiodev->func2); 1216 1217 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_RF_TERM, 1218 &err); 1219 bus->sdcnt.f1regdata++; 1220 1221 /* Wait until the packet has been flushed (device/FIFO stable) */ 1222 for (lastrbc = retries = 0xffff; retries > 0; retries--) { 1223 hi = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_RFRAMEBCHI, 1224 &err); 1225 lo = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_RFRAMEBCLO, 1226 &err); 1227 bus->sdcnt.f1regdata += 2; 1228 1229 if ((hi == 0) && (lo == 0)) 1230 break; 1231 1232 if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) { 1233 brcmf_err("count growing: last 0x%04x now 0x%04x\n", 1234 lastrbc, (hi << 8) + lo); 1235 } 1236 lastrbc = (hi << 8) + lo; 1237 } 1238 1239 if (!retries) 1240 brcmf_err("count never zeroed: last 0x%04x\n", lastrbc); 1241 else 1242 brcmf_dbg(SDIO, "flush took %d iterations\n", 0xffff - retries); 1243 1244 if (rtx) { 1245 bus->sdcnt.rxrtx++; 1246 brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailbox), 1247 SMB_NAK, &err); 1248 1249 bus->sdcnt.f1regdata++; 1250 if (err == 0) 1251 bus->rxskip = true; 1252 } 1253 1254 /* Clear partial in any case */ 1255 bus->cur_read.len = 0; 1256} 1257 1258static void brcmf_sdio_txfail(struct brcmf_sdio *bus) 1259{ 1260 struct brcmf_sdio_dev *sdiodev = bus->sdiodev; 1261 u8 i, hi, lo; 1262 1263 /* On failure, abort the command and terminate the frame */ 1264 brcmf_err("sdio error, abort command and terminate frame\n"); 1265 bus->sdcnt.tx_sderrs++; 1266 1267 brcmf_sdiod_abort(sdiodev, sdiodev->func2); 1268 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM, NULL); 1269 bus->sdcnt.f1regdata++; 1270 1271 for (i = 0; i < 3; i++) { 1272 hi = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_WFRAMEBCHI, NULL); 1273 lo = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_WFRAMEBCLO, NULL); 1274 bus->sdcnt.f1regdata += 2; 1275 if ((hi == 0) && (lo == 0)) 1276 break; 1277 } 1278} 1279 1280/* return total length of buffer chain */ 1281static uint brcmf_sdio_glom_len(struct brcmf_sdio *bus) 1282{ 1283 struct sk_buff *p; 1284 uint total; 1285 1286 total = 0; 1287 skb_queue_walk(&bus->glom, p) 1288 total += p->len; 1289 return total; 1290} 1291 1292static void brcmf_sdio_free_glom(struct brcmf_sdio *bus) 1293{ 1294 struct sk_buff *cur, *next; 1295 1296 skb_queue_walk_safe(&bus->glom, cur, next) { 1297 skb_unlink(cur, &bus->glom); 1298 brcmu_pkt_buf_free_skb(cur); 1299 } 1300} 1301 1302/* 1303 * brcmfmac sdio bus specific header 1304 * This is the lowest layer header wrapped on the packets transmitted between 1305 * host and WiFi dongle which contains information needed for SDIO core and 1306 * firmware 1307 * 1308 * It consists of 3 parts: hardware header, hardware extension header and 1309 * software header 1310 * hardware header (frame tag) - 4 bytes 1311 * Byte 0~1: Frame length 1312 * Byte 2~3: Checksum, bit-wise inverse of frame length 1313 * hardware extension header - 8 bytes 1314 * Tx glom mode only, N/A for Rx or normal Tx 1315 * Byte 0~1: Packet length excluding hw frame tag 1316 * Byte 2: Reserved 1317 * Byte 3: Frame flags, bit 0: last frame indication 1318 * Byte 4~5: Reserved 1319 * Byte 6~7: Tail padding length 1320 * software header - 8 bytes 1321 * Byte 0: Rx/Tx sequence number 1322 * Byte 1: 4 MSB Channel number, 4 LSB arbitrary flag 1323 * Byte 2: Length of next data frame, reserved for Tx 1324 * Byte 3: Data offset 1325 * Byte 4: Flow control bits, reserved for Tx 1326 * Byte 5: Maximum Sequence number allowed by firmware for Tx, N/A for Tx packet 1327 * Byte 6~7: Reserved 1328 */ 1329#define SDPCM_HWHDR_LEN 4 1330#define SDPCM_HWEXT_LEN 8 1331#define SDPCM_SWHDR_LEN 8 1332#define SDPCM_HDRLEN (SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN) 1333/* software header */ 1334#define SDPCM_SEQ_MASK 0x000000ff 1335#define SDPCM_SEQ_WRAP 256 1336#define SDPCM_CHANNEL_MASK 0x00000f00 1337#define SDPCM_CHANNEL_SHIFT 8 1338#define SDPCM_CONTROL_CHANNEL 0 /* Control */ 1339#define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication */ 1340#define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv */ 1341#define SDPCM_GLOM_CHANNEL 3 /* Coalesced packets */ 1342#define SDPCM_TEST_CHANNEL 15 /* Test/debug packets */ 1343#define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80) 1344#define SDPCM_NEXTLEN_MASK 0x00ff0000 1345#define SDPCM_NEXTLEN_SHIFT 16 1346#define SDPCM_DOFFSET_MASK 0xff000000 1347#define SDPCM_DOFFSET_SHIFT 24 1348#define SDPCM_FCMASK_MASK 0x000000ff 1349#define SDPCM_WINDOW_MASK 0x0000ff00 1350#define SDPCM_WINDOW_SHIFT 8 1351 1352static inline u8 brcmf_sdio_getdatoffset(u8 *swheader) 1353{ 1354 u32 hdrvalue; 1355 hdrvalue = le32_to_cpu(*(__le32 *)swheader); 1356 return (u8)((hdrvalue & SDPCM_DOFFSET_MASK) >> SDPCM_DOFFSET_SHIFT); 1357} 1358 1359static inline bool brcmf_sdio_fromevntchan(u8 *swheader) 1360{ 1361 u32 hdrvalue; 1362 u8 ret; 1363 1364 hdrvalue = le32_to_cpu(*(__le32 *)swheader); 1365 ret = (u8)((hdrvalue & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT); 1366 1367 return (ret == SDPCM_EVENT_CHANNEL); 1368} 1369 1370static int brcmf_sdio_hdparse(struct brcmf_sdio *bus, u8 *header, 1371 struct brcmf_sdio_hdrinfo *rd, 1372 enum brcmf_sdio_frmtype type) 1373{ 1374 u16 len, checksum; 1375 u8 rx_seq, fc, tx_seq_max; 1376 u32 swheader; 1377 1378 trace_brcmf_sdpcm_hdr(SDPCM_RX, header); 1379 1380 /* hw header */ 1381 len = get_unaligned_le16(header); 1382 checksum = get_unaligned_le16(header + sizeof(u16)); 1383 /* All zero means no more to read */ 1384 if (!(len | checksum)) { 1385 bus->rxpending = false; 1386 return -ENODATA; 1387 } 1388 if ((u16)(~(len ^ checksum))) { 1389 brcmf_err("HW header checksum error\n"); 1390 bus->sdcnt.rx_badhdr++; 1391 brcmf_sdio_rxfail(bus, false, false); 1392 return -EIO; 1393 } 1394 if (len < SDPCM_HDRLEN) { 1395 brcmf_err("HW header length error\n"); 1396 return -EPROTO; 1397 } 1398 if (type == BRCMF_SDIO_FT_SUPER && 1399 (roundup(len, bus->blocksize) != rd->len)) { 1400 brcmf_err("HW superframe header length error\n"); 1401 return -EPROTO; 1402 } 1403 if (type == BRCMF_SDIO_FT_SUB && len > rd->len) { 1404 brcmf_err("HW subframe header length error\n"); 1405 return -EPROTO; 1406 } 1407 rd->len = len; 1408 1409 /* software header */ 1410 header += SDPCM_HWHDR_LEN; 1411 swheader = le32_to_cpu(*(__le32 *)header); 1412 if (type == BRCMF_SDIO_FT_SUPER && SDPCM_GLOMDESC(header)) { 1413 brcmf_err("Glom descriptor found in superframe head\n"); 1414 rd->len = 0; 1415 return -EINVAL; 1416 } 1417 rx_seq = (u8)(swheader & SDPCM_SEQ_MASK); 1418 rd->channel = (swheader & SDPCM_CHANNEL_MASK) >> SDPCM_CHANNEL_SHIFT; 1419 if (len > MAX_RX_DATASZ && rd->channel != SDPCM_CONTROL_CHANNEL && 1420 type != BRCMF_SDIO_FT_SUPER) { 1421 brcmf_err("HW header length too long\n"); 1422 bus->sdcnt.rx_toolong++; 1423 brcmf_sdio_rxfail(bus, false, false); 1424 rd->len = 0; 1425 return -EPROTO; 1426 } 1427 if (type == BRCMF_SDIO_FT_SUPER && rd->channel != SDPCM_GLOM_CHANNEL) { 1428 brcmf_err("Wrong channel for superframe\n"); 1429 rd->len = 0; 1430 return -EINVAL; 1431 } 1432 if (type == BRCMF_SDIO_FT_SUB && rd->channel != SDPCM_DATA_CHANNEL && 1433 rd->channel != SDPCM_EVENT_CHANNEL) { 1434 brcmf_err("Wrong channel for subframe\n"); 1435 rd->len = 0; 1436 return -EINVAL; 1437 } 1438 rd->dat_offset = brcmf_sdio_getdatoffset(header); 1439 if (rd->dat_offset < SDPCM_HDRLEN || rd->dat_offset > rd->len) { 1440 brcmf_err("seq %d: bad data offset\n", rx_seq); 1441 bus->sdcnt.rx_badhdr++; 1442 brcmf_sdio_rxfail(bus, false, false); 1443 rd->len = 0; 1444 return -ENXIO; 1445 } 1446 if (rd->seq_num != rx_seq) { 1447 brcmf_dbg(SDIO, "seq %d, expected %d\n", rx_seq, rd->seq_num); 1448 bus->sdcnt.rx_badseq++; 1449 rd->seq_num = rx_seq; 1450 } 1451 /* no need to check the reset for subframe */ 1452 if (type == BRCMF_SDIO_FT_SUB) 1453 return 0; 1454 rd->len_nxtfrm = (swheader & SDPCM_NEXTLEN_MASK) >> SDPCM_NEXTLEN_SHIFT; 1455 if (rd->len_nxtfrm << 4 > MAX_RX_DATASZ) { 1456 /* only warm for NON glom packet */ 1457 if (rd->channel != SDPCM_GLOM_CHANNEL) 1458 brcmf_err("seq %d: next length error\n", rx_seq); 1459 rd->len_nxtfrm = 0; 1460 } 1461 swheader = le32_to_cpu(*(__le32 *)(header + 4)); 1462 fc = swheader & SDPCM_FCMASK_MASK; 1463 if (bus->flowcontrol != fc) { 1464 if (~bus->flowcontrol & fc) 1465 bus->sdcnt.fc_xoff++; 1466 if (bus->flowcontrol & ~fc) 1467 bus->sdcnt.fc_xon++; 1468 bus->sdcnt.fc_rcvd++; 1469 bus->flowcontrol = fc; 1470 } 1471 tx_seq_max = (swheader & SDPCM_WINDOW_MASK) >> SDPCM_WINDOW_SHIFT; 1472 if ((u8)(tx_seq_max - bus->tx_seq) > 0x40) { 1473 brcmf_err("seq %d: max tx seq number error\n", rx_seq); 1474 tx_seq_max = bus->tx_seq + 2; 1475 } 1476 bus->tx_max = tx_seq_max; 1477 1478 return 0; 1479} 1480 1481static inline void brcmf_sdio_update_hwhdr(u8 *header, u16 frm_length) 1482{ 1483 *(__le16 *)header = cpu_to_le16(frm_length); 1484 *(((__le16 *)header) + 1) = cpu_to_le16(~frm_length); 1485} 1486 1487static void brcmf_sdio_hdpack(struct brcmf_sdio *bus, u8 *header, 1488 struct brcmf_sdio_hdrinfo *hd_info) 1489{ 1490 u32 hdrval; 1491 u8 hdr_offset; 1492 1493 brcmf_sdio_update_hwhdr(header, hd_info->len); 1494 hdr_offset = SDPCM_HWHDR_LEN; 1495 1496 if (bus->txglom) { 1497 hdrval = (hd_info->len - hdr_offset) | (hd_info->lastfrm << 24); 1498 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval); 1499 hdrval = (u16)hd_info->tail_pad << 16; 1500 *(((__le32 *)(header + hdr_offset)) + 1) = cpu_to_le32(hdrval); 1501 hdr_offset += SDPCM_HWEXT_LEN; 1502 } 1503 1504 hdrval = hd_info->seq_num; 1505 hdrval |= (hd_info->channel << SDPCM_CHANNEL_SHIFT) & 1506 SDPCM_CHANNEL_MASK; 1507 hdrval |= (hd_info->dat_offset << SDPCM_DOFFSET_SHIFT) & 1508 SDPCM_DOFFSET_MASK; 1509 *((__le32 *)(header + hdr_offset)) = cpu_to_le32(hdrval); 1510 *(((__le32 *)(header + hdr_offset)) + 1) = 0; 1511 trace_brcmf_sdpcm_hdr(SDPCM_TX + !!(bus->txglom), header); 1512} 1513 1514static u8 brcmf_sdio_rxglom(struct brcmf_sdio *bus, u8 rxseq) 1515{ 1516 u16 dlen, totlen; 1517 u8 *dptr, num = 0; 1518 u16 sublen; 1519 struct sk_buff *pfirst, *pnext; 1520 1521 int errcode; 1522 u8 doff; 1523 1524 struct brcmf_sdio_hdrinfo rd_new; 1525 1526 /* If packets, issue read(s) and send up packet chain */ 1527 /* Return sequence numbers consumed? */ 1528 1529 brcmf_dbg(SDIO, "start: glomd %p glom %p\n", 1530 bus->glomd, skb_peek(&bus->glom)); 1531 1532 /* If there's a descriptor, generate the packet chain */ 1533 if (bus->glomd) { 1534 pfirst = pnext = NULL; 1535 dlen = (u16) (bus->glomd->len); 1536 dptr = bus->glomd->data; 1537 if (!dlen || (dlen & 1)) { 1538 brcmf_err("bad glomd len(%d), ignore descriptor\n", 1539 dlen); 1540 dlen = 0; 1541 } 1542 1543 for (totlen = num = 0; dlen; num++) { 1544 /* Get (and move past) next length */ 1545 sublen = get_unaligned_le16(dptr); 1546 dlen -= sizeof(u16); 1547 dptr += sizeof(u16); 1548 if ((sublen < SDPCM_HDRLEN) || 1549 ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) { 1550 brcmf_err("descriptor len %d bad: %d\n", 1551 num, sublen); 1552 pnext = NULL; 1553 break; 1554 } 1555 if (sublen % bus->sgentry_align) { 1556 brcmf_err("sublen %d not multiple of %d\n", 1557 sublen, bus->sgentry_align); 1558 } 1559 totlen += sublen; 1560 1561 /* For last frame, adjust read len so total 1562 is a block multiple */ 1563 if (!dlen) { 1564 sublen += 1565 (roundup(totlen, bus->blocksize) - totlen); 1566 totlen = roundup(totlen, bus->blocksize); 1567 } 1568 1569 /* Allocate/chain packet for next subframe */ 1570 pnext = brcmu_pkt_buf_get_skb(sublen + bus->sgentry_align); 1571 if (pnext == NULL) { 1572 brcmf_err("bcm_pkt_buf_get_skb failed, num %d len %d\n", 1573 num, sublen); 1574 break; 1575 } 1576 skb_queue_tail(&bus->glom, pnext); 1577 1578 /* Adhere to start alignment requirements */ 1579 pkt_align(pnext, sublen, bus->sgentry_align); 1580 } 1581 1582 /* If all allocations succeeded, save packet chain 1583 in bus structure */ 1584 if (pnext) { 1585 brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n", 1586 totlen, num); 1587 if (BRCMF_GLOM_ON() && bus->cur_read.len && 1588 totlen != bus->cur_read.len) { 1589 brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n", 1590 bus->cur_read.len, totlen, rxseq); 1591 } 1592 pfirst = pnext = NULL; 1593 } else { 1594 brcmf_sdio_free_glom(bus); 1595 num = 0; 1596 } 1597 1598 /* Done with descriptor packet */ 1599 brcmu_pkt_buf_free_skb(bus->glomd); 1600 bus->glomd = NULL; 1601 bus->cur_read.len = 0; 1602 } 1603 1604 /* Ok -- either we just generated a packet chain, 1605 or had one from before */ 1606 if (!skb_queue_empty(&bus->glom)) { 1607 if (BRCMF_GLOM_ON()) { 1608 brcmf_dbg(GLOM, "try superframe read, packet chain:\n"); 1609 skb_queue_walk(&bus->glom, pnext) { 1610 brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n", 1611 pnext, (u8 *) (pnext->data), 1612 pnext->len, pnext->len); 1613 } 1614 } 1615 1616 pfirst = skb_peek(&bus->glom); 1617 dlen = (u16) brcmf_sdio_glom_len(bus); 1618 1619 /* Do an SDIO read for the superframe. Configurable iovar to 1620 * read directly into the chained packet, or allocate a large 1621 * packet and copy into the chain. 1622 */ 1623 sdio_claim_host(bus->sdiodev->func1); 1624 errcode = brcmf_sdiod_recv_chain(bus->sdiodev, 1625 &bus->glom, dlen); 1626 sdio_release_host(bus->sdiodev->func1); 1627 bus->sdcnt.f2rxdata++; 1628 1629 /* On failure, kill the superframe */ 1630 if (errcode < 0) { 1631 brcmf_err("glom read of %d bytes failed: %d\n", 1632 dlen, errcode); 1633 1634 sdio_claim_host(bus->sdiodev->func1); 1635 brcmf_sdio_rxfail(bus, true, false); 1636 bus->sdcnt.rxglomfail++; 1637 brcmf_sdio_free_glom(bus); 1638 sdio_release_host(bus->sdiodev->func1); 1639 return 0; 1640 } 1641 1642 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 1643 pfirst->data, min_t(int, pfirst->len, 48), 1644 "SUPERFRAME:\n"); 1645 1646 rd_new.seq_num = rxseq; 1647 rd_new.len = dlen; 1648 sdio_claim_host(bus->sdiodev->func1); 1649 errcode = brcmf_sdio_hdparse(bus, pfirst->data, &rd_new, 1650 BRCMF_SDIO_FT_SUPER); 1651 sdio_release_host(bus->sdiodev->func1); 1652 bus->cur_read.len = rd_new.len_nxtfrm << 4; 1653 1654 /* Remove superframe header, remember offset */ 1655 skb_pull(pfirst, rd_new.dat_offset); 1656 num = 0; 1657 1658 /* Validate all the subframe headers */ 1659 skb_queue_walk(&bus->glom, pnext) { 1660 /* leave when invalid subframe is found */ 1661 if (errcode) 1662 break; 1663 1664 rd_new.len = pnext->len; 1665 rd_new.seq_num = rxseq++; 1666 sdio_claim_host(bus->sdiodev->func1); 1667 errcode = brcmf_sdio_hdparse(bus, pnext->data, &rd_new, 1668 BRCMF_SDIO_FT_SUB); 1669 sdio_release_host(bus->sdiodev->func1); 1670 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 1671 pnext->data, 32, "subframe:\n"); 1672 1673 num++; 1674 } 1675 1676 if (errcode) { 1677 /* Terminate frame on error */ 1678 sdio_claim_host(bus->sdiodev->func1); 1679 brcmf_sdio_rxfail(bus, true, false); 1680 bus->sdcnt.rxglomfail++; 1681 brcmf_sdio_free_glom(bus); 1682 sdio_release_host(bus->sdiodev->func1); 1683 bus->cur_read.len = 0; 1684 return 0; 1685 } 1686 1687 /* Basic SD framing looks ok - process each packet (header) */ 1688 1689 skb_queue_walk_safe(&bus->glom, pfirst, pnext) { 1690 dptr = (u8 *) (pfirst->data); 1691 sublen = get_unaligned_le16(dptr); 1692 doff = brcmf_sdio_getdatoffset(&dptr[SDPCM_HWHDR_LEN]); 1693 1694 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), 1695 dptr, pfirst->len, 1696 "Rx Subframe Data:\n"); 1697 1698 __skb_trim(pfirst, sublen); 1699 skb_pull(pfirst, doff); 1700 1701 if (pfirst->len == 0) { 1702 skb_unlink(pfirst, &bus->glom); 1703 brcmu_pkt_buf_free_skb(pfirst); 1704 continue; 1705 } 1706 1707 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 1708 pfirst->data, 1709 min_t(int, pfirst->len, 32), 1710 "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n", 1711 bus->glom.qlen, pfirst, pfirst->data, 1712 pfirst->len, pfirst->next, 1713 pfirst->prev); 1714 skb_unlink(pfirst, &bus->glom); 1715 if (brcmf_sdio_fromevntchan(&dptr[SDPCM_HWHDR_LEN])) 1716 brcmf_rx_event(bus->sdiodev->dev, pfirst); 1717 else 1718 brcmf_rx_frame(bus->sdiodev->dev, pfirst, 1719 false, false); 1720 bus->sdcnt.rxglompkts++; 1721 } 1722 1723 bus->sdcnt.rxglomframes++; 1724 } 1725 return num; 1726} 1727 1728static int brcmf_sdio_dcmd_resp_wait(struct brcmf_sdio *bus, uint *condition, 1729 bool *pending) 1730{ 1731 DECLARE_WAITQUEUE(wait, current); 1732 int timeout = DCMD_RESP_TIMEOUT; 1733 1734 /* Wait until control frame is available */ 1735 add_wait_queue(&bus->dcmd_resp_wait, &wait); 1736 set_current_state(TASK_INTERRUPTIBLE); 1737 1738 while (!(*condition) && (!signal_pending(current) && timeout)) 1739 timeout = schedule_timeout(timeout); 1740 1741 if (signal_pending(current)) 1742 *pending = true; 1743 1744 set_current_state(TASK_RUNNING); 1745 remove_wait_queue(&bus->dcmd_resp_wait, &wait); 1746 1747 return timeout; 1748} 1749 1750static int brcmf_sdio_dcmd_resp_wake(struct brcmf_sdio *bus) 1751{ 1752 wake_up_interruptible(&bus->dcmd_resp_wait); 1753 1754 return 0; 1755} 1756static void 1757brcmf_sdio_read_control(struct brcmf_sdio *bus, u8 *hdr, uint len, uint doff) 1758{ 1759 uint rdlen, pad; 1760 u8 *buf = NULL, *rbuf; 1761 int sdret; 1762 1763 brcmf_dbg(SDIO, "Enter\n"); 1764 if (bus->rxblen) 1765 buf = vzalloc(bus->rxblen); 1766 if (!buf) 1767 goto done; 1768 1769 rbuf = bus->rxbuf; 1770 pad = ((unsigned long)rbuf % bus->head_align); 1771 if (pad) 1772 rbuf += (bus->head_align - pad); 1773 1774 /* Copy the already-read portion over */ 1775 memcpy(buf, hdr, BRCMF_FIRSTREAD); 1776 if (len <= BRCMF_FIRSTREAD) 1777 goto gotpkt; 1778 1779 /* Raise rdlen to next SDIO block to avoid tail command */ 1780 rdlen = len - BRCMF_FIRSTREAD; 1781 if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) { 1782 pad = bus->blocksize - (rdlen % bus->blocksize); 1783 if ((pad <= bus->roundup) && (pad < bus->blocksize) && 1784 ((len + pad) < bus->sdiodev->bus_if->maxctl)) 1785 rdlen += pad; 1786 } else if (rdlen % bus->head_align) { 1787 rdlen += bus->head_align - (rdlen % bus->head_align); 1788 } 1789 1790 /* Drop if the read is too big or it exceeds our maximum */ 1791 if ((rdlen + BRCMF_FIRSTREAD) > bus->sdiodev->bus_if->maxctl) { 1792 brcmf_err("%d-byte control read exceeds %d-byte buffer\n", 1793 rdlen, bus->sdiodev->bus_if->maxctl); 1794 brcmf_sdio_rxfail(bus, false, false); 1795 goto done; 1796 } 1797 1798 if ((len - doff) > bus->sdiodev->bus_if->maxctl) { 1799 brcmf_err("%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n", 1800 len, len - doff, bus->sdiodev->bus_if->maxctl); 1801 bus->sdcnt.rx_toolong++; 1802 brcmf_sdio_rxfail(bus, false, false); 1803 goto done; 1804 } 1805 1806 /* Read remain of frame body */ 1807 sdret = brcmf_sdiod_recv_buf(bus->sdiodev, rbuf, rdlen); 1808 bus->sdcnt.f2rxdata++; 1809 1810 /* Control frame failures need retransmission */ 1811 if (sdret < 0) { 1812 brcmf_err("read %d control bytes failed: %d\n", 1813 rdlen, sdret); 1814 bus->sdcnt.rxc_errors++; 1815 brcmf_sdio_rxfail(bus, true, true); 1816 goto done; 1817 } else 1818 memcpy(buf + BRCMF_FIRSTREAD, rbuf, rdlen); 1819 1820gotpkt: 1821 1822 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), 1823 buf, len, "RxCtrl:\n"); 1824 1825 /* Point to valid data and indicate its length */ 1826 spin_lock_bh(&bus->rxctl_lock); 1827 if (bus->rxctl) { 1828 brcmf_err("last control frame is being processed.\n"); 1829 spin_unlock_bh(&bus->rxctl_lock); 1830 vfree(buf); 1831 goto done; 1832 } 1833 bus->rxctl = buf + doff; 1834 bus->rxctl_orig = buf; 1835 bus->rxlen = len - doff; 1836 spin_unlock_bh(&bus->rxctl_lock); 1837 1838done: 1839 /* Awake any waiters */ 1840 brcmf_sdio_dcmd_resp_wake(bus); 1841} 1842 1843/* Pad read to blocksize for efficiency */ 1844static void brcmf_sdio_pad(struct brcmf_sdio *bus, u16 *pad, u16 *rdlen) 1845{ 1846 if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) { 1847 *pad = bus->blocksize - (*rdlen % bus->blocksize); 1848 if (*pad <= bus->roundup && *pad < bus->blocksize && 1849 *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ) 1850 *rdlen += *pad; 1851 } else if (*rdlen % bus->head_align) { 1852 *rdlen += bus->head_align - (*rdlen % bus->head_align); 1853 } 1854} 1855 1856static uint brcmf_sdio_readframes(struct brcmf_sdio *bus, uint maxframes) 1857{ 1858 struct sk_buff *pkt; /* Packet for event or data frames */ 1859 u16 pad; /* Number of pad bytes to read */ 1860 uint rxleft = 0; /* Remaining number of frames allowed */ 1861 int ret; /* Return code from calls */ 1862 uint rxcount = 0; /* Total frames read */ 1863 struct brcmf_sdio_hdrinfo *rd = &bus->cur_read, rd_new; 1864 u8 head_read = 0; 1865 1866 brcmf_dbg(SDIO, "Enter\n"); 1867 1868 /* Not finished unless we encounter no more frames indication */ 1869 bus->rxpending = true; 1870 1871 for (rd->seq_num = bus->rx_seq, rxleft = maxframes; 1872 !bus->rxskip && rxleft && bus->sdiodev->state == BRCMF_SDIOD_DATA; 1873 rd->seq_num++, rxleft--) { 1874 1875 /* Handle glomming separately */ 1876 if (bus->glomd || !skb_queue_empty(&bus->glom)) { 1877 u8 cnt; 1878 brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n", 1879 bus->glomd, skb_peek(&bus->glom)); 1880 cnt = brcmf_sdio_rxglom(bus, rd->seq_num); 1881 brcmf_dbg(GLOM, "rxglom returned %d\n", cnt); 1882 rd->seq_num += cnt - 1; 1883 rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1; 1884 continue; 1885 } 1886 1887 rd->len_left = rd->len; 1888 /* read header first for unknown frame length */ 1889 sdio_claim_host(bus->sdiodev->func1); 1890 if (!rd->len) { 1891 ret = brcmf_sdiod_recv_buf(bus->sdiodev, 1892 bus->rxhdr, BRCMF_FIRSTREAD); 1893 bus->sdcnt.f2rxhdrs++; 1894 if (ret < 0) { 1895 brcmf_err("RXHEADER FAILED: %d\n", 1896 ret); 1897 bus->sdcnt.rx_hdrfail++; 1898 brcmf_sdio_rxfail(bus, true, true); 1899 sdio_release_host(bus->sdiodev->func1); 1900 continue; 1901 } 1902 1903 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() || BRCMF_HDRS_ON(), 1904 bus->rxhdr, SDPCM_HDRLEN, 1905 "RxHdr:\n"); 1906 1907 if (brcmf_sdio_hdparse(bus, bus->rxhdr, rd, 1908 BRCMF_SDIO_FT_NORMAL)) { 1909 sdio_release_host(bus->sdiodev->func1); 1910 if (!bus->rxpending) 1911 break; 1912 else 1913 continue; 1914 } 1915 1916 if (rd->channel == SDPCM_CONTROL_CHANNEL) { 1917 brcmf_sdio_read_control(bus, bus->rxhdr, 1918 rd->len, 1919 rd->dat_offset); 1920 /* prepare the descriptor for the next read */ 1921 rd->len = rd->len_nxtfrm << 4; 1922 rd->len_nxtfrm = 0; 1923 /* treat all packet as event if we don't know */ 1924 rd->channel = SDPCM_EVENT_CHANNEL; 1925 sdio_release_host(bus->sdiodev->func1); 1926 continue; 1927 } 1928 rd->len_left = rd->len > BRCMF_FIRSTREAD ? 1929 rd->len - BRCMF_FIRSTREAD : 0; 1930 head_read = BRCMF_FIRSTREAD; 1931 } 1932 1933 brcmf_sdio_pad(bus, &pad, &rd->len_left); 1934 1935 pkt = brcmu_pkt_buf_get_skb(rd->len_left + head_read + 1936 bus->head_align); 1937 if (!pkt) { 1938 /* Give up on data, request rtx of events */ 1939 brcmf_err("brcmu_pkt_buf_get_skb failed\n"); 1940 brcmf_sdio_rxfail(bus, false, 1941 RETRYCHAN(rd->channel)); 1942 sdio_release_host(bus->sdiodev->func1); 1943 continue; 1944 } 1945 skb_pull(pkt, head_read); 1946 pkt_align(pkt, rd->len_left, bus->head_align); 1947 1948 ret = brcmf_sdiod_recv_pkt(bus->sdiodev, pkt); 1949 bus->sdcnt.f2rxdata++; 1950 sdio_release_host(bus->sdiodev->func1); 1951 1952 if (ret < 0) { 1953 brcmf_err("read %d bytes from channel %d failed: %d\n", 1954 rd->len, rd->channel, ret); 1955 brcmu_pkt_buf_free_skb(pkt); 1956 sdio_claim_host(bus->sdiodev->func1); 1957 brcmf_sdio_rxfail(bus, true, 1958 RETRYCHAN(rd->channel)); 1959 sdio_release_host(bus->sdiodev->func1); 1960 continue; 1961 } 1962 1963 if (head_read) { 1964 skb_push(pkt, head_read); 1965 memcpy(pkt->data, bus->rxhdr, head_read); 1966 head_read = 0; 1967 } else { 1968 memcpy(bus->rxhdr, pkt->data, SDPCM_HDRLEN); 1969 rd_new.seq_num = rd->seq_num; 1970 sdio_claim_host(bus->sdiodev->func1); 1971 if (brcmf_sdio_hdparse(bus, bus->rxhdr, &rd_new, 1972 BRCMF_SDIO_FT_NORMAL)) { 1973 rd->len = 0; 1974 brcmf_sdio_rxfail(bus, true, true); 1975 sdio_release_host(bus->sdiodev->func1); 1976 brcmu_pkt_buf_free_skb(pkt); 1977 continue; 1978 } 1979 bus->sdcnt.rx_readahead_cnt++; 1980 if (rd->len != roundup(rd_new.len, 16)) { 1981 brcmf_err("frame length mismatch:read %d, should be %d\n", 1982 rd->len, 1983 roundup(rd_new.len, 16) >> 4); 1984 rd->len = 0; 1985 brcmf_sdio_rxfail(bus, true, true); 1986 sdio_release_host(bus->sdiodev->func1); 1987 brcmu_pkt_buf_free_skb(pkt); 1988 continue; 1989 } 1990 sdio_release_host(bus->sdiodev->func1); 1991 rd->len_nxtfrm = rd_new.len_nxtfrm; 1992 rd->channel = rd_new.channel; 1993 rd->dat_offset = rd_new.dat_offset; 1994 1995 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && 1996 BRCMF_DATA_ON()) && 1997 BRCMF_HDRS_ON(), 1998 bus->rxhdr, SDPCM_HDRLEN, 1999 "RxHdr:\n"); 2000 2001 if (rd_new.channel == SDPCM_CONTROL_CHANNEL) { 2002 brcmf_err("readahead on control packet %d?\n", 2003 rd_new.seq_num); 2004 /* Force retry w/normal header read */ 2005 rd->len = 0; 2006 sdio_claim_host(bus->sdiodev->func1); 2007 brcmf_sdio_rxfail(bus, false, true); 2008 sdio_release_host(bus->sdiodev->func1); 2009 brcmu_pkt_buf_free_skb(pkt); 2010 continue; 2011 } 2012 } 2013 2014 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_DATA_ON(), 2015 pkt->data, rd->len, "Rx Data:\n"); 2016 2017 /* Save superframe descriptor and allocate packet frame */ 2018 if (rd->channel == SDPCM_GLOM_CHANNEL) { 2019 if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_HWHDR_LEN])) { 2020 brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n", 2021 rd->len); 2022 brcmf_dbg_hex_dump(BRCMF_GLOM_ON(), 2023 pkt->data, rd->len, 2024 "Glom Data:\n"); 2025 __skb_trim(pkt, rd->len); 2026 skb_pull(pkt, SDPCM_HDRLEN); 2027 bus->glomd = pkt; 2028 } else { 2029 brcmf_err("%s: glom superframe w/o " 2030 "descriptor!\n", __func__); 2031 sdio_claim_host(bus->sdiodev->func1); 2032 brcmf_sdio_rxfail(bus, false, false); 2033 sdio_release_host(bus->sdiodev->func1); 2034 } 2035 /* prepare the descriptor for the next read */ 2036 rd->len = rd->len_nxtfrm << 4; 2037 rd->len_nxtfrm = 0; 2038 /* treat all packet as event if we don't know */ 2039 rd->channel = SDPCM_EVENT_CHANNEL; 2040 continue; 2041 } 2042 2043 /* Fill in packet len and prio, deliver upward */ 2044 __skb_trim(pkt, rd->len); 2045 skb_pull(pkt, rd->dat_offset); 2046 2047 if (pkt->len == 0) 2048 brcmu_pkt_buf_free_skb(pkt); 2049 else if (rd->channel == SDPCM_EVENT_CHANNEL) 2050 brcmf_rx_event(bus->sdiodev->dev, pkt); 2051 else 2052 brcmf_rx_frame(bus->sdiodev->dev, pkt, 2053 false, false); 2054 2055 /* prepare the descriptor for the next read */ 2056 rd->len = rd->len_nxtfrm << 4; 2057 rd->len_nxtfrm = 0; 2058 /* treat all packet as event if we don't know */ 2059 rd->channel = SDPCM_EVENT_CHANNEL; 2060 } 2061 2062 rxcount = maxframes - rxleft; 2063 /* Message if we hit the limit */ 2064 if (!rxleft) 2065 brcmf_dbg(DATA, "hit rx limit of %d frames\n", maxframes); 2066 else 2067 brcmf_dbg(DATA, "processed %d frames\n", rxcount); 2068 /* Back off rxseq if awaiting rtx, update rx_seq */ 2069 if (bus->rxskip) 2070 rd->seq_num--; 2071 bus->rx_seq = rd->seq_num; 2072 2073 return rxcount; 2074} 2075 2076static void 2077brcmf_sdio_wait_event_wakeup(struct brcmf_sdio *bus) 2078{ 2079 wake_up_interruptible(&bus->ctrl_wait); 2080 return; 2081} 2082 2083static int brcmf_sdio_txpkt_hdalign(struct brcmf_sdio *bus, struct sk_buff *pkt) 2084{ 2085 struct brcmf_bus_stats *stats; 2086 u16 head_pad; 2087 u8 *dat_buf; 2088 2089 dat_buf = (u8 *)(pkt->data); 2090 2091 /* Check head padding */ 2092 head_pad = ((unsigned long)dat_buf % bus->head_align); 2093 if (head_pad) { 2094 if (skb_headroom(pkt) < head_pad) { 2095 stats = &bus->sdiodev->bus_if->stats; 2096 atomic_inc(&stats->pktcowed); 2097 if (skb_cow_head(pkt, head_pad)) { 2098 atomic_inc(&stats->pktcow_failed); 2099 return -ENOMEM; 2100 } 2101 head_pad = 0; 2102 } 2103 skb_push(pkt, head_pad); 2104 dat_buf = (u8 *)(pkt->data); 2105 } 2106 memset(dat_buf, 0, head_pad + bus->tx_hdrlen); 2107 return head_pad; 2108} 2109 2110/* 2111 * struct brcmf_skbuff_cb reserves first two bytes in sk_buff::cb for 2112 * bus layer usage. 2113 */ 2114/* flag marking a dummy skb added for DMA alignment requirement */ 2115#define ALIGN_SKB_FLAG 0x8000 2116/* bit mask of data length chopped from the previous packet */ 2117#define ALIGN_SKB_CHOP_LEN_MASK 0x7fff 2118 2119static int brcmf_sdio_txpkt_prep_sg(struct brcmf_sdio *bus, 2120 struct sk_buff_head *pktq, 2121 struct sk_buff *pkt, u16 total_len) 2122{ 2123 struct brcmf_sdio_dev *sdiodev; 2124 struct sk_buff *pkt_pad; 2125 u16 tail_pad, tail_chop, chain_pad; 2126 unsigned int blksize; 2127 bool lastfrm; 2128 int ntail, ret; 2129 2130 sdiodev = bus->sdiodev; 2131 blksize = sdiodev->func2->cur_blksize; 2132 /* sg entry alignment should be a divisor of block size */ 2133 WARN_ON(blksize % bus->sgentry_align); 2134 2135 /* Check tail padding */ 2136 lastfrm = skb_queue_is_last(pktq, pkt); 2137 tail_pad = 0; 2138 tail_chop = pkt->len % bus->sgentry_align; 2139 if (tail_chop) 2140 tail_pad = bus->sgentry_align - tail_chop; 2141 chain_pad = (total_len + tail_pad) % blksize; 2142 if (lastfrm && chain_pad) 2143 tail_pad += blksize - chain_pad; 2144 if (skb_tailroom(pkt) < tail_pad && pkt->len > blksize) { 2145 pkt_pad = brcmu_pkt_buf_get_skb(tail_pad + tail_chop + 2146 bus->head_align); 2147 if (pkt_pad == NULL) 2148 return -ENOMEM; 2149 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_pad); 2150 if (unlikely(ret < 0)) { 2151 kfree_skb(pkt_pad); 2152 return ret; 2153 } 2154 memcpy(pkt_pad->data, 2155 pkt->data + pkt->len - tail_chop, 2156 tail_chop); 2157 *(u16 *)(pkt_pad->cb) = ALIGN_SKB_FLAG + tail_chop; 2158 skb_trim(pkt, pkt->len - tail_chop); 2159 skb_trim(pkt_pad, tail_pad + tail_chop); 2160 __skb_queue_after(pktq, pkt, pkt_pad); 2161 } else { 2162 ntail = pkt->data_len + tail_pad - 2163 (pkt->end - pkt->tail); 2164 if (skb_cloned(pkt) || ntail > 0) 2165 if (pskb_expand_head(pkt, 0, ntail, GFP_ATOMIC)) 2166 return -ENOMEM; 2167 if (skb_linearize(pkt)) 2168 return -ENOMEM; 2169 __skb_put(pkt, tail_pad); 2170 } 2171 2172 return tail_pad; 2173} 2174 2175/** 2176 * brcmf_sdio_txpkt_prep - packet preparation for transmit 2177 * @bus: brcmf_sdio structure pointer 2178 * @pktq: packet list pointer 2179 * @chan: virtual channel to transmit the packet 2180 * 2181 * Processes to be applied to the packet 2182 * - Align data buffer pointer 2183 * - Align data buffer length 2184 * - Prepare header 2185 * Return: negative value if there is error 2186 */ 2187static int 2188brcmf_sdio_txpkt_prep(struct brcmf_sdio *bus, struct sk_buff_head *pktq, 2189 uint chan) 2190{ 2191 u16 head_pad, total_len; 2192 struct sk_buff *pkt_next; 2193 u8 txseq; 2194 int ret; 2195 struct brcmf_sdio_hdrinfo hd_info = {0}; 2196 2197 txseq = bus->tx_seq; 2198 total_len = 0; 2199 skb_queue_walk(pktq, pkt_next) { 2200 /* alignment packet inserted in previous 2201 * loop cycle can be skipped as it is 2202 * already properly aligned and does not 2203 * need an sdpcm header. 2204 */ 2205 if (*(u16 *)(pkt_next->cb) & ALIGN_SKB_FLAG) 2206 continue; 2207 2208 /* align packet data pointer */ 2209 ret = brcmf_sdio_txpkt_hdalign(bus, pkt_next); 2210 if (ret < 0) 2211 return ret; 2212 head_pad = (u16)ret; 2213 if (head_pad) 2214 memset(pkt_next->data + bus->tx_hdrlen, 0, head_pad); 2215 2216 total_len += pkt_next->len; 2217 2218 hd_info.len = pkt_next->len; 2219 hd_info.lastfrm = skb_queue_is_last(pktq, pkt_next); 2220 if (bus->txglom && pktq->qlen > 1) { 2221 ret = brcmf_sdio_txpkt_prep_sg(bus, pktq, 2222 pkt_next, total_len); 2223 if (ret < 0) 2224 return ret; 2225 hd_info.tail_pad = (u16)ret; 2226 total_len += (u16)ret; 2227 } 2228 2229 hd_info.channel = chan; 2230 hd_info.dat_offset = head_pad + bus->tx_hdrlen; 2231 hd_info.seq_num = txseq++; 2232 2233 /* Now fill the header */ 2234 brcmf_sdio_hdpack(bus, pkt_next->data, &hd_info); 2235 2236 if (BRCMF_BYTES_ON() && 2237 ((BRCMF_CTL_ON() && chan == SDPCM_CONTROL_CHANNEL) || 2238 (BRCMF_DATA_ON() && chan != SDPCM_CONTROL_CHANNEL))) 2239 brcmf_dbg_hex_dump(true, pkt_next->data, hd_info.len, 2240 "Tx Frame:\n"); 2241 else if (BRCMF_HDRS_ON()) 2242 brcmf_dbg_hex_dump(true, pkt_next->data, 2243 head_pad + bus->tx_hdrlen, 2244 "Tx Header:\n"); 2245 } 2246 /* Hardware length tag of the first packet should be total 2247 * length of the chain (including padding) 2248 */ 2249 if (bus->txglom) 2250 brcmf_sdio_update_hwhdr(__skb_peek(pktq)->data, total_len); 2251 return 0; 2252} 2253 2254/** 2255 * brcmf_sdio_txpkt_postp - packet post processing for transmit 2256 * @bus: brcmf_sdio structure pointer 2257 * @pktq: packet list pointer 2258 * 2259 * Processes to be applied to the packet 2260 * - Remove head padding 2261 * - Remove tail padding 2262 */ 2263static void 2264brcmf_sdio_txpkt_postp(struct brcmf_sdio *bus, struct sk_buff_head *pktq) 2265{ 2266 u8 *hdr; 2267 u32 dat_offset; 2268 u16 tail_pad; 2269 u16 dummy_flags, chop_len; 2270 struct sk_buff *pkt_next, *tmp, *pkt_prev; 2271 2272 skb_queue_walk_safe(pktq, pkt_next, tmp) { 2273 dummy_flags = *(u16 *)(pkt_next->cb); 2274 if (dummy_flags & ALIGN_SKB_FLAG) { 2275 chop_len = dummy_flags & ALIGN_SKB_CHOP_LEN_MASK; 2276 if (chop_len) { 2277 pkt_prev = pkt_next->prev; 2278 skb_put(pkt_prev, chop_len); 2279 } 2280 __skb_unlink(pkt_next, pktq); 2281 brcmu_pkt_buf_free_skb(pkt_next); 2282 } else { 2283 hdr = pkt_next->data + bus->tx_hdrlen - SDPCM_SWHDR_LEN; 2284 dat_offset = le32_to_cpu(*(__le32 *)hdr); 2285 dat_offset = (dat_offset & SDPCM_DOFFSET_MASK) >> 2286 SDPCM_DOFFSET_SHIFT; 2287 skb_pull(pkt_next, dat_offset); 2288 if (bus->txglom) { 2289 tail_pad = le16_to_cpu(*(__le16 *)(hdr - 2)); 2290 skb_trim(pkt_next, pkt_next->len - tail_pad); 2291 } 2292 } 2293 } 2294} 2295 2296/* Writes a HW/SW header into the packet and sends it. */ 2297/* Assumes: (a) header space already there, (b) caller holds lock */ 2298static int brcmf_sdio_txpkt(struct brcmf_sdio *bus, struct sk_buff_head *pktq, 2299 uint chan) 2300{ 2301 int ret; 2302 struct sk_buff *pkt_next, *tmp; 2303 2304 brcmf_dbg(TRACE, "Enter\n"); 2305 2306 ret = brcmf_sdio_txpkt_prep(bus, pktq, chan); 2307 if (ret) 2308 goto done; 2309 2310 sdio_claim_host(bus->sdiodev->func1); 2311 ret = brcmf_sdiod_send_pkt(bus->sdiodev, pktq); 2312 bus->sdcnt.f2txdata++; 2313 2314 if (ret < 0) 2315 brcmf_sdio_txfail(bus); 2316 2317 sdio_release_host(bus->sdiodev->func1); 2318 2319done: 2320 brcmf_sdio_txpkt_postp(bus, pktq); 2321 if (ret == 0) 2322 bus->tx_seq = (bus->tx_seq + pktq->qlen) % SDPCM_SEQ_WRAP; 2323 skb_queue_walk_safe(pktq, pkt_next, tmp) { 2324 __skb_unlink(pkt_next, pktq); 2325 brcmf_proto_bcdc_txcomplete(bus->sdiodev->dev, pkt_next, 2326 ret == 0); 2327 } 2328 return ret; 2329} 2330 2331static uint brcmf_sdio_sendfromq(struct brcmf_sdio *bus, uint maxframes) 2332{ 2333 struct sk_buff *pkt; 2334 struct sk_buff_head pktq; 2335 u32 intstat_addr = bus->sdio_core->base + SD_REG(intstatus); 2336 u32 intstatus = 0; 2337 int ret = 0, prec_out, i; 2338 uint cnt = 0; 2339 u8 tx_prec_map, pkt_num; 2340 2341 brcmf_dbg(TRACE, "Enter\n"); 2342 2343 tx_prec_map = ~bus->flowcontrol; 2344 2345 /* Send frames until the limit or some other event */ 2346 for (cnt = 0; (cnt < maxframes) && data_ok(bus);) { 2347 pkt_num = 1; 2348 if (bus->txglom) 2349 pkt_num = min_t(u8, bus->tx_max - bus->tx_seq, 2350 bus->sdiodev->txglomsz); 2351 pkt_num = min_t(u32, pkt_num, 2352 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)); 2353 __skb_queue_head_init(&pktq); 2354 spin_lock_bh(&bus->txq_lock); 2355 for (i = 0; i < pkt_num; i++) { 2356 pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, 2357 &prec_out); 2358 if (pkt == NULL) 2359 break; 2360 __skb_queue_tail(&pktq, pkt); 2361 } 2362 spin_unlock_bh(&bus->txq_lock); 2363 if (i == 0) 2364 break; 2365 2366 ret = brcmf_sdio_txpkt(bus, &pktq, SDPCM_DATA_CHANNEL); 2367 2368 cnt += i; 2369 2370 /* In poll mode, need to check for other events */ 2371 if (!bus->intr) { 2372 /* Check device status, signal pending interrupt */ 2373 sdio_claim_host(bus->sdiodev->func1); 2374 intstatus = brcmf_sdiod_readl(bus->sdiodev, 2375 intstat_addr, &ret); 2376 sdio_release_host(bus->sdiodev->func1); 2377 2378 bus->sdcnt.f2txdata++; 2379 if (ret != 0) 2380 break; 2381 if (intstatus & bus->hostintmask) 2382 atomic_set(&bus->ipend, 1); 2383 } 2384 } 2385 2386 /* Deflow-control stack if needed */ 2387 if ((bus->sdiodev->state == BRCMF_SDIOD_DATA) && 2388 bus->txoff && (pktq_len(&bus->txq) < TXLOW)) { 2389 bus->txoff = false; 2390 brcmf_proto_bcdc_txflowblock(bus->sdiodev->dev, false); 2391 } 2392 2393 return cnt; 2394} 2395 2396static int brcmf_sdio_tx_ctrlframe(struct brcmf_sdio *bus, u8 *frame, u16 len) 2397{ 2398 u8 doff; 2399 u16 pad; 2400 uint retries = 0; 2401 struct brcmf_sdio_hdrinfo hd_info = {0}; 2402 int ret; 2403 2404 brcmf_dbg(SDIO, "Enter\n"); 2405 2406 /* Back the pointer to make room for bus header */ 2407 frame -= bus->tx_hdrlen; 2408 len += bus->tx_hdrlen; 2409 2410 /* Add alignment padding (optional for ctl frames) */ 2411 doff = ((unsigned long)frame % bus->head_align); 2412 if (doff) { 2413 frame -= doff; 2414 len += doff; 2415 memset(frame + bus->tx_hdrlen, 0, doff); 2416 } 2417 2418 /* Round send length to next SDIO block */ 2419 pad = 0; 2420 if (bus->roundup && bus->blocksize && (len > bus->blocksize)) { 2421 pad = bus->blocksize - (len % bus->blocksize); 2422 if ((pad > bus->roundup) || (pad >= bus->blocksize)) 2423 pad = 0; 2424 } else if (len % bus->head_align) { 2425 pad = bus->head_align - (len % bus->head_align); 2426 } 2427 len += pad; 2428 2429 hd_info.len = len - pad; 2430 hd_info.channel = SDPCM_CONTROL_CHANNEL; 2431 hd_info.dat_offset = doff + bus->tx_hdrlen; 2432 hd_info.seq_num = bus->tx_seq; 2433 hd_info.lastfrm = true; 2434 hd_info.tail_pad = pad; 2435 brcmf_sdio_hdpack(bus, frame, &hd_info); 2436 2437 if (bus->txglom) 2438 brcmf_sdio_update_hwhdr(frame, len); 2439 2440 brcmf_dbg_hex_dump(BRCMF_BYTES_ON() && BRCMF_CTL_ON(), 2441 frame, len, "Tx Frame:\n"); 2442 brcmf_dbg_hex_dump(!(BRCMF_BYTES_ON() && BRCMF_CTL_ON()) && 2443 BRCMF_HDRS_ON(), 2444 frame, min_t(u16, len, 16), "TxHdr:\n"); 2445 2446 do { 2447 ret = brcmf_sdiod_send_buf(bus->sdiodev, frame, len); 2448 2449 if (ret < 0) 2450 brcmf_sdio_txfail(bus); 2451 else 2452 bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQ_WRAP; 2453 } while (ret < 0 && retries++ < TXRETRIES); 2454 2455 return ret; 2456} 2457 2458static bool brcmf_chip_is_ulp(struct brcmf_chip *ci) 2459{ 2460 if (ci->chip == CY_CC_43012_CHIP_ID) 2461 return true; 2462 else 2463 return false; 2464} 2465 2466static void brcmf_sdio_bus_stop(struct device *dev) 2467{ 2468 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2469 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2470 struct brcmf_sdio *bus = sdiodev->bus; 2471 struct brcmf_core *core = bus->sdio_core; 2472 u32 local_hostintmask; 2473 u8 saveclk, bpreq; 2474 int err; 2475 2476 brcmf_dbg(TRACE, "Enter\n"); 2477 2478 if (bus->watchdog_tsk) { 2479 send_sig(SIGTERM, bus->watchdog_tsk, 1); 2480 kthread_stop(bus->watchdog_tsk); 2481 bus->watchdog_tsk = NULL; 2482 } 2483 2484 if (sdiodev->state != BRCMF_SDIOD_NOMEDIUM) { 2485 sdio_claim_host(sdiodev->func1); 2486 2487 /* Enable clock for device interrupts */ 2488 brcmf_sdio_bus_sleep(bus, false, false); 2489 2490 /* Disable and clear interrupts at the chip level also */ 2491 brcmf_sdiod_writel(sdiodev, core->base + SD_REG(hostintmask), 2492 0, NULL); 2493 2494 local_hostintmask = bus->hostintmask; 2495 bus->hostintmask = 0; 2496 2497 /* Force backplane clocks to assure F2 interrupt propagates */ 2498 saveclk = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 2499 &err); 2500 if (!err) { 2501 bpreq = saveclk; 2502 bpreq |= brcmf_chip_is_ulp(bus->ci) ? 2503 SBSDIO_HT_AVAIL_REQ : SBSDIO_FORCE_HT; 2504 brcmf_sdiod_writeb(sdiodev, 2505 SBSDIO_FUNC1_CHIPCLKCSR, 2506 bpreq, &err); 2507 } 2508 if (err) 2509 brcmf_err("Failed to force clock for F2: err %d\n", 2510 err); 2511 2512 /* Turn off the bus (F2), free any pending packets */ 2513 brcmf_dbg(INTR, "disable SDIO interrupts\n"); 2514 sdio_disable_func(sdiodev->func2); 2515 2516 /* Clear any pending interrupts now that F2 is disabled */ 2517 brcmf_sdiod_writel(sdiodev, core->base + SD_REG(intstatus), 2518 local_hostintmask, NULL); 2519 2520 sdio_release_host(sdiodev->func1); 2521 } 2522 /* Clear the data packet queues */ 2523 brcmu_pktq_flush(&bus->txq, true, NULL, NULL); 2524 2525 /* Clear any held glomming stuff */ 2526 brcmu_pkt_buf_free_skb(bus->glomd); 2527 brcmf_sdio_free_glom(bus); 2528 2529 /* Clear rx control and wake any waiters */ 2530 spin_lock_bh(&bus->rxctl_lock); 2531 bus->rxlen = 0; 2532 spin_unlock_bh(&bus->rxctl_lock); 2533 brcmf_sdio_dcmd_resp_wake(bus); 2534 2535 /* Reset some F2 state stuff */ 2536 bus->rxskip = false; 2537 bus->tx_seq = bus->rx_seq = 0; 2538} 2539 2540static inline void brcmf_sdio_clrintr(struct brcmf_sdio *bus) 2541{ 2542 struct brcmf_sdio_dev *sdiodev; 2543 unsigned long flags; 2544 2545 sdiodev = bus->sdiodev; 2546 if (sdiodev->oob_irq_requested) { 2547 spin_lock_irqsave(&sdiodev->irq_en_lock, flags); 2548 if (!sdiodev->irq_en && !atomic_read(&bus->ipend)) { 2549 enable_irq(sdiodev->settings->bus.sdio.oob_irq_nr); 2550 sdiodev->irq_en = true; 2551 } 2552 spin_unlock_irqrestore(&sdiodev->irq_en_lock, flags); 2553 } 2554} 2555 2556static int brcmf_sdio_intr_rstatus(struct brcmf_sdio *bus) 2557{ 2558 struct brcmf_core *core = bus->sdio_core; 2559 u32 addr; 2560 unsigned long val; 2561 int ret; 2562 2563 addr = core->base + SD_REG(intstatus); 2564 2565 val = brcmf_sdiod_readl(bus->sdiodev, addr, &ret); 2566 bus->sdcnt.f1regdata++; 2567 if (ret != 0) 2568 return ret; 2569 2570 val &= bus->hostintmask; 2571 atomic_set(&bus->fcstate, !!(val & I_HMB_FC_STATE)); 2572 2573 /* Clear interrupts */ 2574 if (val) { 2575 brcmf_sdiod_writel(bus->sdiodev, addr, val, &ret); 2576 bus->sdcnt.f1regdata++; 2577 atomic_or(val, &bus->intstatus); 2578 } 2579 2580 return ret; 2581} 2582 2583static void brcmf_sdio_dpc(struct brcmf_sdio *bus) 2584{ 2585 struct brcmf_sdio_dev *sdiod = bus->sdiodev; 2586 u32 newstatus = 0; 2587 u32 intstat_addr = bus->sdio_core->base + SD_REG(intstatus); 2588 unsigned long intstatus; 2589 uint txlimit = bus->txbound; /* Tx frames to send before resched */ 2590 uint framecnt; /* Temporary counter of tx/rx frames */ 2591 int err = 0; 2592 2593 brcmf_dbg(SDIO, "Enter\n"); 2594 2595 sdio_claim_host(bus->sdiodev->func1); 2596 2597 /* If waiting for HTAVAIL, check status */ 2598 if (!bus->sr_enabled && bus->clkstate == CLK_PENDING) { 2599 u8 clkctl, devctl = 0; 2600 2601#ifdef DEBUG 2602 /* Check for inconsistent device control */ 2603 devctl = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_DEVICE_CTL, 2604 &err); 2605#endif /* DEBUG */ 2606 2607 /* Read CSR, if clock on switch to AVAIL, else ignore */ 2608 clkctl = brcmf_sdiod_readb(bus->sdiodev, 2609 SBSDIO_FUNC1_CHIPCLKCSR, &err); 2610 2611 brcmf_dbg(SDIO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n", 2612 devctl, clkctl); 2613 2614 if (SBSDIO_HTAV(clkctl)) { 2615 devctl = brcmf_sdiod_readb(bus->sdiodev, 2616 SBSDIO_DEVICE_CTL, &err); 2617 devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY; 2618 brcmf_sdiod_writeb(bus->sdiodev, 2619 SBSDIO_DEVICE_CTL, devctl, &err); 2620 bus->clkstate = CLK_AVAIL; 2621 } 2622 } 2623 2624 /* Make sure backplane clock is on */ 2625 brcmf_sdio_bus_sleep(bus, false, true); 2626 2627 /* Pending interrupt indicates new device status */ 2628 if (atomic_read(&bus->ipend) > 0) { 2629 atomic_set(&bus->ipend, 0); 2630 err = brcmf_sdio_intr_rstatus(bus); 2631 } 2632 2633 /* Start with leftover status bits */ 2634 intstatus = atomic_xchg(&bus->intstatus, 0); 2635 2636 /* Handle flow-control change: read new state in case our ack 2637 * crossed another change interrupt. If change still set, assume 2638 * FC ON for safety, let next loop through do the debounce. 2639 */ 2640 if (intstatus & I_HMB_FC_CHANGE) { 2641 intstatus &= ~I_HMB_FC_CHANGE; 2642 brcmf_sdiod_writel(sdiod, intstat_addr, I_HMB_FC_CHANGE, &err); 2643 2644 newstatus = brcmf_sdiod_readl(sdiod, intstat_addr, &err); 2645 2646 bus->sdcnt.f1regdata += 2; 2647 atomic_set(&bus->fcstate, 2648 !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE))); 2649 intstatus |= (newstatus & bus->hostintmask); 2650 } 2651 2652 /* Handle host mailbox indication */ 2653 if (intstatus & I_HMB_HOST_INT) { 2654 intstatus &= ~I_HMB_HOST_INT; 2655 intstatus |= brcmf_sdio_hostmail(bus); 2656 } 2657 2658 sdio_release_host(bus->sdiodev->func1); 2659 2660 /* Generally don't ask for these, can get CRC errors... */ 2661 if (intstatus & I_WR_OOSYNC) { 2662 brcmf_err("Dongle reports WR_OOSYNC\n"); 2663 intstatus &= ~I_WR_OOSYNC; 2664 } 2665 2666 if (intstatus & I_RD_OOSYNC) { 2667 brcmf_err("Dongle reports RD_OOSYNC\n"); 2668 intstatus &= ~I_RD_OOSYNC; 2669 } 2670 2671 if (intstatus & I_SBINT) { 2672 brcmf_err("Dongle reports SBINT\n"); 2673 intstatus &= ~I_SBINT; 2674 } 2675 2676 /* Would be active due to wake-wlan in gSPI */ 2677 if (intstatus & I_CHIPACTIVE) { 2678 brcmf_dbg(SDIO, "Dongle reports CHIPACTIVE\n"); 2679 intstatus &= ~I_CHIPACTIVE; 2680 } 2681 2682 /* Ignore frame indications if rxskip is set */ 2683 if (bus->rxskip) 2684 intstatus &= ~I_HMB_FRAME_IND; 2685 2686 /* On frame indication, read available frames */ 2687 if ((intstatus & I_HMB_FRAME_IND) && (bus->clkstate == CLK_AVAIL)) { 2688 brcmf_sdio_readframes(bus, bus->rxbound); 2689 if (!bus->rxpending) 2690 intstatus &= ~I_HMB_FRAME_IND; 2691 } 2692 2693 /* Keep still-pending events for next scheduling */ 2694 if (intstatus) 2695 atomic_or(intstatus, &bus->intstatus); 2696 2697 brcmf_sdio_clrintr(bus); 2698 2699 if (bus->ctrl_frame_stat && (bus->clkstate == CLK_AVAIL) && 2700 txctl_ok(bus)) { 2701 sdio_claim_host(bus->sdiodev->func1); 2702 if (bus->ctrl_frame_stat) { 2703 err = brcmf_sdio_tx_ctrlframe(bus, bus->ctrl_frame_buf, 2704 bus->ctrl_frame_len); 2705 bus->ctrl_frame_err = err; 2706 wmb(); 2707 bus->ctrl_frame_stat = false; 2708 if (err) 2709 brcmf_err("sdio ctrlframe tx failed err=%d\n", 2710 err); 2711 } 2712 sdio_release_host(bus->sdiodev->func1); 2713 brcmf_sdio_wait_event_wakeup(bus); 2714 } 2715 /* Send queued frames (limit 1 if rx may still be pending) */ 2716 if ((bus->clkstate == CLK_AVAIL) && !atomic_read(&bus->fcstate) && 2717 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit && 2718 data_ok(bus)) { 2719 framecnt = bus->rxpending ? min(txlimit, bus->txminmax) : 2720 txlimit; 2721 brcmf_sdio_sendfromq(bus, framecnt); 2722 } 2723 2724 if ((bus->sdiodev->state != BRCMF_SDIOD_DATA) || (err != 0)) { 2725 brcmf_err("failed backplane access over SDIO, halting operation\n"); 2726 atomic_set(&bus->intstatus, 0); 2727 if (bus->ctrl_frame_stat) { 2728 sdio_claim_host(bus->sdiodev->func1); 2729 if (bus->ctrl_frame_stat) { 2730 bus->ctrl_frame_err = -ENODEV; 2731 wmb(); 2732 bus->ctrl_frame_stat = false; 2733 brcmf_sdio_wait_event_wakeup(bus); 2734 } 2735 sdio_release_host(bus->sdiodev->func1); 2736 } 2737 } else if (atomic_read(&bus->intstatus) || 2738 atomic_read(&bus->ipend) > 0 || 2739 (!atomic_read(&bus->fcstate) && 2740 brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && 2741 data_ok(bus))) { 2742 bus->dpc_triggered = true; 2743 } 2744} 2745 2746static struct pktq *brcmf_sdio_bus_gettxq(struct device *dev) 2747{ 2748 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2749 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2750 struct brcmf_sdio *bus = sdiodev->bus; 2751 2752 return &bus->txq; 2753} 2754 2755static bool brcmf_sdio_prec_enq(struct pktq *q, struct sk_buff *pkt, int prec) 2756{ 2757 struct sk_buff *p; 2758 int eprec = -1; /* precedence to evict from */ 2759 2760 /* Fast case, precedence queue is not full and we are also not 2761 * exceeding total queue length 2762 */ 2763 if (!pktq_pfull(q, prec) && !pktq_full(q)) { 2764 brcmu_pktq_penq(q, prec, pkt); 2765 return true; 2766 } 2767 2768 /* Determine precedence from which to evict packet, if any */ 2769 if (pktq_pfull(q, prec)) { 2770 eprec = prec; 2771 } else if (pktq_full(q)) { 2772 p = brcmu_pktq_peek_tail(q, &eprec); 2773 if (eprec > prec) 2774 return false; 2775 } 2776 2777 /* Evict if needed */ 2778 if (eprec >= 0) { 2779 /* Detect queueing to unconfigured precedence */ 2780 if (eprec == prec) 2781 return false; /* refuse newer (incoming) packet */ 2782 /* Evict packet according to discard policy */ 2783 p = brcmu_pktq_pdeq_tail(q, eprec); 2784 if (p == NULL) 2785 brcmf_err("brcmu_pktq_pdeq_tail() failed\n"); 2786 brcmu_pkt_buf_free_skb(p); 2787 } 2788 2789 /* Enqueue */ 2790 p = brcmu_pktq_penq(q, prec, pkt); 2791 if (p == NULL) 2792 brcmf_err("brcmu_pktq_penq() failed\n"); 2793 2794 return p != NULL; 2795} 2796 2797static int brcmf_sdio_bus_txdata(struct device *dev, struct sk_buff *pkt) 2798{ 2799 int ret = -EBADE; 2800 uint prec; 2801 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2802 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2803 struct brcmf_sdio *bus = sdiodev->bus; 2804 2805 brcmf_dbg(TRACE, "Enter: pkt: data %p len %d\n", pkt->data, pkt->len); 2806 if (sdiodev->state != BRCMF_SDIOD_DATA) 2807 return -EIO; 2808 2809 /* Add space for the header */ 2810 skb_push(pkt, bus->tx_hdrlen); 2811 /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */ 2812 2813 /* In WLAN, priority is always set by the AP using WMM parameters 2814 * and this need not always follow the standard 802.1d priority. 2815 * Based on AP WMM config, map from 802.1d priority to corresponding 2816 * precedence level. 2817 */ 2818 prec = brcmf_map_prio_to_prec(bus_if->drvr->config, 2819 (pkt->priority & PRIOMASK)); 2820 2821 /* Check for existing queue, current flow-control, 2822 pending event, or pending clock */ 2823 brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq)); 2824 bus->sdcnt.fcqueued++; 2825 2826 /* Priority based enq */ 2827 spin_lock_bh(&bus->txq_lock); 2828 /* reset bus_flags in packet cb */ 2829 *(u16 *)(pkt->cb) = 0; 2830 if (!brcmf_sdio_prec_enq(&bus->txq, pkt, prec)) { 2831 skb_pull(pkt, bus->tx_hdrlen); 2832 brcmf_err("out of bus->txq !!!\n"); 2833 ret = -ENOSR; 2834 } else { 2835 ret = 0; 2836 } 2837 2838 if (pktq_len(&bus->txq) >= TXHI) { 2839 bus->txoff = true; 2840 brcmf_proto_bcdc_txflowblock(dev, true); 2841 } 2842 spin_unlock_bh(&bus->txq_lock); 2843 2844#ifdef DEBUG 2845 if (pktq_plen(&bus->txq, prec) > qcount[prec]) 2846 qcount[prec] = pktq_plen(&bus->txq, prec); 2847#endif 2848 2849 brcmf_sdio_trigger_dpc(bus); 2850 return ret; 2851} 2852 2853#ifdef DEBUG 2854#define CONSOLE_LINE_MAX 192 2855 2856static int brcmf_sdio_readconsole(struct brcmf_sdio *bus) 2857{ 2858 struct brcmf_console *c = &bus->console; 2859 u8 line[CONSOLE_LINE_MAX], ch; 2860 u32 n, idx, addr; 2861 int rv; 2862 2863 /* Don't do anything until FWREADY updates console address */ 2864 if (bus->console_addr == 0) 2865 return 0; 2866 2867 /* Read console log struct */ 2868 addr = bus->console_addr + offsetof(struct rte_console, log_le); 2869 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, (u8 *)&c->log_le, 2870 sizeof(c->log_le)); 2871 if (rv < 0) 2872 return rv; 2873 2874 /* Allocate console buffer (one time only) */ 2875 if (c->buf == NULL) { 2876 c->bufsize = le32_to_cpu(c->log_le.buf_size); 2877 c->buf = kmalloc(c->bufsize, GFP_ATOMIC); 2878 if (c->buf == NULL) 2879 return -ENOMEM; 2880 } 2881 2882 idx = le32_to_cpu(c->log_le.idx); 2883 2884 /* Protect against corrupt value */ 2885 if (idx > c->bufsize) 2886 return -EBADE; 2887 2888 /* Skip reading the console buffer if the index pointer 2889 has not moved */ 2890 if (idx == c->last) 2891 return 0; 2892 2893 /* Read the console buffer */ 2894 addr = le32_to_cpu(c->log_le.buf); 2895 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, c->buf, c->bufsize); 2896 if (rv < 0) 2897 return rv; 2898 2899 while (c->last != idx) { 2900 for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) { 2901 if (c->last == idx) { 2902 /* This would output a partial line. 2903 * Instead, back up 2904 * the buffer pointer and output this 2905 * line next time around. 2906 */ 2907 if (c->last >= n) 2908 c->last -= n; 2909 else 2910 c->last = c->bufsize - n; 2911 goto break2; 2912 } 2913 ch = c->buf[c->last]; 2914 c->last = (c->last + 1) % c->bufsize; 2915 if (ch == '\n') 2916 break; 2917 line[n] = ch; 2918 } 2919 2920 if (n > 0) { 2921 if (line[n - 1] == '\r') 2922 n--; 2923 line[n] = 0; 2924 pr_debug("CONSOLE: %s\n", line); 2925 } 2926 } 2927break2: 2928 2929 return 0; 2930} 2931#endif /* DEBUG */ 2932 2933static int 2934brcmf_sdio_bus_txctl(struct device *dev, unsigned char *msg, uint msglen) 2935{ 2936 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 2937 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 2938 struct brcmf_sdio *bus = sdiodev->bus; 2939 int ret; 2940 2941 brcmf_dbg(TRACE, "Enter\n"); 2942 if (sdiodev->state != BRCMF_SDIOD_DATA) 2943 return -EIO; 2944 2945 /* Send from dpc */ 2946 bus->ctrl_frame_buf = msg; 2947 bus->ctrl_frame_len = msglen; 2948 wmb(); 2949 bus->ctrl_frame_stat = true; 2950 2951 brcmf_sdio_trigger_dpc(bus); 2952 wait_event_interruptible_timeout(bus->ctrl_wait, !bus->ctrl_frame_stat, 2953 CTL_DONE_TIMEOUT); 2954 ret = 0; 2955 if (bus->ctrl_frame_stat) { 2956 sdio_claim_host(bus->sdiodev->func1); 2957 if (bus->ctrl_frame_stat) { 2958 brcmf_dbg(SDIO, "ctrl_frame timeout\n"); 2959 bus->ctrl_frame_stat = false; 2960 ret = -ETIMEDOUT; 2961 } 2962 sdio_release_host(bus->sdiodev->func1); 2963 } 2964 if (!ret) { 2965 brcmf_dbg(SDIO, "ctrl_frame complete, err=%d\n", 2966 bus->ctrl_frame_err); 2967 rmb(); 2968 ret = bus->ctrl_frame_err; 2969 } 2970 2971 if (ret) 2972 bus->sdcnt.tx_ctlerrs++; 2973 else 2974 bus->sdcnt.tx_ctlpkts++; 2975 2976 return ret; 2977} 2978 2979#ifdef DEBUG 2980static int brcmf_sdio_dump_console(struct seq_file *seq, struct brcmf_sdio *bus, 2981 struct sdpcm_shared *sh) 2982{ 2983 u32 addr, console_ptr, console_size, console_index; 2984 char *conbuf = NULL; 2985 __le32 sh_val; 2986 int rv; 2987 2988 /* obtain console information from device memory */ 2989 addr = sh->console_addr + offsetof(struct rte_console, log_le); 2990 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, 2991 (u8 *)&sh_val, sizeof(u32)); 2992 if (rv < 0) 2993 return rv; 2994 console_ptr = le32_to_cpu(sh_val); 2995 2996 addr = sh->console_addr + offsetof(struct rte_console, log_le.buf_size); 2997 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, 2998 (u8 *)&sh_val, sizeof(u32)); 2999 if (rv < 0) 3000 return rv; 3001 console_size = le32_to_cpu(sh_val); 3002 3003 addr = sh->console_addr + offsetof(struct rte_console, log_le.idx); 3004 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, addr, 3005 (u8 *)&sh_val, sizeof(u32)); 3006 if (rv < 0) 3007 return rv; 3008 console_index = le32_to_cpu(sh_val); 3009 3010 /* allocate buffer for console data */ 3011 if (console_size <= CONSOLE_BUFFER_MAX) 3012 conbuf = vzalloc(console_size+1); 3013 3014 if (!conbuf) 3015 return -ENOMEM; 3016 3017 /* obtain the console data from device */ 3018 conbuf[console_size] = '\0'; 3019 rv = brcmf_sdiod_ramrw(bus->sdiodev, false, console_ptr, (u8 *)conbuf, 3020 console_size); 3021 if (rv < 0) 3022 goto done; 3023 3024 rv = seq_write(seq, conbuf + console_index, 3025 console_size - console_index); 3026 if (rv < 0) 3027 goto done; 3028 3029 if (console_index > 0) 3030 rv = seq_write(seq, conbuf, console_index - 1); 3031 3032done: 3033 vfree(conbuf); 3034 return rv; 3035} 3036 3037static int brcmf_sdio_trap_info(struct seq_file *seq, struct brcmf_sdio *bus, 3038 struct sdpcm_shared *sh) 3039{ 3040 int error; 3041 struct brcmf_trap_info tr; 3042 3043 if ((sh->flags & SDPCM_SHARED_TRAP) == 0) { 3044 brcmf_dbg(INFO, "no trap in firmware\n"); 3045 return 0; 3046 } 3047 3048 error = brcmf_sdiod_ramrw(bus->sdiodev, false, sh->trap_addr, (u8 *)&tr, 3049 sizeof(struct brcmf_trap_info)); 3050 if (error < 0) 3051 return error; 3052 3053 if (seq) 3054 seq_printf(seq, 3055 "dongle trap info: type 0x%x @ epc 0x%08x\n" 3056 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n" 3057 " lr 0x%08x pc 0x%08x offset 0x%x\n" 3058 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n" 3059 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n", 3060 le32_to_cpu(tr.type), le32_to_cpu(tr.epc), 3061 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr), 3062 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14), 3063 le32_to_cpu(tr.pc), sh->trap_addr, 3064 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1), 3065 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3), 3066 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5), 3067 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7)); 3068 else 3069 pr_debug("dongle trap info: type 0x%x @ epc 0x%08x\n" 3070 " cpsr 0x%08x spsr 0x%08x sp 0x%08x\n" 3071 " lr 0x%08x pc 0x%08x offset 0x%x\n" 3072 " r0 0x%08x r1 0x%08x r2 0x%08x r3 0x%08x\n" 3073 " r4 0x%08x r5 0x%08x r6 0x%08x r7 0x%08x\n", 3074 le32_to_cpu(tr.type), le32_to_cpu(tr.epc), 3075 le32_to_cpu(tr.cpsr), le32_to_cpu(tr.spsr), 3076 le32_to_cpu(tr.r13), le32_to_cpu(tr.r14), 3077 le32_to_cpu(tr.pc), sh->trap_addr, 3078 le32_to_cpu(tr.r0), le32_to_cpu(tr.r1), 3079 le32_to_cpu(tr.r2), le32_to_cpu(tr.r3), 3080 le32_to_cpu(tr.r4), le32_to_cpu(tr.r5), 3081 le32_to_cpu(tr.r6), le32_to_cpu(tr.r7)); 3082 return 0; 3083} 3084 3085static int brcmf_sdio_assert_info(struct seq_file *seq, struct brcmf_sdio *bus, 3086 struct sdpcm_shared *sh) 3087{ 3088 int error = 0; 3089 char file[80] = "?"; 3090 char expr[80] = "<???>"; 3091 3092 if ((sh->flags & SDPCM_SHARED_ASSERT_BUILT) == 0) { 3093 brcmf_dbg(INFO, "firmware not built with -assert\n"); 3094 return 0; 3095 } else if ((sh->flags & SDPCM_SHARED_ASSERT) == 0) { 3096 brcmf_dbg(INFO, "no assert in dongle\n"); 3097 return 0; 3098 } 3099 3100 sdio_claim_host(bus->sdiodev->func1); 3101 if (sh->assert_file_addr != 0) { 3102 error = brcmf_sdiod_ramrw(bus->sdiodev, false, 3103 sh->assert_file_addr, (u8 *)file, 80); 3104 if (error < 0) 3105 return error; 3106 } 3107 if (sh->assert_exp_addr != 0) { 3108 error = brcmf_sdiod_ramrw(bus->sdiodev, false, 3109 sh->assert_exp_addr, (u8 *)expr, 80); 3110 if (error < 0) 3111 return error; 3112 } 3113 sdio_release_host(bus->sdiodev->func1); 3114 3115 seq_printf(seq, "dongle assert: %s:%d: assert(%s)\n", 3116 file, sh->assert_line, expr); 3117 return 0; 3118} 3119 3120static int brcmf_sdio_checkdied(struct brcmf_sdio *bus) 3121{ 3122 int error; 3123 struct sdpcm_shared sh; 3124 3125 error = brcmf_sdio_readshared(bus, &sh); 3126 3127 if (error < 0) 3128 return error; 3129 3130 if ((sh.flags & SDPCM_SHARED_ASSERT_BUILT) == 0) 3131 brcmf_dbg(INFO, "firmware not built with -assert\n"); 3132 else if (sh.flags & SDPCM_SHARED_ASSERT) 3133 brcmf_err("assertion in dongle\n"); 3134 3135 if (sh.flags & SDPCM_SHARED_TRAP) { 3136 brcmf_err("firmware trap in dongle\n"); 3137 brcmf_sdio_trap_info(NULL, bus, &sh); 3138 } 3139 3140 return 0; 3141} 3142 3143static int brcmf_sdio_died_dump(struct seq_file *seq, struct brcmf_sdio *bus) 3144{ 3145 int error = 0; 3146 struct sdpcm_shared sh; 3147 3148 error = brcmf_sdio_readshared(bus, &sh); 3149 if (error < 0) 3150 goto done; 3151 3152 error = brcmf_sdio_assert_info(seq, bus, &sh); 3153 if (error < 0) 3154 goto done; 3155 3156 error = brcmf_sdio_trap_info(seq, bus, &sh); 3157 if (error < 0) 3158 goto done; 3159 3160 error = brcmf_sdio_dump_console(seq, bus, &sh); 3161 3162done: 3163 return error; 3164} 3165 3166static int brcmf_sdio_forensic_read(struct seq_file *seq, void *data) 3167{ 3168 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private); 3169 struct brcmf_sdio *bus = bus_if->bus_priv.sdio->bus; 3170 3171 return brcmf_sdio_died_dump(seq, bus); 3172} 3173 3174static int brcmf_debugfs_sdio_count_read(struct seq_file *seq, void *data) 3175{ 3176 struct brcmf_bus *bus_if = dev_get_drvdata(seq->private); 3177 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3178 struct brcmf_sdio_count *sdcnt = &sdiodev->bus->sdcnt; 3179 3180 seq_printf(seq, 3181 "intrcount: %u\nlastintrs: %u\n" 3182 "pollcnt: %u\nregfails: %u\n" 3183 "tx_sderrs: %u\nfcqueued: %u\n" 3184 "rxrtx: %u\nrx_toolong: %u\n" 3185 "rxc_errors: %u\nrx_hdrfail: %u\n" 3186 "rx_badhdr: %u\nrx_badseq: %u\n" 3187 "fc_rcvd: %u\nfc_xoff: %u\n" 3188 "fc_xon: %u\nrxglomfail: %u\n" 3189 "rxglomframes: %u\nrxglompkts: %u\n" 3190 "f2rxhdrs: %u\nf2rxdata: %u\n" 3191 "f2txdata: %u\nf1regdata: %u\n" 3192 "tickcnt: %u\ntx_ctlerrs: %lu\n" 3193 "tx_ctlpkts: %lu\nrx_ctlerrs: %lu\n" 3194 "rx_ctlpkts: %lu\nrx_readahead: %lu\n", 3195 sdcnt->intrcount, sdcnt->lastintrs, 3196 sdcnt->pollcnt, sdcnt->regfails, 3197 sdcnt->tx_sderrs, sdcnt->fcqueued, 3198 sdcnt->rxrtx, sdcnt->rx_toolong, 3199 sdcnt->rxc_errors, sdcnt->rx_hdrfail, 3200 sdcnt->rx_badhdr, sdcnt->rx_badseq, 3201 sdcnt->fc_rcvd, sdcnt->fc_xoff, 3202 sdcnt->fc_xon, sdcnt->rxglomfail, 3203 sdcnt->rxglomframes, sdcnt->rxglompkts, 3204 sdcnt->f2rxhdrs, sdcnt->f2rxdata, 3205 sdcnt->f2txdata, sdcnt->f1regdata, 3206 sdcnt->tickcnt, sdcnt->tx_ctlerrs, 3207 sdcnt->tx_ctlpkts, sdcnt->rx_ctlerrs, 3208 sdcnt->rx_ctlpkts, sdcnt->rx_readahead_cnt); 3209 3210 return 0; 3211} 3212 3213static void brcmf_sdio_debugfs_create(struct device *dev) 3214{ 3215 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3216 struct brcmf_pub *drvr = bus_if->drvr; 3217 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3218 struct brcmf_sdio *bus = sdiodev->bus; 3219 struct dentry *dentry = brcmf_debugfs_get_devdir(drvr); 3220 3221 if (IS_ERR_OR_NULL(dentry)) 3222 return; 3223 3224 bus->console_interval = BRCMF_CONSOLE; 3225 3226 brcmf_debugfs_add_entry(drvr, "forensics", brcmf_sdio_forensic_read); 3227 brcmf_debugfs_add_entry(drvr, "counters", 3228 brcmf_debugfs_sdio_count_read); 3229 debugfs_create_u32("console_interval", 0644, dentry, 3230 &bus->console_interval); 3231} 3232#else 3233static int brcmf_sdio_checkdied(struct brcmf_sdio *bus) 3234{ 3235 return 0; 3236} 3237 3238static void brcmf_sdio_debugfs_create(struct device *dev) 3239{ 3240} 3241#endif /* DEBUG */ 3242 3243static int 3244brcmf_sdio_bus_rxctl(struct device *dev, unsigned char *msg, uint msglen) 3245{ 3246 int timeleft; 3247 uint rxlen = 0; 3248 bool pending; 3249 u8 *buf; 3250 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3251 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3252 struct brcmf_sdio *bus = sdiodev->bus; 3253 3254 brcmf_dbg(TRACE, "Enter\n"); 3255 if (sdiodev->state != BRCMF_SDIOD_DATA) 3256 return -EIO; 3257 3258 /* Wait until control frame is available */ 3259 timeleft = brcmf_sdio_dcmd_resp_wait(bus, &bus->rxlen, &pending); 3260 3261 spin_lock_bh(&bus->rxctl_lock); 3262 rxlen = bus->rxlen; 3263 memcpy(msg, bus->rxctl, min(msglen, rxlen)); 3264 bus->rxctl = NULL; 3265 buf = bus->rxctl_orig; 3266 bus->rxctl_orig = NULL; 3267 bus->rxlen = 0; 3268 spin_unlock_bh(&bus->rxctl_lock); 3269 vfree(buf); 3270 3271 if (rxlen) { 3272 brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n", 3273 rxlen, msglen); 3274 } else if (timeleft == 0) { 3275 brcmf_err("resumed on timeout\n"); 3276 brcmf_sdio_checkdied(bus); 3277 } else if (pending) { 3278 brcmf_dbg(CTL, "cancelled\n"); 3279 return -ERESTARTSYS; 3280 } else { 3281 brcmf_dbg(CTL, "resumed for unknown reason?\n"); 3282 brcmf_sdio_checkdied(bus); 3283 } 3284 3285 if (rxlen) 3286 bus->sdcnt.rx_ctlpkts++; 3287 else 3288 bus->sdcnt.rx_ctlerrs++; 3289 3290 return rxlen ? (int)rxlen : -ETIMEDOUT; 3291} 3292 3293#ifdef DEBUG 3294static bool 3295brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr, 3296 u8 *ram_data, uint ram_sz) 3297{ 3298 char *ram_cmp; 3299 int err; 3300 bool ret = true; 3301 int address; 3302 int offset; 3303 int len; 3304 3305 /* read back and verify */ 3306 brcmf_dbg(INFO, "Compare RAM dl & ul at 0x%08x; size=%d\n", ram_addr, 3307 ram_sz); 3308 ram_cmp = kmalloc(MEMBLOCK, GFP_KERNEL); 3309 /* do not proceed while no memory but */ 3310 if (!ram_cmp) 3311 return true; 3312 3313 address = ram_addr; 3314 offset = 0; 3315 while (offset < ram_sz) { 3316 len = ((offset + MEMBLOCK) < ram_sz) ? MEMBLOCK : 3317 ram_sz - offset; 3318 err = brcmf_sdiod_ramrw(sdiodev, false, address, ram_cmp, len); 3319 if (err) { 3320 brcmf_err("error %d on reading %d membytes at 0x%08x\n", 3321 err, len, address); 3322 ret = false; 3323 break; 3324 } else if (memcmp(ram_cmp, &ram_data[offset], len)) { 3325 brcmf_err("Downloaded RAM image is corrupted, block offset is %d, len is %d\n", 3326 offset, len); 3327 ret = false; 3328 break; 3329 } 3330 offset += len; 3331 address += len; 3332 } 3333 3334 kfree(ram_cmp); 3335 3336 return ret; 3337} 3338#else /* DEBUG */ 3339static bool 3340brcmf_sdio_verifymemory(struct brcmf_sdio_dev *sdiodev, u32 ram_addr, 3341 u8 *ram_data, uint ram_sz) 3342{ 3343 return true; 3344} 3345#endif /* DEBUG */ 3346 3347static int brcmf_sdio_download_code_file(struct brcmf_sdio *bus, 3348 const struct firmware *fw) 3349{ 3350 int err; 3351 3352 brcmf_dbg(TRACE, "Enter\n"); 3353 3354 err = brcmf_sdiod_ramrw(bus->sdiodev, true, bus->ci->rambase, 3355 (u8 *)fw->data, fw->size); 3356 if (err) 3357 brcmf_err("error %d on writing %d membytes at 0x%08x\n", 3358 err, (int)fw->size, bus->ci->rambase); 3359 else if (!brcmf_sdio_verifymemory(bus->sdiodev, bus->ci->rambase, 3360 (u8 *)fw->data, fw->size)) 3361 err = -EIO; 3362 3363 return err; 3364} 3365 3366static int brcmf_sdio_download_nvram(struct brcmf_sdio *bus, 3367 void *vars, u32 varsz) 3368{ 3369 int address; 3370 int err; 3371 3372 brcmf_dbg(TRACE, "Enter\n"); 3373 3374 address = bus->ci->ramsize - varsz + bus->ci->rambase; 3375 err = brcmf_sdiod_ramrw(bus->sdiodev, true, address, vars, varsz); 3376 if (err) 3377 brcmf_err("error %d on writing %d nvram bytes at 0x%08x\n", 3378 err, varsz, address); 3379 else if (!brcmf_sdio_verifymemory(bus->sdiodev, address, vars, varsz)) 3380 err = -EIO; 3381 3382 return err; 3383} 3384 3385static int brcmf_sdio_download_firmware(struct brcmf_sdio *bus, 3386 const struct firmware *fw, 3387 void *nvram, u32 nvlen) 3388{ 3389 int bcmerror; 3390 u32 rstvec; 3391 3392 sdio_claim_host(bus->sdiodev->func1); 3393 brcmf_sdio_clkctl(bus, CLK_AVAIL, false); 3394 3395 rstvec = get_unaligned_le32(fw->data); 3396 brcmf_dbg(SDIO, "firmware rstvec: %x\n", rstvec); 3397 3398 bcmerror = brcmf_sdio_download_code_file(bus, fw); 3399 release_firmware(fw); 3400 if (bcmerror) { 3401 brcmf_err("dongle image file download failed\n"); 3402 brcmf_fw_nvram_free(nvram); 3403 goto err; 3404 } 3405 3406 bcmerror = brcmf_sdio_download_nvram(bus, nvram, nvlen); 3407 brcmf_fw_nvram_free(nvram); 3408 if (bcmerror) { 3409 brcmf_err("dongle nvram file download failed\n"); 3410 goto err; 3411 } 3412 3413 /* Take arm out of reset */ 3414 if (!brcmf_chip_set_active(bus->ci, rstvec)) { 3415 brcmf_err("error getting out of ARM core reset\n"); 3416 bcmerror = -EIO; 3417 goto err; 3418 } 3419 3420err: 3421 brcmf_sdio_clkctl(bus, CLK_SDONLY, false); 3422 sdio_release_host(bus->sdiodev->func1); 3423 return bcmerror; 3424} 3425 3426static bool brcmf_sdio_aos_no_decode(struct brcmf_sdio *bus) 3427{ 3428 if (bus->ci->chip == BRCM_CC_43751_CHIP_ID || 3429 bus->ci->chip == BRCM_CC_43752_CHIP_ID || 3430 bus->ci->chip == CY_CC_43012_CHIP_ID) 3431 return true; 3432 else 3433 return false; 3434} 3435 3436static void brcmf_sdio_sr_init(struct brcmf_sdio *bus) 3437{ 3438 int err = 0; 3439 u8 val; 3440 u8 wakeupctrl; 3441 u8 cardcap; 3442 u8 chipclkcsr; 3443 3444 brcmf_dbg(TRACE, "Enter\n"); 3445 3446 if (brcmf_chip_is_ulp(bus->ci)) { 3447 wakeupctrl = SBSDIO_FUNC1_WCTRL_ALPWAIT_SHIFT; 3448 chipclkcsr = SBSDIO_HT_AVAIL_REQ; 3449 } else { 3450 wakeupctrl = SBSDIO_FUNC1_WCTRL_HTWAIT_SHIFT; 3451 chipclkcsr = SBSDIO_FORCE_HT; 3452 } 3453 3454 if (brcmf_sdio_aos_no_decode(bus)) { 3455 cardcap = SDIO_CCCR_BRCM_CARDCAP_CMD_NODEC; 3456 } else { 3457 cardcap = (SDIO_CCCR_BRCM_CARDCAP_CMD14_SUPPORT | 3458 SDIO_CCCR_BRCM_CARDCAP_CMD14_EXT); 3459 } 3460 3461 val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, &err); 3462 if (err) { 3463 brcmf_err("error reading SBSDIO_FUNC1_WAKEUPCTRL\n"); 3464 return; 3465 } 3466 val |= 1 << wakeupctrl; 3467 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_WAKEUPCTRL, val, &err); 3468 if (err) { 3469 brcmf_err("error writing SBSDIO_FUNC1_WAKEUPCTRL\n"); 3470 return; 3471 } 3472 3473 /* Add CMD14 Support */ 3474 brcmf_sdiod_func0_wb(bus->sdiodev, SDIO_CCCR_BRCM_CARDCAP, 3475 cardcap, 3476 &err); 3477 if (err) { 3478 brcmf_err("error writing SDIO_CCCR_BRCM_CARDCAP\n"); 3479 return; 3480 } 3481 3482 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 3483 chipclkcsr, &err); 3484 if (err) { 3485 brcmf_err("error writing SBSDIO_FUNC1_CHIPCLKCSR\n"); 3486 return; 3487 } 3488 3489 /* set flag */ 3490 bus->sr_enabled = true; 3491 brcmf_dbg(INFO, "SR enabled\n"); 3492} 3493 3494/* enable KSO bit */ 3495static int brcmf_sdio_kso_init(struct brcmf_sdio *bus) 3496{ 3497 struct brcmf_core *core = bus->sdio_core; 3498 u8 val; 3499 int err = 0; 3500 3501 brcmf_dbg(TRACE, "Enter\n"); 3502 3503 /* KSO bit added in SDIO core rev 12 */ 3504 if (core->rev < 12) 3505 return 0; 3506 3507 val = brcmf_sdiod_readb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, &err); 3508 if (err) { 3509 brcmf_err("error reading SBSDIO_FUNC1_SLEEPCSR\n"); 3510 return err; 3511 } 3512 3513 if (!(val & SBSDIO_FUNC1_SLEEPCSR_KSO_MASK)) { 3514 val |= (SBSDIO_FUNC1_SLEEPCSR_KSO_EN << 3515 SBSDIO_FUNC1_SLEEPCSR_KSO_SHIFT); 3516 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_SLEEPCSR, 3517 val, &err); 3518 if (err) { 3519 brcmf_err("error writing SBSDIO_FUNC1_SLEEPCSR\n"); 3520 return err; 3521 } 3522 } 3523 3524 return 0; 3525} 3526 3527 3528static int brcmf_sdio_bus_preinit(struct device *dev) 3529{ 3530 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3531 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3532 struct brcmf_sdio *bus = sdiodev->bus; 3533 struct brcmf_core *core = bus->sdio_core; 3534 u32 value; 3535 __le32 iovar; 3536 int err; 3537 3538 /* maxctl provided by common layer */ 3539 if (WARN_ON(!bus_if->maxctl)) 3540 return -EINVAL; 3541 3542 /* Allocate control receive buffer */ 3543 bus_if->maxctl += bus->roundup; 3544 value = roundup((bus_if->maxctl + SDPCM_HDRLEN), ALIGNMENT); 3545 value += bus->head_align; 3546 bus->rxbuf = kmalloc(value, GFP_ATOMIC); 3547 if (bus->rxbuf) 3548 bus->rxblen = value; 3549 3550 /* the commands below use the terms tx and rx from 3551 * a device perspective, ie. bus:txglom affects the 3552 * bus transfers from device to host. 3553 */ 3554 if (core->rev < 12) { 3555 /* for sdio core rev < 12, disable txgloming */ 3556 iovar = 0; 3557 err = brcmf_iovar_data_set(dev, "bus:txglom", &iovar, 3558 sizeof(iovar)); 3559 } else { 3560 /* otherwise, set txglomalign */ 3561 value = sdiodev->settings->bus.sdio.sd_sgentry_align; 3562 /* SDIO ADMA requires at least 32 bit alignment */ 3563 iovar = cpu_to_le32(max_t(u32, value, ALIGNMENT)); 3564 err = brcmf_iovar_data_set(dev, "bus:txglomalign", &iovar, 3565 sizeof(iovar)); 3566 } 3567 3568 if (err < 0) 3569 goto done; 3570 3571 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN; 3572 if (sdiodev->sg_support) { 3573 bus->txglom = false; 3574 iovar = cpu_to_le32(1); 3575 err = brcmf_iovar_data_set(bus->sdiodev->dev, "bus:rxglom", 3576 &iovar, sizeof(iovar)); 3577 if (err < 0) { 3578 /* bus:rxglom is allowed to fail */ 3579 err = 0; 3580 } else { 3581 bus->txglom = true; 3582 bus->tx_hdrlen += SDPCM_HWEXT_LEN; 3583 } 3584 } 3585 brcmf_bus_add_txhdrlen(bus->sdiodev->dev, bus->tx_hdrlen); 3586 3587done: 3588 return err; 3589} 3590 3591static size_t brcmf_sdio_bus_get_ramsize(struct device *dev) 3592{ 3593 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3594 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3595 struct brcmf_sdio *bus = sdiodev->bus; 3596 3597 return bus->ci->ramsize - bus->ci->srsize; 3598} 3599 3600static int brcmf_sdio_bus_get_memdump(struct device *dev, void *data, 3601 size_t mem_size) 3602{ 3603 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 3604 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 3605 struct brcmf_sdio *bus = sdiodev->bus; 3606 int err; 3607 int address; 3608 int offset; 3609 int len; 3610 3611 brcmf_dbg(INFO, "dump at 0x%08x: size=%zu\n", bus->ci->rambase, 3612 mem_size); 3613 3614 address = bus->ci->rambase; 3615 offset = err = 0; 3616 sdio_claim_host(sdiodev->func1); 3617 while (offset < mem_size) { 3618 len = ((offset + MEMBLOCK) < mem_size) ? MEMBLOCK : 3619 mem_size - offset; 3620 err = brcmf_sdiod_ramrw(sdiodev, false, address, data, len); 3621 if (err) { 3622 brcmf_err("error %d on reading %d membytes at 0x%08x\n", 3623 err, len, address); 3624 goto done; 3625 } 3626 data += len; 3627 offset += len; 3628 address += len; 3629 } 3630 3631done: 3632 sdio_release_host(sdiodev->func1); 3633 return err; 3634} 3635 3636void brcmf_sdio_trigger_dpc(struct brcmf_sdio *bus) 3637{ 3638 if (!bus->dpc_triggered) { 3639 bus->dpc_triggered = true; 3640 queue_work(bus->brcmf_wq, &bus->datawork); 3641 } 3642} 3643 3644void brcmf_sdio_isr(struct brcmf_sdio *bus, bool in_isr) 3645{ 3646 brcmf_dbg(TRACE, "Enter\n"); 3647 3648 if (!bus) { 3649 brcmf_err("bus is null pointer, exiting\n"); 3650 return; 3651 } 3652 3653 /* Count the interrupt call */ 3654 bus->sdcnt.intrcount++; 3655 if (in_isr) 3656 atomic_set(&bus->ipend, 1); 3657 else 3658 if (brcmf_sdio_intr_rstatus(bus)) { 3659 brcmf_err("failed backplane access\n"); 3660 } 3661 3662 /* Disable additional interrupts (is this needed now)? */ 3663 if (!bus->intr) 3664 brcmf_err("isr w/o interrupt configured!\n"); 3665 3666 bus->dpc_triggered = true; 3667 queue_work(bus->brcmf_wq, &bus->datawork); 3668} 3669 3670static void brcmf_sdio_bus_watchdog(struct brcmf_sdio *bus) 3671{ 3672 brcmf_dbg(TIMER, "Enter\n"); 3673 3674 /* Poll period: check device if appropriate. */ 3675 if (!bus->sr_enabled && 3676 bus->poll && (++bus->polltick >= bus->pollrate)) { 3677 u32 intstatus = 0; 3678 3679 /* Reset poll tick */ 3680 bus->polltick = 0; 3681 3682 /* Check device if no interrupts */ 3683 if (!bus->intr || 3684 (bus->sdcnt.intrcount == bus->sdcnt.lastintrs)) { 3685 3686 if (!bus->dpc_triggered) { 3687 u8 devpend; 3688 3689 sdio_claim_host(bus->sdiodev->func1); 3690 devpend = brcmf_sdiod_func0_rb(bus->sdiodev, 3691 SDIO_CCCR_INTx, NULL); 3692 sdio_release_host(bus->sdiodev->func1); 3693 intstatus = devpend & (INTR_STATUS_FUNC1 | 3694 INTR_STATUS_FUNC2); 3695 } 3696 3697 /* If there is something, make like the ISR and 3698 schedule the DPC */ 3699 if (intstatus) { 3700 bus->sdcnt.pollcnt++; 3701 atomic_set(&bus->ipend, 1); 3702 3703 bus->dpc_triggered = true; 3704 queue_work(bus->brcmf_wq, &bus->datawork); 3705 } 3706 } 3707 3708 /* Update interrupt tracking */ 3709 bus->sdcnt.lastintrs = bus->sdcnt.intrcount; 3710 } 3711#ifdef DEBUG 3712 /* Poll for console output periodically */ 3713 if (bus->sdiodev->state == BRCMF_SDIOD_DATA && BRCMF_FWCON_ON() && 3714 bus->console_interval != 0) { 3715 bus->console.count += jiffies_to_msecs(BRCMF_WD_POLL); 3716 if (bus->console.count >= bus->console_interval) { 3717 bus->console.count -= bus->console_interval; 3718 sdio_claim_host(bus->sdiodev->func1); 3719 /* Make sure backplane clock is on */ 3720 brcmf_sdio_bus_sleep(bus, false, false); 3721 if (brcmf_sdio_readconsole(bus) < 0) 3722 /* stop on error */ 3723 bus->console_interval = 0; 3724 sdio_release_host(bus->sdiodev->func1); 3725 } 3726 } 3727#endif /* DEBUG */ 3728 3729 /* On idle timeout clear activity flag and/or turn off clock */ 3730 if (!bus->dpc_triggered) { 3731 rmb(); 3732 if ((!bus->dpc_running) && (bus->idletime > 0) && 3733 (bus->clkstate == CLK_AVAIL)) { 3734 bus->idlecount++; 3735 if (bus->idlecount > bus->idletime) { 3736 brcmf_dbg(SDIO, "idle\n"); 3737 sdio_claim_host(bus->sdiodev->func1); 3738#ifdef DEBUG 3739 if (!BRCMF_FWCON_ON() || 3740 bus->console_interval == 0) 3741#endif 3742 brcmf_sdio_wd_timer(bus, false); 3743 bus->idlecount = 0; 3744 brcmf_sdio_bus_sleep(bus, true, false); 3745 sdio_release_host(bus->sdiodev->func1); 3746 } 3747 } else { 3748 bus->idlecount = 0; 3749 } 3750 } else { 3751 bus->idlecount = 0; 3752 } 3753} 3754 3755static void brcmf_sdio_dataworker(struct work_struct *work) 3756{ 3757 struct brcmf_sdio *bus = container_of(work, struct brcmf_sdio, 3758 datawork); 3759 3760 bus->dpc_running = true; 3761 wmb(); 3762 while (READ_ONCE(bus->dpc_triggered)) { 3763 bus->dpc_triggered = false; 3764 brcmf_sdio_dpc(bus); 3765 bus->idlecount = 0; 3766 } 3767 bus->dpc_running = false; 3768 if (brcmf_sdiod_freezing(bus->sdiodev)) { 3769 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DOWN); 3770 brcmf_sdiod_try_freeze(bus->sdiodev); 3771 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA); 3772 } 3773} 3774 3775static void 3776brcmf_sdio_drivestrengthinit(struct brcmf_sdio_dev *sdiodev, 3777 struct brcmf_chip *ci, u32 drivestrength) 3778{ 3779 const struct sdiod_drive_str *str_tab = NULL; 3780 u32 str_mask; 3781 u32 str_shift; 3782 u32 i; 3783 u32 drivestrength_sel = 0; 3784 u32 cc_data_temp; 3785 u32 addr; 3786 3787 if (!(ci->cc_caps & CC_CAP_PMU)) 3788 return; 3789 3790 switch (SDIOD_DRVSTR_KEY(ci->chip, ci->pmurev)) { 3791 case SDIOD_DRVSTR_KEY(BRCM_CC_4330_CHIP_ID, 12): 3792 str_tab = sdiod_drvstr_tab1_1v8; 3793 str_mask = 0x00003800; 3794 str_shift = 11; 3795 break; 3796 case SDIOD_DRVSTR_KEY(BRCM_CC_4334_CHIP_ID, 17): 3797 str_tab = sdiod_drvstr_tab6_1v8; 3798 str_mask = 0x00001800; 3799 str_shift = 11; 3800 break; 3801 case SDIOD_DRVSTR_KEY(BRCM_CC_43143_CHIP_ID, 17): 3802 /* note: 43143 does not support tristate */ 3803 i = ARRAY_SIZE(sdiod_drvstr_tab2_3v3) - 1; 3804 if (drivestrength >= sdiod_drvstr_tab2_3v3[i].strength) { 3805 str_tab = sdiod_drvstr_tab2_3v3; 3806 str_mask = 0x00000007; 3807 str_shift = 0; 3808 } else 3809 brcmf_err("Invalid SDIO Drive strength for chip %s, strength=%d\n", 3810 ci->name, drivestrength); 3811 break; 3812 case SDIOD_DRVSTR_KEY(BRCM_CC_43362_CHIP_ID, 13): 3813 str_tab = sdiod_drive_strength_tab5_1v8; 3814 str_mask = 0x00003800; 3815 str_shift = 11; 3816 break; 3817 default: 3818 brcmf_dbg(INFO, "No SDIO driver strength init needed for chip %s rev %d pmurev %d\n", 3819 ci->name, ci->chiprev, ci->pmurev); 3820 break; 3821 } 3822 3823 if (str_tab != NULL) { 3824 struct brcmf_core *pmu = brcmf_chip_get_pmu(ci); 3825 3826 for (i = 0; str_tab[i].strength != 0; i++) { 3827 if (drivestrength >= str_tab[i].strength) { 3828 drivestrength_sel = str_tab[i].sel; 3829 break; 3830 } 3831 } 3832 addr = CORE_CC_REG(pmu->base, chipcontrol_addr); 3833 brcmf_sdiod_writel(sdiodev, addr, 1, NULL); 3834 cc_data_temp = brcmf_sdiod_readl(sdiodev, addr, NULL); 3835 cc_data_temp &= ~str_mask; 3836 drivestrength_sel <<= str_shift; 3837 cc_data_temp |= drivestrength_sel; 3838 brcmf_sdiod_writel(sdiodev, addr, cc_data_temp, NULL); 3839 3840 brcmf_dbg(INFO, "SDIO: %d mA (req=%d mA) drive strength selected, set to 0x%08x\n", 3841 str_tab[i].strength, drivestrength, cc_data_temp); 3842 } 3843} 3844 3845static int brcmf_sdio_buscoreprep(void *ctx) 3846{ 3847 struct brcmf_sdio_dev *sdiodev = ctx; 3848 int err = 0; 3849 u8 clkval, clkset; 3850 3851 /* Try forcing SDIO core to do ALPAvail request only */ 3852 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_ALP_AVAIL_REQ; 3853 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); 3854 if (err) { 3855 brcmf_err("error writing for HT off\n"); 3856 return err; 3857 } 3858 3859 /* If register supported, wait for ALPAvail and then force ALP */ 3860 /* This may take up to 15 milliseconds */ 3861 clkval = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, NULL); 3862 3863 if ((clkval & ~SBSDIO_AVBITS) != clkset) { 3864 brcmf_err("ChipClkCSR access: wrote 0x%02x read 0x%02x\n", 3865 clkset, clkval); 3866 return -EACCES; 3867 } 3868 3869 SPINWAIT(((clkval = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 3870 NULL)), 3871 !SBSDIO_ALPAV(clkval)), 3872 PMU_MAX_TRANSITION_DLY); 3873 3874 if (!SBSDIO_ALPAV(clkval)) { 3875 brcmf_err("timeout on ALPAV wait, clkval 0x%02x\n", 3876 clkval); 3877 return -EBUSY; 3878 } 3879 3880 clkset = SBSDIO_FORCE_HW_CLKREQ_OFF | SBSDIO_FORCE_ALP; 3881 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, clkset, &err); 3882 udelay(65); 3883 3884 /* Also, disable the extra SDIO pull-ups */ 3885 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_SDIOPULLUP, 0, NULL); 3886 3887 return 0; 3888} 3889 3890static void brcmf_sdio_buscore_activate(void *ctx, struct brcmf_chip *chip, 3891 u32 rstvec) 3892{ 3893 struct brcmf_sdio_dev *sdiodev = ctx; 3894 struct brcmf_core *core = sdiodev->bus->sdio_core; 3895 u32 reg_addr; 3896 3897 /* clear all interrupts */ 3898 reg_addr = core->base + SD_REG(intstatus); 3899 brcmf_sdiod_writel(sdiodev, reg_addr, 0xFFFFFFFF, NULL); 3900 3901 if (rstvec) 3902 /* Write reset vector to address 0 */ 3903 brcmf_sdiod_ramrw(sdiodev, true, 0, (void *)&rstvec, 3904 sizeof(rstvec)); 3905} 3906 3907static u32 brcmf_sdio_buscore_read32(void *ctx, u32 addr) 3908{ 3909 struct brcmf_sdio_dev *sdiodev = ctx; 3910 u32 val, rev; 3911 3912 val = brcmf_sdiod_readl(sdiodev, addr, NULL); 3913 3914 /* 3915 * this is a bit of special handling if reading the chipcommon chipid 3916 * register. The 4339 is a next-gen of the 4335. It uses the same 3917 * SDIO device id as 4335 and the chipid register returns 4335 as well. 3918 * It can be identified as 4339 by looking at the chip revision. It 3919 * is corrected here so the chip.c module has the right info. 3920 */ 3921 if (addr == CORE_CC_REG(SI_ENUM_BASE_DEFAULT, chipid) && 3922 (sdiodev->func1->device == SDIO_DEVICE_ID_BROADCOM_4339 || 3923 sdiodev->func1->device == SDIO_DEVICE_ID_BROADCOM_4335_4339)) { 3924 rev = (val & CID_REV_MASK) >> CID_REV_SHIFT; 3925 if (rev >= 2) { 3926 val &= ~CID_ID_MASK; 3927 val |= BRCM_CC_4339_CHIP_ID; 3928 } 3929 } 3930 3931 return val; 3932} 3933 3934static void brcmf_sdio_buscore_write32(void *ctx, u32 addr, u32 val) 3935{ 3936 struct brcmf_sdio_dev *sdiodev = ctx; 3937 3938 brcmf_sdiod_writel(sdiodev, addr, val, NULL); 3939} 3940 3941static const struct brcmf_buscore_ops brcmf_sdio_buscore_ops = { 3942 .prepare = brcmf_sdio_buscoreprep, 3943 .activate = brcmf_sdio_buscore_activate, 3944 .read32 = brcmf_sdio_buscore_read32, 3945 .write32 = brcmf_sdio_buscore_write32, 3946}; 3947 3948static int 3949brcmf_sdio_probe_attach(struct brcmf_sdio *bus) 3950{ 3951 struct brcmf_sdio_dev *sdiodev; 3952 u8 clkctl = 0; 3953 int err = 0; 3954 int reg_addr; 3955 u32 reg_val; 3956 u32 drivestrength; 3957 u32 enum_base; 3958 int ret = -EBADE; 3959 3960 sdiodev = bus->sdiodev; 3961 sdio_claim_host(sdiodev->func1); 3962 3963 enum_base = brcmf_chip_enum_base(sdiodev->func1->device); 3964 3965 pr_debug("F1 signature read @0x%08x=0x%4x\n", enum_base, 3966 brcmf_sdiod_readl(sdiodev, enum_base, NULL)); 3967 3968 /* 3969 * Force PLL off until brcmf_chip_attach() 3970 * programs PLL control regs 3971 */ 3972 3973 brcmf_sdiod_writeb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, BRCMF_INIT_CLKCTL1, 3974 &err); 3975 if (!err) 3976 clkctl = brcmf_sdiod_readb(sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 3977 &err); 3978 3979 if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) { 3980 brcmf_err("ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n", 3981 err, BRCMF_INIT_CLKCTL1, clkctl); 3982 goto fail; 3983 } 3984 3985 bus->ci = brcmf_chip_attach(sdiodev, sdiodev->func1->device, 3986 &brcmf_sdio_buscore_ops); 3987 if (IS_ERR(bus->ci)) { 3988 brcmf_err("brcmf_chip_attach failed!\n"); 3989 bus->ci = NULL; 3990 goto fail; 3991 } 3992 3993 /* Pick up the SDIO core info struct from chip.c */ 3994 bus->sdio_core = brcmf_chip_get_core(bus->ci, BCMA_CORE_SDIO_DEV); 3995 if (!bus->sdio_core) 3996 goto fail; 3997 3998 /* Pick up the CHIPCOMMON core info struct, for bulk IO in bcmsdh.c */ 3999 sdiodev->cc_core = brcmf_chip_get_core(bus->ci, BCMA_CORE_CHIPCOMMON); 4000 if (!sdiodev->cc_core) 4001 goto fail; 4002 4003 sdiodev->settings = brcmf_get_module_param(sdiodev->dev, 4004 BRCMF_BUSTYPE_SDIO, 4005 bus->ci->chip, 4006 bus->ci->chiprev); 4007 if (IS_ERR_OR_NULL(sdiodev->settings)) { 4008 brcmf_err("Failed to get device parameters\n"); 4009 ret = PTR_ERR_OR_ZERO(sdiodev->settings); 4010 goto fail; 4011 } 4012 /* platform specific configuration: 4013 * alignments must be at least 4 bytes for ADMA 4014 */ 4015 bus->head_align = ALIGNMENT; 4016 bus->sgentry_align = ALIGNMENT; 4017 if (sdiodev->settings->bus.sdio.sd_head_align > ALIGNMENT) 4018 bus->head_align = sdiodev->settings->bus.sdio.sd_head_align; 4019 if (sdiodev->settings->bus.sdio.sd_sgentry_align > ALIGNMENT) 4020 bus->sgentry_align = 4021 sdiodev->settings->bus.sdio.sd_sgentry_align; 4022 4023 /* allocate scatter-gather table. sg support 4024 * will be disabled upon allocation failure. 4025 */ 4026 brcmf_sdiod_sgtable_alloc(sdiodev); 4027 4028 /* wowl can be supported when KEEP_POWER is true and (WAKE_SDIO_IRQ 4029 * is true or when platform data OOB irq is true). 4030 */ 4031 if (IS_ENABLED(CONFIG_PM_SLEEP) && 4032 (sdio_get_host_pm_caps(sdiodev->func1) & MMC_PM_KEEP_POWER) && 4033 ((sdio_get_host_pm_caps(sdiodev->func1) & MMC_PM_WAKE_SDIO_IRQ) || 4034 (sdiodev->settings->bus.sdio.oob_irq_supported))) 4035 sdiodev->bus_if->wowl_supported = true; 4036 4037 if (brcmf_sdio_kso_init(bus)) { 4038 brcmf_err("error enabling KSO\n"); 4039 goto fail; 4040 } 4041 4042 if (sdiodev->settings->bus.sdio.drive_strength) 4043 drivestrength = sdiodev->settings->bus.sdio.drive_strength; 4044 else 4045 drivestrength = DEFAULT_SDIO_DRIVE_STRENGTH; 4046 brcmf_sdio_drivestrengthinit(sdiodev, bus->ci, drivestrength); 4047 4048 /* Set card control so an SDIO card reset does a WLAN backplane reset */ 4049 reg_val = brcmf_sdiod_func0_rb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, &err); 4050 if (err) 4051 goto fail; 4052 4053 reg_val |= SDIO_CCCR_BRCM_CARDCTRL_WLANRESET; 4054 4055 brcmf_sdiod_func0_wb(sdiodev, SDIO_CCCR_BRCM_CARDCTRL, reg_val, &err); 4056 if (err) 4057 goto fail; 4058 4059 /* set PMUControl so a backplane reset does PMU state reload */ 4060 reg_addr = CORE_CC_REG(brcmf_chip_get_pmu(bus->ci)->base, pmucontrol); 4061 reg_val = brcmf_sdiod_readl(sdiodev, reg_addr, &err); 4062 if (err) 4063 goto fail; 4064 4065 reg_val |= (BCMA_CC_PMU_CTL_RES_RELOAD << BCMA_CC_PMU_CTL_RES_SHIFT); 4066 4067 brcmf_sdiod_writel(sdiodev, reg_addr, reg_val, &err); 4068 if (err) 4069 goto fail; 4070 4071 sdio_release_host(sdiodev->func1); 4072 4073 brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN); 4074 4075 /* allocate header buffer */ 4076 bus->hdrbuf = kzalloc(MAX_HDR_READ + bus->head_align, GFP_KERNEL); 4077 if (!bus->hdrbuf) 4078 return -ENOMEM; 4079 /* Locate an appropriately-aligned portion of hdrbuf */ 4080 bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0], 4081 bus->head_align); 4082 4083 /* Set the poll and/or interrupt flags */ 4084 bus->intr = true; 4085 bus->poll = false; 4086 if (bus->poll) 4087 bus->pollrate = 1; 4088 4089 return 0; 4090 4091fail: 4092 sdio_release_host(sdiodev->func1); 4093 return ret; 4094} 4095 4096static int 4097brcmf_sdio_watchdog_thread(void *data) 4098{ 4099 struct brcmf_sdio *bus = (struct brcmf_sdio *)data; 4100 int wait; 4101 4102 allow_signal(SIGTERM); 4103 /* Run until signal received */ 4104 brcmf_sdiod_freezer_count(bus->sdiodev); 4105 while (1) { 4106 if (kthread_should_stop()) 4107 break; 4108 brcmf_sdiod_freezer_uncount(bus->sdiodev); 4109 wait = wait_for_completion_interruptible(&bus->watchdog_wait); 4110 brcmf_sdiod_freezer_count(bus->sdiodev); 4111 brcmf_sdiod_try_freeze(bus->sdiodev); 4112 if (!wait) { 4113 brcmf_sdio_bus_watchdog(bus); 4114 /* Count the tick for reference */ 4115 bus->sdcnt.tickcnt++; 4116 reinit_completion(&bus->watchdog_wait); 4117 } else 4118 break; 4119 } 4120 return 0; 4121} 4122 4123static void 4124brcmf_sdio_watchdog(struct timer_list *t) 4125{ 4126 struct brcmf_sdio *bus = timer_container_of(bus, t, timer); 4127 4128 if (bus->watchdog_tsk) { 4129 complete(&bus->watchdog_wait); 4130 /* Reschedule the watchdog */ 4131 if (bus->wd_active) 4132 mod_timer(&bus->timer, 4133 jiffies + BRCMF_WD_POLL); 4134 } 4135} 4136 4137static int brcmf_sdio_get_blob(struct device *dev, const struct firmware **fw, 4138 enum brcmf_blob_type type) 4139{ 4140 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 4141 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 4142 4143 switch (type) { 4144 case BRCMF_BLOB_CLM: 4145 *fw = sdiodev->clm_fw; 4146 sdiodev->clm_fw = NULL; 4147 break; 4148 default: 4149 return -ENOENT; 4150 } 4151 4152 if (!*fw) 4153 return -ENOENT; 4154 4155 return 0; 4156} 4157 4158static int brcmf_sdio_bus_reset(struct device *dev) 4159{ 4160 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 4161 struct brcmf_sdio_dev *sdiodev = bus_if->bus_priv.sdio; 4162 4163 brcmf_dbg(SDIO, "Enter\n"); 4164 4165 /* start by unregistering irqs */ 4166 brcmf_sdiod_intr_unregister(sdiodev); 4167 4168 brcmf_sdiod_remove(sdiodev); 4169 4170 /* reset the adapter */ 4171 sdio_claim_host(sdiodev->func1); 4172 mmc_hw_reset(sdiodev->func1->card); 4173 sdio_release_host(sdiodev->func1); 4174 4175 brcmf_bus_change_state(sdiodev->bus_if, BRCMF_BUS_DOWN); 4176 return 0; 4177} 4178 4179static void brcmf_sdio_bus_remove(struct device *dev) 4180{ 4181 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 4182 struct brcmf_sdio_dev *sdiod = bus_if->bus_priv.sdio; 4183 4184 device_release_driver(&sdiod->func2->dev); 4185 device_release_driver(&sdiod->func1->dev); 4186} 4187 4188static const struct brcmf_bus_ops brcmf_sdio_bus_ops = { 4189 .stop = brcmf_sdio_bus_stop, 4190 .preinit = brcmf_sdio_bus_preinit, 4191 .txdata = brcmf_sdio_bus_txdata, 4192 .txctl = brcmf_sdio_bus_txctl, 4193 .rxctl = brcmf_sdio_bus_rxctl, 4194 .gettxq = brcmf_sdio_bus_gettxq, 4195 .wowl_config = brcmf_sdio_wowl_config, 4196 .get_ramsize = brcmf_sdio_bus_get_ramsize, 4197 .get_memdump = brcmf_sdio_bus_get_memdump, 4198 .get_blob = brcmf_sdio_get_blob, 4199 .debugfs_create = brcmf_sdio_debugfs_create, 4200 .reset = brcmf_sdio_bus_reset, 4201 .remove = brcmf_sdio_bus_remove, 4202}; 4203 4204#define BRCMF_SDIO_FW_CODE 0 4205#define BRCMF_SDIO_FW_NVRAM 1 4206#define BRCMF_SDIO_FW_CLM 2 4207 4208static void brcmf_sdio_firmware_callback(struct device *dev, int err, 4209 struct brcmf_fw_request *fwreq) 4210{ 4211 struct brcmf_bus *bus_if = dev_get_drvdata(dev); 4212 struct brcmf_sdio_dev *sdiod = bus_if->bus_priv.sdio; 4213 struct brcmf_sdio *bus = sdiod->bus; 4214 struct brcmf_core *core = bus->sdio_core; 4215 const struct firmware *code; 4216 void *nvram; 4217 u32 nvram_len; 4218 u8 saveclk, bpreq; 4219 u8 devctl; 4220 4221 brcmf_dbg(TRACE, "Enter: dev=%s, err=%d\n", dev_name(dev), err); 4222 4223 if (err) 4224 goto fail; 4225 4226 code = fwreq->items[BRCMF_SDIO_FW_CODE].binary; 4227 nvram = fwreq->items[BRCMF_SDIO_FW_NVRAM].nv_data.data; 4228 nvram_len = fwreq->items[BRCMF_SDIO_FW_NVRAM].nv_data.len; 4229 sdiod->clm_fw = fwreq->items[BRCMF_SDIO_FW_CLM].binary; 4230 kfree(fwreq); 4231 4232 /* try to download image and nvram to the dongle */ 4233 bus->alp_only = true; 4234 err = brcmf_sdio_download_firmware(bus, code, nvram, nvram_len); 4235 if (err) 4236 goto fail; 4237 bus->alp_only = false; 4238 4239 /* Start the watchdog timer */ 4240 bus->sdcnt.tickcnt = 0; 4241 brcmf_sdio_wd_timer(bus, true); 4242 4243 sdio_claim_host(sdiod->func1); 4244 4245 /* Make sure backplane clock is on, needed to generate F2 interrupt */ 4246 brcmf_sdio_clkctl(bus, CLK_AVAIL, false); 4247 if (bus->clkstate != CLK_AVAIL) 4248 goto release; 4249 4250 /* Force clocks on backplane to be sure F2 interrupt propagates */ 4251 saveclk = brcmf_sdiod_readb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR, &err); 4252 if (!err) { 4253 bpreq = saveclk; 4254 bpreq |= brcmf_chip_is_ulp(bus->ci) ? 4255 SBSDIO_HT_AVAIL_REQ : SBSDIO_FORCE_HT; 4256 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR, 4257 bpreq, &err); 4258 } 4259 if (err) { 4260 brcmf_err("Failed to force clock for F2: err %d\n", err); 4261 goto release; 4262 } 4263 4264 /* Enable function 2 (frame transfers) */ 4265 brcmf_sdiod_writel(sdiod, core->base + SD_REG(tosbmailboxdata), 4266 SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT, NULL); 4267 4268 err = sdio_enable_func(sdiod->func2); 4269 4270 brcmf_dbg(INFO, "enable F2: err=%d\n", err); 4271 4272 /* If F2 successfully enabled, set core and enable interrupts */ 4273 if (!err) { 4274 /* Set up the interrupt mask and enable interrupts */ 4275 bus->hostintmask = HOSTINTMASK; 4276 brcmf_sdiod_writel(sdiod, core->base + SD_REG(hostintmask), 4277 bus->hostintmask, NULL); 4278 4279 switch (sdiod->func1->device) { 4280 case SDIO_DEVICE_ID_BROADCOM_43751: 4281 case SDIO_DEVICE_ID_BROADCOM_43752: 4282 case SDIO_DEVICE_ID_BROADCOM_CYPRESS_4373: 4283 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n", 4284 CY_4373_F2_WATERMARK); 4285 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK, 4286 CY_4373_F2_WATERMARK, &err); 4287 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL, 4288 &err); 4289 devctl |= SBSDIO_DEVCTL_F2WM_ENAB; 4290 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl, 4291 &err); 4292 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL, 4293 CY_4373_F1_MESBUSYCTRL, &err); 4294 break; 4295 case SDIO_DEVICE_ID_BROADCOM_CYPRESS_43012: 4296 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n", 4297 CY_43012_F2_WATERMARK); 4298 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK, 4299 CY_43012_F2_WATERMARK, &err); 4300 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL, 4301 &err); 4302 devctl |= SBSDIO_DEVCTL_F2WM_ENAB; 4303 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl, 4304 &err); 4305 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL, 4306 CY_43012_MESBUSYCTRL, &err); 4307 break; 4308 case SDIO_DEVICE_ID_BROADCOM_4329: 4309 case SDIO_DEVICE_ID_BROADCOM_4339: 4310 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n", 4311 CY_4339_F2_WATERMARK); 4312 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK, 4313 CY_4339_F2_WATERMARK, &err); 4314 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL, 4315 &err); 4316 devctl |= SBSDIO_DEVCTL_F2WM_ENAB; 4317 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl, 4318 &err); 4319 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL, 4320 CY_4339_MESBUSYCTRL, &err); 4321 break; 4322 case SDIO_DEVICE_ID_BROADCOM_43455: 4323 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n", 4324 CY_43455_F2_WATERMARK); 4325 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK, 4326 CY_43455_F2_WATERMARK, &err); 4327 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL, 4328 &err); 4329 devctl |= SBSDIO_DEVCTL_F2WM_ENAB; 4330 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl, 4331 &err); 4332 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL, 4333 CY_43455_MESBUSYCTRL, &err); 4334 break; 4335 case SDIO_DEVICE_ID_BROADCOM_4359: 4336 case SDIO_DEVICE_ID_BROADCOM_4354: 4337 case SDIO_DEVICE_ID_BROADCOM_4356: 4338 brcmf_dbg(INFO, "set F2 watermark to 0x%x*4 bytes\n", 4339 CY_435X_F2_WATERMARK); 4340 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK, 4341 CY_435X_F2_WATERMARK, &err); 4342 devctl = brcmf_sdiod_readb(sdiod, SBSDIO_DEVICE_CTL, 4343 &err); 4344 devctl |= SBSDIO_DEVCTL_F2WM_ENAB; 4345 brcmf_sdiod_writeb(sdiod, SBSDIO_DEVICE_CTL, devctl, 4346 &err); 4347 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_MESBUSYCTRL, 4348 CY_435X_F1_MESBUSYCTRL, &err); 4349 break; 4350 default: 4351 brcmf_sdiod_writeb(sdiod, SBSDIO_WATERMARK, 4352 DEFAULT_F2_WATERMARK, &err); 4353 break; 4354 } 4355 } else { 4356 /* Disable F2 again */ 4357 sdio_disable_func(sdiod->func2); 4358 goto checkdied; 4359 } 4360 4361 if (brcmf_chip_sr_capable(bus->ci)) { 4362 brcmf_sdio_sr_init(bus); 4363 } else { 4364 /* Restore previous clock setting */ 4365 brcmf_sdiod_writeb(sdiod, SBSDIO_FUNC1_CHIPCLKCSR, 4366 saveclk, &err); 4367 } 4368 4369 if (err == 0) { 4370 /* Assign bus interface call back */ 4371 sdiod->bus_if->dev = sdiod->dev; 4372 sdiod->bus_if->ops = &brcmf_sdio_bus_ops; 4373 sdiod->bus_if->chip = bus->ci->chip; 4374 sdiod->bus_if->chiprev = bus->ci->chiprev; 4375 4376 /* Allow full data communication using DPC from now on. */ 4377 brcmf_sdiod_change_state(bus->sdiodev, BRCMF_SDIOD_DATA); 4378 4379 err = brcmf_sdiod_intr_register(sdiod); 4380 if (err != 0) 4381 brcmf_err("intr register failed:%d\n", err); 4382 } 4383 4384 /* If we didn't come up, turn off backplane clock */ 4385 if (err != 0) { 4386 brcmf_sdio_clkctl(bus, CLK_NONE, false); 4387 goto checkdied; 4388 } 4389 4390 sdio_release_host(sdiod->func1); 4391 4392 err = brcmf_alloc(sdiod->dev, sdiod->settings); 4393 if (err) { 4394 brcmf_err("brcmf_alloc failed\n"); 4395 goto claim; 4396 } 4397 4398 /* Attach to the common layer, reserve hdr space */ 4399 err = brcmf_attach(sdiod->dev); 4400 if (err != 0) { 4401 brcmf_err("brcmf_attach failed\n"); 4402 goto free; 4403 } 4404 4405 /* ready */ 4406 return; 4407 4408free: 4409 brcmf_free(sdiod->dev); 4410claim: 4411 sdio_claim_host(sdiod->func1); 4412checkdied: 4413 brcmf_sdio_checkdied(bus); 4414release: 4415 sdio_release_host(sdiod->func1); 4416fail: 4417 brcmf_dbg(TRACE, "failed: dev=%s, err=%d\n", dev_name(dev), err); 4418 device_release_driver(&sdiod->func2->dev); 4419 device_release_driver(dev); 4420} 4421 4422static struct brcmf_fw_request * 4423brcmf_sdio_prepare_fw_request(struct brcmf_sdio *bus) 4424{ 4425 struct brcmf_fw_request *fwreq; 4426 struct brcmf_fw_name fwnames[] = { 4427 { ".bin", bus->sdiodev->fw_name }, 4428 { ".txt", bus->sdiodev->nvram_name }, 4429 { ".clm_blob", bus->sdiodev->clm_name }, 4430 }; 4431 4432 fwreq = brcmf_fw_alloc_request(bus->ci->chip, bus->ci->chiprev, 4433 brcmf_sdio_fwnames, 4434 ARRAY_SIZE(brcmf_sdio_fwnames), 4435 fwnames, ARRAY_SIZE(fwnames)); 4436 if (!fwreq) 4437 return NULL; 4438 4439 fwreq->items[BRCMF_SDIO_FW_CODE].type = BRCMF_FW_TYPE_BINARY; 4440 fwreq->items[BRCMF_SDIO_FW_NVRAM].type = BRCMF_FW_TYPE_NVRAM; 4441 fwreq->items[BRCMF_SDIO_FW_CLM].type = BRCMF_FW_TYPE_BINARY; 4442 fwreq->items[BRCMF_SDIO_FW_CLM].flags = BRCMF_FW_REQF_OPTIONAL; 4443 fwreq->board_types[0] = bus->sdiodev->settings->board_type; 4444 4445 return fwreq; 4446} 4447 4448int brcmf_sdio_probe(struct brcmf_sdio_dev *sdiodev) 4449{ 4450 int ret; 4451 struct brcmf_sdio *bus; 4452 struct workqueue_struct *wq; 4453 struct brcmf_fw_request *fwreq; 4454 4455 brcmf_dbg(TRACE, "Enter\n"); 4456 4457 /* Allocate private bus interface state */ 4458 bus = kzalloc(sizeof(*bus), GFP_ATOMIC); 4459 if (!bus) { 4460 ret = -ENOMEM; 4461 goto fail; 4462 } 4463 4464 bus->sdiodev = sdiodev; 4465 sdiodev->bus = bus; 4466 skb_queue_head_init(&bus->glom); 4467 bus->txbound = BRCMF_TXBOUND; 4468 bus->rxbound = BRCMF_RXBOUND; 4469 bus->txminmax = BRCMF_TXMINMAX; 4470 bus->tx_seq = SDPCM_SEQ_WRAP - 1; 4471 4472 /* single-threaded workqueue */ 4473 wq = alloc_ordered_workqueue("brcmf_wq/%s", WQ_MEM_RECLAIM | WQ_HIGHPRI, 4474 dev_name(&sdiodev->func1->dev)); 4475 if (!wq) { 4476 brcmf_err("insufficient memory to create txworkqueue\n"); 4477 ret = -ENOMEM; 4478 goto fail; 4479 } 4480 brcmf_sdiod_freezer_count(sdiodev); 4481 INIT_WORK(&bus->datawork, brcmf_sdio_dataworker); 4482 bus->brcmf_wq = wq; 4483 4484 /* attempt to attach to the dongle */ 4485 ret = brcmf_sdio_probe_attach(bus); 4486 if (ret < 0) { 4487 brcmf_err("brcmf_sdio_probe_attach failed\n"); 4488 goto fail; 4489 } 4490 4491 spin_lock_init(&bus->rxctl_lock); 4492 spin_lock_init(&bus->txq_lock); 4493 init_waitqueue_head(&bus->ctrl_wait); 4494 init_waitqueue_head(&bus->dcmd_resp_wait); 4495 4496 /* Set up the watchdog timer */ 4497 timer_setup(&bus->timer, brcmf_sdio_watchdog, 0); 4498 /* Initialize watchdog thread */ 4499 init_completion(&bus->watchdog_wait); 4500 bus->watchdog_tsk = kthread_run(brcmf_sdio_watchdog_thread, 4501 bus, "brcmf_wdog/%s", 4502 dev_name(&sdiodev->func1->dev)); 4503 if (IS_ERR(bus->watchdog_tsk)) { 4504 pr_warn("brcmf_watchdog thread failed to start\n"); 4505 bus->watchdog_tsk = NULL; 4506 } 4507 /* Initialize DPC thread */ 4508 bus->dpc_triggered = false; 4509 bus->dpc_running = false; 4510 4511 /* default sdio bus header length for tx packet */ 4512 bus->tx_hdrlen = SDPCM_HWHDR_LEN + SDPCM_SWHDR_LEN; 4513 4514 /* Query the F2 block size, set roundup accordingly */ 4515 bus->blocksize = bus->sdiodev->func2->cur_blksize; 4516 bus->roundup = min(max_roundup, bus->blocksize); 4517 4518 sdio_claim_host(bus->sdiodev->func1); 4519 4520 /* Disable F2 to clear any intermediate frame state on the dongle */ 4521 sdio_disable_func(bus->sdiodev->func2); 4522 4523 bus->rxflow = false; 4524 4525 /* Done with backplane-dependent accesses, can drop clock... */ 4526 brcmf_sdiod_writeb(bus->sdiodev, SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL); 4527 4528 sdio_release_host(bus->sdiodev->func1); 4529 4530 /* ...and initialize clock/power states */ 4531 bus->clkstate = CLK_SDONLY; 4532 bus->idletime = BRCMF_IDLE_INTERVAL; 4533 bus->idleclock = BRCMF_IDLE_ACTIVE; 4534 4535 /* SR state */ 4536 bus->sr_enabled = false; 4537 4538 brcmf_dbg(INFO, "completed!!\n"); 4539 4540 fwreq = brcmf_sdio_prepare_fw_request(bus); 4541 if (!fwreq) { 4542 ret = -ENOMEM; 4543 goto fail; 4544 } 4545 4546 ret = brcmf_fw_get_firmwares(sdiodev->dev, fwreq, 4547 brcmf_sdio_firmware_callback); 4548 if (ret != 0) { 4549 brcmf_err("async firmware request failed: %d\n", ret); 4550 kfree(fwreq); 4551 goto fail; 4552 } 4553 4554 return 0; 4555 4556fail: 4557 brcmf_sdio_remove(bus); 4558 sdiodev->bus = NULL; 4559 return ret; 4560} 4561 4562/* Detach and free everything */ 4563void brcmf_sdio_remove(struct brcmf_sdio *bus) 4564{ 4565 brcmf_dbg(TRACE, "Enter\n"); 4566 4567 if (bus) { 4568 /* Stop watchdog task */ 4569 if (bus->watchdog_tsk) { 4570 send_sig(SIGTERM, bus->watchdog_tsk, 1); 4571 kthread_stop(bus->watchdog_tsk); 4572 bus->watchdog_tsk = NULL; 4573 } 4574 4575 /* De-register interrupt handler */ 4576 brcmf_sdiod_intr_unregister(bus->sdiodev); 4577 4578 brcmf_detach(bus->sdiodev->dev); 4579 brcmf_free(bus->sdiodev->dev); 4580 4581 cancel_work_sync(&bus->datawork); 4582 if (bus->brcmf_wq) 4583 destroy_workqueue(bus->brcmf_wq); 4584 4585 if (bus->ci) { 4586 if (bus->sdiodev->state != BRCMF_SDIOD_NOMEDIUM) { 4587 sdio_claim_host(bus->sdiodev->func1); 4588 brcmf_sdio_wd_timer(bus, false); 4589 brcmf_sdio_clkctl(bus, CLK_AVAIL, false); 4590 /* Leave the device in state where it is 4591 * 'passive'. This is done by resetting all 4592 * necessary cores. 4593 */ 4594 msleep(20); 4595 brcmf_chip_set_passive(bus->ci); 4596 brcmf_sdio_clkctl(bus, CLK_NONE, false); 4597 sdio_release_host(bus->sdiodev->func1); 4598 } 4599 brcmf_chip_detach(bus->ci); 4600 } 4601 if (bus->sdiodev->settings) 4602 brcmf_release_module_param(bus->sdiodev->settings); 4603 4604 release_firmware(bus->sdiodev->clm_fw); 4605 bus->sdiodev->clm_fw = NULL; 4606 kfree(bus->rxbuf); 4607 kfree(bus->hdrbuf); 4608 kfree(bus); 4609 } 4610 4611 brcmf_dbg(TRACE, "Disconnected\n"); 4612} 4613 4614void brcmf_sdio_wd_timer(struct brcmf_sdio *bus, bool active) 4615{ 4616 /* Totally stop the timer */ 4617 if (!active && bus->wd_active) { 4618 timer_delete_sync(&bus->timer); 4619 bus->wd_active = false; 4620 return; 4621 } 4622 4623 /* don't start the wd until fw is loaded */ 4624 if (bus->sdiodev->state != BRCMF_SDIOD_DATA) 4625 return; 4626 4627 if (active) { 4628 if (!bus->wd_active) { 4629 /* Create timer again when watchdog period is 4630 dynamically changed or in the first instance 4631 */ 4632 bus->timer.expires = jiffies + BRCMF_WD_POLL; 4633 add_timer(&bus->timer); 4634 bus->wd_active = true; 4635 } else { 4636 /* Re arm the timer, at last watchdog period */ 4637 mod_timer(&bus->timer, jiffies + BRCMF_WD_POLL); 4638 } 4639 } 4640} 4641 4642int brcmf_sdio_sleep(struct brcmf_sdio *bus, bool sleep) 4643{ 4644 int ret; 4645 4646 sdio_claim_host(bus->sdiodev->func1); 4647 ret = brcmf_sdio_bus_sleep(bus, sleep, false); 4648 sdio_release_host(bus->sdiodev->func1); 4649 4650 return ret; 4651}
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