pcie.c

   1// SPDX-License-Identifier: ISC
   2/*
   3 * Copyright (c) 2014 Broadcom Corporation
   4 */
   5
   6#include <linux/kernel.h>
   7#include <linux/module.h>
   8#include <linux/firmware.h>
   9#include <linux/pci.h>
  10#include <linux/vmalloc.h>
  11#include <linux/delay.h>
  12#include <linux/interrupt.h>
  13#include <linux/bcma/bcma.h>
  14#include <linux/sched.h>
  15#include <linux/sched/signal.h>
  16#include <linux/kthread.h>
  17#include <linux/io.h>
  18#include <linux/random.h>
  19#include <linux/unaligned.h>
  20
  21#include <soc.h>
  22#include <chipcommon.h>
  23#include <brcmu_utils.h>
  24#include <brcmu_wifi.h>
  25#include <brcm_hw_ids.h>
  26
  27/* Custom brcmf_err() that takes bus arg and passes it further */
  28#define brcmf_err(bus, fmt, ...)					\
  29	do {								\
  30		if (IS_ENABLED(CONFIG_BRCMDBG) ||			\
  31		    IS_ENABLED(CONFIG_BRCM_TRACING) ||			\
  32		    net_ratelimit())					\
  33			__brcmf_err(bus, __func__, fmt, ##__VA_ARGS__);	\
  34	} while (0)
  35
  36#include "debug.h"
  37#include "bus.h"
  38#include "commonring.h"
  39#include "msgbuf.h"
  40#include "pcie.h"
  41#include "firmware.h"
  42#include "chip.h"
  43#include "core.h"
  44#include "common.h"
  45
  46
  47enum brcmf_pcie_state {
  48	BRCMFMAC_PCIE_STATE_DOWN,
  49	BRCMFMAC_PCIE_STATE_UP
  50};
  51
  52BRCMF_FW_DEF(43602, "brcmfmac43602-pcie");
  53BRCMF_FW_DEF(4350, "brcmfmac4350-pcie");
  54BRCMF_FW_DEF(4350C, "brcmfmac4350c2-pcie");
  55BRCMF_FW_CLM_DEF(4355, "brcmfmac4355-pcie");
  56BRCMF_FW_CLM_DEF(4355C1, "brcmfmac4355c1-pcie");
  57BRCMF_FW_CLM_DEF(4356, "brcmfmac4356-pcie");
  58BRCMF_FW_CLM_DEF(43570, "brcmfmac43570-pcie");
  59BRCMF_FW_DEF(4358, "brcmfmac4358-pcie");
  60BRCMF_FW_DEF(4359, "brcmfmac4359-pcie");
  61BRCMF_FW_DEF(4359C, "brcmfmac4359c-pcie");
  62BRCMF_FW_CLM_DEF(4364B2, "brcmfmac4364b2-pcie");
  63BRCMF_FW_CLM_DEF(4364B3, "brcmfmac4364b3-pcie");
  64BRCMF_FW_DEF(4365B, "brcmfmac4365b-pcie");
  65BRCMF_FW_DEF(4365C, "brcmfmac4365c-pcie");
  66BRCMF_FW_DEF(4366B, "brcmfmac4366b-pcie");
  67BRCMF_FW_DEF(4366C, "brcmfmac4366c-pcie");
  68BRCMF_FW_DEF(4371, "brcmfmac4371-pcie");
  69BRCMF_FW_CLM_DEF(43752, "brcmfmac43752-pcie");
  70BRCMF_FW_CLM_DEF(4377B3, "brcmfmac4377b3-pcie");
  71BRCMF_FW_CLM_DEF(4378B1, "brcmfmac4378b1-pcie");
  72BRCMF_FW_CLM_DEF(4378B3, "brcmfmac4378b3-pcie");
  73BRCMF_FW_CLM_DEF(4387C2, "brcmfmac4387c2-pcie");
  74BRCMF_FW_CLM_DEF(54591, "brcmfmac54591-pcie");
  75
  76/* firmware config files */
  77MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.txt");
  78MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.txt");
  79
  80/* per-board firmware binaries */
  81MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.bin");
  82MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.clm_blob");
  83MODULE_FIRMWARE(BRCMF_FW_DEFAULT_PATH "brcmfmac*-pcie.*.txcap_blob");
  84
  85static const struct brcmf_firmware_mapping brcmf_pcie_fwnames[] = {
  86	BRCMF_FW_ENTRY(BRCM_CC_43602_CHIP_ID, 0xFFFFFFFF, 43602),
  87	BRCMF_FW_ENTRY(BRCM_CC_43465_CHIP_ID, 0xFFFFFFF0, 4366C),
  88	BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0x000000FF, 4350C),
  89	BRCMF_FW_ENTRY(BRCM_CC_4350_CHIP_ID, 0xFFFFFF00, 4350),
  90	BRCMF_FW_ENTRY(BRCM_CC_43525_CHIP_ID, 0xFFFFFFF0, 4365C),
  91	BRCMF_FW_ENTRY(BRCM_CC_4355_CHIP_ID, 0x000007FF, 4355),
  92	BRCMF_FW_ENTRY(BRCM_CC_4355_CHIP_ID, 0x00002000, 54591),
  93	BRCMF_FW_ENTRY(BRCM_CC_4355_CHIP_ID, 0xFFFFF800, 4355C1), /* rev ID 12/C2 seen */
  94	BRCMF_FW_ENTRY(BRCM_CC_4356_CHIP_ID, 0xFFFFFFFF, 4356),
  95	BRCMF_FW_ENTRY(BRCM_CC_43567_CHIP_ID, 0xFFFFFFFF, 43570),
  96	BRCMF_FW_ENTRY(BRCM_CC_43569_CHIP_ID, 0xFFFFFFFF, 43570),
  97	BRCMF_FW_ENTRY(BRCM_CC_43570_CHIP_ID, 0xFFFFFFFF, 43570),
  98	BRCMF_FW_ENTRY(BRCM_CC_4358_CHIP_ID, 0xFFFFFFFF, 4358),
  99	BRCMF_FW_ENTRY(BRCM_CC_4359_CHIP_ID, 0x000001FF, 4359),
 100	BRCMF_FW_ENTRY(BRCM_CC_4359_CHIP_ID, 0xFFFFFE00, 4359C),
 101	BRCMF_FW_ENTRY(BRCM_CC_4364_CHIP_ID, 0x0000000F, 4364B2), /* 3 */
 102	BRCMF_FW_ENTRY(BRCM_CC_4364_CHIP_ID, 0xFFFFFFF0, 4364B3), /* 4 */
 103	BRCMF_FW_ENTRY(BRCM_CC_4365_CHIP_ID, 0x0000000F, 4365B),
 104	BRCMF_FW_ENTRY(BRCM_CC_4365_CHIP_ID, 0xFFFFFFF0, 4365C),
 105	BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0x0000000F, 4366B),
 106	BRCMF_FW_ENTRY(BRCM_CC_4366_CHIP_ID, 0xFFFFFFF0, 4366C),
 107	BRCMF_FW_ENTRY(BRCM_CC_43664_CHIP_ID, 0xFFFFFFF0, 4366C),
 108	BRCMF_FW_ENTRY(BRCM_CC_43666_CHIP_ID, 0xFFFFFFF0, 4366C),
 109	BRCMF_FW_ENTRY(BRCM_CC_4371_CHIP_ID, 0xFFFFFFFF, 4371),
 110	BRCMF_FW_ENTRY(BRCM_CC_43752_CHIP_ID, 0xFFFFFFFF, 43752),
 111	BRCMF_FW_ENTRY(BRCM_CC_4377_CHIP_ID, 0xFFFFFFFF, 4377B3), /* revision ID 4 */
 112	BRCMF_FW_ENTRY(BRCM_CC_4378_CHIP_ID, 0x0000000F, 4378B1), /* revision ID 3 */
 113	BRCMF_FW_ENTRY(BRCM_CC_4378_CHIP_ID, 0xFFFFFFE0, 4378B3), /* revision ID 5 */
 114	BRCMF_FW_ENTRY(BRCM_CC_4387_CHIP_ID, 0xFFFFFFFF, 4387C2), /* revision ID 7 */
 115};
 116
 117#define BRCMF_PCIE_FW_UP_TIMEOUT		5000 /* msec */
 118
 119#define BRCMF_PCIE_REG_MAP_SIZE			(32 * 1024)
 120
 121/* backplane addres space accessed by BAR0 */
 122#define	BRCMF_PCIE_BAR0_WINDOW			0x80
 123#define BRCMF_PCIE_BAR0_REG_SIZE		0x1000
 124#define	BRCMF_PCIE_BAR0_WRAPPERBASE		0x70
 125
 126#define BRCMF_PCIE_BAR0_WRAPBASE_DMP_OFFSET	0x1000
 127#define BRCMF_PCIE_BARO_PCIE_ENUM_OFFSET	0x2000
 128
 129#define BRCMF_PCIE_ARMCR4REG_BANKIDX		0x40
 130#define BRCMF_PCIE_ARMCR4REG_BANKPDA		0x4C
 131
 132#define BRCMF_PCIE_REG_INTSTATUS		0x90
 133#define BRCMF_PCIE_REG_INTMASK			0x94
 134#define BRCMF_PCIE_REG_SBMBX			0x98
 135
 136#define BRCMF_PCIE_REG_LINK_STATUS_CTRL		0xBC
 137
 138#define BRCMF_PCIE_PCIE2REG_INTMASK		0x24
 139#define BRCMF_PCIE_PCIE2REG_MAILBOXINT		0x48
 140#define BRCMF_PCIE_PCIE2REG_MAILBOXMASK		0x4C
 141#define BRCMF_PCIE_PCIE2REG_CONFIGADDR		0x120
 142#define BRCMF_PCIE_PCIE2REG_CONFIGDATA		0x124
 143#define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0	0x140
 144#define BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1	0x144
 145
 146#define BRCMF_PCIE_64_PCIE2REG_INTMASK		0xC14
 147#define BRCMF_PCIE_64_PCIE2REG_MAILBOXINT	0xC30
 148#define BRCMF_PCIE_64_PCIE2REG_MAILBOXMASK	0xC34
 149#define BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_0	0xA20
 150#define BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_1	0xA24
 151
 152#define BRCMF_PCIE2_INTA			0x01
 153#define BRCMF_PCIE2_INTB			0x02
 154
 155#define BRCMF_PCIE_INT_0			0x01
 156#define BRCMF_PCIE_INT_1			0x02
 157#define BRCMF_PCIE_INT_DEF			(BRCMF_PCIE_INT_0 | \
 158						 BRCMF_PCIE_INT_1)
 159
 160#define BRCMF_PCIE_MB_INT_FN0_0			0x0100
 161#define BRCMF_PCIE_MB_INT_FN0_1			0x0200
 162#define	BRCMF_PCIE_MB_INT_D2H0_DB0		0x10000
 163#define	BRCMF_PCIE_MB_INT_D2H0_DB1		0x20000
 164#define	BRCMF_PCIE_MB_INT_D2H1_DB0		0x40000
 165#define	BRCMF_PCIE_MB_INT_D2H1_DB1		0x80000
 166#define	BRCMF_PCIE_MB_INT_D2H2_DB0		0x100000
 167#define	BRCMF_PCIE_MB_INT_D2H2_DB1		0x200000
 168#define	BRCMF_PCIE_MB_INT_D2H3_DB0		0x400000
 169#define	BRCMF_PCIE_MB_INT_D2H3_DB1		0x800000
 170
 171#define BRCMF_PCIE_MB_INT_FN0			(BRCMF_PCIE_MB_INT_FN0_0 | \
 172						 BRCMF_PCIE_MB_INT_FN0_1)
 173#define BRCMF_PCIE_MB_INT_D2H_DB		(BRCMF_PCIE_MB_INT_D2H0_DB0 | \
 174						 BRCMF_PCIE_MB_INT_D2H0_DB1 | \
 175						 BRCMF_PCIE_MB_INT_D2H1_DB0 | \
 176						 BRCMF_PCIE_MB_INT_D2H1_DB1 | \
 177						 BRCMF_PCIE_MB_INT_D2H2_DB0 | \
 178						 BRCMF_PCIE_MB_INT_D2H2_DB1 | \
 179						 BRCMF_PCIE_MB_INT_D2H3_DB0 | \
 180						 BRCMF_PCIE_MB_INT_D2H3_DB1)
 181
 182#define	BRCMF_PCIE_64_MB_INT_D2H0_DB0		0x1
 183#define	BRCMF_PCIE_64_MB_INT_D2H0_DB1		0x2
 184#define	BRCMF_PCIE_64_MB_INT_D2H1_DB0		0x4
 185#define	BRCMF_PCIE_64_MB_INT_D2H1_DB1		0x8
 186#define	BRCMF_PCIE_64_MB_INT_D2H2_DB0		0x10
 187#define	BRCMF_PCIE_64_MB_INT_D2H2_DB1		0x20
 188#define	BRCMF_PCIE_64_MB_INT_D2H3_DB0		0x40
 189#define	BRCMF_PCIE_64_MB_INT_D2H3_DB1		0x80
 190#define	BRCMF_PCIE_64_MB_INT_D2H4_DB0		0x100
 191#define	BRCMF_PCIE_64_MB_INT_D2H4_DB1		0x200
 192#define	BRCMF_PCIE_64_MB_INT_D2H5_DB0		0x400
 193#define	BRCMF_PCIE_64_MB_INT_D2H5_DB1		0x800
 194#define	BRCMF_PCIE_64_MB_INT_D2H6_DB0		0x1000
 195#define	BRCMF_PCIE_64_MB_INT_D2H6_DB1		0x2000
 196#define	BRCMF_PCIE_64_MB_INT_D2H7_DB0		0x4000
 197#define	BRCMF_PCIE_64_MB_INT_D2H7_DB1		0x8000
 198
 199#define BRCMF_PCIE_64_MB_INT_D2H_DB		(BRCMF_PCIE_64_MB_INT_D2H0_DB0 | \
 200						 BRCMF_PCIE_64_MB_INT_D2H0_DB1 | \
 201						 BRCMF_PCIE_64_MB_INT_D2H1_DB0 | \
 202						 BRCMF_PCIE_64_MB_INT_D2H1_DB1 | \
 203						 BRCMF_PCIE_64_MB_INT_D2H2_DB0 | \
 204						 BRCMF_PCIE_64_MB_INT_D2H2_DB1 | \
 205						 BRCMF_PCIE_64_MB_INT_D2H3_DB0 | \
 206						 BRCMF_PCIE_64_MB_INT_D2H3_DB1 | \
 207						 BRCMF_PCIE_64_MB_INT_D2H4_DB0 | \
 208						 BRCMF_PCIE_64_MB_INT_D2H4_DB1 | \
 209						 BRCMF_PCIE_64_MB_INT_D2H5_DB0 | \
 210						 BRCMF_PCIE_64_MB_INT_D2H5_DB1 | \
 211						 BRCMF_PCIE_64_MB_INT_D2H6_DB0 | \
 212						 BRCMF_PCIE_64_MB_INT_D2H6_DB1 | \
 213						 BRCMF_PCIE_64_MB_INT_D2H7_DB0 | \
 214						 BRCMF_PCIE_64_MB_INT_D2H7_DB1)
 215
 216#define BRCMF_PCIE_SHARED_VERSION_7		7
 217#define BRCMF_PCIE_MIN_SHARED_VERSION		5
 218#define BRCMF_PCIE_MAX_SHARED_VERSION		BRCMF_PCIE_SHARED_VERSION_7
 219#define BRCMF_PCIE_SHARED_VERSION_MASK		0x00FF
 220#define BRCMF_PCIE_SHARED_DMA_INDEX		0x10000
 221#define BRCMF_PCIE_SHARED_DMA_2B_IDX		0x100000
 222#define BRCMF_PCIE_SHARED_HOSTRDY_DB1		0x10000000
 223
 224#define BRCMF_PCIE_FLAGS_HTOD_SPLIT		0x4000
 225#define BRCMF_PCIE_FLAGS_DTOH_SPLIT		0x8000
 226
 227#define BRCMF_SHARED_MAX_RXBUFPOST_OFFSET	34
 228#define BRCMF_SHARED_RING_BASE_OFFSET		52
 229#define BRCMF_SHARED_RX_DATAOFFSET_OFFSET	36
 230#define BRCMF_SHARED_CONSOLE_ADDR_OFFSET	20
 231#define BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET	40
 232#define BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET	44
 233#define BRCMF_SHARED_RING_INFO_ADDR_OFFSET	48
 234#define BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET	52
 235#define BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET	56
 236#define BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET	64
 237#define BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET	68
 238
 239#define BRCMF_RING_H2D_RING_COUNT_OFFSET	0
 240#define BRCMF_RING_D2H_RING_COUNT_OFFSET	1
 241#define BRCMF_RING_H2D_RING_MEM_OFFSET		4
 242#define BRCMF_RING_H2D_RING_STATE_OFFSET	8
 243
 244#define BRCMF_RING_MEM_BASE_ADDR_OFFSET		8
 245#define BRCMF_RING_MAX_ITEM_OFFSET		4
 246#define BRCMF_RING_LEN_ITEMS_OFFSET		6
 247#define BRCMF_RING_MEM_SZ			16
 248#define BRCMF_RING_STATE_SZ			8
 249
 250#define BRCMF_DEF_MAX_RXBUFPOST			255
 251
 252#define BRCMF_CONSOLE_BUFADDR_OFFSET		8
 253#define BRCMF_CONSOLE_BUFSIZE_OFFSET		12
 254#define BRCMF_CONSOLE_WRITEIDX_OFFSET		16
 255
 256#define BRCMF_DMA_D2H_SCRATCH_BUF_LEN		8
 257#define BRCMF_DMA_D2H_RINGUPD_BUF_LEN		1024
 258
 259#define BRCMF_D2H_DEV_D3_ACK			0x00000001
 260#define BRCMF_D2H_DEV_DS_ENTER_REQ		0x00000002
 261#define BRCMF_D2H_DEV_DS_EXIT_NOTE		0x00000004
 262#define BRCMF_D2H_DEV_FWHALT			0x10000000
 263
 264#define BRCMF_H2D_HOST_D3_INFORM		0x00000001
 265#define BRCMF_H2D_HOST_DS_ACK			0x00000002
 266#define BRCMF_H2D_HOST_D0_INFORM_IN_USE		0x00000008
 267#define BRCMF_H2D_HOST_D0_INFORM		0x00000010
 268
 269#define BRCMF_PCIE_MBDATA_TIMEOUT		msecs_to_jiffies(2000)
 270
 271#define BRCMF_PCIE_CFGREG_STATUS_CMD		0x4
 272#define BRCMF_PCIE_CFGREG_PM_CSR		0x4C
 273#define BRCMF_PCIE_CFGREG_MSI_CAP		0x58
 274#define BRCMF_PCIE_CFGREG_MSI_ADDR_L		0x5C
 275#define BRCMF_PCIE_CFGREG_MSI_ADDR_H		0x60
 276#define BRCMF_PCIE_CFGREG_MSI_DATA		0x64
 277#define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL	0xBC
 278#define BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2	0xDC
 279#define BRCMF_PCIE_CFGREG_RBAR_CTRL		0x228
 280#define BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1	0x248
 281#define BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG	0x4E0
 282#define BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG	0x4F4
 283#define BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB	3
 284
 285/* Magic number at a magic location to find RAM size */
 286#define BRCMF_RAMSIZE_MAGIC			0x534d4152	/* SMAR */
 287#define BRCMF_RAMSIZE_OFFSET			0x6c
 288
 289
 290struct brcmf_pcie_console {
 291	u32 base_addr;
 292	u32 buf_addr;
 293	u32 bufsize;
 294	u32 read_idx;
 295	u8 log_str[256];
 296	u8 log_idx;
 297};
 298
 299struct brcmf_pcie_shared_info {
 300	u32 tcm_base_address;
 301	u32 flags;
 302	struct brcmf_pcie_ringbuf *commonrings[BRCMF_NROF_COMMON_MSGRINGS];
 303	struct brcmf_pcie_ringbuf *flowrings;
 304	u16 max_rxbufpost;
 305	u16 max_flowrings;
 306	u16 max_submissionrings;
 307	u16 max_completionrings;
 308	u32 rx_dataoffset;
 309	u32 htod_mb_data_addr;
 310	u32 dtoh_mb_data_addr;
 311	u32 ring_info_addr;
 312	struct brcmf_pcie_console console;
 313	void *scratch;
 314	dma_addr_t scratch_dmahandle;
 315	void *ringupd;
 316	dma_addr_t ringupd_dmahandle;
 317	u8 version;
 318};
 319
 320#define BRCMF_OTP_MAX_PARAM_LEN 16
 321
 322struct brcmf_otp_params {
 323	char module[BRCMF_OTP_MAX_PARAM_LEN];
 324	char vendor[BRCMF_OTP_MAX_PARAM_LEN];
 325	char version[BRCMF_OTP_MAX_PARAM_LEN];
 326	bool valid;
 327};
 328
 329struct brcmf_pciedev_info {
 330	enum brcmf_pcie_state state;
 331	bool in_irq;
 332	struct pci_dev *pdev;
 333	char fw_name[BRCMF_FW_NAME_LEN];
 334	char nvram_name[BRCMF_FW_NAME_LEN];
 335	char clm_name[BRCMF_FW_NAME_LEN];
 336	char txcap_name[BRCMF_FW_NAME_LEN];
 337	const struct firmware *clm_fw;
 338	const struct firmware *txcap_fw;
 339	const struct brcmf_pcie_reginfo *reginfo;
 340	void __iomem *regs;
 341	void __iomem *tcm;
 342	u32 ram_base;
 343	u32 ram_size;
 344	struct brcmf_chip *ci;
 345	u32 coreid;
 346	struct brcmf_pcie_shared_info shared;
 347	wait_queue_head_t mbdata_resp_wait;
 348	bool mbdata_completed;
 349	bool irq_allocated;
 350	bool wowl_enabled;
 351	u8 dma_idx_sz;
 352	void *idxbuf;
 353	u32 idxbuf_sz;
 354	dma_addr_t idxbuf_dmahandle;
 355	u16 (*read_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset);
 356	void (*write_ptr)(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 357			  u16 value);
 358	struct brcmf_mp_device *settings;
 359	struct brcmf_otp_params otp;
 360	bool fwseed;
 361#ifdef DEBUG
 362	u32 console_interval;
 363	bool console_active;
 364	struct timer_list timer;
 365#endif
 366};
 367
 368struct brcmf_pcie_ringbuf {
 369	struct brcmf_commonring commonring;
 370	dma_addr_t dma_handle;
 371	u32 w_idx_addr;
 372	u32 r_idx_addr;
 373	struct brcmf_pciedev_info *devinfo;
 374	u8 id;
 375};
 376
 377/**
 378 * struct brcmf_pcie_dhi_ringinfo - dongle/host interface shared ring info
 379 *
 380 * @ringmem: dongle memory pointer to ring memory location
 381 * @h2d_w_idx_ptr: h2d ring write indices dongle memory pointers
 382 * @h2d_r_idx_ptr: h2d ring read indices dongle memory pointers
 383 * @d2h_w_idx_ptr: d2h ring write indices dongle memory pointers
 384 * @d2h_r_idx_ptr: d2h ring read indices dongle memory pointers
 385 * @h2d_w_idx_hostaddr: h2d ring write indices host memory pointers
 386 * @h2d_r_idx_hostaddr: h2d ring read indices host memory pointers
 387 * @d2h_w_idx_hostaddr: d2h ring write indices host memory pointers
 388 * @d2h_r_idx_hostaddr: d2h ring reaD indices host memory pointers
 389 * @max_flowrings: maximum number of tx flow rings supported.
 390 * @max_submissionrings: maximum number of submission rings(h2d) supported.
 391 * @max_completionrings: maximum number of completion rings(d2h) supported.
 392 */
 393struct brcmf_pcie_dhi_ringinfo {
 394	__le32			ringmem;
 395	__le32			h2d_w_idx_ptr;
 396	__le32			h2d_r_idx_ptr;
 397	__le32			d2h_w_idx_ptr;
 398	__le32			d2h_r_idx_ptr;
 399	struct msgbuf_buf_addr	h2d_w_idx_hostaddr;
 400	struct msgbuf_buf_addr	h2d_r_idx_hostaddr;
 401	struct msgbuf_buf_addr	d2h_w_idx_hostaddr;
 402	struct msgbuf_buf_addr	d2h_r_idx_hostaddr;
 403	__le16			max_flowrings;
 404	__le16			max_submissionrings;
 405	__le16			max_completionrings;
 406};
 407
 408static const u32 brcmf_ring_max_item[BRCMF_NROF_COMMON_MSGRINGS] = {
 409	BRCMF_H2D_MSGRING_CONTROL_SUBMIT_MAX_ITEM,
 410	BRCMF_H2D_MSGRING_RXPOST_SUBMIT_MAX_ITEM,
 411	BRCMF_D2H_MSGRING_CONTROL_COMPLETE_MAX_ITEM,
 412	BRCMF_D2H_MSGRING_TX_COMPLETE_MAX_ITEM,
 413	BRCMF_D2H_MSGRING_RX_COMPLETE_MAX_ITEM
 414};
 415
 416static const u32 brcmf_ring_itemsize_pre_v7[BRCMF_NROF_COMMON_MSGRINGS] = {
 417	BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
 418	BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
 419	BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
 420	BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE_PRE_V7,
 421	BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE_PRE_V7
 422};
 423
 424static const u32 brcmf_ring_itemsize[BRCMF_NROF_COMMON_MSGRINGS] = {
 425	BRCMF_H2D_MSGRING_CONTROL_SUBMIT_ITEMSIZE,
 426	BRCMF_H2D_MSGRING_RXPOST_SUBMIT_ITEMSIZE,
 427	BRCMF_D2H_MSGRING_CONTROL_COMPLETE_ITEMSIZE,
 428	BRCMF_D2H_MSGRING_TX_COMPLETE_ITEMSIZE,
 429	BRCMF_D2H_MSGRING_RX_COMPLETE_ITEMSIZE
 430};
 431
 432struct brcmf_pcie_reginfo {
 433	u32 intmask;
 434	u32 mailboxint;
 435	u32 mailboxmask;
 436	u32 h2d_mailbox_0;
 437	u32 h2d_mailbox_1;
 438	u32 int_d2h_db;
 439	u32 int_fn0;
 440};
 441
 442static const struct brcmf_pcie_reginfo brcmf_reginfo_default = {
 443	.intmask = BRCMF_PCIE_PCIE2REG_INTMASK,
 444	.mailboxint = BRCMF_PCIE_PCIE2REG_MAILBOXINT,
 445	.mailboxmask = BRCMF_PCIE_PCIE2REG_MAILBOXMASK,
 446	.h2d_mailbox_0 = BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_0,
 447	.h2d_mailbox_1 = BRCMF_PCIE_PCIE2REG_H2D_MAILBOX_1,
 448	.int_d2h_db = BRCMF_PCIE_MB_INT_D2H_DB,
 449	.int_fn0 = BRCMF_PCIE_MB_INT_FN0,
 450};
 451
 452static const struct brcmf_pcie_reginfo brcmf_reginfo_64 = {
 453	.intmask = BRCMF_PCIE_64_PCIE2REG_INTMASK,
 454	.mailboxint = BRCMF_PCIE_64_PCIE2REG_MAILBOXINT,
 455	.mailboxmask = BRCMF_PCIE_64_PCIE2REG_MAILBOXMASK,
 456	.h2d_mailbox_0 = BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_0,
 457	.h2d_mailbox_1 = BRCMF_PCIE_64_PCIE2REG_H2D_MAILBOX_1,
 458	.int_d2h_db = BRCMF_PCIE_64_MB_INT_D2H_DB,
 459	.int_fn0 = 0,
 460};
 461
 462static void brcmf_pcie_setup(struct device *dev, int ret,
 463			     struct brcmf_fw_request *fwreq);
 464static struct brcmf_fw_request *
 465brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo);
 466static void
 467brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info *devinfo, bool active);
 468static void brcmf_pcie_debugfs_create(struct device *dev);
 469
 470static u16
 471brcmf_pcie_read_reg16(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
 472{
 473	void __iomem *address = devinfo->regs + reg_offset;
 474
 475	return ioread16(address);
 476}
 477
 478static u32
 479brcmf_pcie_read_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset)
 480{
 481	void __iomem *address = devinfo->regs + reg_offset;
 482
 483	return (ioread32(address));
 484}
 485
 486
 487static void
 488brcmf_pcie_write_reg32(struct brcmf_pciedev_info *devinfo, u32 reg_offset,
 489		       u32 value)
 490{
 491	void __iomem *address = devinfo->regs + reg_offset;
 492
 493	iowrite32(value, address);
 494}
 495
 496
 497static u8
 498brcmf_pcie_read_tcm8(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 499{
 500	void __iomem *address = devinfo->tcm + mem_offset;
 501
 502	return (ioread8(address));
 503}
 504
 505
 506static u16
 507brcmf_pcie_read_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 508{
 509	void __iomem *address = devinfo->tcm + mem_offset;
 510
 511	return (ioread16(address));
 512}
 513
 514
 515static void
 516brcmf_pcie_write_tcm16(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 517		       u16 value)
 518{
 519	void __iomem *address = devinfo->tcm + mem_offset;
 520
 521	iowrite16(value, address);
 522}
 523
 524
 525static u16
 526brcmf_pcie_read_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 527{
 528	u16 *address = devinfo->idxbuf + mem_offset;
 529
 530	return (*(address));
 531}
 532
 533
 534static void
 535brcmf_pcie_write_idx(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 536		     u16 value)
 537{
 538	u16 *address = devinfo->idxbuf + mem_offset;
 539
 540	*(address) = value;
 541}
 542
 543
 544static u32
 545brcmf_pcie_read_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 546{
 547	void __iomem *address = devinfo->tcm + mem_offset;
 548
 549	return (ioread32(address));
 550}
 551
 552
 553static void
 554brcmf_pcie_write_tcm32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 555		       u32 value)
 556{
 557	void __iomem *address = devinfo->tcm + mem_offset;
 558
 559	iowrite32(value, address);
 560}
 561
 562
 563static u32
 564brcmf_pcie_read_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset)
 565{
 566	void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
 567
 568	return (ioread32(addr));
 569}
 570
 571
 572static void
 573brcmf_pcie_write_ram32(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 574		       u32 value)
 575{
 576	void __iomem *addr = devinfo->tcm + devinfo->ci->rambase + mem_offset;
 577
 578	iowrite32(value, addr);
 579}
 580
 581
 582static void
 583brcmf_pcie_copy_dev_tomem(struct brcmf_pciedev_info *devinfo, u32 mem_offset,
 584			  void *dstaddr, u32 len)
 585{
 586	void __iomem *address = devinfo->tcm + mem_offset;
 587	__le32 *dst32;
 588	__le16 *dst16;
 589	u8 *dst8;
 590
 591	if (((ulong)address & 4) || ((ulong)dstaddr & 4) || (len & 4)) {
 592		if (((ulong)address & 2) || ((ulong)dstaddr & 2) || (len & 2)) {
 593			dst8 = (u8 *)dstaddr;
 594			while (len) {
 595				*dst8 = ioread8(address);
 596				address++;
 597				dst8++;
 598				len--;
 599			}
 600		} else {
 601			len = len / 2;
 602			dst16 = (__le16 *)dstaddr;
 603			while (len) {
 604				*dst16 = cpu_to_le16(ioread16(address));
 605				address += 2;
 606				dst16++;
 607				len--;
 608			}
 609		}
 610	} else {
 611		len = len / 4;
 612		dst32 = (__le32 *)dstaddr;
 613		while (len) {
 614			*dst32 = cpu_to_le32(ioread32(address));
 615			address += 4;
 616			dst32++;
 617			len--;
 618		}
 619	}
 620}
 621
 622
 623#define READCC32(devinfo, reg) brcmf_pcie_read_reg32(devinfo, \
 624		CHIPCREGOFFS(reg))
 625#define WRITECC32(devinfo, reg, value) brcmf_pcie_write_reg32(devinfo, \
 626		CHIPCREGOFFS(reg), value)
 627
 628
 629static void
 630brcmf_pcie_select_core(struct brcmf_pciedev_info *devinfo, u16 coreid)
 631{
 632	const struct pci_dev *pdev = devinfo->pdev;
 633	struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
 634	struct brcmf_core *core;
 635	u32 bar0_win;
 636
 637	core = brcmf_chip_get_core(devinfo->ci, coreid);
 638	if (core) {
 639		bar0_win = core->base;
 640		pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, bar0_win);
 641		if (pci_read_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW,
 642					  &bar0_win) == 0) {
 643			if (bar0_win != core->base) {
 644				bar0_win = core->base;
 645				pci_write_config_dword(pdev,
 646						       BRCMF_PCIE_BAR0_WINDOW,
 647						       bar0_win);
 648			}
 649		}
 650	} else {
 651		brcmf_err(bus, "Unsupported core selected %x\n", coreid);
 652	}
 653}
 654
 655
 656static void brcmf_pcie_reset_device(struct brcmf_pciedev_info *devinfo)
 657{
 658	struct brcmf_core *core;
 659	static const u16 cfg_offset[] = {
 660		BRCMF_PCIE_CFGREG_STATUS_CMD,
 661		BRCMF_PCIE_CFGREG_PM_CSR,
 662		BRCMF_PCIE_CFGREG_MSI_CAP,
 663		BRCMF_PCIE_CFGREG_MSI_ADDR_L,
 664		BRCMF_PCIE_CFGREG_MSI_ADDR_H,
 665		BRCMF_PCIE_CFGREG_MSI_DATA,
 666		BRCMF_PCIE_CFGREG_LINK_STATUS_CTRL2,
 667		BRCMF_PCIE_CFGREG_RBAR_CTRL,
 668		BRCMF_PCIE_CFGREG_PML1_SUB_CTRL1,
 669		BRCMF_PCIE_CFGREG_REG_BAR2_CONFIG,
 670		BRCMF_PCIE_CFGREG_REG_BAR3_CONFIG
 671	};
 672	u32 i;
 673	u32 val;
 674	u32 lsc;
 675
 676	if (!devinfo->ci)
 677		return;
 678
 679	/* Disable ASPM */
 680	brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 681	pci_read_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 682			      &lsc);
 683	val = lsc & (~BRCMF_PCIE_LINK_STATUS_CTRL_ASPM_ENAB);
 684	pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 685			       val);
 686
 687	/* Watchdog reset */
 688	brcmf_pcie_select_core(devinfo, BCMA_CORE_CHIPCOMMON);
 689	WRITECC32(devinfo, watchdog, 4);
 690	msleep(100);
 691
 692	/* Restore ASPM */
 693	brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 694	pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_LINK_STATUS_CTRL,
 695			       lsc);
 696
 697	core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
 698	if (core->rev <= 13) {
 699		for (i = 0; i < ARRAY_SIZE(cfg_offset); i++) {
 700			brcmf_pcie_write_reg32(devinfo,
 701					       BRCMF_PCIE_PCIE2REG_CONFIGADDR,
 702					       cfg_offset[i]);
 703			val = brcmf_pcie_read_reg32(devinfo,
 704				BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 705			brcmf_dbg(PCIE, "config offset 0x%04x, value 0x%04x\n",
 706				  cfg_offset[i], val);
 707			brcmf_pcie_write_reg32(devinfo,
 708					       BRCMF_PCIE_PCIE2REG_CONFIGDATA,
 709					       val);
 710		}
 711	}
 712}
 713
 714
 715static void brcmf_pcie_attach(struct brcmf_pciedev_info *devinfo)
 716{
 717	u32 config;
 718
 719	/* BAR1 window may not be sized properly */
 720	brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
 721	brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGADDR, 0x4e0);
 722	config = brcmf_pcie_read_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA);
 723	brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_PCIE2REG_CONFIGDATA, config);
 724
 725	device_wakeup_enable(&devinfo->pdev->dev);
 726}
 727
 728
 729static int brcmf_pcie_enter_download_state(struct brcmf_pciedev_info *devinfo)
 730{
 731	if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
 732		brcmf_pcie_select_core(devinfo, BCMA_CORE_ARM_CR4);
 733		brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
 734				       5);
 735		brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
 736				       0);
 737		brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKIDX,
 738				       7);
 739		brcmf_pcie_write_reg32(devinfo, BRCMF_PCIE_ARMCR4REG_BANKPDA,
 740				       0);
 741	}
 742	return 0;
 743}
 744
 745
 746static int brcmf_pcie_exit_download_state(struct brcmf_pciedev_info *devinfo,
 747					  u32 resetintr)
 748{
 749	struct brcmf_core *core;
 750
 751	if (devinfo->ci->chip == BRCM_CC_43602_CHIP_ID) {
 752		core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_INTERNAL_MEM);
 753		brcmf_chip_resetcore(core, 0, 0, 0);
 754	}
 755
 756	if (!brcmf_chip_set_active(devinfo->ci, resetintr))
 757		return -EIO;
 758	return 0;
 759}
 760
 761
 762static int
 763brcmf_pcie_send_mb_data(struct brcmf_pciedev_info *devinfo, u32 htod_mb_data)
 764{
 765	struct brcmf_pcie_shared_info *shared;
 766	struct brcmf_core *core;
 767	u32 addr;
 768	u32 cur_htod_mb_data;
 769	u32 i;
 770
 771	shared = &devinfo->shared;
 772	addr = shared->htod_mb_data_addr;
 773	cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 774
 775	if (cur_htod_mb_data != 0)
 776		brcmf_dbg(PCIE, "MB transaction is already pending 0x%04x\n",
 777			  cur_htod_mb_data);
 778
 779	i = 0;
 780	while (cur_htod_mb_data != 0) {
 781		msleep(10);
 782		i++;
 783		if (i > 100)
 784			return -EIO;
 785		cur_htod_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 786	}
 787
 788	brcmf_pcie_write_tcm32(devinfo, addr, htod_mb_data);
 789	pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
 790
 791	/* Send mailbox interrupt twice as a hardware workaround */
 792	core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
 793	if (core->rev <= 13)
 794		pci_write_config_dword(devinfo->pdev, BRCMF_PCIE_REG_SBMBX, 1);
 795
 796	return 0;
 797}
 798
 799
 800static void brcmf_pcie_handle_mb_data(struct brcmf_pciedev_info *devinfo)
 801{
 802	struct brcmf_pcie_shared_info *shared;
 803	u32 addr;
 804	u32 dtoh_mb_data;
 805
 806	shared = &devinfo->shared;
 807	addr = shared->dtoh_mb_data_addr;
 808	dtoh_mb_data = brcmf_pcie_read_tcm32(devinfo, addr);
 809
 810	if (!dtoh_mb_data)
 811		return;
 812
 813	brcmf_pcie_write_tcm32(devinfo, addr, 0);
 814
 815	brcmf_dbg(PCIE, "D2H_MB_DATA: 0x%04x\n", dtoh_mb_data);
 816	if (dtoh_mb_data & BRCMF_D2H_DEV_DS_ENTER_REQ)  {
 817		brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP REQ\n");
 818		brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_DS_ACK);
 819		brcmf_dbg(PCIE, "D2H_MB_DATA: sent DEEP SLEEP ACK\n");
 820	}
 821	if (dtoh_mb_data & BRCMF_D2H_DEV_DS_EXIT_NOTE)
 822		brcmf_dbg(PCIE, "D2H_MB_DATA: DEEP SLEEP EXIT\n");
 823	if (dtoh_mb_data & BRCMF_D2H_DEV_D3_ACK) {
 824		brcmf_dbg(PCIE, "D2H_MB_DATA: D3 ACK\n");
 825		devinfo->mbdata_completed = true;
 826		wake_up(&devinfo->mbdata_resp_wait);
 827	}
 828	if (dtoh_mb_data & BRCMF_D2H_DEV_FWHALT) {
 829		brcmf_dbg(PCIE, "D2H_MB_DATA: FW HALT\n");
 830		brcmf_fw_crashed(&devinfo->pdev->dev);
 831	}
 832}
 833
 834
 835static void brcmf_pcie_bus_console_init(struct brcmf_pciedev_info *devinfo)
 836{
 837	struct brcmf_pcie_shared_info *shared;
 838	struct brcmf_pcie_console *console;
 839	u32 addr;
 840
 841	shared = &devinfo->shared;
 842	console = &shared->console;
 843	addr = shared->tcm_base_address + BRCMF_SHARED_CONSOLE_ADDR_OFFSET;
 844	console->base_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 845
 846	addr = console->base_addr + BRCMF_CONSOLE_BUFADDR_OFFSET;
 847	console->buf_addr = brcmf_pcie_read_tcm32(devinfo, addr);
 848	addr = console->base_addr + BRCMF_CONSOLE_BUFSIZE_OFFSET;
 849	console->bufsize = brcmf_pcie_read_tcm32(devinfo, addr);
 850
 851	brcmf_dbg(FWCON, "Console: base %x, buf %x, size %d\n",
 852		  console->base_addr, console->buf_addr, console->bufsize);
 853}
 854
 855/**
 856 * brcmf_pcie_bus_console_read - reads firmware messages
 857 *
 858 * @devinfo: pointer to the device data structure
 859 * @error: specifies if error has occurred (prints messages unconditionally)
 860 */
 861static void brcmf_pcie_bus_console_read(struct brcmf_pciedev_info *devinfo,
 862					bool error)
 863{
 864	struct pci_dev *pdev = devinfo->pdev;
 865	struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
 866	struct brcmf_pcie_console *console;
 867	u32 addr;
 868	u8 ch;
 869	u32 newidx;
 870
 871	if (!error && !BRCMF_FWCON_ON())
 872		return;
 873
 874	console = &devinfo->shared.console;
 875	if (!console->base_addr)
 876		return;
 877	addr = console->base_addr + BRCMF_CONSOLE_WRITEIDX_OFFSET;
 878	newidx = brcmf_pcie_read_tcm32(devinfo, addr);
 879	while (newidx != console->read_idx) {
 880		addr = console->buf_addr + console->read_idx;
 881		ch = brcmf_pcie_read_tcm8(devinfo, addr);
 882		console->read_idx++;
 883		if (console->read_idx == console->bufsize)
 884			console->read_idx = 0;
 885		if (ch == '\r')
 886			continue;
 887		console->log_str[console->log_idx] = ch;
 888		console->log_idx++;
 889		if ((ch != '\n') &&
 890		    (console->log_idx == (sizeof(console->log_str) - 2))) {
 891			ch = '\n';
 892			console->log_str[console->log_idx] = ch;
 893			console->log_idx++;
 894		}
 895		if (ch == '\n') {
 896			console->log_str[console->log_idx] = 0;
 897			if (error)
 898				__brcmf_err(bus, __func__, "CONSOLE: %s",
 899					    console->log_str);
 900			else
 901				pr_debug("CONSOLE: %s", console->log_str);
 902			console->log_idx = 0;
 903		}
 904	}
 905}
 906
 907
 908static void brcmf_pcie_intr_disable(struct brcmf_pciedev_info *devinfo)
 909{
 910	brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxmask, 0);
 911}
 912
 913
 914static void brcmf_pcie_intr_enable(struct brcmf_pciedev_info *devinfo)
 915{
 916	brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxmask,
 917			       devinfo->reginfo->int_d2h_db |
 918			       devinfo->reginfo->int_fn0);
 919}
 920
 921static void brcmf_pcie_hostready(struct brcmf_pciedev_info *devinfo)
 922{
 923	if (devinfo->shared.flags & BRCMF_PCIE_SHARED_HOSTRDY_DB1)
 924		brcmf_pcie_write_reg32(devinfo,
 925				       devinfo->reginfo->h2d_mailbox_1, 1);
 926}
 927
 928static irqreturn_t brcmf_pcie_quick_check_isr(int irq, void *arg)
 929{
 930	struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 931
 932	if (brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint)) {
 933		brcmf_pcie_intr_disable(devinfo);
 934		brcmf_dbg(PCIE, "Enter\n");
 935		return IRQ_WAKE_THREAD;
 936	}
 937	return IRQ_NONE;
 938}
 939
 940
 941static irqreturn_t brcmf_pcie_isr_thread(int irq, void *arg)
 942{
 943	struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)arg;
 944	u32 status;
 945
 946	devinfo->in_irq = true;
 947	status = brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint);
 948	brcmf_dbg(PCIE, "Enter %x\n", status);
 949	if (status) {
 950		brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxint,
 951				       status);
 952		if (status & devinfo->reginfo->int_fn0)
 953			brcmf_pcie_handle_mb_data(devinfo);
 954		if (status & devinfo->reginfo->int_d2h_db) {
 955			if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 956				brcmf_proto_msgbuf_rx_trigger(
 957							&devinfo->pdev->dev);
 958		}
 959	}
 960	brcmf_pcie_bus_console_read(devinfo, false);
 961	if (devinfo->state == BRCMFMAC_PCIE_STATE_UP)
 962		brcmf_pcie_intr_enable(devinfo);
 963	devinfo->in_irq = false;
 964	return IRQ_HANDLED;
 965}
 966
 967
 968static int brcmf_pcie_request_irq(struct brcmf_pciedev_info *devinfo)
 969{
 970	struct pci_dev *pdev = devinfo->pdev;
 971	struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
 972
 973	brcmf_pcie_intr_disable(devinfo);
 974
 975	brcmf_dbg(PCIE, "Enter\n");
 976
 977	pci_enable_msi(pdev);
 978	if (request_threaded_irq(pdev->irq, brcmf_pcie_quick_check_isr,
 979				 brcmf_pcie_isr_thread, IRQF_SHARED,
 980				 "brcmf_pcie_intr", devinfo)) {
 981		pci_disable_msi(pdev);
 982		brcmf_err(bus, "Failed to request IRQ %d\n", pdev->irq);
 983		return -EIO;
 984	}
 985	devinfo->irq_allocated = true;
 986	return 0;
 987}
 988
 989
 990static void brcmf_pcie_release_irq(struct brcmf_pciedev_info *devinfo)
 991{
 992	struct pci_dev *pdev = devinfo->pdev;
 993	struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
 994	u32 status;
 995	u32 count;
 996
 997	if (!devinfo->irq_allocated)
 998		return;
 999
1000	brcmf_pcie_intr_disable(devinfo);
1001	free_irq(pdev->irq, devinfo);
1002	pci_disable_msi(pdev);
1003
1004	msleep(50);
1005	count = 0;
1006	while ((devinfo->in_irq) && (count < 20)) {
1007		msleep(50);
1008		count++;
1009	}
1010	if (devinfo->in_irq)
1011		brcmf_err(bus, "Still in IRQ (processing) !!!\n");
1012
1013	status = brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->mailboxint);
1014	brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->mailboxint, status);
1015
1016	devinfo->irq_allocated = false;
1017}
1018
1019
1020static int brcmf_pcie_ring_mb_write_rptr(void *ctx)
1021{
1022	struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1023	struct brcmf_pciedev_info *devinfo = ring->devinfo;
1024	struct brcmf_commonring *commonring = &ring->commonring;
1025
1026	if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1027		return -EIO;
1028
1029	brcmf_dbg(PCIE, "W r_ptr %d (%d), ring %d\n", commonring->r_ptr,
1030		  commonring->w_ptr, ring->id);
1031
1032	devinfo->write_ptr(devinfo, ring->r_idx_addr, commonring->r_ptr);
1033
1034	return 0;
1035}
1036
1037
1038static int brcmf_pcie_ring_mb_write_wptr(void *ctx)
1039{
1040	struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1041	struct brcmf_pciedev_info *devinfo = ring->devinfo;
1042	struct brcmf_commonring *commonring = &ring->commonring;
1043
1044	if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1045		return -EIO;
1046
1047	brcmf_dbg(PCIE, "W w_ptr %d (%d), ring %d\n", commonring->w_ptr,
1048		  commonring->r_ptr, ring->id);
1049
1050	devinfo->write_ptr(devinfo, ring->w_idx_addr, commonring->w_ptr);
1051
1052	return 0;
1053}
1054
1055
1056static int brcmf_pcie_ring_mb_ring_bell(void *ctx)
1057{
1058	struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1059	struct brcmf_pciedev_info *devinfo = ring->devinfo;
1060
1061	if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1062		return -EIO;
1063
1064	brcmf_dbg(PCIE, "RING !\n");
1065	/* Any arbitrary value will do, lets use 1 */
1066	brcmf_pcie_write_reg32(devinfo, devinfo->reginfo->h2d_mailbox_0, 1);
1067
1068	return 0;
1069}
1070
1071
1072static int brcmf_pcie_ring_mb_update_rptr(void *ctx)
1073{
1074	struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1075	struct brcmf_pciedev_info *devinfo = ring->devinfo;
1076	struct brcmf_commonring *commonring = &ring->commonring;
1077
1078	if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1079		return -EIO;
1080
1081	commonring->r_ptr = devinfo->read_ptr(devinfo, ring->r_idx_addr);
1082
1083	brcmf_dbg(PCIE, "R r_ptr %d (%d), ring %d\n", commonring->r_ptr,
1084		  commonring->w_ptr, ring->id);
1085
1086	return 0;
1087}
1088
1089
1090static int brcmf_pcie_ring_mb_update_wptr(void *ctx)
1091{
1092	struct brcmf_pcie_ringbuf *ring = (struct brcmf_pcie_ringbuf *)ctx;
1093	struct brcmf_pciedev_info *devinfo = ring->devinfo;
1094	struct brcmf_commonring *commonring = &ring->commonring;
1095
1096	if (devinfo->state != BRCMFMAC_PCIE_STATE_UP)
1097		return -EIO;
1098
1099	commonring->w_ptr = devinfo->read_ptr(devinfo, ring->w_idx_addr);
1100
1101	brcmf_dbg(PCIE, "R w_ptr %d (%d), ring %d\n", commonring->w_ptr,
1102		  commonring->r_ptr, ring->id);
1103
1104	return 0;
1105}
1106
1107
1108static void *
1109brcmf_pcie_init_dmabuffer_for_device(struct brcmf_pciedev_info *devinfo,
1110				     u32 size, u32 tcm_dma_phys_addr,
1111				     dma_addr_t *dma_handle)
1112{
1113	void *ring;
1114	u64 address;
1115
1116	ring = dma_alloc_coherent(&devinfo->pdev->dev, size, dma_handle,
1117				  GFP_KERNEL);
1118	if (!ring)
1119		return NULL;
1120
1121	address = (u64)*dma_handle;
1122	brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr,
1123			       address & 0xffffffff);
1124	brcmf_pcie_write_tcm32(devinfo, tcm_dma_phys_addr + 4, address >> 32);
1125
1126	return (ring);
1127}
1128
1129
1130static struct brcmf_pcie_ringbuf *
1131brcmf_pcie_alloc_dma_and_ring(struct brcmf_pciedev_info *devinfo, u32 ring_id,
1132			      u32 tcm_ring_phys_addr)
1133{
1134	void *dma_buf;
1135	dma_addr_t dma_handle;
1136	struct brcmf_pcie_ringbuf *ring;
1137	u32 size;
1138	u32 addr;
1139	const u32 *ring_itemsize_array;
1140
1141	if (devinfo->shared.version < BRCMF_PCIE_SHARED_VERSION_7)
1142		ring_itemsize_array = brcmf_ring_itemsize_pre_v7;
1143	else
1144		ring_itemsize_array = brcmf_ring_itemsize;
1145
1146	size = brcmf_ring_max_item[ring_id] * ring_itemsize_array[ring_id];
1147	dma_buf = brcmf_pcie_init_dmabuffer_for_device(devinfo, size,
1148			tcm_ring_phys_addr + BRCMF_RING_MEM_BASE_ADDR_OFFSET,
1149			&dma_handle);
1150	if (!dma_buf)
1151		return NULL;
1152
1153	addr = tcm_ring_phys_addr + BRCMF_RING_MAX_ITEM_OFFSET;
1154	brcmf_pcie_write_tcm16(devinfo, addr, brcmf_ring_max_item[ring_id]);
1155	addr = tcm_ring_phys_addr + BRCMF_RING_LEN_ITEMS_OFFSET;
1156	brcmf_pcie_write_tcm16(devinfo, addr, ring_itemsize_array[ring_id]);
1157
1158	ring = kzalloc(sizeof(*ring), GFP_KERNEL);
1159	if (!ring) {
1160		dma_free_coherent(&devinfo->pdev->dev, size, dma_buf,
1161				  dma_handle);
1162		return NULL;
1163	}
1164	brcmf_commonring_config(&ring->commonring, brcmf_ring_max_item[ring_id],
1165				ring_itemsize_array[ring_id], dma_buf);
1166	ring->dma_handle = dma_handle;
1167	ring->devinfo = devinfo;
1168	brcmf_commonring_register_cb(&ring->commonring,
1169				     brcmf_pcie_ring_mb_ring_bell,
1170				     brcmf_pcie_ring_mb_update_rptr,
1171				     brcmf_pcie_ring_mb_update_wptr,
1172				     brcmf_pcie_ring_mb_write_rptr,
1173				     brcmf_pcie_ring_mb_write_wptr, ring);
1174
1175	return (ring);
1176}
1177
1178
1179static void brcmf_pcie_release_ringbuffer(struct device *dev,
1180					  struct brcmf_pcie_ringbuf *ring)
1181{
1182	void *dma_buf;
1183	u32 size;
1184
1185	if (!ring)
1186		return;
1187
1188	dma_buf = ring->commonring.buf_addr;
1189	if (dma_buf) {
1190		size = ring->commonring.depth * ring->commonring.item_len;
1191		dma_free_coherent(dev, size, dma_buf, ring->dma_handle);
1192	}
1193	kfree(ring);
1194}
1195
1196
1197static void brcmf_pcie_release_ringbuffers(struct brcmf_pciedev_info *devinfo)
1198{
1199	u32 i;
1200
1201	for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1202		brcmf_pcie_release_ringbuffer(&devinfo->pdev->dev,
1203					      devinfo->shared.commonrings[i]);
1204		devinfo->shared.commonrings[i] = NULL;
1205	}
1206	kfree(devinfo->shared.flowrings);
1207	devinfo->shared.flowrings = NULL;
1208	if (devinfo->idxbuf) {
1209		dma_free_coherent(&devinfo->pdev->dev,
1210				  devinfo->idxbuf_sz,
1211				  devinfo->idxbuf,
1212				  devinfo->idxbuf_dmahandle);
1213		devinfo->idxbuf = NULL;
1214	}
1215}
1216
1217
1218static int brcmf_pcie_init_ringbuffers(struct brcmf_pciedev_info *devinfo)
1219{
1220	struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev);
1221	struct brcmf_pcie_ringbuf *ring;
1222	struct brcmf_pcie_ringbuf *rings;
1223	u32 d2h_w_idx_ptr;
1224	u32 d2h_r_idx_ptr;
1225	u32 h2d_w_idx_ptr;
1226	u32 h2d_r_idx_ptr;
1227	u32 ring_mem_ptr;
1228	u32 i;
1229	u64 address;
1230	u32 bufsz;
1231	u8 idx_offset;
1232	struct brcmf_pcie_dhi_ringinfo ringinfo;
1233	u16 max_flowrings;
1234	u16 max_submissionrings;
1235	u16 max_completionrings;
1236
1237	memcpy_fromio(&ringinfo, devinfo->tcm + devinfo->shared.ring_info_addr,
1238		      sizeof(ringinfo));
1239	if (devinfo->shared.version >= 6) {
1240		max_submissionrings = le16_to_cpu(ringinfo.max_submissionrings);
1241		max_flowrings = le16_to_cpu(ringinfo.max_flowrings);
1242		max_completionrings = le16_to_cpu(ringinfo.max_completionrings);
1243	} else {
1244		max_submissionrings = le16_to_cpu(ringinfo.max_flowrings);
1245		max_flowrings = max_submissionrings -
1246				BRCMF_NROF_H2D_COMMON_MSGRINGS;
1247		max_completionrings = BRCMF_NROF_D2H_COMMON_MSGRINGS;
1248	}
1249	if (max_flowrings > 512) {
1250		brcmf_err(bus, "invalid max_flowrings(%d)\n", max_flowrings);
1251		return -EIO;
1252	}
1253
1254	if (devinfo->dma_idx_sz != 0) {
1255		bufsz = (max_submissionrings + max_completionrings) *
1256			devinfo->dma_idx_sz * 2;
1257		devinfo->idxbuf = dma_alloc_coherent(&devinfo->pdev->dev, bufsz,
1258						     &devinfo->idxbuf_dmahandle,
1259						     GFP_KERNEL);
1260		if (!devinfo->idxbuf)
1261			devinfo->dma_idx_sz = 0;
1262	}
1263
1264	if (devinfo->dma_idx_sz == 0) {
1265		d2h_w_idx_ptr = le32_to_cpu(ringinfo.d2h_w_idx_ptr);
1266		d2h_r_idx_ptr = le32_to_cpu(ringinfo.d2h_r_idx_ptr);
1267		h2d_w_idx_ptr = le32_to_cpu(ringinfo.h2d_w_idx_ptr);
1268		h2d_r_idx_ptr = le32_to_cpu(ringinfo.h2d_r_idx_ptr);
1269		idx_offset = sizeof(u32);
1270		devinfo->write_ptr = brcmf_pcie_write_tcm16;
1271		devinfo->read_ptr = brcmf_pcie_read_tcm16;
1272		brcmf_dbg(PCIE, "Using TCM indices\n");
1273	} else {
1274		memset(devinfo->idxbuf, 0, bufsz);
1275		devinfo->idxbuf_sz = bufsz;
1276		idx_offset = devinfo->dma_idx_sz;
1277		devinfo->write_ptr = brcmf_pcie_write_idx;
1278		devinfo->read_ptr = brcmf_pcie_read_idx;
1279
1280		h2d_w_idx_ptr = 0;
1281		address = (u64)devinfo->idxbuf_dmahandle;
1282		ringinfo.h2d_w_idx_hostaddr.low_addr =
1283			cpu_to_le32(address & 0xffffffff);
1284		ringinfo.h2d_w_idx_hostaddr.high_addr =
1285			cpu_to_le32(address >> 32);
1286
1287		h2d_r_idx_ptr = h2d_w_idx_ptr +
1288				max_submissionrings * idx_offset;
1289		address += max_submissionrings * idx_offset;
1290		ringinfo.h2d_r_idx_hostaddr.low_addr =
1291			cpu_to_le32(address & 0xffffffff);
1292		ringinfo.h2d_r_idx_hostaddr.high_addr =
1293			cpu_to_le32(address >> 32);
1294
1295		d2h_w_idx_ptr = h2d_r_idx_ptr +
1296				max_submissionrings * idx_offset;
1297		address += max_submissionrings * idx_offset;
1298		ringinfo.d2h_w_idx_hostaddr.low_addr =
1299			cpu_to_le32(address & 0xffffffff);
1300		ringinfo.d2h_w_idx_hostaddr.high_addr =
1301			cpu_to_le32(address >> 32);
1302
1303		d2h_r_idx_ptr = d2h_w_idx_ptr +
1304				max_completionrings * idx_offset;
1305		address += max_completionrings * idx_offset;
1306		ringinfo.d2h_r_idx_hostaddr.low_addr =
1307			cpu_to_le32(address & 0xffffffff);
1308		ringinfo.d2h_r_idx_hostaddr.high_addr =
1309			cpu_to_le32(address >> 32);
1310
1311		memcpy_toio(devinfo->tcm + devinfo->shared.ring_info_addr,
1312			    &ringinfo, sizeof(ringinfo));
1313		brcmf_dbg(PCIE, "Using host memory indices\n");
1314	}
1315
1316	ring_mem_ptr = le32_to_cpu(ringinfo.ringmem);
1317
1318	for (i = 0; i < BRCMF_NROF_H2D_COMMON_MSGRINGS; i++) {
1319		ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1320		if (!ring)
1321			goto fail;
1322		ring->w_idx_addr = h2d_w_idx_ptr;
1323		ring->r_idx_addr = h2d_r_idx_ptr;
1324		ring->id = i;
1325		devinfo->shared.commonrings[i] = ring;
1326
1327		h2d_w_idx_ptr += idx_offset;
1328		h2d_r_idx_ptr += idx_offset;
1329		ring_mem_ptr += BRCMF_RING_MEM_SZ;
1330	}
1331
1332	for (i = BRCMF_NROF_H2D_COMMON_MSGRINGS;
1333	     i < BRCMF_NROF_COMMON_MSGRINGS; i++) {
1334		ring = brcmf_pcie_alloc_dma_and_ring(devinfo, i, ring_mem_ptr);
1335		if (!ring)
1336			goto fail;
1337		ring->w_idx_addr = d2h_w_idx_ptr;
1338		ring->r_idx_addr = d2h_r_idx_ptr;
1339		ring->id = i;
1340		devinfo->shared.commonrings[i] = ring;
1341
1342		d2h_w_idx_ptr += idx_offset;
1343		d2h_r_idx_ptr += idx_offset;
1344		ring_mem_ptr += BRCMF_RING_MEM_SZ;
1345	}
1346
1347	devinfo->shared.max_flowrings = max_flowrings;
1348	devinfo->shared.max_submissionrings = max_submissionrings;
1349	devinfo->shared.max_completionrings = max_completionrings;
1350	rings = kcalloc(max_flowrings, sizeof(*ring), GFP_KERNEL);
1351	if (!rings)
1352		goto fail;
1353
1354	brcmf_dbg(PCIE, "Nr of flowrings is %d\n", max_flowrings);
1355
1356	for (i = 0; i < max_flowrings; i++) {
1357		ring = &rings[i];
1358		ring->devinfo = devinfo;
1359		ring->id = i + BRCMF_H2D_MSGRING_FLOWRING_IDSTART;
1360		brcmf_commonring_register_cb(&ring->commonring,
1361					     brcmf_pcie_ring_mb_ring_bell,
1362					     brcmf_pcie_ring_mb_update_rptr,
1363					     brcmf_pcie_ring_mb_update_wptr,
1364					     brcmf_pcie_ring_mb_write_rptr,
1365					     brcmf_pcie_ring_mb_write_wptr,
1366					     ring);
1367		ring->w_idx_addr = h2d_w_idx_ptr;
1368		ring->r_idx_addr = h2d_r_idx_ptr;
1369		h2d_w_idx_ptr += idx_offset;
1370		h2d_r_idx_ptr += idx_offset;
1371	}
1372	devinfo->shared.flowrings = rings;
1373
1374	return 0;
1375
1376fail:
1377	brcmf_err(bus, "Allocating ring buffers failed\n");
1378	brcmf_pcie_release_ringbuffers(devinfo);
1379	return -ENOMEM;
1380}
1381
1382
1383static void
1384brcmf_pcie_release_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1385{
1386	if (devinfo->shared.scratch)
1387		dma_free_coherent(&devinfo->pdev->dev,
1388				  BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1389				  devinfo->shared.scratch,
1390				  devinfo->shared.scratch_dmahandle);
1391	if (devinfo->shared.ringupd)
1392		dma_free_coherent(&devinfo->pdev->dev,
1393				  BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1394				  devinfo->shared.ringupd,
1395				  devinfo->shared.ringupd_dmahandle);
1396}
1397
1398static int brcmf_pcie_init_scratchbuffers(struct brcmf_pciedev_info *devinfo)
1399{
1400	struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev);
1401	u64 address;
1402	u32 addr;
1403
1404	devinfo->shared.scratch =
1405		dma_alloc_coherent(&devinfo->pdev->dev,
1406				   BRCMF_DMA_D2H_SCRATCH_BUF_LEN,
1407				   &devinfo->shared.scratch_dmahandle,
1408				   GFP_KERNEL);
1409	if (!devinfo->shared.scratch)
1410		goto fail;
1411
1412	addr = devinfo->shared.tcm_base_address +
1413	       BRCMF_SHARED_DMA_SCRATCH_ADDR_OFFSET;
1414	address = (u64)devinfo->shared.scratch_dmahandle;
1415	brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1416	brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1417	addr = devinfo->shared.tcm_base_address +
1418	       BRCMF_SHARED_DMA_SCRATCH_LEN_OFFSET;
1419	brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_SCRATCH_BUF_LEN);
1420
1421	devinfo->shared.ringupd =
1422		dma_alloc_coherent(&devinfo->pdev->dev,
1423				   BRCMF_DMA_D2H_RINGUPD_BUF_LEN,
1424				   &devinfo->shared.ringupd_dmahandle,
1425				   GFP_KERNEL);
1426	if (!devinfo->shared.ringupd)
1427		goto fail;
1428
1429	addr = devinfo->shared.tcm_base_address +
1430	       BRCMF_SHARED_DMA_RINGUPD_ADDR_OFFSET;
1431	address = (u64)devinfo->shared.ringupd_dmahandle;
1432	brcmf_pcie_write_tcm32(devinfo, addr, address & 0xffffffff);
1433	brcmf_pcie_write_tcm32(devinfo, addr + 4, address >> 32);
1434	addr = devinfo->shared.tcm_base_address +
1435	       BRCMF_SHARED_DMA_RINGUPD_LEN_OFFSET;
1436	brcmf_pcie_write_tcm32(devinfo, addr, BRCMF_DMA_D2H_RINGUPD_BUF_LEN);
1437	return 0;
1438
1439fail:
1440	brcmf_err(bus, "Allocating scratch buffers failed\n");
1441	brcmf_pcie_release_scratchbuffers(devinfo);
1442	return -ENOMEM;
1443}
1444
1445
1446static void brcmf_pcie_down(struct device *dev)
1447{
1448	struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1449	struct brcmf_pciedev *pcie_bus_dev = bus_if->bus_priv.pcie;
1450	struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo;
1451
1452	brcmf_pcie_fwcon_timer(devinfo, false);
1453}
1454
1455static int brcmf_pcie_preinit(struct device *dev)
1456{
1457	struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1458	struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1459
1460	brcmf_dbg(PCIE, "Enter\n");
1461
1462	brcmf_pcie_intr_enable(buspub->devinfo);
1463	brcmf_pcie_hostready(buspub->devinfo);
1464
1465	return 0;
1466}
1467
1468static int brcmf_pcie_tx(struct device *dev, struct sk_buff *skb)
1469{
1470	return 0;
1471}
1472
1473
1474static int brcmf_pcie_tx_ctlpkt(struct device *dev, unsigned char *msg,
1475				uint len)
1476{
1477	return 0;
1478}
1479
1480
1481static int brcmf_pcie_rx_ctlpkt(struct device *dev, unsigned char *msg,
1482				uint len)
1483{
1484	return 0;
1485}
1486
1487
1488static void brcmf_pcie_wowl_config(struct device *dev, bool enabled)
1489{
1490	struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1491	struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1492	struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1493
1494	brcmf_dbg(PCIE, "Configuring WOWL, enabled=%d\n", enabled);
1495	devinfo->wowl_enabled = enabled;
1496}
1497
1498
1499static size_t brcmf_pcie_get_ramsize(struct device *dev)
1500{
1501	struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1502	struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1503	struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1504
1505	return devinfo->ci->ramsize - devinfo->ci->srsize;
1506}
1507
1508
1509static int brcmf_pcie_get_memdump(struct device *dev, void *data, size_t len)
1510{
1511	struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1512	struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1513	struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1514
1515	brcmf_dbg(PCIE, "dump at 0x%08X: len=%zu\n", devinfo->ci->rambase, len);
1516	brcmf_pcie_copy_dev_tomem(devinfo, devinfo->ci->rambase, data, len);
1517	return 0;
1518}
1519
1520static int brcmf_pcie_get_blob(struct device *dev, const struct firmware **fw,
1521			       enum brcmf_blob_type type)
1522{
1523	struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1524	struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1525	struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1526
1527	switch (type) {
1528	case BRCMF_BLOB_CLM:
1529		*fw = devinfo->clm_fw;
1530		devinfo->clm_fw = NULL;
1531		break;
1532	case BRCMF_BLOB_TXCAP:
1533		*fw = devinfo->txcap_fw;
1534		devinfo->txcap_fw = NULL;
1535		break;
1536	default:
1537		return -ENOENT;
1538	}
1539
1540	if (!*fw)
1541		return -ENOENT;
1542
1543	return 0;
1544}
1545
1546static int brcmf_pcie_reset(struct device *dev)
1547{
1548	struct brcmf_bus *bus_if = dev_get_drvdata(dev);
1549	struct brcmf_pciedev *buspub = bus_if->bus_priv.pcie;
1550	struct brcmf_pciedev_info *devinfo = buspub->devinfo;
1551	struct brcmf_fw_request *fwreq;
1552	int err;
1553
1554	brcmf_pcie_intr_disable(devinfo);
1555
1556	brcmf_pcie_bus_console_read(devinfo, true);
1557
1558	brcmf_detach(dev);
1559
1560	brcmf_pcie_release_irq(devinfo);
1561	brcmf_pcie_release_scratchbuffers(devinfo);
1562	brcmf_pcie_release_ringbuffers(devinfo);
1563	brcmf_pcie_reset_device(devinfo);
1564
1565	fwreq = brcmf_pcie_prepare_fw_request(devinfo);
1566	if (!fwreq) {
1567		dev_err(dev, "Failed to prepare FW request\n");
1568		return -ENOMEM;
1569	}
1570
1571	err = brcmf_fw_get_firmwares(dev, fwreq, brcmf_pcie_setup);
1572	if (err) {
1573		dev_err(dev, "Failed to prepare FW request\n");
1574		kfree(fwreq);
1575	}
1576
1577	return err;
1578}
1579
1580static const struct brcmf_bus_ops brcmf_pcie_bus_ops = {
1581	.preinit = brcmf_pcie_preinit,
1582	.txdata = brcmf_pcie_tx,
1583	.stop = brcmf_pcie_down,
1584	.txctl = brcmf_pcie_tx_ctlpkt,
1585	.rxctl = brcmf_pcie_rx_ctlpkt,
1586	.wowl_config = brcmf_pcie_wowl_config,
1587	.get_ramsize = brcmf_pcie_get_ramsize,
1588	.get_memdump = brcmf_pcie_get_memdump,
1589	.get_blob = brcmf_pcie_get_blob,
1590	.reset = brcmf_pcie_reset,
1591	.debugfs_create = brcmf_pcie_debugfs_create,
1592};
1593
1594
1595static void
1596brcmf_pcie_adjust_ramsize(struct brcmf_pciedev_info *devinfo, u8 *data,
1597			  u32 data_len)
1598{
1599	__le32 *field;
1600	u32 newsize;
1601
1602	if (data_len < BRCMF_RAMSIZE_OFFSET + 8)
1603		return;
1604
1605	field = (__le32 *)&data[BRCMF_RAMSIZE_OFFSET];
1606	if (le32_to_cpup(field) != BRCMF_RAMSIZE_MAGIC)
1607		return;
1608	field++;
1609	newsize = le32_to_cpup(field);
1610
1611	brcmf_dbg(PCIE, "Found ramsize info in FW, adjusting to 0x%x\n",
1612		  newsize);
1613	devinfo->ci->ramsize = newsize;
1614}
1615
1616
1617static int
1618brcmf_pcie_init_share_ram_info(struct brcmf_pciedev_info *devinfo,
1619			       u32 sharedram_addr)
1620{
1621	struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev);
1622	struct brcmf_pcie_shared_info *shared;
1623	u32 addr;
1624
1625	shared = &devinfo->shared;
1626	shared->tcm_base_address = sharedram_addr;
1627
1628	shared->flags = brcmf_pcie_read_tcm32(devinfo, sharedram_addr);
1629	shared->version = (u8)(shared->flags & BRCMF_PCIE_SHARED_VERSION_MASK);
1630	brcmf_dbg(PCIE, "PCIe protocol version %d\n", shared->version);
1631	if ((shared->version > BRCMF_PCIE_MAX_SHARED_VERSION) ||
1632	    (shared->version < BRCMF_PCIE_MIN_SHARED_VERSION)) {
1633		brcmf_err(bus, "Unsupported PCIE version %d\n",
1634			  shared->version);
1635		return -EINVAL;
1636	}
1637
1638	/* check firmware support dma indicies */
1639	if (shared->flags & BRCMF_PCIE_SHARED_DMA_INDEX) {
1640		if (shared->flags & BRCMF_PCIE_SHARED_DMA_2B_IDX)
1641			devinfo->dma_idx_sz = sizeof(u16);
1642		else
1643			devinfo->dma_idx_sz = sizeof(u32);
1644	}
1645
1646	addr = sharedram_addr + BRCMF_SHARED_MAX_RXBUFPOST_OFFSET;
1647	shared->max_rxbufpost = brcmf_pcie_read_tcm16(devinfo, addr);
1648	if (shared->max_rxbufpost == 0)
1649		shared->max_rxbufpost = BRCMF_DEF_MAX_RXBUFPOST;
1650
1651	addr = sharedram_addr + BRCMF_SHARED_RX_DATAOFFSET_OFFSET;
1652	shared->rx_dataoffset = brcmf_pcie_read_tcm32(devinfo, addr);
1653
1654	addr = sharedram_addr + BRCMF_SHARED_HTOD_MB_DATA_ADDR_OFFSET;
1655	shared->htod_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1656
1657	addr = sharedram_addr + BRCMF_SHARED_DTOH_MB_DATA_ADDR_OFFSET;
1658	shared->dtoh_mb_data_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1659
1660	addr = sharedram_addr + BRCMF_SHARED_RING_INFO_ADDR_OFFSET;
1661	shared->ring_info_addr = brcmf_pcie_read_tcm32(devinfo, addr);
1662
1663	brcmf_dbg(PCIE, "max rx buf post %d, rx dataoffset %d\n",
1664		  shared->max_rxbufpost, shared->rx_dataoffset);
1665
1666	brcmf_pcie_bus_console_init(devinfo);
1667	brcmf_pcie_bus_console_read(devinfo, false);
1668
1669	return 0;
1670}
1671
1672struct brcmf_random_seed_footer {
1673	__le32 length;
1674	__le32 magic;
1675};
1676
1677#define BRCMF_RANDOM_SEED_MAGIC		0xfeedc0de
1678#define BRCMF_RANDOM_SEED_LENGTH	0x100
1679
1680static noinline_for_stack void
1681brcmf_pcie_provide_random_bytes(struct brcmf_pciedev_info *devinfo, u32 address)
1682{
1683	u8 randbuf[BRCMF_RANDOM_SEED_LENGTH];
1684
1685	get_random_bytes(randbuf, BRCMF_RANDOM_SEED_LENGTH);
1686	memcpy_toio(devinfo->tcm + address, randbuf, BRCMF_RANDOM_SEED_LENGTH);
1687}
1688
1689static int brcmf_pcie_download_fw_nvram(struct brcmf_pciedev_info *devinfo,
1690					const struct firmware *fw, void *nvram,
1691					u32 nvram_len)
1692{
1693	struct brcmf_bus *bus = dev_get_drvdata(&devinfo->pdev->dev);
1694	u32 sharedram_addr;
1695	u32 sharedram_addr_written;
1696	u32 loop_counter;
1697	int err;
1698	u32 address;
1699	u32 resetintr;
1700
1701	brcmf_dbg(PCIE, "Halt ARM.\n");
1702	err = brcmf_pcie_enter_download_state(devinfo);
1703	if (err)
1704		return err;
1705
1706	brcmf_dbg(PCIE, "Download FW %s\n", devinfo->fw_name);
1707	memcpy_toio(devinfo->tcm + devinfo->ci->rambase,
1708		    (void *)fw->data, fw->size);
1709
1710	resetintr = get_unaligned_le32(fw->data);
1711	release_firmware(fw);
1712
1713	/* reset last 4 bytes of RAM address. to be used for shared
1714	 * area. This identifies when FW is running
1715	 */
1716	brcmf_pcie_write_ram32(devinfo, devinfo->ci->ramsize - 4, 0);
1717
1718	if (nvram) {
1719		brcmf_dbg(PCIE, "Download NVRAM %s\n", devinfo->nvram_name);
1720		address = devinfo->ci->rambase + devinfo->ci->ramsize -
1721			  nvram_len;
1722		memcpy_toio(devinfo->tcm + address, nvram, nvram_len);
1723		brcmf_fw_nvram_free(nvram);
1724
1725		if (devinfo->fwseed) {
1726			size_t rand_len = BRCMF_RANDOM_SEED_LENGTH;
1727			struct brcmf_random_seed_footer footer = {
1728				.length = cpu_to_le32(rand_len),
1729				.magic = cpu_to_le32(BRCMF_RANDOM_SEED_MAGIC),
1730			};
1731
1732			/* Some chips/firmwares expect a buffer of random
1733			 * data to be present before NVRAM
1734			 */
1735			brcmf_dbg(PCIE, "Download random seed\n");
1736
1737			address -= sizeof(footer);
1738			memcpy_toio(devinfo->tcm + address, &footer,
1739				    sizeof(footer));
1740
1741			address -= rand_len;
1742			brcmf_pcie_provide_random_bytes(devinfo, address);
1743		}
1744	} else {
1745		brcmf_dbg(PCIE, "No matching NVRAM file found %s\n",
1746			  devinfo->nvram_name);
1747	}
1748
1749	sharedram_addr_written = brcmf_pcie_read_ram32(devinfo,
1750						       devinfo->ci->ramsize -
1751						       4);
1752	brcmf_dbg(PCIE, "Bring ARM in running state\n");
1753	err = brcmf_pcie_exit_download_state(devinfo, resetintr);
1754	if (err)
1755		return err;
1756
1757	brcmf_dbg(PCIE, "Wait for FW init\n");
1758	sharedram_addr = sharedram_addr_written;
1759	loop_counter = BRCMF_PCIE_FW_UP_TIMEOUT / 50;
1760	while ((sharedram_addr == sharedram_addr_written) && (loop_counter)) {
1761		msleep(50);
1762		sharedram_addr = brcmf_pcie_read_ram32(devinfo,
1763						       devinfo->ci->ramsize -
1764						       4);
1765		loop_counter--;
1766	}
1767	if (sharedram_addr == sharedram_addr_written) {
1768		brcmf_err(bus, "FW failed to initialize\n");
1769		return -ENODEV;
1770	}
1771	if (sharedram_addr < devinfo->ci->rambase ||
1772	    sharedram_addr >= devinfo->ci->rambase + devinfo->ci->ramsize) {
1773		brcmf_err(bus, "Invalid shared RAM address 0x%08x\n",
1774			  sharedram_addr);
1775		return -ENODEV;
1776	}
1777	brcmf_dbg(PCIE, "Shared RAM addr: 0x%08x\n", sharedram_addr);
1778
1779	return (brcmf_pcie_init_share_ram_info(devinfo, sharedram_addr));
1780}
1781
1782
1783static int brcmf_pcie_get_resource(struct brcmf_pciedev_info *devinfo)
1784{
1785	struct pci_dev *pdev = devinfo->pdev;
1786	struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
1787	int err;
1788	phys_addr_t  bar0_addr, bar1_addr;
1789	ulong bar1_size;
1790
1791	err = pci_enable_device(pdev);
1792	if (err) {
1793		brcmf_err(bus, "pci_enable_device failed err=%d\n", err);
1794		return err;
1795	}
1796
1797	pci_set_master(pdev);
1798
1799	/* Bar-0 mapped address */
1800	bar0_addr = pci_resource_start(pdev, 0);
1801	/* Bar-1 mapped address */
1802	bar1_addr = pci_resource_start(pdev, 2);
1803	/* read Bar-1 mapped memory range */
1804	bar1_size = pci_resource_len(pdev, 2);
1805	if ((bar1_size == 0) || (bar1_addr == 0)) {
1806		brcmf_err(bus, "BAR1 Not enabled, device size=%ld, addr=%#016llx\n",
1807			  bar1_size, (unsigned long long)bar1_addr);
1808		return -EINVAL;
1809	}
1810
1811	devinfo->regs = ioremap(bar0_addr, BRCMF_PCIE_REG_MAP_SIZE);
1812	devinfo->tcm = ioremap(bar1_addr, bar1_size);
1813
1814	if (!devinfo->regs || !devinfo->tcm) {
1815		brcmf_err(bus, "ioremap() failed (%p,%p)\n", devinfo->regs,
1816			  devinfo->tcm);
1817		return -EINVAL;
1818	}
1819	brcmf_dbg(PCIE, "Phys addr : reg space = %p base addr %#016llx\n",
1820		  devinfo->regs, (unsigned long long)bar0_addr);
1821	brcmf_dbg(PCIE, "Phys addr : mem space = %p base addr %#016llx size 0x%x\n",
1822		  devinfo->tcm, (unsigned long long)bar1_addr,
1823		  (unsigned int)bar1_size);
1824
1825	return 0;
1826}
1827
1828
1829static void brcmf_pcie_release_resource(struct brcmf_pciedev_info *devinfo)
1830{
1831	if (devinfo->tcm)
1832		iounmap(devinfo->tcm);
1833	if (devinfo->regs)
1834		iounmap(devinfo->regs);
1835
1836	pci_disable_device(devinfo->pdev);
1837}
1838
1839
1840static u32 brcmf_pcie_buscore_prep_addr(const struct pci_dev *pdev, u32 addr)
1841{
1842	u32 ret_addr;
1843
1844	ret_addr = addr & (BRCMF_PCIE_BAR0_REG_SIZE - 1);
1845	addr &= ~(BRCMF_PCIE_BAR0_REG_SIZE - 1);
1846	pci_write_config_dword(pdev, BRCMF_PCIE_BAR0_WINDOW, addr);
1847
1848	return ret_addr;
1849}
1850
1851
1852static u32 brcmf_pcie_buscore_read32(void *ctx, u32 addr)
1853{
1854	struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1855
1856	addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1857	return brcmf_pcie_read_reg32(devinfo, addr);
1858}
1859
1860
1861static void brcmf_pcie_buscore_write32(void *ctx, u32 addr, u32 value)
1862{
1863	struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1864
1865	addr = brcmf_pcie_buscore_prep_addr(devinfo->pdev, addr);
1866	brcmf_pcie_write_reg32(devinfo, addr, value);
1867}
1868
1869
1870static int brcmf_pcie_buscoreprep(void *ctx)
1871{
1872	return brcmf_pcie_get_resource(ctx);
1873}
1874
1875
1876static int brcmf_pcie_buscore_reset(void *ctx, struct brcmf_chip *chip)
1877{
1878	struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1879	struct brcmf_core *core;
1880	u32 val, reg;
1881
1882	devinfo->ci = chip;
1883	brcmf_pcie_reset_device(devinfo);
1884
1885	/* reginfo is not ready yet */
1886	core = brcmf_chip_get_core(chip, BCMA_CORE_PCIE2);
1887	if (core->rev >= 64)
1888		reg = BRCMF_PCIE_64_PCIE2REG_MAILBOXINT;
1889	else
1890		reg = BRCMF_PCIE_PCIE2REG_MAILBOXINT;
1891
1892	val = brcmf_pcie_read_reg32(devinfo, reg);
1893	if (val != 0xffffffff)
1894		brcmf_pcie_write_reg32(devinfo, reg, val);
1895
1896	return 0;
1897}
1898
1899
1900static void brcmf_pcie_buscore_activate(void *ctx, struct brcmf_chip *chip,
1901					u32 rstvec)
1902{
1903	struct brcmf_pciedev_info *devinfo = (struct brcmf_pciedev_info *)ctx;
1904
1905	brcmf_pcie_write_tcm32(devinfo, 0, rstvec);
1906}
1907
1908
1909static const struct brcmf_buscore_ops brcmf_pcie_buscore_ops = {
1910	.prepare = brcmf_pcie_buscoreprep,
1911	.reset = brcmf_pcie_buscore_reset,
1912	.activate = brcmf_pcie_buscore_activate,
1913	.read32 = brcmf_pcie_buscore_read32,
1914	.write32 = brcmf_pcie_buscore_write32,
1915};
1916
1917#define BRCMF_OTP_SYS_VENDOR	0x15
1918#define BRCMF_OTP_BRCM_CIS	0x80
1919
1920#define BRCMF_OTP_VENDOR_HDR	0x00000008
1921
1922static int
1923brcmf_pcie_parse_otp_sys_vendor(struct brcmf_pciedev_info *devinfo,
1924				u8 *data, size_t size)
1925{
1926	int idx = 4;
1927	const char *chip_params;
1928	const char *board_params;
1929	const char *p;
1930
1931	/* 4-byte header and two empty strings */
1932	if (size < 6)
1933		return -EINVAL;
1934
1935	if (get_unaligned_le32(data) != BRCMF_OTP_VENDOR_HDR)
1936		return -EINVAL;
1937
1938	chip_params = &data[idx];
1939
1940	/* Skip first string, including terminator */
1941	idx += strnlen(chip_params, size - idx) + 1;
1942	if (idx >= size)
1943		return -EINVAL;
1944
1945	board_params = &data[idx];
1946
1947	/* Skip to terminator of second string */
1948	idx += strnlen(board_params, size - idx);
1949	if (idx >= size)
1950		return -EINVAL;
1951
1952	/* At this point both strings are guaranteed NUL-terminated */
1953	brcmf_dbg(PCIE, "OTP: chip_params='%s' board_params='%s'\n",
1954		  chip_params, board_params);
1955
1956	p = skip_spaces(board_params);
1957	while (*p) {
1958		char tag = *p++;
1959		const char *end;
1960		size_t len;
1961
1962		if (*p++ != '=') /* implicit NUL check */
1963			return -EINVAL;
1964
1965		/* *p might be NUL here, if so end == p and len == 0 */
1966		end = strchrnul(p, ' ');
1967		len = end - p;
1968
1969		/* leave 1 byte for NUL in destination string */
1970		if (len > (BRCMF_OTP_MAX_PARAM_LEN - 1))
1971			return -EINVAL;
1972
1973		/* Copy len characters plus a NUL terminator */
1974		switch (tag) {
1975		case 'M':
1976			strscpy(devinfo->otp.module, p, len + 1);
1977			break;
1978		case 'V':
1979			strscpy(devinfo->otp.vendor, p, len + 1);
1980			break;
1981		case 'm':
1982			strscpy(devinfo->otp.version, p, len + 1);
1983			break;
1984		}
1985
1986		/* Skip to next arg, if any */
1987		p = skip_spaces(end);
1988	}
1989
1990	brcmf_dbg(PCIE, "OTP: module=%s vendor=%s version=%s\n",
1991		  devinfo->otp.module, devinfo->otp.vendor,
1992		  devinfo->otp.version);
1993
1994	if (!devinfo->otp.module[0] ||
1995	    !devinfo->otp.vendor[0] ||
1996	    !devinfo->otp.version[0])
1997		return -EINVAL;
1998
1999	devinfo->otp.valid = true;
2000	return 0;
2001}
2002
2003static int
2004brcmf_pcie_parse_otp(struct brcmf_pciedev_info *devinfo, u8 *otp, size_t size)
2005{
2006	int p = 0;
2007	int ret = -EINVAL;
2008
2009	brcmf_dbg(PCIE, "parse_otp size=%zd\n", size);
2010
2011	while (p < (size - 1)) {
2012		u8 type = otp[p];
2013		u8 length = otp[p + 1];
2014
2015		if (type == 0)
2016			break;
2017
2018		if ((p + 2 + length) > size)
2019			break;
2020
2021		switch (type) {
2022		case BRCMF_OTP_SYS_VENDOR:
2023			brcmf_dbg(PCIE, "OTP @ 0x%x (%d): SYS_VENDOR\n",
2024				  p, length);
2025			ret = brcmf_pcie_parse_otp_sys_vendor(devinfo,
2026							      &otp[p + 2],
2027							      length);
2028			break;
2029		case BRCMF_OTP_BRCM_CIS:
2030			brcmf_dbg(PCIE, "OTP @ 0x%x (%d): BRCM_CIS\n",
2031				  p, length);
2032			break;
2033		default:
2034			brcmf_dbg(PCIE, "OTP @ 0x%x (%d): Unknown type 0x%x\n",
2035				  p, length, type);
2036			break;
2037		}
2038
2039		p += 2 + length;
2040	}
2041
2042	return ret;
2043}
2044
2045static int brcmf_pcie_read_otp(struct brcmf_pciedev_info *devinfo)
2046{
2047	const struct pci_dev *pdev = devinfo->pdev;
2048	struct brcmf_bus *bus = dev_get_drvdata(&pdev->dev);
2049	u32 coreid, base, words, idx, sromctl;
2050	u16 *otp;
2051	struct brcmf_core *core;
2052	int ret;
2053
2054	switch (devinfo->ci->chip) {
2055	case BRCM_CC_4355_CHIP_ID:
2056		coreid = BCMA_CORE_CHIPCOMMON;
2057		base = 0x8c0;
2058		words = 0xb2;
2059		break;
2060	case BRCM_CC_4364_CHIP_ID:
2061		coreid = BCMA_CORE_CHIPCOMMON;
2062		base = 0x8c0;
2063		words = 0x1a0;
2064		break;
2065	case BRCM_CC_4377_CHIP_ID:
2066	case BRCM_CC_4378_CHIP_ID:
2067		coreid = BCMA_CORE_GCI;
2068		base = 0x1120;
2069		words = 0x170;
2070		break;
2071	case BRCM_CC_4387_CHIP_ID:
2072		coreid = BCMA_CORE_GCI;
2073		base = 0x113c;
2074		words = 0x170;
2075		break;
2076	default:
2077		/* OTP not supported on this chip */
2078		return 0;
2079	}
2080
2081	core = brcmf_chip_get_core(devinfo->ci, coreid);
2082	if (!core) {
2083		brcmf_err(bus, "No OTP core\n");
2084		return -ENODEV;
2085	}
2086
2087	if (coreid == BCMA_CORE_CHIPCOMMON) {
2088		/* Chips with OTP accessed via ChipCommon need additional
2089		 * handling to access the OTP
2090		 */
2091		brcmf_pcie_select_core(devinfo, coreid);
2092		sromctl = READCC32(devinfo, sromcontrol);
2093
2094		if (!(sromctl & BCMA_CC_SROM_CONTROL_OTP_PRESENT)) {
2095			/* Chip lacks OTP, try without it... */
2096			brcmf_err(bus,
2097				  "OTP unavailable, using default firmware\n");
2098			return 0;
2099		}
2100
2101		/* Map OTP to shadow area */
2102		WRITECC32(devinfo, sromcontrol,
2103			  sromctl | BCMA_CC_SROM_CONTROL_OTPSEL);
2104	}
2105
2106	otp = kcalloc(words, sizeof(u16), GFP_KERNEL);
2107	if (!otp)
2108		return -ENOMEM;
2109
2110	/* Map bus window to SROM/OTP shadow area in core */
2111	base = brcmf_pcie_buscore_prep_addr(devinfo->pdev, base + core->base);
2112
2113	brcmf_dbg(PCIE, "OTP data:\n");
2114	for (idx = 0; idx < words; idx++) {
2115		otp[idx] = brcmf_pcie_read_reg16(devinfo, base + 2 * idx);
2116		brcmf_dbg(PCIE, "[%8x] 0x%04x\n", base + 2 * idx, otp[idx]);
2117	}
2118
2119	if (coreid == BCMA_CORE_CHIPCOMMON) {
2120		brcmf_pcie_select_core(devinfo, coreid);
2121		WRITECC32(devinfo, sromcontrol, sromctl);
2122	}
2123
2124	ret = brcmf_pcie_parse_otp(devinfo, (u8 *)otp, 2 * words);
2125	kfree(otp);
2126
2127	return ret;
2128}
2129
2130#define BRCMF_PCIE_FW_CODE	0
2131#define BRCMF_PCIE_FW_NVRAM	1
2132#define BRCMF_PCIE_FW_CLM	2
2133#define BRCMF_PCIE_FW_TXCAP	3
2134
2135static void brcmf_pcie_setup(struct device *dev, int ret,
2136			     struct brcmf_fw_request *fwreq)
2137{
2138	const struct firmware *fw;
2139	void *nvram;
2140	struct brcmf_bus *bus;
2141	struct brcmf_pciedev *pcie_bus_dev;
2142	struct brcmf_pciedev_info *devinfo;
2143	struct brcmf_commonring **flowrings;
2144	u32 i, nvram_len;
2145
2146	bus = dev_get_drvdata(dev);
2147	pcie_bus_dev = bus->bus_priv.pcie;
2148	devinfo = pcie_bus_dev->devinfo;
2149
2150	/* check firmware loading result */
2151	if (ret)
2152		goto fail;
2153
2154	brcmf_pcie_attach(devinfo);
2155
2156	fw = fwreq->items[BRCMF_PCIE_FW_CODE].binary;
2157	nvram = fwreq->items[BRCMF_PCIE_FW_NVRAM].nv_data.data;
2158	nvram_len = fwreq->items[BRCMF_PCIE_FW_NVRAM].nv_data.len;
2159	devinfo->clm_fw = fwreq->items[BRCMF_PCIE_FW_CLM].binary;
2160	devinfo->txcap_fw = fwreq->items[BRCMF_PCIE_FW_TXCAP].binary;
2161	kfree(fwreq);
2162
2163	ret = brcmf_chip_get_raminfo(devinfo->ci);
2164	if (ret) {
2165		brcmf_err(bus, "Failed to get RAM info\n");
2166		release_firmware(fw);
2167		brcmf_fw_nvram_free(nvram);
2168		goto fail;
2169	}
2170
2171	/* Some of the firmwares have the size of the memory of the device
2172	 * defined inside the firmware. This is because part of the memory in
2173	 * the device is shared and the devision is determined by FW. Parse
2174	 * the firmware and adjust the chip memory size now.
2175	 */
2176	brcmf_pcie_adjust_ramsize(devinfo, (u8 *)fw->data, fw->size);
2177
2178	ret = brcmf_pcie_download_fw_nvram(devinfo, fw, nvram, nvram_len);
2179	if (ret)
2180		goto fail;
2181
2182	devinfo->state = BRCMFMAC_PCIE_STATE_UP;
2183
2184	ret = brcmf_pcie_init_ringbuffers(devinfo);
2185	if (ret)
2186		goto fail;
2187
2188	ret = brcmf_pcie_init_scratchbuffers(devinfo);
2189	if (ret)
2190		goto fail;
2191
2192	brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
2193	ret = brcmf_pcie_request_irq(devinfo);
2194	if (ret)
2195		goto fail;
2196
2197	/* hook the commonrings in the bus structure. */
2198	for (i = 0; i < BRCMF_NROF_COMMON_MSGRINGS; i++)
2199		bus->msgbuf->commonrings[i] =
2200				&devinfo->shared.commonrings[i]->commonring;
2201
2202	flowrings = kcalloc(devinfo->shared.max_flowrings, sizeof(*flowrings),
2203			    GFP_KERNEL);
2204	if (!flowrings)
2205		goto fail;
2206
2207	for (i = 0; i < devinfo->shared.max_flowrings; i++)
2208		flowrings[i] = &devinfo->shared.flowrings[i].commonring;
2209	bus->msgbuf->flowrings = flowrings;
2210
2211	bus->msgbuf->rx_dataoffset = devinfo->shared.rx_dataoffset;
2212	bus->msgbuf->max_rxbufpost = devinfo->shared.max_rxbufpost;
2213	bus->msgbuf->max_flowrings = devinfo->shared.max_flowrings;
2214
2215	init_waitqueue_head(&devinfo->mbdata_resp_wait);
2216
2217	ret = brcmf_attach(&devinfo->pdev->dev);
2218	if (ret)
2219		goto fail;
2220
2221	brcmf_pcie_bus_console_read(devinfo, false);
2222
2223	brcmf_pcie_fwcon_timer(devinfo, true);
2224
2225	return;
2226
2227fail:
2228	brcmf_err(bus, "Dongle setup failed\n");
2229	brcmf_pcie_bus_console_read(devinfo, true);
2230	brcmf_fw_crashed(dev);
2231	device_release_driver(dev);
2232}
2233
2234static struct brcmf_fw_request *
2235brcmf_pcie_prepare_fw_request(struct brcmf_pciedev_info *devinfo)
2236{
2237	struct brcmf_fw_request *fwreq;
2238	struct brcmf_fw_name fwnames[] = {
2239		{ ".bin", devinfo->fw_name },
2240		{ ".txt", devinfo->nvram_name },
2241		{ ".clm_blob", devinfo->clm_name },
2242		{ ".txcap_blob", devinfo->txcap_name },
2243	};
2244
2245	fwreq = brcmf_fw_alloc_request(devinfo->ci->chip, devinfo->ci->chiprev,
2246				       brcmf_pcie_fwnames,
2247				       ARRAY_SIZE(brcmf_pcie_fwnames),
2248				       fwnames, ARRAY_SIZE(fwnames));
2249	if (!fwreq)
2250		return NULL;
2251
2252	fwreq->items[BRCMF_PCIE_FW_CODE].type = BRCMF_FW_TYPE_BINARY;
2253	fwreq->items[BRCMF_PCIE_FW_NVRAM].type = BRCMF_FW_TYPE_NVRAM;
2254	fwreq->items[BRCMF_PCIE_FW_NVRAM].flags = BRCMF_FW_REQF_OPTIONAL;
2255	fwreq->items[BRCMF_PCIE_FW_CLM].type = BRCMF_FW_TYPE_BINARY;
2256	fwreq->items[BRCMF_PCIE_FW_CLM].flags = BRCMF_FW_REQF_OPTIONAL;
2257	fwreq->items[BRCMF_PCIE_FW_TXCAP].type = BRCMF_FW_TYPE_BINARY;
2258	fwreq->items[BRCMF_PCIE_FW_TXCAP].flags = BRCMF_FW_REQF_OPTIONAL;
2259	/* NVRAM reserves PCI domain 0 for Broadcom's SDK faked bus */
2260	fwreq->domain_nr = pci_domain_nr(devinfo->pdev->bus) + 1;
2261	fwreq->bus_nr = devinfo->pdev->bus->number;
2262
2263	/* Apple platforms with fancy firmware/NVRAM selection */
2264	if (devinfo->settings->board_type &&
2265	    devinfo->settings->antenna_sku &&
2266	    devinfo->otp.valid) {
2267		const struct brcmf_otp_params *otp = &devinfo->otp;
2268		struct device *dev = &devinfo->pdev->dev;
2269		const char **bt = fwreq->board_types;
2270
2271		brcmf_dbg(PCIE, "Apple board: %s\n",
2272			  devinfo->settings->board_type);
2273
2274		/* Example: apple,shikoku-RASP-m-6.11-X3 */
2275		bt[0] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s-%s-%s-%s",
2276				       devinfo->settings->board_type,
2277				       otp->module, otp->vendor, otp->version,
2278				       devinfo->settings->antenna_sku);
2279		bt[1] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s-%s-%s",
2280				       devinfo->settings->board_type,
2281				       otp->module, otp->vendor, otp->version);
2282		bt[2] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s-%s",
2283				       devinfo->settings->board_type,
2284				       otp->module, otp->vendor);
2285		bt[3] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s",
2286				       devinfo->settings->board_type,
2287				       otp->module);
2288		bt[4] = devm_kasprintf(dev, GFP_KERNEL, "%s-%s",
2289				       devinfo->settings->board_type,
2290				       devinfo->settings->antenna_sku);
2291		bt[5] = devinfo->settings->board_type;
2292
2293		if (!bt[0] || !bt[1] || !bt[2] || !bt[3] || !bt[4]) {
2294			kfree(fwreq);
2295			return NULL;
2296		}
2297	} else {
2298		brcmf_dbg(PCIE, "Board: %s\n", devinfo->settings->board_type);
2299		fwreq->board_types[0] = devinfo->settings->board_type;
2300	}
2301
2302	return fwreq;
2303}
2304
2305#ifdef DEBUG
2306static void
2307brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info *devinfo, bool active)
2308{
2309	if (!active) {
2310		if (devinfo->console_active) {
2311			timer_delete_sync(&devinfo->timer);
2312			devinfo->console_active = false;
2313		}
2314		return;
2315	}
2316
2317	/* don't start the timer */
2318	if (devinfo->state != BRCMFMAC_PCIE_STATE_UP ||
2319	    !devinfo->console_interval || !BRCMF_FWCON_ON())
2320		return;
2321
2322	if (!devinfo->console_active) {
2323		devinfo->timer.expires = jiffies + devinfo->console_interval;
2324		add_timer(&devinfo->timer);
2325		devinfo->console_active = true;
2326	} else {
2327		/* Reschedule the timer */
2328		mod_timer(&devinfo->timer, jiffies + devinfo->console_interval);
2329	}
2330}
2331
2332static void
2333brcmf_pcie_fwcon(struct timer_list *t)
2334{
2335	struct brcmf_pciedev_info *devinfo = timer_container_of(devinfo, t,
2336								timer);
2337
2338	if (!devinfo->console_active)
2339		return;
2340
2341	brcmf_pcie_bus_console_read(devinfo, false);
2342
2343	/* Reschedule the timer if console interval is not zero */
2344	mod_timer(&devinfo->timer, jiffies + devinfo->console_interval);
2345}
2346
2347static int brcmf_pcie_console_interval_get(void *data, u64 *val)
2348{
2349	struct brcmf_pciedev_info *devinfo = data;
2350
2351	*val = devinfo->console_interval;
2352
2353	return 0;
2354}
2355
2356static int brcmf_pcie_console_interval_set(void *data, u64 val)
2357{
2358	struct brcmf_pciedev_info *devinfo = data;
2359
2360	if (val > MAX_CONSOLE_INTERVAL)
2361		return -EINVAL;
2362
2363	devinfo->console_interval = val;
2364
2365	if (!val && devinfo->console_active)
2366		brcmf_pcie_fwcon_timer(devinfo, false);
2367	else if (val)
2368		brcmf_pcie_fwcon_timer(devinfo, true);
2369
2370	return 0;
2371}
2372
2373DEFINE_SIMPLE_ATTRIBUTE(brcmf_pcie_console_interval_fops,
2374			brcmf_pcie_console_interval_get,
2375			brcmf_pcie_console_interval_set,
2376			"%llu\n");
2377
2378static void brcmf_pcie_debugfs_create(struct device *dev)
2379{
2380	struct brcmf_bus *bus_if = dev_get_drvdata(dev);
2381	struct brcmf_pub *drvr = bus_if->drvr;
2382	struct brcmf_pciedev *pcie_bus_dev = bus_if->bus_priv.pcie;
2383	struct brcmf_pciedev_info *devinfo = pcie_bus_dev->devinfo;
2384	struct dentry *dentry = brcmf_debugfs_get_devdir(drvr);
2385
2386	if (IS_ERR_OR_NULL(dentry))
2387		return;
2388
2389	devinfo->console_interval = BRCMF_CONSOLE;
2390
2391	debugfs_create_file("console_interval", 0644, dentry, devinfo,
2392			    &brcmf_pcie_console_interval_fops);
2393}
2394
2395#else
2396void brcmf_pcie_fwcon_timer(struct brcmf_pciedev_info *devinfo, bool active)
2397{
2398}
2399
2400static void brcmf_pcie_debugfs_create(struct device *dev)
2401{
2402}
2403#endif
2404
2405struct brcmf_pcie_drvdata {
2406	enum brcmf_fwvendor vendor;
2407	bool fw_seed;
2408};
2409
2410enum {
2411	BRCMF_DRVDATA_CYW,
2412	BRCMF_DRVDATA_BCA,
2413	BRCMF_DRVDATA_WCC,
2414	BRCMF_DRVDATA_WCC_SEED,
2415};
2416
2417static const struct brcmf_pcie_drvdata drvdata[] = {
2418	[BRCMF_DRVDATA_CYW] = {
2419		.vendor = BRCMF_FWVENDOR_CYW,
2420		.fw_seed = false,
2421	},
2422	[BRCMF_DRVDATA_BCA] = {
2423		.vendor = BRCMF_FWVENDOR_BCA,
2424		.fw_seed = false,
2425	},
2426	[BRCMF_DRVDATA_WCC] = {
2427		.vendor = BRCMF_FWVENDOR_WCC,
2428		.fw_seed = false,
2429	},
2430	[BRCMF_DRVDATA_WCC_SEED] = {
2431		.vendor = BRCMF_FWVENDOR_WCC,
2432		.fw_seed = true,
2433	},
2434};
2435
2436/* Forward declaration for pci_match_id() call */
2437static const struct pci_device_id brcmf_pcie_devid_table[];
2438
2439static int
2440brcmf_pcie_probe(struct pci_dev *pdev, const struct pci_device_id *id)
2441{
2442	int ret;
2443	struct brcmf_fw_request *fwreq;
2444	struct brcmf_pciedev_info *devinfo;
2445	struct brcmf_pciedev *pcie_bus_dev;
2446	struct brcmf_core *core;
2447	struct brcmf_bus *bus;
2448
2449	if (!id) {
2450		id = pci_match_id(brcmf_pcie_devid_table, pdev);
2451		if (!id) {
2452			pci_err(pdev, "Error could not find pci_device_id for %x:%x\n", pdev->vendor, pdev->device);
2453			return -ENODEV;
2454		}
2455	}
2456
2457	brcmf_dbg(PCIE, "Enter %x:%x\n", pdev->vendor, pdev->device);
2458
2459	ret = -ENOMEM;
2460	devinfo = kzalloc(sizeof(*devinfo), GFP_KERNEL);
2461	if (devinfo == NULL)
2462		return ret;
2463
2464	devinfo->pdev = pdev;
2465	pcie_bus_dev = NULL;
2466	devinfo->ci = brcmf_chip_attach(devinfo, pdev->device,
2467					&brcmf_pcie_buscore_ops);
2468	if (IS_ERR(devinfo->ci)) {
2469		ret = PTR_ERR(devinfo->ci);
2470		devinfo->ci = NULL;
2471		goto fail;
2472	}
2473
2474	core = brcmf_chip_get_core(devinfo->ci, BCMA_CORE_PCIE2);
2475	if (core->rev >= 64)
2476		devinfo->reginfo = &brcmf_reginfo_64;
2477	else
2478		devinfo->reginfo = &brcmf_reginfo_default;
2479
2480	pcie_bus_dev = kzalloc(sizeof(*pcie_bus_dev), GFP_KERNEL);
2481	if (pcie_bus_dev == NULL) {
2482		ret = -ENOMEM;
2483		goto fail;
2484	}
2485
2486	devinfo->settings = brcmf_get_module_param(&devinfo->pdev->dev,
2487						   BRCMF_BUSTYPE_PCIE,
2488						   devinfo->ci->chip,
2489						   devinfo->ci->chiprev);
2490	if (!devinfo->settings) {
2491		ret = -ENOMEM;
2492		goto fail;
2493	}
2494	ret = PTR_ERR_OR_ZERO(devinfo->settings);
2495	if (ret < 0)
2496		goto fail;
2497
2498	bus = kzalloc(sizeof(*bus), GFP_KERNEL);
2499	if (!bus) {
2500		ret = -ENOMEM;
2501		goto fail;
2502	}
2503	bus->msgbuf = kzalloc(sizeof(*bus->msgbuf), GFP_KERNEL);
2504	if (!bus->msgbuf) {
2505		ret = -ENOMEM;
2506		kfree(bus);
2507		goto fail;
2508	}
2509
2510	/* hook it all together. */
2511	pcie_bus_dev->devinfo = devinfo;
2512	pcie_bus_dev->bus = bus;
2513	bus->dev = &pdev->dev;
2514	bus->bus_priv.pcie = pcie_bus_dev;
2515	bus->ops = &brcmf_pcie_bus_ops;
2516	bus->proto_type = BRCMF_PROTO_MSGBUF;
2517	bus->chip = devinfo->coreid;
2518	bus->wowl_supported = pci_pme_capable(pdev, PCI_D3hot);
2519	bus->fwvid = drvdata[id->driver_data].vendor;
2520	devinfo->fwseed = drvdata[id->driver_data].fw_seed;
2521	dev_set_drvdata(&pdev->dev, bus);
2522
2523	ret = brcmf_alloc(&devinfo->pdev->dev, devinfo->settings);
2524	if (ret)
2525		goto fail_bus;
2526
2527	/* otp read operation */
2528	switch (bus->fwvid) {
2529	case BRCMF_FWVENDOR_WCC:
2530	case BRCMF_FWVENDOR_BCA:
2531		ret = brcmf_pcie_read_otp(devinfo);
2532		if (ret) {
2533			brcmf_err(bus, "failed to parse OTP\n");
2534			goto fail_brcmf;
2535		}
2536		break;
2537	case BRCMF_FWVENDOR_CYW:
2538	default:
2539		break;
2540	}
2541
2542#ifdef DEBUG
2543	/* Set up the fwcon timer */
2544	timer_setup(&devinfo->timer, brcmf_pcie_fwcon, 0);
2545#endif
2546
2547	fwreq = brcmf_pcie_prepare_fw_request(devinfo);
2548	if (!fwreq) {
2549		ret = -ENOMEM;
2550		goto fail_brcmf;
2551	}
2552
2553	ret = brcmf_fw_get_firmwares(bus->dev, fwreq, brcmf_pcie_setup);
2554	if (ret < 0) {
2555		kfree(fwreq);
2556		goto fail_brcmf;
2557	}
2558	return 0;
2559
2560fail_brcmf:
2561	brcmf_free(&devinfo->pdev->dev);
2562fail_bus:
2563	kfree(bus->msgbuf);
2564	kfree(bus);
2565fail:
2566	brcmf_err(NULL, "failed %x:%x\n", pdev->vendor, pdev->device);
2567	brcmf_pcie_release_resource(devinfo);
2568	if (devinfo->ci)
2569		brcmf_chip_detach(devinfo->ci);
2570	if (devinfo->settings)
2571		brcmf_release_module_param(devinfo->settings);
2572	kfree(pcie_bus_dev);
2573	kfree(devinfo);
2574	return ret;
2575}
2576
2577
2578static void
2579brcmf_pcie_remove(struct pci_dev *pdev)
2580{
2581	struct brcmf_pciedev_info *devinfo;
2582	struct brcmf_bus *bus;
2583
2584	brcmf_dbg(PCIE, "Enter\n");
2585
2586	bus = dev_get_drvdata(&pdev->dev);
2587	if (bus == NULL)
2588		return;
2589
2590	devinfo = bus->bus_priv.pcie->devinfo;
2591	brcmf_pcie_bus_console_read(devinfo, false);
2592	brcmf_pcie_fwcon_timer(devinfo, false);
2593
2594	devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
2595	if (devinfo->ci)
2596		brcmf_pcie_intr_disable(devinfo);
2597
2598	brcmf_detach(&pdev->dev);
2599	brcmf_free(&pdev->dev);
2600
2601	kfree(bus->bus_priv.pcie);
2602	kfree(bus->msgbuf->flowrings);
2603	kfree(bus->msgbuf);
2604	kfree(bus);
2605
2606	brcmf_pcie_release_irq(devinfo);
2607	brcmf_pcie_release_scratchbuffers(devinfo);
2608	brcmf_pcie_release_ringbuffers(devinfo);
2609	brcmf_pcie_reset_device(devinfo);
2610	brcmf_pcie_release_resource(devinfo);
2611	release_firmware(devinfo->clm_fw);
2612	release_firmware(devinfo->txcap_fw);
2613
2614	if (devinfo->ci)
2615		brcmf_chip_detach(devinfo->ci);
2616	if (devinfo->settings)
2617		brcmf_release_module_param(devinfo->settings);
2618
2619	kfree(devinfo);
2620	dev_set_drvdata(&pdev->dev, NULL);
2621}
2622
2623
2624#ifdef CONFIG_PM
2625
2626
2627static int brcmf_pcie_pm_enter_D3(struct device *dev)
2628{
2629	struct brcmf_pciedev_info *devinfo;
2630	struct brcmf_bus *bus;
2631
2632	brcmf_dbg(PCIE, "Enter\n");
2633
2634	bus = dev_get_drvdata(dev);
2635	devinfo = bus->bus_priv.pcie->devinfo;
2636
2637	brcmf_pcie_fwcon_timer(devinfo, false);
2638	brcmf_bus_change_state(bus, BRCMF_BUS_DOWN);
2639
2640	devinfo->mbdata_completed = false;
2641	brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D3_INFORM);
2642
2643	wait_event_timeout(devinfo->mbdata_resp_wait, devinfo->mbdata_completed,
2644			   BRCMF_PCIE_MBDATA_TIMEOUT);
2645	if (!devinfo->mbdata_completed) {
2646		brcmf_err(bus, "Timeout on response for entering D3 substate\n");
2647		brcmf_bus_change_state(bus, BRCMF_BUS_UP);
2648		return -EIO;
2649	}
2650
2651	devinfo->state = BRCMFMAC_PCIE_STATE_DOWN;
2652
2653	return 0;
2654}
2655
2656
2657static int brcmf_pcie_pm_leave_D3(struct device *dev)
2658{
2659	struct brcmf_pciedev_info *devinfo;
2660	struct brcmf_bus *bus;
2661	struct pci_dev *pdev;
2662	int err;
2663
2664	brcmf_dbg(PCIE, "Enter\n");
2665
2666	bus = dev_get_drvdata(dev);
2667	devinfo = bus->bus_priv.pcie->devinfo;
2668	brcmf_dbg(PCIE, "Enter, dev=%p, bus=%p\n", dev, bus);
2669
2670	/* Check if device is still up and running, if so we are ready */
2671	if (brcmf_pcie_read_reg32(devinfo, devinfo->reginfo->intmask) != 0) {
2672		brcmf_dbg(PCIE, "Try to wakeup device....\n");
2673		if (brcmf_pcie_send_mb_data(devinfo, BRCMF_H2D_HOST_D0_INFORM))
2674			goto cleanup;
2675		brcmf_dbg(PCIE, "Hot resume, continue....\n");
2676		devinfo->state = BRCMFMAC_PCIE_STATE_UP;
2677		brcmf_pcie_select_core(devinfo, BCMA_CORE_PCIE2);
2678		brcmf_bus_change_state(bus, BRCMF_BUS_UP);
2679		brcmf_pcie_intr_enable(devinfo);
2680		brcmf_pcie_hostready(devinfo);
2681		brcmf_pcie_fwcon_timer(devinfo, true);
2682		return 0;
2683	}
2684
2685cleanup:
2686	brcmf_chip_detach(devinfo->ci);
2687	devinfo->ci = NULL;
2688	pdev = devinfo->pdev;
2689	brcmf_pcie_remove(pdev);
2690
2691	err = brcmf_pcie_probe(pdev, NULL);
2692	if (err)
2693		__brcmf_err(NULL, __func__, "probe after resume failed, err=%d\n", err);
2694
2695	return err;
2696}
2697
2698
2699static const struct dev_pm_ops brcmf_pciedrvr_pm = {
2700	.suspend = brcmf_pcie_pm_enter_D3,
2701	.resume = brcmf_pcie_pm_leave_D3,
2702	.freeze = brcmf_pcie_pm_enter_D3,
2703	.restore = brcmf_pcie_pm_leave_D3,
2704};
2705
2706
2707#endif /* CONFIG_PM */
2708
2709
2710#define BRCMF_PCIE_DEVICE(dev_id, fw_vend) \
2711	{ \
2712		BRCM_PCIE_VENDOR_ID_BROADCOM, (dev_id), \
2713		PCI_ANY_ID, PCI_ANY_ID, \
2714		PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, \
2715		BRCMF_DRVDATA_ ## fw_vend \
2716	}
2717#define BRCMF_PCIE_DEVICE_SUB(dev_id, subvend, subdev, fw_vend) \
2718	{ \
2719		BRCM_PCIE_VENDOR_ID_BROADCOM, (dev_id), \
2720		(subvend), (subdev), \
2721		PCI_CLASS_NETWORK_OTHER << 8, 0xffff00, \
2722		BRCMF_DRVDATA_ ## fw_vend \
2723	}
2724
2725static const struct pci_device_id brcmf_pcie_devid_table[] = {
2726	BRCMF_PCIE_DEVICE(BRCM_PCIE_4350_DEVICE_ID, WCC),
2727	BRCMF_PCIE_DEVICE_SUB(0x4355, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4355, WCC),
2728	BRCMF_PCIE_DEVICE(BRCM_PCIE_4354_RAW_DEVICE_ID, WCC),
2729	BRCMF_PCIE_DEVICE(BRCM_PCIE_4355_DEVICE_ID, WCC_SEED),
2730	BRCMF_PCIE_DEVICE(BRCM_PCIE_4356_DEVICE_ID, WCC),
2731	BRCMF_PCIE_DEVICE(BRCM_PCIE_43567_DEVICE_ID, WCC),
2732	BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_DEVICE_ID, WCC),
2733	BRCMF_PCIE_DEVICE(BRCM_PCIE_43570_RAW_DEVICE_ID, WCC),
2734	BRCMF_PCIE_DEVICE(BRCM_PCIE_4358_DEVICE_ID, WCC),
2735	BRCMF_PCIE_DEVICE(BRCM_PCIE_4359_DEVICE_ID, WCC),
2736	BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_DEVICE_ID, WCC),
2737	BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_2G_DEVICE_ID, WCC),
2738	BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_5G_DEVICE_ID, WCC),
2739	BRCMF_PCIE_DEVICE(BRCM_PCIE_43602_RAW_DEVICE_ID, WCC),
2740	BRCMF_PCIE_DEVICE(BRCM_PCIE_4364_DEVICE_ID, WCC_SEED),
2741	BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_DEVICE_ID, BCA),
2742	BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_2G_DEVICE_ID, BCA),
2743	BRCMF_PCIE_DEVICE(BRCM_PCIE_4365_5G_DEVICE_ID, BCA),
2744	BRCMF_PCIE_DEVICE_SUB(0x4365, BRCM_PCIE_VENDOR_ID_BROADCOM, 0x4365, BCA),
2745	BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_DEVICE_ID, BCA),
2746	BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_2G_DEVICE_ID, BCA),
2747	BRCMF_PCIE_DEVICE(BRCM_PCIE_4366_5G_DEVICE_ID, BCA),
2748	BRCMF_PCIE_DEVICE(BRCM_PCIE_4371_DEVICE_ID, WCC),
2749	BRCMF_PCIE_DEVICE(BRCM_PCIE_43596_DEVICE_ID, CYW),
2750	BRCMF_PCIE_DEVICE(BRCM_PCIE_4377_DEVICE_ID, WCC_SEED),
2751	BRCMF_PCIE_DEVICE(BRCM_PCIE_4378_DEVICE_ID, WCC_SEED),
2752	BRCMF_PCIE_DEVICE(BRCM_PCIE_4387_DEVICE_ID, WCC_SEED),
2753	BRCMF_PCIE_DEVICE(BRCM_PCIE_43752_DEVICE_ID, WCC_SEED),
2754	BRCMF_PCIE_DEVICE(CY_PCIE_54591_DEVICE_ID, CYW),
2755	{ /* end: all zeroes */ }
2756};
2757
2758
2759MODULE_DEVICE_TABLE(pci, brcmf_pcie_devid_table);
2760
2761
2762static struct pci_driver brcmf_pciedrvr = {
2763	.name = KBUILD_MODNAME,
2764	.id_table = brcmf_pcie_devid_table,
2765	.probe = brcmf_pcie_probe,
2766	.remove = brcmf_pcie_remove,
2767#ifdef CONFIG_PM
2768	.driver.pm = &brcmf_pciedrvr_pm,
2769#endif
2770	.driver.coredump = brcmf_dev_coredump,
2771};
2772
2773
2774int brcmf_pcie_register(void)
2775{
2776	brcmf_dbg(PCIE, "Enter\n");
2777	return pci_register_driver(&brcmf_pciedrvr);
2778}
2779
2780
2781void brcmf_pcie_exit(void)
2782{
2783	brcmf_dbg(PCIE, "Enter\n");
2784	pci_unregister_driver(&brcmf_pciedrvr);
2785}