init.c

   1/*
   2 * Copyright (c) 2008-2011 Atheros Communications Inc.
   3 *
   4 * Permission to use, copy, modify, and/or distribute this software for any
   5 * purpose with or without fee is hereby granted, provided that the above
   6 * copyright notice and this permission notice appear in all copies.
   7 *
   8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15 */
  16
  17#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  18
  19#include <linux/dma-mapping.h>
  20#include <linux/slab.h>
  21#include <linux/module.h>
  22#include <linux/of.h>
  23#include <linux/of_net.h>
  24#include <linux/nvmem-consumer.h>
  25#include <linux/relay.h>
  26#include <linux/dmi.h>
  27#include <net/ieee80211_radiotap.h>
  28
  29#include "ath9k.h"
  30
  31struct ath9k_eeprom_ctx {
  32	struct completion complete;
  33	struct ath_hw *ah;
  34};
  35
  36static char *dev_info = "ath9k";
  37
  38MODULE_AUTHOR("Atheros Communications");
  39MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  40MODULE_LICENSE("Dual BSD/GPL");
  41
  42static unsigned int ath9k_debug = ATH_DBG_DEFAULT;
  43module_param_named(debug, ath9k_debug, uint, 0);
  44MODULE_PARM_DESC(debug, "Debugging mask");
  45
  46int ath9k_modparam_nohwcrypt;
  47module_param_named(nohwcrypt, ath9k_modparam_nohwcrypt, int, 0444);
  48MODULE_PARM_DESC(nohwcrypt, "Disable hardware encryption");
  49
  50int ath9k_led_blink;
  51module_param_named(blink, ath9k_led_blink, int, 0444);
  52MODULE_PARM_DESC(blink, "Enable LED blink on activity");
  53
  54static int ath9k_led_active_high = -1;
  55module_param_named(led_active_high, ath9k_led_active_high, int, 0444);
  56MODULE_PARM_DESC(led_active_high, "Invert LED polarity");
  57
  58static int ath9k_btcoex_enable;
  59module_param_named(btcoex_enable, ath9k_btcoex_enable, int, 0444);
  60MODULE_PARM_DESC(btcoex_enable, "Enable wifi-BT coexistence");
  61
  62static int ath9k_bt_ant_diversity;
  63module_param_named(bt_ant_diversity, ath9k_bt_ant_diversity, int, 0444);
  64MODULE_PARM_DESC(bt_ant_diversity, "Enable WLAN/BT RX antenna diversity");
  65
  66static int ath9k_ps_enable;
  67module_param_named(ps_enable, ath9k_ps_enable, int, 0444);
  68MODULE_PARM_DESC(ps_enable, "Enable WLAN PowerSave");
  69
  70#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
  71
  72int ath9k_use_chanctx;
  73module_param_named(use_chanctx, ath9k_use_chanctx, int, 0444);
  74MODULE_PARM_DESC(use_chanctx, "Enable channel context for concurrency");
  75
  76#endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
  77
  78int ath9k_use_msi;
  79module_param_named(use_msi, ath9k_use_msi, int, 0444);
  80MODULE_PARM_DESC(use_msi, "Use MSI instead of INTx if possible");
  81
  82bool is_ath9k_unloaded;
  83
  84#ifdef CONFIG_MAC80211_LEDS
  85static const struct ieee80211_tpt_blink ath9k_tpt_blink[] = {
  86	{ .throughput = 0 * 1024, .blink_time = 334 },
  87	{ .throughput = 1 * 1024, .blink_time = 260 },
  88	{ .throughput = 5 * 1024, .blink_time = 220 },
  89	{ .throughput = 10 * 1024, .blink_time = 190 },
  90	{ .throughput = 20 * 1024, .blink_time = 170 },
  91	{ .throughput = 50 * 1024, .blink_time = 150 },
  92	{ .throughput = 70 * 1024, .blink_time = 130 },
  93	{ .throughput = 100 * 1024, .blink_time = 110 },
  94	{ .throughput = 200 * 1024, .blink_time = 80 },
  95	{ .throughput = 300 * 1024, .blink_time = 50 },
  96};
  97#endif
  98
  99static int __init set_use_msi(const struct dmi_system_id *dmi)
 100{
 101	ath9k_use_msi = 1;
 102	return 1;
 103}
 104
 105static const struct dmi_system_id ath9k_quirks[] __initconst = {
 106	{
 107		.callback = set_use_msi,
 108		.ident = "Dell Inspiron 24-3460",
 109		.matches = {
 110			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 111			DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 24-3460"),
 112		},
 113	},
 114	{
 115		.callback = set_use_msi,
 116		.ident = "Dell Vostro 3262",
 117		.matches = {
 118			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 119			DMI_MATCH(DMI_PRODUCT_NAME, "Vostro 3262"),
 120		},
 121	},
 122	{
 123		.callback = set_use_msi,
 124		.ident = "Dell Inspiron 3472",
 125		.matches = {
 126			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 127			DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 3472"),
 128		},
 129	},
 130	{
 131		.callback = set_use_msi,
 132		.ident = "Dell Vostro 15-3572",
 133		.matches = {
 134			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 135			DMI_MATCH(DMI_PRODUCT_NAME, "Vostro 15-3572"),
 136		},
 137	},
 138	{
 139		.callback = set_use_msi,
 140		.ident = "Dell Inspiron 14-3473",
 141		.matches = {
 142			DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
 143			DMI_MATCH(DMI_PRODUCT_NAME, "Inspiron 14-3473"),
 144		},
 145	},
 146	{}
 147};
 148
 149static void ath9k_deinit_softc(struct ath_softc *sc);
 150
 151static void ath9k_op_ps_wakeup(struct ath_common *common)
 152{
 153	ath9k_ps_wakeup(common->priv);
 154}
 155
 156static void ath9k_op_ps_restore(struct ath_common *common)
 157{
 158	ath9k_ps_restore(common->priv);
 159}
 160
 161static const struct ath_ps_ops ath9k_ps_ops = {
 162	.wakeup = ath9k_op_ps_wakeup,
 163	.restore = ath9k_op_ps_restore,
 164};
 165
 166/*
 167 * Read and write, they both share the same lock. We do this to serialize
 168 * reads and writes on Atheros 802.11n PCI devices only. This is required
 169 * as the FIFO on these devices can only accept sanely 2 requests.
 170 */
 171
 172static void ath9k_iowrite32(void *hw_priv, u32 val, u32 reg_offset)
 173{
 174	struct ath_hw *ah = hw_priv;
 175	struct ath_common *common = ath9k_hw_common(ah);
 176	struct ath_softc *sc = common->priv;
 177
 178	if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
 179		unsigned long flags;
 180		spin_lock_irqsave(&sc->sc_serial_rw, flags);
 181		iowrite32(val, sc->mem + reg_offset);
 182		spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
 183	} else
 184		iowrite32(val, sc->mem + reg_offset);
 185}
 186
 187static unsigned int ath9k_ioread32(void *hw_priv, u32 reg_offset)
 188{
 189	struct ath_hw *ah = hw_priv;
 190	struct ath_common *common = ath9k_hw_common(ah);
 191	struct ath_softc *sc = common->priv;
 192	u32 val;
 193
 194	if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
 195		unsigned long flags;
 196		spin_lock_irqsave(&sc->sc_serial_rw, flags);
 197		val = ioread32(sc->mem + reg_offset);
 198		spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
 199	} else
 200		val = ioread32(sc->mem + reg_offset);
 201	return val;
 202}
 203
 204static void ath9k_multi_ioread32(void *hw_priv, u32 *addr,
 205                                u32 *val, u16 count)
 206{
 207	int i;
 208
 209	for (i = 0; i < count; i++)
 210		val[i] = ath9k_ioread32(hw_priv, addr[i]);
 211}
 212
 213
 214static unsigned int __ath9k_reg_rmw(struct ath_softc *sc, u32 reg_offset,
 215				    u32 set, u32 clr)
 216{
 217	u32 val;
 218
 219	val = ioread32(sc->mem + reg_offset);
 220	val &= ~clr;
 221	val |= set;
 222	iowrite32(val, sc->mem + reg_offset);
 223
 224	return val;
 225}
 226
 227static unsigned int ath9k_reg_rmw(void *hw_priv, u32 reg_offset, u32 set, u32 clr)
 228{
 229	struct ath_hw *ah = hw_priv;
 230	struct ath_common *common = ath9k_hw_common(ah);
 231	struct ath_softc *sc = common->priv;
 232	unsigned long flags;
 233	u32 val;
 234
 235	if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_ON) {
 236		spin_lock_irqsave(&sc->sc_serial_rw, flags);
 237		val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
 238		spin_unlock_irqrestore(&sc->sc_serial_rw, flags);
 239	} else
 240		val = __ath9k_reg_rmw(sc, reg_offset, set, clr);
 241
 242	return val;
 243}
 244
 245/**************************/
 246/*     Initialization     */
 247/**************************/
 248
 249static void ath9k_reg_notifier(struct wiphy *wiphy,
 250			       struct regulatory_request *request)
 251{
 252	struct ieee80211_hw *hw = wiphy_to_ieee80211_hw(wiphy);
 253	struct ath_softc *sc = hw->priv;
 254	struct ath_hw *ah = sc->sc_ah;
 255	struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
 256
 257	ath_reg_notifier_apply(wiphy, request, reg);
 258
 259	/* synchronize DFS detector if regulatory domain changed */
 260	if (sc->dfs_detector != NULL)
 261		sc->dfs_detector->set_dfs_domain(sc->dfs_detector,
 262						 request->dfs_region);
 263
 264	/* Set tx power */
 265	if (!ah->curchan)
 266		return;
 267
 268	sc->cur_chan->txpower = 2 * ah->curchan->chan->max_power;
 269	ath9k_ps_wakeup(sc);
 270	ath9k_hw_set_txpowerlimit(ah, sc->cur_chan->txpower, false);
 271	ath9k_cmn_update_txpow(ah, sc->cur_chan->cur_txpower,
 272			       sc->cur_chan->txpower,
 273			       &sc->cur_chan->cur_txpower);
 274	ath9k_ps_restore(sc);
 275}
 276
 277/*
 278 *  This function will allocate both the DMA descriptor structure, and the
 279 *  buffers it contains.  These are used to contain the descriptors used
 280 *  by the system.
 281*/
 282int ath_descdma_setup(struct ath_softc *sc, struct ath_descdma *dd,
 283		      struct list_head *head, const char *name,
 284		      int nbuf, int ndesc, bool is_tx)
 285{
 286	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 287	u8 *ds;
 288	int i, bsize, desc_len;
 289
 290	ath_dbg(common, CONFIG, "%s DMA: %u buffers %u desc/buf\n",
 291		name, nbuf, ndesc);
 292
 293	INIT_LIST_HEAD(head);
 294
 295	if (is_tx)
 296		desc_len = sc->sc_ah->caps.tx_desc_len;
 297	else
 298		desc_len = sizeof(struct ath_desc);
 299
 300	/* ath_desc must be a multiple of DWORDs */
 301	if ((desc_len % 4) != 0) {
 302		ath_err(common, "ath_desc not DWORD aligned\n");
 303		BUG_ON((desc_len % 4) != 0);
 304		return -ENOMEM;
 305	}
 306
 307	dd->dd_desc_len = desc_len * nbuf * ndesc;
 308
 309	/*
 310	 * Need additional DMA memory because we can't use
 311	 * descriptors that cross the 4K page boundary. Assume
 312	 * one skipped descriptor per 4K page.
 313	 */
 314	if (!(sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_4KB_SPLITTRANS)) {
 315		u32 ndesc_skipped =
 316			ATH_DESC_4KB_BOUND_NUM_SKIPPED(dd->dd_desc_len);
 317		u32 dma_len;
 318
 319		while (ndesc_skipped) {
 320			dma_len = ndesc_skipped * desc_len;
 321			dd->dd_desc_len += dma_len;
 322
 323			ndesc_skipped = ATH_DESC_4KB_BOUND_NUM_SKIPPED(dma_len);
 324		}
 325	}
 326
 327	/* allocate descriptors */
 328	dd->dd_desc = dmam_alloc_coherent(sc->dev, dd->dd_desc_len,
 329					  &dd->dd_desc_paddr, GFP_KERNEL);
 330	if (!dd->dd_desc)
 331		return -ENOMEM;
 332
 333	ds = dd->dd_desc;
 334	ath_dbg(common, CONFIG, "%s DMA map: %p (%u) -> %llx (%u)\n",
 335		name, ds, (u32) dd->dd_desc_len,
 336		ito64(dd->dd_desc_paddr), /*XXX*/(u32) dd->dd_desc_len);
 337
 338	/* allocate buffers */
 339	if (is_tx) {
 340		struct ath_buf *bf;
 341
 342		bsize = sizeof(struct ath_buf) * nbuf;
 343		bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
 344		if (!bf)
 345			return -ENOMEM;
 346
 347		for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
 348			bf->bf_desc = ds;
 349			bf->bf_daddr = DS2PHYS(dd, ds);
 350
 351			if (!(sc->sc_ah->caps.hw_caps &
 352				  ATH9K_HW_CAP_4KB_SPLITTRANS)) {
 353				/*
 354				 * Skip descriptor addresses which can cause 4KB
 355				 * boundary crossing (addr + length) with a 32 dword
 356				 * descriptor fetch.
 357				 */
 358				while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
 359					BUG_ON((caddr_t) bf->bf_desc >=
 360						   ((caddr_t) dd->dd_desc +
 361						dd->dd_desc_len));
 362
 363					ds += (desc_len * ndesc);
 364					bf->bf_desc = ds;
 365					bf->bf_daddr = DS2PHYS(dd, ds);
 366				}
 367			}
 368			list_add_tail(&bf->list, head);
 369		}
 370	} else {
 371		struct ath_rxbuf *bf;
 372
 373		bsize = sizeof(struct ath_rxbuf) * nbuf;
 374		bf = devm_kzalloc(sc->dev, bsize, GFP_KERNEL);
 375		if (!bf)
 376			return -ENOMEM;
 377
 378		for (i = 0; i < nbuf; i++, bf++, ds += (desc_len * ndesc)) {
 379			bf->bf_desc = ds;
 380			bf->bf_daddr = DS2PHYS(dd, ds);
 381
 382			if (!(sc->sc_ah->caps.hw_caps &
 383				  ATH9K_HW_CAP_4KB_SPLITTRANS)) {
 384				/*
 385				 * Skip descriptor addresses which can cause 4KB
 386				 * boundary crossing (addr + length) with a 32 dword
 387				 * descriptor fetch.
 388				 */
 389				while (ATH_DESC_4KB_BOUND_CHECK(bf->bf_daddr)) {
 390					BUG_ON((caddr_t) bf->bf_desc >=
 391						   ((caddr_t) dd->dd_desc +
 392						dd->dd_desc_len));
 393
 394					ds += (desc_len * ndesc);
 395					bf->bf_desc = ds;
 396					bf->bf_daddr = DS2PHYS(dd, ds);
 397				}
 398			}
 399			list_add_tail(&bf->list, head);
 400		}
 401	}
 402	return 0;
 403}
 404
 405static int ath9k_init_queues(struct ath_softc *sc)
 406{
 407	int i = 0;
 408
 409	sc->beacon.beaconq = ath9k_hw_beaconq_setup(sc->sc_ah);
 410	sc->beacon.cabq = ath_txq_setup(sc, ATH9K_TX_QUEUE_CAB, 0);
 411	ath_cabq_update(sc);
 412
 413	sc->tx.uapsdq = ath_txq_setup(sc, ATH9K_TX_QUEUE_UAPSD, 0);
 414
 415	for (i = 0; i < IEEE80211_NUM_ACS; i++) {
 416		sc->tx.txq_map[i] = ath_txq_setup(sc, ATH9K_TX_QUEUE_DATA, i);
 417		sc->tx.txq_map[i]->mac80211_qnum = i;
 418	}
 419	return 0;
 420}
 421
 422static void ath9k_init_misc(struct ath_softc *sc)
 423{
 424	struct ath_common *common = ath9k_hw_common(sc->sc_ah);
 425	int i = 0;
 426
 427	timer_setup(&common->ani.timer, ath_ani_calibrate, 0);
 428
 429	common->last_rssi = ATH_RSSI_DUMMY_MARKER;
 430	eth_broadcast_addr(common->bssidmask);
 431	sc->beacon.slottime = 9;
 432
 433	for (i = 0; i < ARRAY_SIZE(sc->beacon.bslot); i++)
 434		sc->beacon.bslot[i] = NULL;
 435
 436	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
 437		sc->ant_comb.count = ATH_ANT_DIV_COMB_INIT_COUNT;
 438
 439	sc->spec_priv.ah = sc->sc_ah;
 440	sc->spec_priv.spec_config.enabled = 0;
 441	sc->spec_priv.spec_config.short_repeat = true;
 442	sc->spec_priv.spec_config.count = 8;
 443	sc->spec_priv.spec_config.endless = false;
 444	sc->spec_priv.spec_config.period = 0xFF;
 445	sc->spec_priv.spec_config.fft_period = 0xF;
 446}
 447
 448static void ath9k_init_pcoem_platform(struct ath_softc *sc)
 449{
 450	struct ath_hw *ah = sc->sc_ah;
 451	struct ath9k_hw_capabilities *pCap = &ah->caps;
 452	struct ath_common *common = ath9k_hw_common(ah);
 453
 454	if (!IS_ENABLED(CONFIG_ATH9K_PCOEM))
 455		return;
 456
 457	if (common->bus_ops->ath_bus_type != ATH_PCI)
 458		return;
 459
 460	if (sc->driver_data & (ATH9K_PCI_CUS198 |
 461			       ATH9K_PCI_CUS230)) {
 462		ah->config.xlna_gpio = 9;
 463		ah->config.xatten_margin_cfg = true;
 464		ah->config.alt_mingainidx = true;
 465		ah->config.ant_ctrl_comm2g_switch_enable = 0x000BBB88;
 466		sc->ant_comb.low_rssi_thresh = 20;
 467		sc->ant_comb.fast_div_bias = 3;
 468
 469		ath_info(common, "Set parameters for %s\n",
 470			 (sc->driver_data & ATH9K_PCI_CUS198) ?
 471			 "CUS198" : "CUS230");
 472	}
 473
 474	if (sc->driver_data & ATH9K_PCI_CUS217)
 475		ath_info(common, "CUS217 card detected\n");
 476
 477	if (sc->driver_data & ATH9K_PCI_CUS252)
 478		ath_info(common, "CUS252 card detected\n");
 479
 480	if (sc->driver_data & ATH9K_PCI_AR9565_1ANT)
 481		ath_info(common, "WB335 1-ANT card detected\n");
 482
 483	if (sc->driver_data & ATH9K_PCI_AR9565_2ANT)
 484		ath_info(common, "WB335 2-ANT card detected\n");
 485
 486	if (sc->driver_data & ATH9K_PCI_KILLER)
 487		ath_info(common, "Killer Wireless card detected\n");
 488
 489	/*
 490	 * Some WB335 cards do not support antenna diversity. Since
 491	 * we use a hardcoded value for AR9565 instead of using the
 492	 * EEPROM/OTP data, remove the combining feature from
 493	 * the HW capabilities bitmap.
 494	 */
 495	if (sc->driver_data & (ATH9K_PCI_AR9565_1ANT | ATH9K_PCI_AR9565_2ANT)) {
 496		if (!(sc->driver_data & ATH9K_PCI_BT_ANT_DIV))
 497			pCap->hw_caps &= ~ATH9K_HW_CAP_ANT_DIV_COMB;
 498	}
 499
 500	if (sc->driver_data & ATH9K_PCI_BT_ANT_DIV) {
 501		pCap->hw_caps |= ATH9K_HW_CAP_BT_ANT_DIV;
 502		ath_info(common, "Set BT/WLAN RX diversity capability\n");
 503	}
 504
 505	if (sc->driver_data & ATH9K_PCI_D3_L1_WAR) {
 506		ah->config.pcie_waen = 0x0040473b;
 507		ath_info(common, "Enable WAR for ASPM D3/L1\n");
 508	}
 509
 510	/*
 511	 * The default value of pll_pwrsave is 1.
 512	 * For certain AR9485 cards, it is set to 0.
 513	 * For AR9462, AR9565 it's set to 7.
 514	 */
 515	ah->config.pll_pwrsave = 1;
 516
 517	if (sc->driver_data & ATH9K_PCI_NO_PLL_PWRSAVE) {
 518		ah->config.pll_pwrsave = 0;
 519		ath_info(common, "Disable PLL PowerSave\n");
 520	}
 521
 522	if (sc->driver_data & ATH9K_PCI_LED_ACT_HI)
 523		ah->config.led_active_high = true;
 524}
 525
 526static void ath9k_eeprom_request_cb(const struct firmware *eeprom_blob,
 527				    void *ctx)
 528{
 529	struct ath9k_eeprom_ctx *ec = ctx;
 530
 531	if (eeprom_blob)
 532		ec->ah->eeprom_blob = eeprom_blob;
 533
 534	complete(&ec->complete);
 535}
 536
 537static int ath9k_eeprom_request(struct ath_softc *sc, const char *name)
 538{
 539	struct ath9k_eeprom_ctx ec;
 540	struct ath_hw *ah = sc->sc_ah;
 541	int err;
 542
 543	/* try to load the EEPROM content asynchronously */
 544	init_completion(&ec.complete);
 545	ec.ah = sc->sc_ah;
 546
 547	err = request_firmware_nowait(THIS_MODULE, 1, name, sc->dev, GFP_KERNEL,
 548				      &ec, ath9k_eeprom_request_cb);
 549	if (err < 0) {
 550		ath_err(ath9k_hw_common(ah),
 551			"EEPROM request failed\n");
 552		return err;
 553	}
 554
 555	wait_for_completion(&ec.complete);
 556
 557	if (!ah->eeprom_blob) {
 558		ath_err(ath9k_hw_common(ah),
 559			"Unable to load EEPROM file %s\n", name);
 560		return -EINVAL;
 561	}
 562
 563	return 0;
 564}
 565
 566static void ath9k_eeprom_release(struct ath_softc *sc)
 567{
 568	release_firmware(sc->sc_ah->eeprom_blob);
 569}
 570
 571static int ath9k_nvmem_request_eeprom(struct ath_softc *sc)
 572{
 573	struct ath_hw *ah = sc->sc_ah;
 574	struct nvmem_cell *cell;
 575	void *buf;
 576	size_t len;
 577	int err;
 578
 579	cell = devm_nvmem_cell_get(sc->dev, "calibration");
 580	if (IS_ERR(cell)) {
 581		err = PTR_ERR(cell);
 582
 583		/* nvmem cell might not be defined, or the nvmem
 584		 * subsystem isn't included. In this case, follow
 585		 * the established "just return 0;" convention
 586		 * to say:
 587		 * "All good. Nothing to see here. Please go on."
 588		 */
 589		if (err == -ENOENT || err == -EOPNOTSUPP)
 590			return 0;
 591
 592		return err;
 593	}
 594
 595	buf = nvmem_cell_read(cell, &len);
 596	if (IS_ERR(buf))
 597		return PTR_ERR(buf);
 598
 599	/* run basic sanity checks on the returned nvram cell length.
 600	 * That length has to be a multiple of a "u16" (i.e.: & 1).
 601	 * Furthermore, it has to be more than "let's say" 512 bytes
 602	 * but less than the maximum of AR9300_EEPROM_SIZE (16kb).
 603	 */
 604	if ((len & 1) == 1 || len < 512 || len >= AR9300_EEPROM_SIZE) {
 605		kfree(buf);
 606		return -EINVAL;
 607	}
 608
 609	/* devres manages the calibration values release on shutdown */
 610	ah->nvmem_blob = devm_kmemdup(sc->dev, buf, len, GFP_KERNEL);
 611	kfree(buf);
 612	if (!ah->nvmem_blob)
 613		return -ENOMEM;
 614
 615	ah->nvmem_blob_len = len;
 616	ah->ah_flags &= ~AH_USE_EEPROM;
 617	ah->ah_flags |= AH_NO_EEP_SWAP;
 618
 619	return 0;
 620}
 621
 622static int ath9k_of_init(struct ath_softc *sc)
 623{
 624	struct device_node *np = sc->dev->of_node;
 625	struct ath_hw *ah = sc->sc_ah;
 626	struct ath_common *common = ath9k_hw_common(ah);
 627	enum ath_bus_type bus_type = common->bus_ops->ath_bus_type;
 628	char eeprom_name[100];
 629	int ret;
 630
 631	if (!of_device_is_available(np))
 632		return 0;
 633
 634	ath_dbg(common, CONFIG, "parsing configuration from OF node\n");
 635
 636	if (of_property_read_bool(np, "qca,no-eeprom")) {
 637		/* ath9k-eeprom-<bus>-<id>.bin */
 638		scnprintf(eeprom_name, sizeof(eeprom_name),
 639			  "ath9k-eeprom-%s-%s.bin",
 640			  ath_bus_type_to_string(bus_type), dev_name(ah->dev));
 641
 642		ret = ath9k_eeprom_request(sc, eeprom_name);
 643		if (ret)
 644			return ret;
 645
 646		ah->ah_flags &= ~AH_USE_EEPROM;
 647		ah->ah_flags |= AH_NO_EEP_SWAP;
 648	}
 649
 650	ret = of_get_mac_address(np, common->macaddr);
 651	if (ret == -EPROBE_DEFER)
 652		return ret;
 653
 654	return 0;
 655}
 656
 657static int ath9k_init_softc(u16 devid, struct ath_softc *sc,
 658			    const struct ath_bus_ops *bus_ops)
 659{
 660	struct ath_hw *ah = NULL;
 661	struct ath9k_hw_capabilities *pCap;
 662	struct ath_common *common;
 663	int ret = 0, i;
 664	int csz = 0;
 665
 666	ah = devm_kzalloc(sc->dev, sizeof(struct ath_hw), GFP_KERNEL);
 667	if (!ah)
 668		return -ENOMEM;
 669
 670	ah->dev = sc->dev;
 671	ah->hw = sc->hw;
 672	ah->hw_version.devid = devid;
 673	ah->ah_flags |= AH_USE_EEPROM;
 674	ah->led_pin = -1;
 675	ah->reg_ops.read = ath9k_ioread32;
 676	ah->reg_ops.multi_read = ath9k_multi_ioread32;
 677	ah->reg_ops.write = ath9k_iowrite32;
 678	ah->reg_ops.rmw = ath9k_reg_rmw;
 679	pCap = &ah->caps;
 680
 681	common = ath9k_hw_common(ah);
 682
 683	/* Will be cleared in ath9k_start() */
 684	set_bit(ATH_OP_INVALID, &common->op_flags);
 685
 686	sc->sc_ah = ah;
 687	sc->dfs_detector = dfs_pattern_detector_init(common, NL80211_DFS_UNSET);
 688	sc->tx99_power = MAX_RATE_POWER + 1;
 689	init_waitqueue_head(&sc->tx_wait);
 690	sc->cur_chan = &sc->chanctx[0];
 691	if (!ath9k_is_chanctx_enabled())
 692		sc->cur_chan->hw_queue_base = 0;
 693
 694	common->ops = &ah->reg_ops;
 695	common->bus_ops = bus_ops;
 696	common->ps_ops = &ath9k_ps_ops;
 697	common->ah = ah;
 698	common->hw = sc->hw;
 699	common->priv = sc;
 700	common->debug_mask = ath9k_debug;
 701	common->btcoex_enabled = ath9k_btcoex_enable == 1;
 702	common->disable_ani = false;
 703
 704	/*
 705	 * Platform quirks.
 706	 */
 707	ath9k_init_pcoem_platform(sc);
 708
 709	ret = ath9k_of_init(sc);
 710	if (ret)
 711		return ret;
 712
 713	ret = ath9k_nvmem_request_eeprom(sc);
 714	if (ret)
 715		return ret;
 716
 717	if (ath9k_led_active_high != -1)
 718		ah->config.led_active_high = ath9k_led_active_high == 1;
 719
 720	/*
 721	 * Enable WLAN/BT RX Antenna diversity only when:
 722	 *
 723	 * - BTCOEX is disabled.
 724	 * - the user manually requests the feature.
 725	 * - the HW cap is set using the platform data.
 726	 */
 727	if (!common->btcoex_enabled && ath9k_bt_ant_diversity &&
 728	    (pCap->hw_caps & ATH9K_HW_CAP_BT_ANT_DIV))
 729		common->bt_ant_diversity = 1;
 730
 731	spin_lock_init(&common->cc_lock);
 732	spin_lock_init(&sc->intr_lock);
 733	spin_lock_init(&sc->sc_serial_rw);
 734	spin_lock_init(&sc->sc_pm_lock);
 735	spin_lock_init(&sc->chan_lock);
 736	mutex_init(&sc->mutex);
 737	tasklet_setup(&sc->intr_tq, ath9k_tasklet);
 738	tasklet_setup(&sc->bcon_tasklet, ath9k_beacon_tasklet);
 739
 740	timer_setup(&sc->sleep_timer, ath_ps_full_sleep, 0);
 741	INIT_WORK(&sc->hw_reset_work, ath_reset_work);
 742	INIT_WORK(&sc->paprd_work, ath_paprd_calibrate);
 743	INIT_DELAYED_WORK(&sc->hw_pll_work, ath_hw_pll_work);
 744	INIT_DELAYED_WORK(&sc->hw_check_work, ath_hw_check_work);
 745
 746	ath9k_init_channel_context(sc);
 747
 748	/*
 749	 * Cache line size is used to size and align various
 750	 * structures used to communicate with the hardware.
 751	 */
 752	ath_read_cachesize(common, &csz);
 753	common->cachelsz = csz << 2; /* convert to bytes */
 754
 755	/* Initializes the hardware for all supported chipsets */
 756	ret = ath9k_hw_init(ah);
 757	if (ret)
 758		goto err_hw;
 759
 760	ret = ath9k_init_queues(sc);
 761	if (ret)
 762		goto err_queues;
 763
 764	ret =  ath9k_init_btcoex(sc);
 765	if (ret)
 766		goto err_btcoex;
 767
 768	ret = ath9k_cmn_init_channels_rates(common);
 769	if (ret)
 770		goto err_btcoex;
 771
 772	ret = ath9k_init_p2p(sc);
 773	if (ret)
 774		goto err_btcoex;
 775
 776	ath9k_cmn_init_crypto(sc->sc_ah);
 777	ath9k_init_misc(sc);
 778	ath_chanctx_init(sc);
 779	ath9k_offchannel_init(sc);
 780
 781	if (common->bus_ops->aspm_init)
 782		common->bus_ops->aspm_init(common);
 783
 784	return 0;
 785
 786err_btcoex:
 787	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
 788		if (ATH_TXQ_SETUP(sc, i))
 789			ath_tx_cleanupq(sc, &sc->tx.txq[i]);
 790err_queues:
 791	ath9k_hw_deinit(ah);
 792err_hw:
 793	ath9k_eeprom_release(sc);
 794	dev_kfree_skb_any(sc->tx99_skb);
 795	return ret;
 796}
 797
 798static void ath9k_init_band_txpower(struct ath_softc *sc, int band)
 799{
 800	struct ieee80211_supported_band *sband;
 801	struct ieee80211_channel *chan;
 802	struct ath_hw *ah = sc->sc_ah;
 803	struct ath_common *common = ath9k_hw_common(ah);
 804	struct cfg80211_chan_def chandef;
 805	int i;
 806
 807	sband = &common->sbands[band];
 808	for (i = 0; i < sband->n_channels; i++) {
 809		chan = &sband->channels[i];
 810		ah->curchan = &ah->channels[chan->hw_value];
 811		cfg80211_chandef_create(&chandef, chan, NL80211_CHAN_HT20);
 812		ath9k_cmn_get_channel(sc->hw, ah, &chandef);
 813		ath9k_hw_set_txpowerlimit(ah, MAX_COMBINED_POWER, true);
 814	}
 815}
 816
 817static void ath9k_init_txpower_limits(struct ath_softc *sc)
 818{
 819	struct ath_hw *ah = sc->sc_ah;
 820	struct ath9k_channel *curchan = ah->curchan;
 821
 822	if (ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
 823		ath9k_init_band_txpower(sc, NL80211_BAND_2GHZ);
 824	if (ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
 825		ath9k_init_band_txpower(sc, NL80211_BAND_5GHZ);
 826
 827	ah->curchan = curchan;
 828}
 829
 830static const struct ieee80211_iface_limit if_limits[] = {
 831	{ .max = 2048,	.types = BIT(NL80211_IFTYPE_STATION) },
 832	{ .max = 8,	.types =
 833#ifdef CONFIG_MAC80211_MESH
 834				 BIT(NL80211_IFTYPE_MESH_POINT) |
 835#endif
 836				 BIT(NL80211_IFTYPE_AP) },
 837	{ .max = 1,	.types = BIT(NL80211_IFTYPE_P2P_CLIENT) |
 838				 BIT(NL80211_IFTYPE_P2P_GO) },
 839};
 840
 841#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
 842
 843static const struct ieee80211_iface_limit if_limits_multi[] = {
 844	{ .max = 2,	.types = BIT(NL80211_IFTYPE_STATION) |
 845				 BIT(NL80211_IFTYPE_AP) |
 846				 BIT(NL80211_IFTYPE_P2P_CLIENT) |
 847				 BIT(NL80211_IFTYPE_P2P_GO) },
 848	{ .max = 1,	.types = BIT(NL80211_IFTYPE_ADHOC) },
 849	{ .max = 1,	.types = BIT(NL80211_IFTYPE_P2P_DEVICE) },
 850};
 851
 852static const struct ieee80211_iface_combination if_comb_multi[] = {
 853	{
 854		.limits = if_limits_multi,
 855		.n_limits = ARRAY_SIZE(if_limits_multi),
 856		.max_interfaces = 3,
 857		.num_different_channels = 2,
 858		.beacon_int_infra_match = true,
 859	},
 860};
 861
 862#endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
 863
 864static const struct ieee80211_iface_combination if_comb[] = {
 865	{
 866		.limits = if_limits,
 867		.n_limits = ARRAY_SIZE(if_limits),
 868		.max_interfaces = 2048,
 869		.num_different_channels = 1,
 870		.beacon_int_infra_match = true,
 871#ifdef CONFIG_ATH9K_DFS_CERTIFIED
 872		.radar_detect_widths =	BIT(NL80211_CHAN_WIDTH_20_NOHT) |
 873					BIT(NL80211_CHAN_WIDTH_20) |
 874					BIT(NL80211_CHAN_WIDTH_40),
 875#endif
 876	},
 877};
 878
 879#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
 880static void ath9k_set_mcc_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
 881{
 882	struct ath_hw *ah = sc->sc_ah;
 883	struct ath_common *common = ath9k_hw_common(ah);
 884
 885	if (!ath9k_is_chanctx_enabled())
 886		return;
 887
 888	ieee80211_hw_set(hw, QUEUE_CONTROL);
 889	hw->queues = ATH9K_NUM_TX_QUEUES;
 890	hw->offchannel_tx_hw_queue = hw->queues - 1;
 891	hw->wiphy->iface_combinations = if_comb_multi;
 892	hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb_multi);
 893	hw->wiphy->max_scan_ssids = 255;
 894	hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
 895	hw->wiphy->max_remain_on_channel_duration = 10000;
 896	hw->chanctx_data_size = sizeof(void *);
 897	hw->extra_beacon_tailroom =
 898		sizeof(struct ieee80211_p2p_noa_attr) + 9;
 899
 900	ath_dbg(common, CHAN_CTX, "Use channel contexts\n");
 901}
 902#endif /* CONFIG_ATH9K_CHANNEL_CONTEXT */
 903
 904static void ath9k_set_hw_capab(struct ath_softc *sc, struct ieee80211_hw *hw)
 905{
 906	struct ath_hw *ah = sc->sc_ah;
 907	struct ath_common *common = ath9k_hw_common(ah);
 908
 909	ieee80211_hw_set(hw, SUPPORTS_HT_CCK_RATES);
 910	ieee80211_hw_set(hw, SUPPORTS_RC_TABLE);
 911	ieee80211_hw_set(hw, REPORTS_TX_ACK_STATUS);
 912	ieee80211_hw_set(hw, SPECTRUM_MGMT);
 913	ieee80211_hw_set(hw, PS_NULLFUNC_STACK);
 914	ieee80211_hw_set(hw, SIGNAL_DBM);
 915	ieee80211_hw_set(hw, RX_INCLUDES_FCS);
 916	ieee80211_hw_set(hw, HOST_BROADCAST_PS_BUFFERING);
 917	ieee80211_hw_set(hw, SUPPORT_FAST_XMIT);
 918	ieee80211_hw_set(hw, SUPPORTS_CLONED_SKBS);
 919
 920	if (ath9k_ps_enable)
 921		ieee80211_hw_set(hw, SUPPORTS_PS);
 922
 923	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_HT) {
 924		ieee80211_hw_set(hw, AMPDU_AGGREGATION);
 925
 926		if (AR_SREV_9280_20_OR_LATER(ah))
 927			hw->radiotap_mcs_details |=
 928				IEEE80211_RADIOTAP_MCS_HAVE_STBC;
 929	}
 930
 931	if (AR_SREV_9160_10_OR_LATER(sc->sc_ah) || ath9k_modparam_nohwcrypt)
 932		ieee80211_hw_set(hw, MFP_CAPABLE);
 933
 934	hw->wiphy->features |= NL80211_FEATURE_ACTIVE_MONITOR |
 935			       NL80211_FEATURE_AP_MODE_CHAN_WIDTH_CHANGE |
 936			       NL80211_FEATURE_P2P_GO_CTWIN;
 937
 938	if (!IS_ENABLED(CONFIG_ATH9K_TX99)) {
 939		hw->wiphy->interface_modes =
 940			BIT(NL80211_IFTYPE_P2P_GO) |
 941			BIT(NL80211_IFTYPE_P2P_CLIENT) |
 942			BIT(NL80211_IFTYPE_AP) |
 943			BIT(NL80211_IFTYPE_STATION) |
 944			BIT(NL80211_IFTYPE_ADHOC) |
 945			BIT(NL80211_IFTYPE_MESH_POINT) |
 946			BIT(NL80211_IFTYPE_OCB);
 947
 948		if (ath9k_is_chanctx_enabled())
 949			hw->wiphy->interface_modes |=
 950					BIT(NL80211_IFTYPE_P2P_DEVICE);
 951
 952		hw->wiphy->iface_combinations = if_comb;
 953		hw->wiphy->n_iface_combinations = ARRAY_SIZE(if_comb);
 954	}
 955
 956	hw->wiphy->flags &= ~WIPHY_FLAG_PS_ON_BY_DEFAULT;
 957
 958	hw->wiphy->flags |= WIPHY_FLAG_IBSS_RSN;
 959	hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_TDLS;
 960	hw->wiphy->flags |= WIPHY_FLAG_HAS_REMAIN_ON_CHANNEL;
 961	hw->wiphy->flags |= WIPHY_FLAG_SUPPORTS_5_10_MHZ;
 962	hw->wiphy->flags |= WIPHY_FLAG_HAS_CHANNEL_SWITCH;
 963	hw->wiphy->flags |= WIPHY_FLAG_AP_UAPSD;
 964
 965	hw->queues = 4;
 966	hw->max_rates = 4;
 967	hw->max_listen_interval = 10;
 968	hw->max_rate_tries = 10;
 969	hw->sta_data_size = sizeof(struct ath_node);
 970	hw->vif_data_size = sizeof(struct ath_vif);
 971	hw->txq_data_size = sizeof(struct ath_atx_tid);
 972	hw->extra_tx_headroom = 4;
 973
 974	hw->wiphy->available_antennas_rx = BIT(ah->caps.max_rxchains) - 1;
 975	hw->wiphy->available_antennas_tx = BIT(ah->caps.max_txchains) - 1;
 976
 977	/* single chain devices with rx diversity */
 978	if (ah->caps.hw_caps & ATH9K_HW_CAP_ANT_DIV_COMB)
 979		hw->wiphy->available_antennas_rx = BIT(0) | BIT(1);
 980
 981	sc->ant_rx = hw->wiphy->available_antennas_rx;
 982	sc->ant_tx = hw->wiphy->available_antennas_tx;
 983
 984	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_2GHZ)
 985		hw->wiphy->bands[NL80211_BAND_2GHZ] =
 986			&common->sbands[NL80211_BAND_2GHZ];
 987	if (sc->sc_ah->caps.hw_caps & ATH9K_HW_CAP_5GHZ)
 988		hw->wiphy->bands[NL80211_BAND_5GHZ] =
 989			&common->sbands[NL80211_BAND_5GHZ];
 990
 991#ifdef CONFIG_ATH9K_CHANNEL_CONTEXT
 992	ath9k_set_mcc_capab(sc, hw);
 993#endif
 994	ath9k_init_wow(hw);
 995	ath9k_cmn_reload_chainmask(ah);
 996
 997	SET_IEEE80211_PERM_ADDR(hw, common->macaddr);
 998
 999	wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CQM_RSSI_LIST);
1000	wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_AIRTIME_FAIRNESS);
1001	wiphy_ext_feature_set(hw->wiphy,
1002			      NL80211_EXT_FEATURE_MULTICAST_REGISTRATIONS);
1003	wiphy_ext_feature_set(hw->wiphy, NL80211_EXT_FEATURE_CAN_REPLACE_PTK0);
1004}
1005
1006int ath9k_init_device(u16 devid, struct ath_softc *sc,
1007		    const struct ath_bus_ops *bus_ops)
1008{
1009	struct ieee80211_hw *hw = sc->hw;
1010	struct ath_common *common;
1011	struct ath_hw *ah;
1012	int error = 0;
1013	struct ath_regulatory *reg;
1014
1015	/* Bring up device */
1016	error = ath9k_init_softc(devid, sc, bus_ops);
1017	if (error)
1018		return error;
1019
1020	ah = sc->sc_ah;
1021	common = ath9k_hw_common(ah);
1022	ath9k_set_hw_capab(sc, hw);
1023
1024	/* Initialize regulatory */
1025	error = ath_regd_init(&common->regulatory, sc->hw->wiphy,
1026			      ath9k_reg_notifier);
1027	if (error)
1028		goto deinit;
1029
1030	reg = &common->regulatory;
1031
1032	/* Setup TX DMA */
1033	error = ath_tx_init(sc, ATH_TXBUF);
1034	if (error != 0)
1035		goto deinit;
1036
1037	/* Setup RX DMA */
1038	error = ath_rx_init(sc, ATH_RXBUF);
1039	if (error != 0)
1040		goto deinit;
1041
1042	ath9k_init_txpower_limits(sc);
1043
1044#ifdef CONFIG_MAC80211_LEDS
1045	/* must be initialized before ieee80211_register_hw */
1046	sc->led_cdev.default_trigger = ieee80211_create_tpt_led_trigger(sc->hw,
1047		IEEE80211_TPT_LEDTRIG_FL_RADIO, ath9k_tpt_blink,
1048		ARRAY_SIZE(ath9k_tpt_blink));
1049#endif
1050
1051	wiphy_read_of_freq_limits(hw->wiphy);
1052
1053	/* Register with mac80211 */
1054	error = ieee80211_register_hw(hw);
1055	if (error)
1056		goto rx_cleanup;
1057
1058	error = ath9k_init_debug(ah);
1059	if (error) {
1060		ath_err(common, "Unable to create debugfs files\n");
1061		goto unregister;
1062	}
1063
1064	/* Handle world regulatory */
1065	if (!ath_is_world_regd(reg)) {
1066		error = regulatory_hint(hw->wiphy, reg->alpha2);
1067		if (error)
1068			goto debug_cleanup;
1069	}
1070
1071	ath_init_leds(sc);
1072	ath_start_rfkill_poll(sc);
1073
1074	return 0;
1075
1076debug_cleanup:
1077	ath9k_deinit_debug(sc);
1078unregister:
1079	ieee80211_unregister_hw(hw);
1080rx_cleanup:
1081	ath_rx_cleanup(sc);
1082deinit:
1083	ath9k_deinit_softc(sc);
1084	return error;
1085}
1086
1087/*****************************/
1088/*     De-Initialization     */
1089/*****************************/
1090
1091static void ath9k_deinit_softc(struct ath_softc *sc)
1092{
1093	int i = 0;
1094
1095	ath9k_deinit_p2p(sc);
1096	ath9k_deinit_btcoex(sc);
1097
1098	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1099		if (ATH_TXQ_SETUP(sc, i))
1100			ath_tx_cleanupq(sc, &sc->tx.txq[i]);
1101
1102	timer_delete_sync(&sc->sleep_timer);
1103	ath9k_hw_deinit(sc->sc_ah);
1104	if (sc->dfs_detector != NULL)
1105		sc->dfs_detector->exit(sc->dfs_detector);
1106
1107	ath9k_eeprom_release(sc);
1108}
1109
1110void ath9k_deinit_device(struct ath_softc *sc)
1111{
1112	struct ieee80211_hw *hw = sc->hw;
1113
1114	ath9k_ps_wakeup(sc);
1115
1116	wiphy_rfkill_stop_polling(sc->hw->wiphy);
1117	ath_deinit_leds(sc);
1118
1119	ath9k_ps_restore(sc);
1120
1121	ath9k_deinit_debug(sc);
1122	ath9k_deinit_wow(hw);
1123	ieee80211_unregister_hw(hw);
1124	ath_rx_cleanup(sc);
1125	ath9k_deinit_softc(sc);
1126}
1127
1128/************************/
1129/*     Module Hooks     */
1130/************************/
1131
1132static int __init ath9k_init(void)
1133{
1134	int error;
1135
1136	error = ath_pci_init();
1137	if (error < 0) {
1138		pr_err("No PCI devices found, driver not installed\n");
1139		error = -ENODEV;
1140		goto err_out;
1141	}
1142
1143	error = ath_ahb_init();
1144	if (error < 0) {
1145		error = -ENODEV;
1146		goto err_pci_exit;
1147	}
1148
1149	dmi_check_system(ath9k_quirks);
1150
1151	return 0;
1152
1153 err_pci_exit:
1154	ath_pci_exit();
1155 err_out:
1156	return error;
1157}
1158module_init(ath9k_init);
1159
1160static void __exit ath9k_exit(void)
1161{
1162	is_ath9k_unloaded = true;
1163	ath_ahb_exit();
1164	ath_pci_exit();
1165	pr_info("%s: Driver unloaded\n", dev_info);
1166}
1167module_exit(ath9k_exit);