hw.c

   1/*
   2 * Copyright (c) 2008-2011 Atheros Communications Inc.
   3 *
   4 * Permission to use, copy, modify, and/or distribute this software for any
   5 * purpose with or without fee is hereby granted, provided that the above
   6 * copyright notice and this permission notice appear in all copies.
   7 *
   8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
   9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15 */
  16
  17#include <linux/export.h>
  18#include <linux/io.h>
  19#include <linux/slab.h>
  20#include <linux/module.h>
  21#include <linux/time.h>
  22#include <linux/bitops.h>
  23#include <linux/etherdevice.h>
  24#include <linux/gpio.h>
  25#include <linux/unaligned.h>
  26
  27#include "hw.h"
  28#include "hw-ops.h"
  29#include "ar9003_mac.h"
  30#include "ar9003_mci.h"
  31#include "ar9003_phy.h"
  32#include "ath9k.h"
  33
  34static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type);
  35
  36MODULE_AUTHOR("Atheros Communications");
  37MODULE_DESCRIPTION("Support for Atheros 802.11n wireless LAN cards.");
  38MODULE_LICENSE("Dual BSD/GPL");
  39
  40static void ath9k_hw_set_clockrate(struct ath_hw *ah)
  41{
  42	struct ath_common *common = ath9k_hw_common(ah);
  43	struct ath9k_channel *chan = ah->curchan;
  44	unsigned int clockrate;
  45
  46	/* AR9287 v1.3+ uses async FIFO and runs the MAC at 117 MHz */
  47	if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah))
  48		clockrate = 117;
  49	else if (!chan) /* should really check for CCK instead */
  50		clockrate = ATH9K_CLOCK_RATE_CCK;
  51	else if (IS_CHAN_2GHZ(chan))
  52		clockrate = ATH9K_CLOCK_RATE_2GHZ_OFDM;
  53	else if (ah->caps.hw_caps & ATH9K_HW_CAP_FASTCLOCK)
  54		clockrate = ATH9K_CLOCK_FAST_RATE_5GHZ_OFDM;
  55	else
  56		clockrate = ATH9K_CLOCK_RATE_5GHZ_OFDM;
  57
  58	if (chan) {
  59		if (IS_CHAN_HT40(chan))
  60			clockrate *= 2;
  61		if (IS_CHAN_HALF_RATE(chan))
  62			clockrate /= 2;
  63		if (IS_CHAN_QUARTER_RATE(chan))
  64			clockrate /= 4;
  65	}
  66
  67	common->clockrate = clockrate;
  68}
  69
  70static u32 ath9k_hw_mac_to_clks(struct ath_hw *ah, u32 usecs)
  71{
  72	struct ath_common *common = ath9k_hw_common(ah);
  73
  74	return usecs * common->clockrate;
  75}
  76
  77bool ath9k_hw_wait(struct ath_hw *ah, u32 reg, u32 mask, u32 val, u32 timeout)
  78{
  79	int i;
  80
  81	BUG_ON(timeout < AH_TIME_QUANTUM);
  82
  83	for (i = 0; i < (timeout / AH_TIME_QUANTUM); i++) {
  84		if ((REG_READ(ah, reg) & mask) == val)
  85			return true;
  86
  87		udelay(AH_TIME_QUANTUM);
  88	}
  89
  90	ath_dbg(ath9k_hw_common(ah), ANY,
  91		"timeout (%d us) on reg 0x%x: 0x%08x & 0x%08x != 0x%08x\n",
  92		timeout, reg, REG_READ(ah, reg), mask, val);
  93
  94	return false;
  95}
  96EXPORT_SYMBOL(ath9k_hw_wait);
  97
  98void ath9k_hw_synth_delay(struct ath_hw *ah, struct ath9k_channel *chan,
  99			  int hw_delay)
 100{
 101	hw_delay /= 10;
 102
 103	if (IS_CHAN_HALF_RATE(chan))
 104		hw_delay *= 2;
 105	else if (IS_CHAN_QUARTER_RATE(chan))
 106		hw_delay *= 4;
 107
 108	udelay(hw_delay + BASE_ACTIVATE_DELAY);
 109}
 110
 111void ath9k_hw_write_array(struct ath_hw *ah, const struct ar5416IniArray *array,
 112			  int column, unsigned int *writecnt)
 113{
 114	int r;
 115
 116	ENABLE_REGWRITE_BUFFER(ah);
 117	for (r = 0; r < array->ia_rows; r++) {
 118		REG_WRITE(ah, INI_RA(array, r, 0),
 119			  INI_RA(array, r, column));
 120		DO_DELAY(*writecnt);
 121	}
 122	REGWRITE_BUFFER_FLUSH(ah);
 123}
 124
 125void ath9k_hw_read_array(struct ath_hw *ah, u32 array[][2], int size)
 126{
 127	u32 *tmp_reg_list, *tmp_data;
 128	int i;
 129
 130	tmp_reg_list = kmalloc_array(size, sizeof(u32), GFP_KERNEL);
 131	if (!tmp_reg_list) {
 132		dev_err(ah->dev, "%s: tmp_reg_list: alloc filed\n", __func__);
 133		return;
 134	}
 135
 136	tmp_data = kmalloc_array(size, sizeof(u32), GFP_KERNEL);
 137	if (!tmp_data) {
 138		dev_err(ah->dev, "%s tmp_data: alloc filed\n", __func__);
 139		goto error_tmp_data;
 140	}
 141
 142	for (i = 0; i < size; i++)
 143		tmp_reg_list[i] = array[i][0];
 144
 145	REG_READ_MULTI(ah, tmp_reg_list, tmp_data, size);
 146
 147	for (i = 0; i < size; i++)
 148		array[i][1] = tmp_data[i];
 149
 150	kfree(tmp_data);
 151error_tmp_data:
 152	kfree(tmp_reg_list);
 153}
 154
 155u32 ath9k_hw_reverse_bits(u32 val, u32 n)
 156{
 157	u32 retval;
 158	int i;
 159
 160	for (i = 0, retval = 0; i < n; i++) {
 161		retval = (retval << 1) | (val & 1);
 162		val >>= 1;
 163	}
 164	return retval;
 165}
 166
 167u16 ath9k_hw_computetxtime(struct ath_hw *ah,
 168			   u8 phy, int kbps,
 169			   u32 frameLen, u16 rateix,
 170			   bool shortPreamble)
 171{
 172	u32 bitsPerSymbol, numBits, numSymbols, phyTime, txTime;
 173
 174	if (kbps == 0)
 175		return 0;
 176
 177	switch (phy) {
 178	case WLAN_RC_PHY_CCK:
 179		phyTime = CCK_PREAMBLE_BITS + CCK_PLCP_BITS;
 180		if (shortPreamble)
 181			phyTime >>= 1;
 182		numBits = frameLen << 3;
 183		txTime = CCK_SIFS_TIME + phyTime + ((numBits * 1000) / kbps);
 184		break;
 185	case WLAN_RC_PHY_OFDM:
 186		if (ah->curchan && IS_CHAN_QUARTER_RATE(ah->curchan)) {
 187			bitsPerSymbol =
 188				((kbps >> 2) * OFDM_SYMBOL_TIME_QUARTER) / 1000;
 189			numBits = OFDM_PLCP_BITS + (frameLen << 3);
 190			numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 191			txTime = OFDM_SIFS_TIME_QUARTER
 192				+ OFDM_PREAMBLE_TIME_QUARTER
 193				+ (numSymbols * OFDM_SYMBOL_TIME_QUARTER);
 194		} else if (ah->curchan &&
 195			   IS_CHAN_HALF_RATE(ah->curchan)) {
 196			bitsPerSymbol =
 197				((kbps >> 1) * OFDM_SYMBOL_TIME_HALF) / 1000;
 198			numBits = OFDM_PLCP_BITS + (frameLen << 3);
 199			numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 200			txTime = OFDM_SIFS_TIME_HALF +
 201				OFDM_PREAMBLE_TIME_HALF
 202				+ (numSymbols * OFDM_SYMBOL_TIME_HALF);
 203		} else {
 204			bitsPerSymbol = (kbps * OFDM_SYMBOL_TIME) / 1000;
 205			numBits = OFDM_PLCP_BITS + (frameLen << 3);
 206			numSymbols = DIV_ROUND_UP(numBits, bitsPerSymbol);
 207			txTime = OFDM_SIFS_TIME + OFDM_PREAMBLE_TIME
 208				+ (numSymbols * OFDM_SYMBOL_TIME);
 209		}
 210		break;
 211	default:
 212		ath_err(ath9k_hw_common(ah),
 213			"Unknown phy %u (rate ix %u)\n", phy, rateix);
 214		txTime = 0;
 215		break;
 216	}
 217
 218	return txTime;
 219}
 220EXPORT_SYMBOL(ath9k_hw_computetxtime);
 221
 222void ath9k_hw_get_channel_centers(struct ath_hw *ah,
 223				  struct ath9k_channel *chan,
 224				  struct chan_centers *centers)
 225{
 226	int8_t extoff;
 227
 228	if (!IS_CHAN_HT40(chan)) {
 229		centers->ctl_center = centers->ext_center =
 230			centers->synth_center = chan->channel;
 231		return;
 232	}
 233
 234	if (IS_CHAN_HT40PLUS(chan)) {
 235		centers->synth_center =
 236			chan->channel + HT40_CHANNEL_CENTER_SHIFT;
 237		extoff = 1;
 238	} else {
 239		centers->synth_center =
 240			chan->channel - HT40_CHANNEL_CENTER_SHIFT;
 241		extoff = -1;
 242	}
 243
 244	centers->ctl_center =
 245		centers->synth_center - (extoff * HT40_CHANNEL_CENTER_SHIFT);
 246	/* 25 MHz spacing is supported by hw but not on upper layers */
 247	centers->ext_center =
 248		centers->synth_center + (extoff * HT40_CHANNEL_CENTER_SHIFT);
 249}
 250
 251/******************/
 252/* Chip Revisions */
 253/******************/
 254
 255static bool ath9k_hw_read_revisions(struct ath_hw *ah)
 256{
 257	u32 srev;
 258	u32 val;
 259
 260	if (ah->get_mac_revision)
 261		ah->hw_version.macRev = ah->get_mac_revision();
 262
 263	switch (ah->hw_version.devid) {
 264	case AR5416_AR9100_DEVID:
 265		ah->hw_version.macVersion = AR_SREV_VERSION_9100;
 266		break;
 267	case AR9300_DEVID_AR9330:
 268		ah->hw_version.macVersion = AR_SREV_VERSION_9330;
 269		if (!ah->get_mac_revision) {
 270			val = REG_READ(ah, AR_SREV(ah));
 271			ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 272		}
 273		return true;
 274	case AR9300_DEVID_AR9340:
 275		ah->hw_version.macVersion = AR_SREV_VERSION_9340;
 276		return true;
 277	case AR9300_DEVID_QCA955X:
 278		ah->hw_version.macVersion = AR_SREV_VERSION_9550;
 279		return true;
 280	case AR9300_DEVID_AR953X:
 281		ah->hw_version.macVersion = AR_SREV_VERSION_9531;
 282		return true;
 283	case AR9300_DEVID_QCA956X:
 284		ah->hw_version.macVersion = AR_SREV_VERSION_9561;
 285		return true;
 286	}
 287
 288	srev = REG_READ(ah, AR_SREV(ah));
 289
 290	if (srev == -1) {
 291		ath_err(ath9k_hw_common(ah),
 292			"Failed to read SREV register");
 293		return false;
 294	}
 295
 296	val = srev & AR_SREV_ID(ah);
 297
 298	if (val == 0xFF) {
 299		val = srev;
 300		ah->hw_version.macVersion =
 301			(val & AR_SREV_VERSION2) >> AR_SREV_TYPE2_S;
 302		ah->hw_version.macRev = MS(val, AR_SREV_REVISION2);
 303
 304		if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
 305			ah->is_pciexpress = true;
 306		else
 307			ah->is_pciexpress = (val &
 308					     AR_SREV_TYPE2_HOST_MODE) ? 0 : 1;
 309	} else {
 310		if (!AR_SREV_9100(ah))
 311			ah->hw_version.macVersion = MS(val, AR_SREV_VERSION);
 312
 313		ah->hw_version.macRev = val & AR_SREV_REVISION;
 314
 315		if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCIE)
 316			ah->is_pciexpress = true;
 317	}
 318
 319	return true;
 320}
 321
 322/************************************/
 323/* HW Attach, Detach, Init Routines */
 324/************************************/
 325
 326static void ath9k_hw_disablepcie(struct ath_hw *ah)
 327{
 328	if (!AR_SREV_5416(ah))
 329		return;
 330
 331	REG_WRITE(ah, AR_PCIE_SERDES, 0x9248fc00);
 332	REG_WRITE(ah, AR_PCIE_SERDES, 0x24924924);
 333	REG_WRITE(ah, AR_PCIE_SERDES, 0x28000029);
 334	REG_WRITE(ah, AR_PCIE_SERDES, 0x57160824);
 335	REG_WRITE(ah, AR_PCIE_SERDES, 0x25980579);
 336	REG_WRITE(ah, AR_PCIE_SERDES, 0x00000000);
 337	REG_WRITE(ah, AR_PCIE_SERDES, 0x1aaabe40);
 338	REG_WRITE(ah, AR_PCIE_SERDES, 0xbe105554);
 339	REG_WRITE(ah, AR_PCIE_SERDES, 0x000e1007);
 340
 341	REG_WRITE(ah, AR_PCIE_SERDES2, 0x00000000);
 342}
 343
 344/* This should work for all families including legacy */
 345static bool ath9k_hw_chip_test(struct ath_hw *ah)
 346{
 347	struct ath_common *common = ath9k_hw_common(ah);
 348	u32 regAddr[2] = { AR_STA_ID0 };
 349	u32 regHold[2];
 350	static const u32 patternData[4] = {
 351		0x55555555, 0xaaaaaaaa, 0x66666666, 0x99999999
 352	};
 353	int i, j, loop_max;
 354
 355	if (!AR_SREV_9300_20_OR_LATER(ah)) {
 356		loop_max = 2;
 357		regAddr[1] = AR_PHY_BASE + (8 << 2);
 358	} else
 359		loop_max = 1;
 360
 361	for (i = 0; i < loop_max; i++) {
 362		u32 addr = regAddr[i];
 363		u32 wrData, rdData;
 364
 365		regHold[i] = REG_READ(ah, addr);
 366		for (j = 0; j < 0x100; j++) {
 367			wrData = (j << 16) | j;
 368			REG_WRITE(ah, addr, wrData);
 369			rdData = REG_READ(ah, addr);
 370			if (rdData != wrData) {
 371				ath_err(common,
 372					"address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 373					addr, wrData, rdData);
 374				return false;
 375			}
 376		}
 377		for (j = 0; j < 4; j++) {
 378			wrData = patternData[j];
 379			REG_WRITE(ah, addr, wrData);
 380			rdData = REG_READ(ah, addr);
 381			if (wrData != rdData) {
 382				ath_err(common,
 383					"address test failed addr: 0x%08x - wr:0x%08x != rd:0x%08x\n",
 384					addr, wrData, rdData);
 385				return false;
 386			}
 387		}
 388		REG_WRITE(ah, regAddr[i], regHold[i]);
 389	}
 390	udelay(100);
 391
 392	return true;
 393}
 394
 395static void ath9k_hw_init_config(struct ath_hw *ah)
 396{
 397	struct ath_common *common = ath9k_hw_common(ah);
 398
 399	ah->config.dma_beacon_response_time = 1;
 400	ah->config.sw_beacon_response_time = 6;
 401	ah->config.cwm_ignore_extcca = false;
 402	ah->config.analog_shiftreg = 1;
 403
 404	ah->config.rx_intr_mitigation = true;
 405
 406	if (AR_SREV_9300_20_OR_LATER(ah)) {
 407		ah->config.rimt_last = 500;
 408		ah->config.rimt_first = 2000;
 409	} else {
 410		ah->config.rimt_last = 250;
 411		ah->config.rimt_first = 700;
 412	}
 413
 414	if (AR_SREV_9462(ah) || AR_SREV_9565(ah))
 415		ah->config.pll_pwrsave = 7;
 416
 417	/*
 418	 * We need this for PCI devices only (Cardbus, PCI, miniPCI)
 419	 * _and_ if on non-uniprocessor systems (Multiprocessor/HT).
 420	 * This means we use it for all AR5416 devices, and the few
 421	 * minor PCI AR9280 devices out there.
 422	 *
 423	 * Serialization is required because these devices do not handle
 424	 * well the case of two concurrent reads/writes due to the latency
 425	 * involved. During one read/write another read/write can be issued
 426	 * on another CPU while the previous read/write may still be working
 427	 * on our hardware, if we hit this case the hardware poops in a loop.
 428	 * We prevent this by serializing reads and writes.
 429	 *
 430	 * This issue is not present on PCI-Express devices or pre-AR5416
 431	 * devices (legacy, 802.11abg).
 432	 */
 433	if (num_possible_cpus() > 1)
 434		ah->config.serialize_regmode = SER_REG_MODE_AUTO;
 435
 436	if (NR_CPUS > 1 && ah->config.serialize_regmode == SER_REG_MODE_AUTO) {
 437		if (ah->hw_version.macVersion == AR_SREV_VERSION_5416_PCI ||
 438		    ((AR_SREV_9160(ah) || AR_SREV_9280(ah) || AR_SREV_9287(ah)) &&
 439		     !ah->is_pciexpress)) {
 440			ah->config.serialize_regmode = SER_REG_MODE_ON;
 441		} else {
 442			ah->config.serialize_regmode = SER_REG_MODE_OFF;
 443		}
 444	}
 445
 446	ath_dbg(common, RESET, "serialize_regmode is %d\n",
 447		ah->config.serialize_regmode);
 448
 449	if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 450		ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD >> 1;
 451	else
 452		ah->config.max_txtrig_level = MAX_TX_FIFO_THRESHOLD;
 453}
 454
 455static void ath9k_hw_init_defaults(struct ath_hw *ah)
 456{
 457	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
 458
 459	regulatory->country_code = CTRY_DEFAULT;
 460	regulatory->power_limit = MAX_COMBINED_POWER;
 461
 462	ah->hw_version.magic = AR5416_MAGIC;
 463	ah->hw_version.subvendorid = 0;
 464
 465	ah->sta_id1_defaults = AR_STA_ID1_CRPT_MIC_ENABLE |
 466			       AR_STA_ID1_MCAST_KSRCH;
 467	if (AR_SREV_9100(ah))
 468		ah->sta_id1_defaults |= AR_STA_ID1_AR9100_BA_FIX;
 469
 470	ah->slottime = 9;
 471	ah->globaltxtimeout = (u32) -1;
 472	ah->power_mode = ATH9K_PM_UNDEFINED;
 473	ah->htc_reset_init = true;
 474
 475	ah->tpc_enabled = false;
 476
 477	ah->ani_function = ATH9K_ANI_ALL;
 478	if (!AR_SREV_9300_20_OR_LATER(ah))
 479		ah->ani_function &= ~ATH9K_ANI_MRC_CCK;
 480
 481	if (AR_SREV_9285(ah) || AR_SREV_9271(ah))
 482		ah->tx_trig_level = (AR_FTRIG_256B >> AR_FTRIG_S);
 483	else
 484		ah->tx_trig_level = (AR_FTRIG_512B >> AR_FTRIG_S);
 485}
 486
 487static void ath9k_hw_init_macaddr(struct ath_hw *ah)
 488{
 489	struct ath_common *common = ath9k_hw_common(ah);
 490	int i;
 491	u16 eeval;
 492	static const u32 EEP_MAC[] = { EEP_MAC_LSW, EEP_MAC_MID, EEP_MAC_MSW };
 493
 494	/* MAC address may already be loaded via NVMEM */
 495	if (is_valid_ether_addr(common->macaddr))
 496		return;
 497
 498	for (i = 0; i < 3; i++) {
 499		eeval = ah->eep_ops->get_eeprom(ah, EEP_MAC[i]);
 500		common->macaddr[2 * i] = eeval >> 8;
 501		common->macaddr[2 * i + 1] = eeval & 0xff;
 502	}
 503
 504	if (is_valid_ether_addr(common->macaddr))
 505		return;
 506
 507	ath_err(common, "eeprom contains invalid mac address: %pM\n",
 508		common->macaddr);
 509
 510	eth_random_addr(common->macaddr);
 511	ath_err(common, "random mac address will be used: %pM\n",
 512		common->macaddr);
 513
 514	return;
 515}
 516
 517static int ath9k_hw_post_init(struct ath_hw *ah)
 518{
 519	struct ath_common *common = ath9k_hw_common(ah);
 520	int ecode;
 521
 522	if (common->bus_ops->ath_bus_type != ATH_USB) {
 523		if (!ath9k_hw_chip_test(ah))
 524			return -ENODEV;
 525	}
 526
 527	if (!AR_SREV_9300_20_OR_LATER(ah)) {
 528		ecode = ar9002_hw_rf_claim(ah);
 529		if (ecode != 0)
 530			return ecode;
 531	}
 532
 533	ecode = ath9k_hw_eeprom_init(ah);
 534	if (ecode != 0)
 535		return ecode;
 536
 537	ath_dbg(ath9k_hw_common(ah), CONFIG, "Eeprom VER: %d, REV: %d\n",
 538		ah->eep_ops->get_eeprom_ver(ah),
 539		ah->eep_ops->get_eeprom_rev(ah));
 540
 541	ath9k_hw_ani_init(ah);
 542
 543	/*
 544	 * EEPROM needs to be initialized before we do this.
 545	 * This is required for regulatory compliance.
 546	 */
 547	if (AR_SREV_9300_20_OR_LATER(ah)) {
 548		u16 regdmn = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
 549		if ((regdmn & 0xF0) == CTL_FCC) {
 550			ah->nf_2g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_2GHZ;
 551			ah->nf_5g.max = AR_PHY_CCA_MAX_GOOD_VAL_9300_FCC_5GHZ;
 552		}
 553	}
 554
 555	return 0;
 556}
 557
 558static int ath9k_hw_attach_ops(struct ath_hw *ah)
 559{
 560	if (!AR_SREV_9300_20_OR_LATER(ah))
 561		return ar9002_hw_attach_ops(ah);
 562
 563	ar9003_hw_attach_ops(ah);
 564	return 0;
 565}
 566
 567/* Called for all hardware families */
 568static int __ath9k_hw_init(struct ath_hw *ah)
 569{
 570	struct ath_common *common = ath9k_hw_common(ah);
 571	int r = 0;
 572
 573	if (!ath9k_hw_read_revisions(ah)) {
 574		ath_err(common, "Could not read hardware revisions");
 575		return -EOPNOTSUPP;
 576	}
 577
 578	switch (ah->hw_version.macVersion) {
 579	case AR_SREV_VERSION_5416_PCI:
 580	case AR_SREV_VERSION_5416_PCIE:
 581	case AR_SREV_VERSION_9160:
 582	case AR_SREV_VERSION_9100:
 583	case AR_SREV_VERSION_9280:
 584	case AR_SREV_VERSION_9285:
 585	case AR_SREV_VERSION_9287:
 586	case AR_SREV_VERSION_9271:
 587	case AR_SREV_VERSION_9300:
 588	case AR_SREV_VERSION_9330:
 589	case AR_SREV_VERSION_9485:
 590	case AR_SREV_VERSION_9340:
 591	case AR_SREV_VERSION_9462:
 592	case AR_SREV_VERSION_9550:
 593	case AR_SREV_VERSION_9565:
 594	case AR_SREV_VERSION_9531:
 595	case AR_SREV_VERSION_9561:
 596		break;
 597	default:
 598		ath_err(common,
 599			"Mac Chip Rev 0x%02x.%x is not supported by this driver\n",
 600			ah->hw_version.macVersion, ah->hw_version.macRev);
 601		return -EOPNOTSUPP;
 602	}
 603
 604	/*
 605	 * Read back AR_WA(ah) into a permanent copy and set bits 14 and 17.
 606	 * We need to do this to avoid RMW of this register. We cannot
 607	 * read the reg when chip is asleep.
 608	 */
 609	if (AR_SREV_9300_20_OR_LATER(ah)) {
 610		ah->WARegVal = REG_READ(ah, AR_WA(ah));
 611		ah->WARegVal |= (AR_WA_D3_L1_DISABLE |
 612				 AR_WA_ASPM_TIMER_BASED_DISABLE);
 613	}
 614
 615	if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
 616		ath_err(common, "Couldn't reset chip\n");
 617		return -EIO;
 618	}
 619
 620	if (AR_SREV_9565(ah)) {
 621		ah->WARegVal |= AR_WA_BIT22;
 622		REG_WRITE(ah, AR_WA(ah), ah->WARegVal);
 623	}
 624
 625	ath9k_hw_init_defaults(ah);
 626	ath9k_hw_init_config(ah);
 627
 628	r = ath9k_hw_attach_ops(ah);
 629	if (r)
 630		return r;
 631
 632	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE)) {
 633		ath_err(common, "Couldn't wakeup chip\n");
 634		return -EIO;
 635	}
 636
 637	if (AR_SREV_9271(ah) || AR_SREV_9100(ah) || AR_SREV_9340(ah) ||
 638	    AR_SREV_9330(ah) || AR_SREV_9550(ah))
 639		ah->is_pciexpress = false;
 640
 641	ah->hw_version.phyRev = REG_READ(ah, AR_PHY_CHIP_ID);
 642	ath9k_hw_init_cal_settings(ah);
 643
 644	if (!ah->is_pciexpress)
 645		ath9k_hw_disablepcie(ah);
 646
 647	r = ath9k_hw_post_init(ah);
 648	if (r)
 649		return r;
 650
 651	ath9k_hw_init_mode_gain_regs(ah);
 652	r = ath9k_hw_fill_cap_info(ah);
 653	if (r)
 654		return r;
 655
 656	ath9k_hw_init_macaddr(ah);
 657	ath9k_hw_init_hang_checks(ah);
 658
 659	common->state = ATH_HW_INITIALIZED;
 660
 661	return 0;
 662}
 663
 664int ath9k_hw_init(struct ath_hw *ah)
 665{
 666	int ret;
 667	struct ath_common *common = ath9k_hw_common(ah);
 668
 669	/* These are all the AR5008/AR9001/AR9002/AR9003 hardware family of chipsets */
 670	switch (ah->hw_version.devid) {
 671	case AR5416_DEVID_PCI:
 672	case AR5416_DEVID_PCIE:
 673	case AR5416_AR9100_DEVID:
 674	case AR9160_DEVID_PCI:
 675	case AR9280_DEVID_PCI:
 676	case AR9280_DEVID_PCIE:
 677	case AR9285_DEVID_PCIE:
 678	case AR9287_DEVID_PCI:
 679	case AR9287_DEVID_PCIE:
 680	case AR2427_DEVID_PCIE:
 681	case AR9300_DEVID_PCIE:
 682	case AR9300_DEVID_AR9485_PCIE:
 683	case AR9300_DEVID_AR9330:
 684	case AR9300_DEVID_AR9340:
 685	case AR9300_DEVID_QCA955X:
 686	case AR9300_DEVID_AR9580:
 687	case AR9300_DEVID_AR9462:
 688	case AR9485_DEVID_AR1111:
 689	case AR9300_DEVID_AR9565:
 690	case AR9300_DEVID_AR953X:
 691	case AR9300_DEVID_QCA956X:
 692		break;
 693	default:
 694		if (common->bus_ops->ath_bus_type == ATH_USB)
 695			break;
 696		ath_err(common, "Hardware device ID 0x%04x not supported\n",
 697			ah->hw_version.devid);
 698		return -EOPNOTSUPP;
 699	}
 700
 701	ret = __ath9k_hw_init(ah);
 702	if (ret) {
 703		ath_err(common,
 704			"Unable to initialize hardware; initialization status: %d\n",
 705			ret);
 706		return ret;
 707	}
 708
 709	ath_dynack_init(ah);
 710
 711	return 0;
 712}
 713EXPORT_SYMBOL(ath9k_hw_init);
 714
 715static void ath9k_hw_init_qos(struct ath_hw *ah)
 716{
 717	ENABLE_REGWRITE_BUFFER(ah);
 718
 719	REG_WRITE(ah, AR_MIC_QOS_CONTROL, 0x100aa);
 720	REG_WRITE(ah, AR_MIC_QOS_SELECT, 0x3210);
 721
 722	REG_WRITE(ah, AR_QOS_NO_ACK,
 723		  SM(2, AR_QOS_NO_ACK_TWO_BIT) |
 724		  SM(5, AR_QOS_NO_ACK_BIT_OFF) |
 725		  SM(0, AR_QOS_NO_ACK_BYTE_OFF));
 726
 727	REG_WRITE(ah, AR_TXOP_X, AR_TXOP_X_VAL);
 728	REG_WRITE(ah, AR_TXOP_0_3, 0xFFFFFFFF);
 729	REG_WRITE(ah, AR_TXOP_4_7, 0xFFFFFFFF);
 730	REG_WRITE(ah, AR_TXOP_8_11, 0xFFFFFFFF);
 731	REG_WRITE(ah, AR_TXOP_12_15, 0xFFFFFFFF);
 732
 733	REGWRITE_BUFFER_FLUSH(ah);
 734}
 735
 736u32 ar9003_get_pll_sqsum_dvc(struct ath_hw *ah)
 737{
 738	struct ath_common *common = ath9k_hw_common(ah);
 739	int i = 0;
 740
 741	REG_CLR_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
 742	udelay(100);
 743	REG_SET_BIT(ah, PLL3, PLL3_DO_MEAS_MASK);
 744
 745	while ((REG_READ(ah, PLL4) & PLL4_MEAS_DONE) == 0) {
 746
 747		udelay(100);
 748
 749		if (WARN_ON_ONCE(i >= 100)) {
 750			ath_err(common, "PLL4 measurement not done\n");
 751			break;
 752		}
 753
 754		i++;
 755	}
 756
 757	return (REG_READ(ah, PLL3) & SQSUM_DVC_MASK) >> 3;
 758}
 759EXPORT_SYMBOL(ar9003_get_pll_sqsum_dvc);
 760
 761static void ath9k_hw_init_pll(struct ath_hw *ah,
 762			      struct ath9k_channel *chan)
 763{
 764	u32 pll;
 765
 766	pll = ath9k_hw_compute_pll_control(ah, chan);
 767
 768	if (AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
 769		/* program BB PLL ki and kd value, ki=0x4, kd=0x40 */
 770		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
 771			      AR_CH0_BB_DPLL2_PLL_PWD, 0x1);
 772		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
 773			      AR_CH0_DPLL2_KD, 0x40);
 774		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
 775			      AR_CH0_DPLL2_KI, 0x4);
 776
 777		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
 778			      AR_CH0_BB_DPLL1_REFDIV, 0x5);
 779		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
 780			      AR_CH0_BB_DPLL1_NINI, 0x58);
 781		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL1,
 782			      AR_CH0_BB_DPLL1_NFRAC, 0x0);
 783
 784		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
 785			      AR_CH0_BB_DPLL2_OUTDIV, 0x1);
 786		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
 787			      AR_CH0_BB_DPLL2_LOCAL_PLL, 0x1);
 788		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
 789			      AR_CH0_BB_DPLL2_EN_NEGTRIG, 0x1);
 790
 791		/* program BB PLL phase_shift to 0x6 */
 792		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
 793			      AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x6);
 794
 795		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2,
 796			      AR_CH0_BB_DPLL2_PLL_PWD, 0x0);
 797		udelay(1000);
 798	} else if (AR_SREV_9330(ah)) {
 799		u32 ddr_dpll2, pll_control2, kd;
 800
 801		if (ah->is_clk_25mhz) {
 802			ddr_dpll2 = 0x18e82f01;
 803			pll_control2 = 0xe04a3d;
 804			kd = 0x1d;
 805		} else {
 806			ddr_dpll2 = 0x19e82f01;
 807			pll_control2 = 0x886666;
 808			kd = 0x3d;
 809		}
 810
 811		/* program DDR PLL ki and kd value */
 812		REG_WRITE(ah, AR_CH0_DDR_DPLL2, ddr_dpll2);
 813
 814		/* program DDR PLL phase_shift */
 815		REG_RMW_FIELD(ah, AR_CH0_DDR_DPLL3,
 816			      AR_CH0_DPLL3_PHASE_SHIFT, 0x1);
 817
 818		REG_WRITE(ah, AR_RTC_PLL_CONTROL(ah),
 819			  pll | AR_RTC_9300_PLL_BYPASS);
 820		udelay(1000);
 821
 822		/* program refdiv, nint, frac to RTC register */
 823		REG_WRITE(ah, AR_RTC_PLL_CONTROL2, pll_control2);
 824
 825		/* program BB PLL kd and ki value */
 826		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KD, kd);
 827		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL2, AR_CH0_DPLL2_KI, 0x06);
 828
 829		/* program BB PLL phase_shift */
 830		REG_RMW_FIELD(ah, AR_CH0_BB_DPLL3,
 831			      AR_CH0_BB_DPLL3_PHASE_SHIFT, 0x1);
 832	} else if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
 833		   AR_SREV_9561(ah)) {
 834		u32 regval, pll2_divint, pll2_divfrac, refdiv;
 835
 836		REG_WRITE(ah, AR_RTC_PLL_CONTROL(ah),
 837			  pll | AR_RTC_9300_SOC_PLL_BYPASS);
 838		udelay(1000);
 839
 840		REG_SET_BIT(ah, AR_PHY_PLL_MODE, 0x1 << 16);
 841		udelay(100);
 842
 843		if (ah->is_clk_25mhz) {
 844			if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
 845				pll2_divint = 0x1c;
 846				pll2_divfrac = 0xa3d2;
 847				refdiv = 1;
 848			} else {
 849				pll2_divint = 0x54;
 850				pll2_divfrac = 0x1eb85;
 851				refdiv = 3;
 852			}
 853		} else {
 854			if (AR_SREV_9340(ah)) {
 855				pll2_divint = 88;
 856				pll2_divfrac = 0;
 857				refdiv = 5;
 858			} else {
 859				pll2_divint = 0x11;
 860				pll2_divfrac = (AR_SREV_9531(ah) ||
 861						AR_SREV_9561(ah)) ?
 862						0x26665 : 0x26666;
 863				refdiv = 1;
 864			}
 865		}
 866
 867		regval = REG_READ(ah, AR_PHY_PLL_MODE);
 868		if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
 869			regval |= (0x1 << 22);
 870		else
 871			regval |= (0x1 << 16);
 872		REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
 873		udelay(100);
 874
 875		REG_WRITE(ah, AR_PHY_PLL_CONTROL, (refdiv << 27) |
 876			  (pll2_divint << 18) | pll2_divfrac);
 877		udelay(100);
 878
 879		regval = REG_READ(ah, AR_PHY_PLL_MODE);
 880		if (AR_SREV_9340(ah))
 881			regval = (regval & 0x80071fff) |
 882				(0x1 << 30) |
 883				(0x1 << 13) |
 884				(0x4 << 26) |
 885				(0x18 << 19);
 886		else if (AR_SREV_9531(ah) || AR_SREV_9561(ah)) {
 887			regval = (regval & 0x01c00fff) |
 888				(0x1 << 31) |
 889				(0x2 << 29) |
 890				(0xa << 25) |
 891				(0x1 << 19);
 892
 893			if (AR_SREV_9531(ah))
 894				regval |= (0x6 << 12);
 895		} else
 896			regval = (regval & 0x80071fff) |
 897				(0x3 << 30) |
 898				(0x1 << 13) |
 899				(0x4 << 26) |
 900				(0x60 << 19);
 901		REG_WRITE(ah, AR_PHY_PLL_MODE, regval);
 902
 903		if (AR_SREV_9531(ah) || AR_SREV_9561(ah))
 904			REG_WRITE(ah, AR_PHY_PLL_MODE,
 905				  REG_READ(ah, AR_PHY_PLL_MODE) & 0xffbfffff);
 906		else
 907			REG_WRITE(ah, AR_PHY_PLL_MODE,
 908				  REG_READ(ah, AR_PHY_PLL_MODE) & 0xfffeffff);
 909
 910		udelay(1000);
 911	}
 912
 913	if (AR_SREV_9565(ah))
 914		pll |= 0x40000;
 915	REG_WRITE(ah, AR_RTC_PLL_CONTROL(ah), pll);
 916
 917	if (AR_SREV_9485(ah) || AR_SREV_9340(ah) || AR_SREV_9330(ah) ||
 918	    AR_SREV_9550(ah))
 919		udelay(1000);
 920
 921	/* Switch the core clock for ar9271 to 117Mhz */
 922	if (AR_SREV_9271(ah)) {
 923		udelay(500);
 924		REG_WRITE(ah, 0x50040, 0x304);
 925	}
 926
 927	udelay(RTC_PLL_SETTLE_DELAY);
 928
 929	REG_WRITE(ah, AR_RTC_SLEEP_CLK(ah), AR_RTC_FORCE_DERIVED_CLK);
 930}
 931
 932static void ath9k_hw_init_interrupt_masks(struct ath_hw *ah,
 933					  enum nl80211_iftype opmode)
 934{
 935	u32 sync_default = AR_INTR_SYNC_DEFAULT;
 936	u32 imr_reg = AR_IMR_TXERR |
 937		AR_IMR_TXURN |
 938		AR_IMR_RXERR |
 939		AR_IMR_RXORN |
 940		AR_IMR_BCNMISC;
 941	u32 msi_cfg = 0;
 942
 943	if (AR_SREV_9340(ah) || AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
 944	    AR_SREV_9561(ah))
 945		sync_default &= ~AR_INTR_SYNC_HOST1_FATAL;
 946
 947	if (AR_SREV_9300_20_OR_LATER(ah)) {
 948		imr_reg |= AR_IMR_RXOK_HP;
 949		if (ah->config.rx_intr_mitigation) {
 950			imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
 951			msi_cfg |= AR_INTCFG_MSI_RXINTM | AR_INTCFG_MSI_RXMINTR;
 952		} else {
 953			imr_reg |= AR_IMR_RXOK_LP;
 954			msi_cfg |= AR_INTCFG_MSI_RXOK;
 955		}
 956	} else {
 957		if (ah->config.rx_intr_mitigation) {
 958			imr_reg |= AR_IMR_RXINTM | AR_IMR_RXMINTR;
 959			msi_cfg |= AR_INTCFG_MSI_RXINTM | AR_INTCFG_MSI_RXMINTR;
 960		} else {
 961			imr_reg |= AR_IMR_RXOK;
 962			msi_cfg |= AR_INTCFG_MSI_RXOK;
 963		}
 964	}
 965
 966	if (ah->config.tx_intr_mitigation) {
 967		imr_reg |= AR_IMR_TXINTM | AR_IMR_TXMINTR;
 968		msi_cfg |= AR_INTCFG_MSI_TXINTM | AR_INTCFG_MSI_TXMINTR;
 969	} else {
 970		imr_reg |= AR_IMR_TXOK;
 971		msi_cfg |= AR_INTCFG_MSI_TXOK;
 972	}
 973
 974	ENABLE_REGWRITE_BUFFER(ah);
 975
 976	REG_WRITE(ah, AR_IMR, imr_reg);
 977	ah->imrs2_reg |= AR_IMR_S2_GTT;
 978	REG_WRITE(ah, AR_IMR_S2, ah->imrs2_reg);
 979
 980	if (ah->msi_enabled) {
 981		ah->msi_reg = REG_READ(ah, AR_PCIE_MSI(ah));
 982		ah->msi_reg |= AR_PCIE_MSI_HW_DBI_WR_EN;
 983		ah->msi_reg &= AR_PCIE_MSI_HW_INT_PENDING_ADDR_MSI_64;
 984		REG_WRITE(ah, AR_INTCFG, msi_cfg);
 985		ath_dbg(ath9k_hw_common(ah), ANY,
 986			"value of AR_INTCFG=0x%X, msi_cfg=0x%X\n",
 987			REG_READ(ah, AR_INTCFG), msi_cfg);
 988	}
 989
 990	if (!AR_SREV_9100(ah)) {
 991		REG_WRITE(ah, AR_INTR_SYNC_CAUSE(ah), 0xFFFFFFFF);
 992		REG_WRITE(ah, AR_INTR_SYNC_ENABLE(ah), sync_default);
 993		REG_WRITE(ah, AR_INTR_SYNC_MASK(ah), 0);
 994	}
 995
 996	REGWRITE_BUFFER_FLUSH(ah);
 997
 998	if (AR_SREV_9300_20_OR_LATER(ah)) {
 999		REG_WRITE(ah, AR_INTR_PRIO_ASYNC_ENABLE(ah), 0);
1000		REG_WRITE(ah, AR_INTR_PRIO_ASYNC_MASK(ah), 0);
1001		REG_WRITE(ah, AR_INTR_PRIO_SYNC_ENABLE(ah), 0);
1002		REG_WRITE(ah, AR_INTR_PRIO_SYNC_MASK(ah), 0);
1003	}
1004}
1005
1006static void ath9k_hw_set_sifs_time(struct ath_hw *ah, u32 us)
1007{
1008	u32 val = ath9k_hw_mac_to_clks(ah, us - 2);
1009	val = min(val, (u32) 0xFFFF);
1010	REG_WRITE(ah, AR_D_GBL_IFS_SIFS, val);
1011}
1012
1013void ath9k_hw_setslottime(struct ath_hw *ah, u32 us)
1014{
1015	u32 val = ath9k_hw_mac_to_clks(ah, us);
1016	val = min(val, (u32) 0xFFFF);
1017	REG_WRITE(ah, AR_D_GBL_IFS_SLOT, val);
1018}
1019
1020void ath9k_hw_set_ack_timeout(struct ath_hw *ah, u32 us)
1021{
1022	u32 val = ath9k_hw_mac_to_clks(ah, us);
1023	val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_ACK));
1024	REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_ACK, val);
1025}
1026
1027void ath9k_hw_set_cts_timeout(struct ath_hw *ah, u32 us)
1028{
1029	u32 val = ath9k_hw_mac_to_clks(ah, us);
1030	val = min(val, (u32) MS(0xFFFFFFFF, AR_TIME_OUT_CTS));
1031	REG_RMW_FIELD(ah, AR_TIME_OUT, AR_TIME_OUT_CTS, val);
1032}
1033
1034static bool ath9k_hw_set_global_txtimeout(struct ath_hw *ah, u32 tu)
1035{
1036	if (tu > 0xFFFF) {
1037		ath_dbg(ath9k_hw_common(ah), XMIT, "bad global tx timeout %u\n",
1038			tu);
1039		ah->globaltxtimeout = (u32) -1;
1040		return false;
1041	} else {
1042		REG_RMW_FIELD(ah, AR_GTXTO, AR_GTXTO_TIMEOUT_LIMIT, tu);
1043		ah->globaltxtimeout = tu;
1044		return true;
1045	}
1046}
1047
1048void ath9k_hw_init_global_settings(struct ath_hw *ah)
1049{
1050	struct ath_common *common = ath9k_hw_common(ah);
1051	const struct ath9k_channel *chan = ah->curchan;
1052	int acktimeout, ctstimeout, ack_offset = 0;
1053	int slottime;
1054	int sifstime;
1055	int rx_lat = 0, tx_lat = 0, eifs = 0, ack_shift = 0;
1056	u32 reg;
1057
1058	ath_dbg(ath9k_hw_common(ah), RESET, "ah->misc_mode 0x%x\n",
1059		ah->misc_mode);
1060
1061	if (!chan)
1062		return;
1063
1064	if (ah->misc_mode != 0)
1065		REG_SET_BIT(ah, AR_PCU_MISC, ah->misc_mode);
1066
1067	if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1068		rx_lat = 41;
1069	else
1070		rx_lat = 37;
1071	tx_lat = 54;
1072
1073	if (IS_CHAN_5GHZ(chan))
1074		sifstime = 16;
1075	else
1076		sifstime = 10;
1077
1078	if (IS_CHAN_HALF_RATE(chan)) {
1079		eifs = 175;
1080		rx_lat *= 2;
1081		tx_lat *= 2;
1082		if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1083		    tx_lat += 11;
1084
1085		sifstime = 32;
1086		ack_offset = 16;
1087		ack_shift = 3;
1088		slottime = 13;
1089	} else if (IS_CHAN_QUARTER_RATE(chan)) {
1090		eifs = 340;
1091		rx_lat = (rx_lat * 4) - 1;
1092		tx_lat *= 4;
1093		if (IS_CHAN_A_FAST_CLOCK(ah, chan))
1094		    tx_lat += 22;
1095
1096		sifstime = 64;
1097		ack_offset = 32;
1098		ack_shift = 1;
1099		slottime = 21;
1100	} else {
1101		if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1102			eifs = AR_D_GBL_IFS_EIFS_ASYNC_FIFO;
1103			reg = AR_USEC_ASYNC_FIFO;
1104		} else {
1105			eifs = REG_READ(ah, AR_D_GBL_IFS_EIFS)/
1106				common->clockrate;
1107			reg = REG_READ(ah, AR_USEC);
1108		}
1109		rx_lat = MS(reg, AR_USEC_RX_LAT);
1110		tx_lat = MS(reg, AR_USEC_TX_LAT);
1111
1112		slottime = ah->slottime;
1113	}
1114
1115	/* As defined by IEEE 802.11-2007 17.3.8.6 */
1116	slottime += 3 * ah->coverage_class;
1117	acktimeout = slottime + sifstime + ack_offset;
1118	ctstimeout = acktimeout;
1119
1120	/*
1121	 * Workaround for early ACK timeouts, add an offset to match the
1122	 * initval's 64us ack timeout value. Use 48us for the CTS timeout.
1123	 * This was initially only meant to work around an issue with delayed
1124	 * BA frames in some implementations, but it has been found to fix ACK
1125	 * timeout issues in other cases as well.
1126	 */
1127	if (IS_CHAN_2GHZ(chan) &&
1128	    !IS_CHAN_HALF_RATE(chan) && !IS_CHAN_QUARTER_RATE(chan)) {
1129		acktimeout += 64 - sifstime - ah->slottime;
1130		ctstimeout += 48 - sifstime - ah->slottime;
1131	}
1132
1133	if (ah->dynack.enabled) {
1134		acktimeout = ah->dynack.ackto;
1135		ctstimeout = acktimeout;
1136		slottime = (acktimeout - 3) / 2;
1137	} else {
1138		ah->dynack.ackto = acktimeout;
1139	}
1140
1141	ath9k_hw_set_sifs_time(ah, sifstime);
1142	ath9k_hw_setslottime(ah, slottime);
1143	ath9k_hw_set_ack_timeout(ah, acktimeout);
1144	ath9k_hw_set_cts_timeout(ah, ctstimeout);
1145	if (ah->globaltxtimeout != (u32) -1)
1146		ath9k_hw_set_global_txtimeout(ah, ah->globaltxtimeout);
1147
1148	REG_WRITE(ah, AR_D_GBL_IFS_EIFS, ath9k_hw_mac_to_clks(ah, eifs));
1149	REG_RMW(ah, AR_USEC,
1150		(common->clockrate - 1) |
1151		SM(rx_lat, AR_USEC_RX_LAT) |
1152		SM(tx_lat, AR_USEC_TX_LAT),
1153		AR_USEC_TX_LAT | AR_USEC_RX_LAT | AR_USEC_USEC);
1154
1155	if (IS_CHAN_HALF_RATE(chan) || IS_CHAN_QUARTER_RATE(chan))
1156		REG_RMW(ah, AR_TXSIFS,
1157			sifstime | SM(ack_shift, AR_TXSIFS_ACK_SHIFT),
1158			(AR_TXSIFS_TIME | AR_TXSIFS_ACK_SHIFT));
1159}
1160EXPORT_SYMBOL(ath9k_hw_init_global_settings);
1161
1162void ath9k_hw_deinit(struct ath_hw *ah)
1163{
1164	struct ath_common *common = ath9k_hw_common(ah);
1165
1166	if (common->state < ATH_HW_INITIALIZED)
1167		return;
1168
1169	ath9k_hw_setpower(ah, ATH9K_PM_FULL_SLEEP);
1170}
1171EXPORT_SYMBOL(ath9k_hw_deinit);
1172
1173/*******/
1174/* INI */
1175/*******/
1176
1177u32 ath9k_regd_get_ctl(struct ath_regulatory *reg, struct ath9k_channel *chan)
1178{
1179	u32 ctl = ath_regd_get_band_ctl(reg, chan->chan->band);
1180
1181	if (IS_CHAN_2GHZ(chan))
1182		ctl |= CTL_11G;
1183	else
1184		ctl |= CTL_11A;
1185
1186	return ctl;
1187}
1188
1189/****************************************/
1190/* Reset and Channel Switching Routines */
1191/****************************************/
1192
1193static inline void ath9k_hw_set_dma(struct ath_hw *ah)
1194{
1195	struct ath_common *common = ath9k_hw_common(ah);
1196	int txbuf_size;
1197
1198	ENABLE_REGWRITE_BUFFER(ah);
1199
1200	/*
1201	 * set AHB_MODE not to do cacheline prefetches
1202	*/
1203	if (!AR_SREV_9300_20_OR_LATER(ah))
1204		REG_SET_BIT(ah, AR_AHB_MODE, AR_AHB_PREFETCH_RD_EN);
1205
1206	/*
1207	 * let mac dma reads be in 128 byte chunks
1208	 */
1209	REG_RMW(ah, AR_TXCFG, AR_TXCFG_DMASZ_128B, AR_TXCFG_DMASZ_MASK);
1210
1211	REGWRITE_BUFFER_FLUSH(ah);
1212
1213	/*
1214	 * Restore TX Trigger Level to its pre-reset value.
1215	 * The initial value depends on whether aggregation is enabled, and is
1216	 * adjusted whenever underruns are detected.
1217	 */
1218	if (!AR_SREV_9300_20_OR_LATER(ah))
1219		REG_RMW_FIELD(ah, AR_TXCFG, AR_FTRIG, ah->tx_trig_level);
1220
1221	ENABLE_REGWRITE_BUFFER(ah);
1222
1223	/*
1224	 * let mac dma writes be in 128 byte chunks
1225	 */
1226	REG_RMW(ah, AR_RXCFG, AR_RXCFG_DMASZ_128B, AR_RXCFG_DMASZ_MASK);
1227
1228	/*
1229	 * Setup receive FIFO threshold to hold off TX activities
1230	 */
1231	REG_WRITE(ah, AR_RXFIFO_CFG, 0x200);
1232
1233	if (AR_SREV_9300_20_OR_LATER(ah)) {
1234		REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_HP, 0x1);
1235		REG_RMW_FIELD(ah, AR_RXBP_THRESH, AR_RXBP_THRESH_LP, 0x1);
1236
1237		ath9k_hw_set_rx_bufsize(ah, common->rx_bufsize -
1238			ah->caps.rx_status_len);
1239	}
1240
1241	/*
1242	 * reduce the number of usable entries in PCU TXBUF to avoid
1243	 * wrap around issues.
1244	 */
1245	if (AR_SREV_9285(ah)) {
1246		/* For AR9285 the number of Fifos are reduced to half.
1247		 * So set the usable tx buf size also to half to
1248		 * avoid data/delimiter underruns
1249		 */
1250		txbuf_size = AR_9285_PCU_TXBUF_CTRL_USABLE_SIZE;
1251	} else if (AR_SREV_9340_13_OR_LATER(ah)) {
1252		/* Uses fewer entries for AR934x v1.3+ to prevent rx overruns */
1253		txbuf_size = AR_9340_PCU_TXBUF_CTRL_USABLE_SIZE;
1254	} else {
1255		txbuf_size = AR_PCU_TXBUF_CTRL_USABLE_SIZE;
1256	}
1257
1258	if (!AR_SREV_9271(ah))
1259		REG_WRITE(ah, AR_PCU_TXBUF_CTRL, txbuf_size);
1260
1261	REGWRITE_BUFFER_FLUSH(ah);
1262
1263	if (AR_SREV_9300_20_OR_LATER(ah))
1264		ath9k_hw_reset_txstatus_ring(ah);
1265}
1266
1267static void ath9k_hw_set_operating_mode(struct ath_hw *ah, int opmode)
1268{
1269	u32 mask = AR_STA_ID1_STA_AP | AR_STA_ID1_ADHOC;
1270	u32 set = AR_STA_ID1_KSRCH_MODE;
1271
1272	ENABLE_REG_RMW_BUFFER(ah);
1273	switch (opmode) {
1274	case NL80211_IFTYPE_ADHOC:
1275		if (!AR_SREV_9340_13(ah)) {
1276			set |= AR_STA_ID1_ADHOC;
1277			REG_SET_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1278			break;
1279		}
1280		fallthrough;
1281	case NL80211_IFTYPE_OCB:
1282	case NL80211_IFTYPE_MESH_POINT:
1283	case NL80211_IFTYPE_AP:
1284		set |= AR_STA_ID1_STA_AP;
1285		fallthrough;
1286	case NL80211_IFTYPE_STATION:
1287		REG_CLR_BIT(ah, AR_CFG, AR_CFG_AP_ADHOC_INDICATION);
1288		break;
1289	default:
1290		if (!ah->is_monitoring)
1291			set = 0;
1292		break;
1293	}
1294	REG_RMW(ah, AR_STA_ID1, set, mask);
1295	REG_RMW_BUFFER_FLUSH(ah);
1296}
1297
1298void ath9k_hw_get_delta_slope_vals(struct ath_hw *ah, u32 coef_scaled,
1299				   u32 *coef_mantissa, u32 *coef_exponent)
1300{
1301	u32 coef_exp, coef_man;
1302
1303	for (coef_exp = 31; coef_exp > 0; coef_exp--)
1304		if ((coef_scaled >> coef_exp) & 0x1)
1305			break;
1306
1307	coef_exp = 14 - (coef_exp - COEF_SCALE_S);
1308
1309	coef_man = coef_scaled + (1 << (COEF_SCALE_S - coef_exp - 1));
1310
1311	*coef_mantissa = coef_man >> (COEF_SCALE_S - coef_exp);
1312	*coef_exponent = coef_exp - 16;
1313}
1314
1315/* AR9330 WAR:
1316 * call external reset function to reset WMAC if:
1317 * - doing a cold reset
1318 * - we have pending frames in the TX queues.
1319 */
1320static bool ath9k_hw_ar9330_reset_war(struct ath_hw *ah, int type)
1321{
1322	int i, npend = 0;
1323
1324	for (i = 0; i < AR_NUM_QCU; i++) {
1325		npend = ath9k_hw_numtxpending(ah, i);
1326		if (npend)
1327			break;
1328	}
1329
1330	if (ah->external_reset &&
1331	    (npend || type == ATH9K_RESET_COLD)) {
1332		int reset_err = 0;
1333
1334		ath_dbg(ath9k_hw_common(ah), RESET,
1335			"reset MAC via external reset\n");
1336
1337		reset_err = ah->external_reset();
1338		if (reset_err) {
1339			ath_err(ath9k_hw_common(ah),
1340				"External reset failed, err=%d\n",
1341				reset_err);
1342			return false;
1343		}
1344
1345		REG_WRITE(ah, AR_RTC_RESET(ah), 1);
1346	}
1347
1348	return true;
1349}
1350
1351static bool ath9k_hw_set_reset(struct ath_hw *ah, int type)
1352{
1353	u32 rst_flags;
1354	u32 tmpReg;
1355
1356	if (AR_SREV_9100(ah)) {
1357		REG_RMW_FIELD(ah, AR_RTC_DERIVED_CLK(ah),
1358			      AR_RTC_DERIVED_CLK_PERIOD, 1);
1359		(void)REG_READ(ah, AR_RTC_DERIVED_CLK(ah));
1360	}
1361
1362	ENABLE_REGWRITE_BUFFER(ah);
1363
1364	if (AR_SREV_9300_20_OR_LATER(ah)) {
1365		REG_WRITE(ah, AR_WA(ah), ah->WARegVal);
1366		udelay(10);
1367	}
1368
1369	REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_EN |
1370		  AR_RTC_FORCE_WAKE_ON_INT);
1371
1372	if (AR_SREV_9100(ah)) {
1373		rst_flags = AR_RTC_RC_MAC_WARM | AR_RTC_RC_MAC_COLD |
1374			AR_RTC_RC_COLD_RESET | AR_RTC_RC_WARM_RESET;
1375	} else {
1376		tmpReg = REG_READ(ah, AR_INTR_SYNC_CAUSE(ah));
1377		if (AR_SREV_9340(ah))
1378			tmpReg &= AR9340_INTR_SYNC_LOCAL_TIMEOUT;
1379		else
1380			tmpReg &= AR_INTR_SYNC_LOCAL_TIMEOUT |
1381				  AR_INTR_SYNC_RADM_CPL_TIMEOUT;
1382
1383		if (tmpReg) {
1384			u32 val;
1385			REG_WRITE(ah, AR_INTR_SYNC_ENABLE(ah), 0);
1386
1387			val = AR_RC_HOSTIF;
1388			if (!AR_SREV_9300_20_OR_LATER(ah))
1389				val |= AR_RC_AHB;
1390			REG_WRITE(ah, AR_RC, val);
1391
1392		} else if (!AR_SREV_9300_20_OR_LATER(ah))
1393			REG_WRITE(ah, AR_RC, AR_RC_AHB);
1394
1395		rst_flags = AR_RTC_RC_MAC_WARM;
1396		if (type == ATH9K_RESET_COLD)
1397			rst_flags |= AR_RTC_RC_MAC_COLD;
1398	}
1399
1400	if (AR_SREV_9330(ah)) {
1401		if (!ath9k_hw_ar9330_reset_war(ah, type))
1402			return false;
1403	}
1404
1405	if (ath9k_hw_mci_is_enabled(ah))
1406		ar9003_mci_check_gpm_offset(ah);
1407
1408	/* DMA HALT added to resolve ar9300 and ar9580 bus error during
1409	 * RTC_RC reg read
1410	 */
1411	if (AR_SREV_9300(ah) || AR_SREV_9580(ah)) {
1412		REG_SET_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
1413		ath9k_hw_wait(ah, AR_CFG, AR_CFG_HALT_ACK, AR_CFG_HALT_ACK,
1414			      20 * AH_WAIT_TIMEOUT);
1415		REG_CLR_BIT(ah, AR_CFG, AR_CFG_HALT_REQ);
1416	}
1417
1418	REG_WRITE(ah, AR_RTC_RC(ah), rst_flags);
1419
1420	REGWRITE_BUFFER_FLUSH(ah);
1421
1422	if (AR_SREV_9300_20_OR_LATER(ah))
1423		udelay(50);
1424	else if (AR_SREV_9100(ah))
1425		mdelay(10);
1426	else
1427		udelay(100);
1428
1429	REG_WRITE(ah, AR_RTC_RC(ah), 0);
1430	if (!ath9k_hw_wait(ah, AR_RTC_RC(ah), AR_RTC_RC_M, 0, AH_WAIT_TIMEOUT)) {
1431		ath_dbg(ath9k_hw_common(ah), RESET, "RTC stuck in MAC reset\n");
1432		return false;
1433	}
1434
1435	if (!AR_SREV_9100(ah))
1436		REG_WRITE(ah, AR_RC, 0);
1437
1438	if (AR_SREV_9100(ah))
1439		udelay(50);
1440
1441	return true;
1442}
1443
1444static bool ath9k_hw_set_reset_power_on(struct ath_hw *ah)
1445{
1446	ENABLE_REGWRITE_BUFFER(ah);
1447
1448	if (AR_SREV_9300_20_OR_LATER(ah)) {
1449		REG_WRITE(ah, AR_WA(ah), ah->WARegVal);
1450		udelay(10);
1451	}
1452
1453	REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_EN |
1454		  AR_RTC_FORCE_WAKE_ON_INT);
1455
1456	if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1457		REG_WRITE(ah, AR_RC, AR_RC_AHB);
1458
1459	REG_WRITE(ah, AR_RTC_RESET(ah), 0);
1460
1461	REGWRITE_BUFFER_FLUSH(ah);
1462
1463	udelay(2);
1464
1465	if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
1466		REG_WRITE(ah, AR_RC, 0);
1467
1468	REG_WRITE(ah, AR_RTC_RESET(ah), 1);
1469
1470	if (!ath9k_hw_wait(ah,
1471			   AR_RTC_STATUS(ah),
1472			   AR_RTC_STATUS_M(ah),
1473			   AR_RTC_STATUS_ON,
1474			   AH_WAIT_TIMEOUT)) {
1475		ath_dbg(ath9k_hw_common(ah), RESET, "RTC not waking up\n");
1476		return false;
1477	}
1478
1479	return ath9k_hw_set_reset(ah, ATH9K_RESET_WARM);
1480}
1481
1482static bool ath9k_hw_set_reset_reg(struct ath_hw *ah, u32 type)
1483{
1484	bool ret = false;
1485
1486	if (AR_SREV_9300_20_OR_LATER(ah)) {
1487		REG_WRITE(ah, AR_WA(ah), ah->WARegVal);
1488		udelay(10);
1489	}
1490
1491	REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah),
1492		  AR_RTC_FORCE_WAKE_EN | AR_RTC_FORCE_WAKE_ON_INT);
1493
1494	if (!ah->reset_power_on)
1495		type = ATH9K_RESET_POWER_ON;
1496
1497	switch (type) {
1498	case ATH9K_RESET_POWER_ON:
1499		ret = ath9k_hw_set_reset_power_on(ah);
1500		if (ret)
1501			ah->reset_power_on = true;
1502		break;
1503	case ATH9K_RESET_WARM:
1504	case ATH9K_RESET_COLD:
1505		ret = ath9k_hw_set_reset(ah, type);
1506		break;
1507	default:
1508		break;
1509	}
1510
1511	return ret;
1512}
1513
1514static bool ath9k_hw_chip_reset(struct ath_hw *ah,
1515				struct ath9k_channel *chan)
1516{
1517	int reset_type = ATH9K_RESET_WARM;
1518
1519	if (AR_SREV_9280(ah)) {
1520		if (ah->eep_ops->get_eeprom(ah, EEP_OL_PWRCTRL))
1521			reset_type = ATH9K_RESET_POWER_ON;
1522		else
1523			reset_type = ATH9K_RESET_COLD;
1524	} else if (ah->chip_fullsleep || REG_READ(ah, AR_Q_TXE) ||
1525		   (REG_READ(ah, AR_CR) & AR_CR_RXE(ah)))
1526		reset_type = ATH9K_RESET_COLD;
1527
1528	if (!ath9k_hw_set_reset_reg(ah, reset_type))
1529		return false;
1530
1531	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1532		return false;
1533
1534	ah->chip_fullsleep = false;
1535
1536	if (AR_SREV_9330(ah))
1537		ar9003_hw_internal_regulator_apply(ah);
1538	ath9k_hw_init_pll(ah, chan);
1539
1540	return true;
1541}
1542
1543static bool ath9k_hw_channel_change(struct ath_hw *ah,
1544				    struct ath9k_channel *chan)
1545{
1546	struct ath_common *common = ath9k_hw_common(ah);
1547	struct ath9k_hw_capabilities *pCap = &ah->caps;
1548	bool band_switch = false, mode_diff = false;
1549	u8 ini_reloaded = 0;
1550	u32 qnum;
1551	int r;
1552
1553	if (pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) {
1554		u32 flags_diff = chan->channelFlags ^ ah->curchan->channelFlags;
1555		band_switch = !!(flags_diff & CHANNEL_5GHZ);
1556		mode_diff = !!(flags_diff & ~CHANNEL_HT);
1557	}
1558
1559	for (qnum = 0; qnum < AR_NUM_QCU; qnum++) {
1560		if (ath9k_hw_numtxpending(ah, qnum)) {
1561			ath_dbg(common, QUEUE,
1562				"Transmit frames pending on queue %d\n", qnum);
1563			return false;
1564		}
1565	}
1566
1567	if (!ath9k_hw_rfbus_req(ah)) {
1568		ath_err(common, "Could not kill baseband RX\n");
1569		return false;
1570	}
1571
1572	if (band_switch || mode_diff) {
1573		ath9k_hw_mark_phy_inactive(ah);
1574		udelay(5);
1575
1576		if (band_switch)
1577			ath9k_hw_init_pll(ah, chan);
1578
1579		if (ath9k_hw_fast_chan_change(ah, chan, &ini_reloaded)) {
1580			ath_err(common, "Failed to do fast channel change\n");
1581			return false;
1582		}
1583	}
1584
1585	ath9k_hw_set_channel_regs(ah, chan);
1586
1587	r = ath9k_hw_rf_set_freq(ah, chan);
1588	if (r) {
1589		ath_err(common, "Failed to set channel\n");
1590		return false;
1591	}
1592	ath9k_hw_set_clockrate(ah);
1593	ath9k_hw_apply_txpower(ah, chan, false);
1594
1595	ath9k_hw_set_delta_slope(ah, chan);
1596	ath9k_hw_spur_mitigate_freq(ah, chan);
1597
1598	if (band_switch || ini_reloaded)
1599		ah->eep_ops->set_board_values(ah, chan);
1600
1601	ath9k_hw_init_bb(ah, chan);
1602	ath9k_hw_rfbus_done(ah);
1603
1604	if (band_switch || ini_reloaded) {
1605		ah->ah_flags |= AH_FASTCC;
1606		ath9k_hw_init_cal(ah, chan);
1607		ah->ah_flags &= ~AH_FASTCC;
1608	}
1609
1610	return true;
1611}
1612
1613static void ath9k_hw_apply_gpio_override(struct ath_hw *ah)
1614{
1615	u32 gpio_mask = ah->gpio_mask;
1616	int i;
1617
1618	for (i = 0; gpio_mask; i++, gpio_mask >>= 1) {
1619		if (!(gpio_mask & 1))
1620			continue;
1621
1622		ath9k_hw_gpio_request_out(ah, i, NULL,
1623					  AR_GPIO_OUTPUT_MUX_AS_OUTPUT);
1624		ath9k_hw_set_gpio(ah, i, !!(ah->gpio_val & BIT(i)));
1625	}
1626}
1627
1628void ath9k_hw_check_nav(struct ath_hw *ah)
1629{
1630	struct ath_common *common = ath9k_hw_common(ah);
1631	u32 val;
1632
1633	val = REG_READ(ah, AR_NAV);
1634	if (val != 0xdeadbeef && val > 0x7fff) {
1635		ath_dbg(common, BSTUCK, "Abnormal NAV: 0x%x\n", val);
1636		REG_WRITE(ah, AR_NAV, 0);
1637	}
1638}
1639EXPORT_SYMBOL(ath9k_hw_check_nav);
1640
1641bool ath9k_hw_check_alive(struct ath_hw *ah)
1642{
1643	int count = 50;
1644	u32 reg, last_val;
1645
1646	/* Check if chip failed to wake up */
1647	if (REG_READ(ah, AR_CFG) == 0xdeadbeef)
1648		return false;
1649
1650	if (AR_SREV_9300(ah))
1651		return !ath9k_hw_detect_mac_hang(ah);
1652
1653	if (AR_SREV_9285_12_OR_LATER(ah))
1654		return true;
1655
1656	last_val = REG_READ(ah, AR_OBS_BUS_1);
1657	do {
1658		reg = REG_READ(ah, AR_OBS_BUS_1);
1659		if (reg != last_val)
1660			return true;
1661
1662		udelay(1);
1663		last_val = reg;
1664		if ((reg & 0x7E7FFFEF) == 0x00702400)
1665			continue;
1666
1667		switch (reg & 0x7E000B00) {
1668		case 0x1E000000:
1669		case 0x52000B00:
1670		case 0x18000B00:
1671			continue;
1672		default:
1673			return true;
1674		}
1675	} while (count-- > 0);
1676
1677	return false;
1678}
1679EXPORT_SYMBOL(ath9k_hw_check_alive);
1680
1681static void ath9k_hw_init_mfp(struct ath_hw *ah)
1682{
1683	/* Setup MFP options for CCMP */
1684	if (AR_SREV_9280_20_OR_LATER(ah)) {
1685		/* Mask Retry(b11), PwrMgt(b12), MoreData(b13) to 0 in mgmt
1686		 * frames when constructing CCMP AAD. */
1687		REG_RMW_FIELD(ah, AR_AES_MUTE_MASK1, AR_AES_MUTE_MASK1_FC_MGMT,
1688			      0xc7ff);
1689		if (AR_SREV_9271(ah) || AR_DEVID_7010(ah))
1690			ah->sw_mgmt_crypto_tx = true;
1691		else
1692			ah->sw_mgmt_crypto_tx = false;
1693		ah->sw_mgmt_crypto_rx = false;
1694	} else if (AR_SREV_9160_10_OR_LATER(ah)) {
1695		/* Disable hardware crypto for management frames */
1696		REG_CLR_BIT(ah, AR_PCU_MISC_MODE2,
1697			    AR_PCU_MISC_MODE2_MGMT_CRYPTO_ENABLE);
1698		REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
1699			    AR_PCU_MISC_MODE2_NO_CRYPTO_FOR_NON_DATA_PKT);
1700		ah->sw_mgmt_crypto_tx = true;
1701		ah->sw_mgmt_crypto_rx = true;
1702	} else {
1703		ah->sw_mgmt_crypto_tx = true;
1704		ah->sw_mgmt_crypto_rx = true;
1705	}
1706}
1707
1708static void ath9k_hw_reset_opmode(struct ath_hw *ah,
1709				  u32 macStaId1, u32 saveDefAntenna)
1710{
1711	struct ath_common *common = ath9k_hw_common(ah);
1712
1713	ENABLE_REGWRITE_BUFFER(ah);
1714
1715	REG_RMW(ah, AR_STA_ID1, macStaId1
1716		  | AR_STA_ID1_RTS_USE_DEF
1717		  | ah->sta_id1_defaults,
1718		  ~AR_STA_ID1_SADH_MASK);
1719	ath_hw_setbssidmask(common);
1720	REG_WRITE(ah, AR_DEF_ANTENNA, saveDefAntenna);
1721	ath9k_hw_write_associd(ah);
1722	REG_WRITE(ah, AR_ISR, ~0);
1723	REG_WRITE(ah, AR_RSSI_THR, INIT_RSSI_THR);
1724
1725	REGWRITE_BUFFER_FLUSH(ah);
1726
1727	ath9k_hw_set_operating_mode(ah, ah->opmode);
1728}
1729
1730static void ath9k_hw_init_queues(struct ath_hw *ah)
1731{
1732	int i;
1733
1734	ENABLE_REGWRITE_BUFFER(ah);
1735
1736	for (i = 0; i < AR_NUM_DCU; i++)
1737		REG_WRITE(ah, AR_DQCUMASK(i), 1 << i);
1738
1739	REGWRITE_BUFFER_FLUSH(ah);
1740
1741	ah->intr_txqs = 0;
1742	for (i = 0; i < ATH9K_NUM_TX_QUEUES; i++)
1743		ath9k_hw_resettxqueue(ah, i);
1744}
1745
1746/*
1747 * For big endian systems turn on swapping for descriptors
1748 */
1749static void ath9k_hw_init_desc(struct ath_hw *ah)
1750{
1751	struct ath_common *common = ath9k_hw_common(ah);
1752
1753	if (AR_SREV_9100(ah)) {
1754		u32 mask;
1755		mask = REG_READ(ah, AR_CFG);
1756		if (mask & (AR_CFG_SWRB | AR_CFG_SWTB | AR_CFG_SWRG)) {
1757			ath_dbg(common, RESET, "CFG Byte Swap Set 0x%x\n",
1758				mask);
1759		} else {
1760			mask = INIT_CONFIG_STATUS | AR_CFG_SWRB | AR_CFG_SWTB;
1761			REG_WRITE(ah, AR_CFG, mask);
1762			ath_dbg(common, RESET, "Setting CFG 0x%x\n",
1763				REG_READ(ah, AR_CFG));
1764		}
1765	} else {
1766		if (common->bus_ops->ath_bus_type == ATH_USB) {
1767			/* Configure AR9271 target WLAN */
1768			if (AR_SREV_9271(ah))
1769				REG_WRITE(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB);
1770			else
1771				REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1772		}
1773#ifdef __BIG_ENDIAN
1774		else if (AR_SREV_9330(ah) || AR_SREV_9340(ah) ||
1775			 AR_SREV_9550(ah) || AR_SREV_9531(ah) ||
1776			 AR_SREV_9561(ah))
1777			REG_RMW(ah, AR_CFG, AR_CFG_SWRB | AR_CFG_SWTB, 0);
1778		else
1779			REG_WRITE(ah, AR_CFG, AR_CFG_SWTD | AR_CFG_SWRD);
1780#endif
1781	}
1782}
1783
1784/*
1785 * Fast channel change:
1786 * (Change synthesizer based on channel freq without resetting chip)
1787 */
1788static int ath9k_hw_do_fastcc(struct ath_hw *ah, struct ath9k_channel *chan)
1789{
1790	struct ath_common *common = ath9k_hw_common(ah);
1791	struct ath9k_hw_capabilities *pCap = &ah->caps;
1792	int ret;
1793
1794	if (AR_SREV_9280(ah) && common->bus_ops->ath_bus_type == ATH_PCI)
1795		goto fail;
1796
1797	if (ah->chip_fullsleep)
1798		goto fail;
1799
1800	if (!ah->curchan)
1801		goto fail;
1802
1803	if (chan->channel == ah->curchan->channel)
1804		goto fail;
1805
1806	if ((ah->curchan->channelFlags | chan->channelFlags) &
1807	    (CHANNEL_HALF | CHANNEL_QUARTER))
1808		goto fail;
1809
1810	/*
1811	 * If cross-band fcc is not supoprted, bail out if channelFlags differ.
1812	 */
1813	if (!(pCap->hw_caps & ATH9K_HW_CAP_FCC_BAND_SWITCH) &&
1814	    ((chan->channelFlags ^ ah->curchan->channelFlags) & ~CHANNEL_HT))
1815		goto fail;
1816
1817	if (!ath9k_hw_check_alive(ah))
1818		goto fail;
1819
1820	/*
1821	 * For AR9462, make sure that calibration data for
1822	 * re-using are present.
1823	 */
1824	if (AR_SREV_9462(ah) && (ah->caldata &&
1825				 (!test_bit(TXIQCAL_DONE, &ah->caldata->cal_flags) ||
1826				  !test_bit(TXCLCAL_DONE, &ah->caldata->cal_flags) ||
1827				  !test_bit(RTT_DONE, &ah->caldata->cal_flags))))
1828		goto fail;
1829
1830	ath_dbg(common, RESET, "FastChannelChange for %d -> %d\n",
1831		ah->curchan->channel, chan->channel);
1832
1833	ret = ath9k_hw_channel_change(ah, chan);
1834	if (!ret)
1835		goto fail;
1836
1837	if (ath9k_hw_mci_is_enabled(ah))
1838		ar9003_mci_2g5g_switch(ah, false);
1839
1840	ath9k_hw_loadnf(ah, ah->curchan);
1841	ath9k_hw_start_nfcal(ah, true);
1842
1843	if (AR_SREV_9271(ah))
1844		ar9002_hw_load_ani_reg(ah, chan);
1845
1846	return 0;
1847fail:
1848	return -EINVAL;
1849}
1850
1851u32 ath9k_hw_get_tsf_offset(ktime_t last, ktime_t cur)
1852{
1853	if (cur == 0)
1854		cur = ktime_get_raw();
1855	return ktime_us_delta(cur, last);
1856}
1857EXPORT_SYMBOL(ath9k_hw_get_tsf_offset);
1858
1859int ath9k_hw_reset(struct ath_hw *ah, struct ath9k_channel *chan,
1860		   struct ath9k_hw_cal_data *caldata, bool fastcc)
1861{
1862	struct ath_common *common = ath9k_hw_common(ah);
1863	u32 saveLedState;
1864	u32 saveDefAntenna;
1865	u32 macStaId1;
1866	ktime_t tsf_ts;
1867	u32 tsf_offset;
1868	u64 tsf = 0;
1869	int r;
1870	bool start_mci_reset = false;
1871	bool save_fullsleep = ah->chip_fullsleep;
1872
1873	if (ath9k_hw_mci_is_enabled(ah)) {
1874		start_mci_reset = ar9003_mci_start_reset(ah, chan);
1875		if (start_mci_reset)
1876			return 0;
1877	}
1878
1879	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
1880		return -EIO;
1881
1882	if (ah->curchan && !ah->chip_fullsleep)
1883		ath9k_hw_getnf(ah, ah->curchan);
1884
1885	ah->caldata = caldata;
1886	if (caldata && (chan->channel != caldata->channel ||
1887			chan->channelFlags != caldata->channelFlags)) {
1888		/* Operating channel changed, reset channel calibration data */
1889		memset(caldata, 0, sizeof(*caldata));
1890		ath9k_init_nfcal_hist_buffer(ah, chan);
1891	} else if (caldata) {
1892		clear_bit(PAPRD_PACKET_SENT, &caldata->cal_flags);
1893	}
1894	ah->noise = ath9k_hw_getchan_noise(ah, chan, chan->noisefloor);
1895
1896	if (fastcc) {
1897		r = ath9k_hw_do_fastcc(ah, chan);
1898		if (!r)
1899			return r;
1900	}
1901
1902	if (ath9k_hw_mci_is_enabled(ah))
1903		ar9003_mci_stop_bt(ah, save_fullsleep);
1904
1905	saveDefAntenna = REG_READ(ah, AR_DEF_ANTENNA);
1906	if (saveDefAntenna == 0)
1907		saveDefAntenna = 1;
1908
1909	macStaId1 = REG_READ(ah, AR_STA_ID1) & AR_STA_ID1_BASE_RATE_11B;
1910
1911	/* Save TSF before chip reset, a cold reset clears it */
1912	tsf_ts = ktime_get_raw();
1913	tsf = ath9k_hw_gettsf64(ah);
1914
1915	saveLedState = REG_READ(ah, AR_CFG_LED) &
1916		(AR_CFG_LED_ASSOC_CTL | AR_CFG_LED_MODE_SEL |
1917		 AR_CFG_LED_BLINK_THRESH_SEL | AR_CFG_LED_BLINK_SLOW);
1918
1919	ath9k_hw_mark_phy_inactive(ah);
1920
1921	ah->paprd_table_write_done = false;
1922
1923	/* Only required on the first reset */
1924	if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1925		REG_WRITE(ah,
1926			  AR9271_RESET_POWER_DOWN_CONTROL,
1927			  AR9271_RADIO_RF_RST);
1928		udelay(50);
1929	}
1930
1931	if (!ath9k_hw_chip_reset(ah, chan)) {
1932		ath_err(common, "Chip reset failed\n");
1933		return -EINVAL;
1934	}
1935
1936	/* Only required on the first reset */
1937	if (AR_SREV_9271(ah) && ah->htc_reset_init) {
1938		ah->htc_reset_init = false;
1939		REG_WRITE(ah,
1940			  AR9271_RESET_POWER_DOWN_CONTROL,
1941			  AR9271_GATE_MAC_CTL);
1942		udelay(50);
1943	}
1944
1945	/* Restore TSF */
1946	tsf_offset = ath9k_hw_get_tsf_offset(tsf_ts, 0);
1947	ath9k_hw_settsf64(ah, tsf + tsf_offset);
1948
1949	if (AR_SREV_9280_20_OR_LATER(ah))
1950		REG_SET_BIT(ah, AR_GPIO_INPUT_EN_VAL(ah), AR_GPIO_JTAG_DISABLE);
1951
1952	if (!AR_SREV_9300_20_OR_LATER(ah))
1953		ar9002_hw_enable_async_fifo(ah);
1954
1955	r = ath9k_hw_process_ini(ah, chan);
1956	if (r)
1957		return r;
1958
1959	ath9k_hw_set_rfmode(ah, chan);
1960
1961	if (ath9k_hw_mci_is_enabled(ah))
1962		ar9003_mci_reset(ah, false, IS_CHAN_2GHZ(chan), save_fullsleep);
1963
1964	/*
1965	 * Some AR91xx SoC devices frequently fail to accept TSF writes
1966	 * right after the chip reset. When that happens, write a new
1967	 * value after the initvals have been applied.
1968	 */
1969	if (AR_SREV_9100(ah) && (ath9k_hw_gettsf64(ah) < tsf)) {
1970		tsf_offset = ath9k_hw_get_tsf_offset(tsf_ts, 0);
1971		ath9k_hw_settsf64(ah, tsf + tsf_offset);
1972	}
1973
1974	ath9k_hw_init_mfp(ah);
1975
1976	ath9k_hw_set_delta_slope(ah, chan);
1977	ath9k_hw_spur_mitigate_freq(ah, chan);
1978	ah->eep_ops->set_board_values(ah, chan);
1979
1980	ath9k_hw_reset_opmode(ah, macStaId1, saveDefAntenna);
1981
1982	r = ath9k_hw_rf_set_freq(ah, chan);
1983	if (r)
1984		return r;
1985
1986	ath9k_hw_set_clockrate(ah);
1987
1988	ath9k_hw_init_queues(ah);
1989	ath9k_hw_init_interrupt_masks(ah, ah->opmode);
1990	ath9k_hw_ani_cache_ini_regs(ah);
1991	ath9k_hw_init_qos(ah);
1992
1993	if (ah->caps.hw_caps & ATH9K_HW_CAP_RFSILENT)
1994		ath9k_hw_gpio_request_in(ah, ah->rfkill_gpio, "ath9k-rfkill");
1995
1996	ath9k_hw_init_global_settings(ah);
1997
1998	if (AR_SREV_9287(ah) && AR_SREV_9287_13_OR_LATER(ah)) {
1999		REG_SET_BIT(ah, AR_MAC_PCU_LOGIC_ANALYZER,
2000			    AR_MAC_PCU_LOGIC_ANALYZER_DISBUG20768);
2001		REG_RMW_FIELD(ah, AR_AHB_MODE, AR_AHB_CUSTOM_BURST_EN,
2002			      AR_AHB_CUSTOM_BURST_ASYNC_FIFO_VAL);
2003		REG_SET_BIT(ah, AR_PCU_MISC_MODE2,
2004			    AR_PCU_MISC_MODE2_ENABLE_AGGWEP);
2005	}
2006
2007	REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PRESERVE_SEQNUM);
2008
2009	ath9k_hw_set_dma(ah);
2010
2011	if (!ath9k_hw_mci_is_enabled(ah))
2012		REG_WRITE(ah, AR_OBS(ah), 8);
2013
2014	ENABLE_REG_RMW_BUFFER(ah);
2015	if (ah->config.rx_intr_mitigation) {
2016		REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_LAST, ah->config.rimt_last);
2017		REG_RMW_FIELD(ah, AR_RIMT, AR_RIMT_FIRST, ah->config.rimt_first);
2018	}
2019
2020	if (ah->config.tx_intr_mitigation) {
2021		REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_LAST, 300);
2022		REG_RMW_FIELD(ah, AR_TIMT, AR_TIMT_FIRST, 750);
2023	}
2024	REG_RMW_BUFFER_FLUSH(ah);
2025
2026	ath9k_hw_init_bb(ah, chan);
2027
2028	if (caldata) {
2029		clear_bit(TXIQCAL_DONE, &caldata->cal_flags);
2030		clear_bit(TXCLCAL_DONE, &caldata->cal_flags);
2031	}
2032	if (!ath9k_hw_init_cal(ah, chan))
2033		return -EIO;
2034
2035	if (ath9k_hw_mci_is_enabled(ah) && ar9003_mci_end_reset(ah, chan, caldata))
2036		return -EIO;
2037
2038	ENABLE_REGWRITE_BUFFER(ah);
2039
2040	ath9k_hw_restore_chainmask(ah);
2041	REG_WRITE(ah, AR_CFG_LED, saveLedState | AR_CFG_SCLK_32KHZ);
2042
2043	REGWRITE_BUFFER_FLUSH(ah);
2044
2045	ath9k_hw_gen_timer_start_tsf2(ah);
2046
2047	ath9k_hw_init_desc(ah);
2048
2049	if (ath9k_hw_btcoex_is_enabled(ah))
2050		ath9k_hw_btcoex_enable(ah);
2051
2052	if (ath9k_hw_mci_is_enabled(ah))
2053		ar9003_mci_check_bt(ah);
2054
2055	if (AR_SREV_9300_20_OR_LATER(ah)) {
2056		ath9k_hw_loadnf(ah, chan);
2057		ath9k_hw_start_nfcal(ah, true);
2058	}
2059
2060	if (AR_SREV_9300_20_OR_LATER(ah))
2061		ar9003_hw_bb_watchdog_config(ah);
2062
2063	if (ah->config.hw_hang_checks & HW_PHYRESTART_CLC_WAR)
2064		ar9003_hw_disable_phy_restart(ah);
2065
2066	ath9k_hw_apply_gpio_override(ah);
2067
2068	if (AR_SREV_9565(ah) && common->bt_ant_diversity)
2069		REG_SET_BIT(ah, AR_BTCOEX_WL_LNADIV, AR_BTCOEX_WL_LNADIV_FORCE_ON);
2070
2071	if (ah->hw->conf.radar_enabled) {
2072		/* set HW specific DFS configuration */
2073		ah->radar_conf.ext_channel = IS_CHAN_HT40(chan);
2074		ath9k_hw_set_radar_params(ah);
2075	}
2076
2077	return 0;
2078}
2079EXPORT_SYMBOL(ath9k_hw_reset);
2080
2081/******************************/
2082/* Power Management (Chipset) */
2083/******************************/
2084
2085/*
2086 * Notify Power Mgt is disabled in self-generated frames.
2087 * If requested, force chip to sleep.
2088 */
2089static void ath9k_set_power_sleep(struct ath_hw *ah)
2090{
2091	REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2092
2093	if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2094		REG_CLR_BIT(ah, AR_TIMER_MODE, 0xff);
2095		REG_CLR_BIT(ah, AR_NDP2_TIMER_MODE, 0xff);
2096		REG_CLR_BIT(ah, AR_SLP32_INC, 0xfffff);
2097		/* xxx Required for WLAN only case ? */
2098		REG_WRITE(ah, AR_MCI_INTERRUPT_RX_MSG_EN, 0);
2099		udelay(100);
2100	}
2101
2102	/*
2103	 * Clear the RTC force wake bit to allow the
2104	 * mac to go to sleep.
2105	 */
2106	REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_EN);
2107
2108	if (ath9k_hw_mci_is_enabled(ah))
2109		udelay(100);
2110
2111	if (!AR_SREV_9100(ah) && !AR_SREV_9300_20_OR_LATER(ah))
2112		REG_WRITE(ah, AR_RC, AR_RC_AHB | AR_RC_HOSTIF);
2113
2114	/* Shutdown chip. Active low */
2115	if (!AR_SREV_5416(ah) && !AR_SREV_9271(ah)) {
2116		REG_CLR_BIT(ah, AR_RTC_RESET(ah), AR_RTC_RESET_EN);
2117		udelay(2);
2118	}
2119
2120	/* Clear Bit 14 of AR_WA(ah) after putting chip into Full Sleep mode. */
2121	if (AR_SREV_9300_20_OR_LATER(ah))
2122		REG_WRITE(ah, AR_WA(ah), ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2123}
2124
2125/*
2126 * Notify Power Management is enabled in self-generating
2127 * frames. If request, set power mode of chip to
2128 * auto/normal.  Duration in units of 128us (1/8 TU).
2129 */
2130static void ath9k_set_power_network_sleep(struct ath_hw *ah)
2131{
2132	struct ath9k_hw_capabilities *pCap = &ah->caps;
2133
2134	REG_SET_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2135
2136	if (!(pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)) {
2137		/* Set WakeOnInterrupt bit; clear ForceWake bit */
2138		REG_WRITE(ah, AR_RTC_FORCE_WAKE(ah),
2139			  AR_RTC_FORCE_WAKE_ON_INT);
2140	} else {
2141
2142		/* When chip goes into network sleep, it could be waken
2143		 * up by MCI_INT interrupt caused by BT's HW messages
2144		 * (LNA_xxx, CONT_xxx) which could be in a very fast
2145		 * rate (~100us). This will cause chip to leave and
2146		 * re-enter network sleep mode frequently, which in
2147		 * consequence will have WLAN MCI HW to generate lots of
2148		 * SYS_WAKING and SYS_SLEEPING messages which will make
2149		 * BT CPU to busy to process.
2150		 */
2151		if (ath9k_hw_mci_is_enabled(ah))
2152			REG_CLR_BIT(ah, AR_MCI_INTERRUPT_RX_MSG_EN,
2153				    AR_MCI_INTERRUPT_RX_HW_MSG_MASK);
2154		/*
2155		 * Clear the RTC force wake bit to allow the
2156		 * mac to go to sleep.
2157		 */
2158		REG_CLR_BIT(ah, AR_RTC_FORCE_WAKE(ah), AR_RTC_FORCE_WAKE_EN);
2159
2160		if (ath9k_hw_mci_is_enabled(ah))
2161			udelay(30);
2162	}
2163
2164	/* Clear Bit 14 of AR_WA(ah) after putting chip into Net Sleep mode. */
2165	if (AR_SREV_9300_20_OR_LATER(ah))
2166		REG_WRITE(ah, AR_WA(ah), ah->WARegVal & ~AR_WA_D3_L1_DISABLE);
2167}
2168
2169static bool ath9k_hw_set_power_awake(struct ath_hw *ah)
2170{
2171	u32 val;
2172	int i;
2173
2174	/* Set Bits 14 and 17 of AR_WA(ah) before powering on the chip. */
2175	if (AR_SREV_9300_20_OR_LATER(ah)) {
2176		REG_WRITE(ah, AR_WA(ah), ah->WARegVal);
2177		udelay(10);
2178	}
2179
2180	if ((REG_READ(ah, AR_RTC_STATUS(ah)) &
2181	     AR_RTC_STATUS_M(ah)) == AR_RTC_STATUS_SHUTDOWN) {
2182		if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_POWER_ON)) {
2183			return false;
2184		}
2185		if (!AR_SREV_9300_20_OR_LATER(ah))
2186			ath9k_hw_init_pll(ah, NULL);
2187	}
2188	if (AR_SREV_9100(ah))
2189		REG_SET_BIT(ah, AR_RTC_RESET(ah),
2190			    AR_RTC_RESET_EN);
2191
2192	REG_SET_BIT(ah, AR_RTC_FORCE_WAKE(ah),
2193		    AR_RTC_FORCE_WAKE_EN);
2194	if (AR_SREV_9100(ah))
2195		mdelay(10);
2196	else
2197		udelay(50);
2198
2199	for (i = POWER_UP_TIME / 50; i > 0; i--) {
2200		val = REG_READ(ah, AR_RTC_STATUS(ah)) & AR_RTC_STATUS_M(ah);
2201		if (val == AR_RTC_STATUS_ON)
2202			break;
2203		udelay(50);
2204		REG_SET_BIT(ah, AR_RTC_FORCE_WAKE(ah),
2205			    AR_RTC_FORCE_WAKE_EN);
2206	}
2207	if (i == 0) {
2208		ath_err(ath9k_hw_common(ah),
2209			"Failed to wakeup in %uus\n",
2210			POWER_UP_TIME / 20);
2211		return false;
2212	}
2213
2214	if (ath9k_hw_mci_is_enabled(ah))
2215		ar9003_mci_set_power_awake(ah);
2216
2217	REG_CLR_BIT(ah, AR_STA_ID1, AR_STA_ID1_PWR_SAV);
2218
2219	return true;
2220}
2221
2222bool ath9k_hw_setpower(struct ath_hw *ah, enum ath9k_power_mode mode)
2223{
2224	struct ath_common *common = ath9k_hw_common(ah);
2225	int status = true;
2226	static const char *modes[] = {
2227		"AWAKE",
2228		"FULL-SLEEP",
2229		"NETWORK SLEEP",
2230		"UNDEFINED"
2231	};
2232
2233	if (ah->power_mode == mode)
2234		return status;
2235
2236	ath_dbg(common, RESET, "%s -> %s\n",
2237		modes[ah->power_mode], modes[mode]);
2238
2239	switch (mode) {
2240	case ATH9K_PM_AWAKE:
2241		status = ath9k_hw_set_power_awake(ah);
2242		break;
2243	case ATH9K_PM_FULL_SLEEP:
2244		if (ath9k_hw_mci_is_enabled(ah))
2245			ar9003_mci_set_full_sleep(ah);
2246
2247		ath9k_set_power_sleep(ah);
2248		ah->chip_fullsleep = true;
2249		break;
2250	case ATH9K_PM_NETWORK_SLEEP:
2251		ath9k_set_power_network_sleep(ah);
2252		break;
2253	default:
2254		ath_err(common, "Unknown power mode %u\n", mode);
2255		return false;
2256	}
2257	ah->power_mode = mode;
2258
2259	/*
2260	 * XXX: If this warning never comes up after a while then
2261	 * simply keep the ATH_DBG_WARN_ON_ONCE() but make
2262	 * ath9k_hw_setpower() return type void.
2263	 */
2264
2265	if (!(ah->ah_flags & AH_UNPLUGGED))
2266		ATH_DBG_WARN_ON_ONCE(!status);
2267
2268	return status;
2269}
2270EXPORT_SYMBOL(ath9k_hw_setpower);
2271
2272/*******************/
2273/* Beacon Handling */
2274/*******************/
2275
2276void ath9k_hw_beaconinit(struct ath_hw *ah, u32 next_beacon, u32 beacon_period)
2277{
2278	int flags = 0;
2279
2280	ENABLE_REGWRITE_BUFFER(ah);
2281
2282	switch (ah->opmode) {
2283	case NL80211_IFTYPE_ADHOC:
2284		REG_SET_BIT(ah, AR_TXCFG,
2285			    AR_TXCFG_ADHOC_BEACON_ATIM_TX_POLICY);
2286		fallthrough;
2287	case NL80211_IFTYPE_MESH_POINT:
2288	case NL80211_IFTYPE_AP:
2289		REG_WRITE(ah, AR_NEXT_TBTT_TIMER, next_beacon);
2290		REG_WRITE(ah, AR_NEXT_DMA_BEACON_ALERT, next_beacon -
2291			  TU_TO_USEC(ah->config.dma_beacon_response_time));
2292		REG_WRITE(ah, AR_NEXT_SWBA, next_beacon -
2293			  TU_TO_USEC(ah->config.sw_beacon_response_time));
2294		flags |=
2295			AR_TBTT_TIMER_EN | AR_DBA_TIMER_EN | AR_SWBA_TIMER_EN;
2296		break;
2297	default:
2298		ath_dbg(ath9k_hw_common(ah), BEACON,
2299			"%s: unsupported opmode: %d\n", __func__, ah->opmode);
2300		return;
2301	}
2302
2303	REG_WRITE(ah, AR_BEACON_PERIOD, beacon_period);
2304	REG_WRITE(ah, AR_DMA_BEACON_PERIOD, beacon_period);
2305	REG_WRITE(ah, AR_SWBA_PERIOD, beacon_period);
2306
2307	REGWRITE_BUFFER_FLUSH(ah);
2308
2309	REG_SET_BIT(ah, AR_TIMER_MODE, flags);
2310}
2311EXPORT_SYMBOL(ath9k_hw_beaconinit);
2312
2313void ath9k_hw_set_sta_beacon_timers(struct ath_hw *ah,
2314				    const struct ath9k_beacon_state *bs)
2315{
2316	u32 nextTbtt, beaconintval, dtimperiod, beacontimeout;
2317	struct ath9k_hw_capabilities *pCap = &ah->caps;
2318	struct ath_common *common = ath9k_hw_common(ah);
2319
2320	ENABLE_REGWRITE_BUFFER(ah);
2321
2322	REG_WRITE(ah, AR_NEXT_TBTT_TIMER, bs->bs_nexttbtt);
2323	REG_WRITE(ah, AR_BEACON_PERIOD, bs->bs_intval);
2324	REG_WRITE(ah, AR_DMA_BEACON_PERIOD, bs->bs_intval);
2325
2326	REGWRITE_BUFFER_FLUSH(ah);
2327
2328	REG_RMW_FIELD(ah, AR_RSSI_THR,
2329		      AR_RSSI_THR_BM_THR, bs->bs_bmissthreshold);
2330
2331	beaconintval = bs->bs_intval;
2332
2333	if (bs->bs_sleepduration > beaconintval)
2334		beaconintval = bs->bs_sleepduration;
2335
2336	dtimperiod = bs->bs_dtimperiod;
2337	if (bs->bs_sleepduration > dtimperiod)
2338		dtimperiod = bs->bs_sleepduration;
2339
2340	if (beaconintval == dtimperiod)
2341		nextTbtt = bs->bs_nextdtim;
2342	else
2343		nextTbtt = bs->bs_nexttbtt;
2344
2345	ath_dbg(common, BEACON, "next DTIM %u\n", bs->bs_nextdtim);
2346	ath_dbg(common, BEACON, "next beacon %u\n", nextTbtt);
2347	ath_dbg(common, BEACON, "beacon period %u\n", beaconintval);
2348	ath_dbg(common, BEACON, "DTIM period %u\n", dtimperiod);
2349
2350	ENABLE_REGWRITE_BUFFER(ah);
2351
2352	REG_WRITE(ah, AR_NEXT_DTIM, bs->bs_nextdtim - SLEEP_SLOP);
2353	REG_WRITE(ah, AR_NEXT_TIM, nextTbtt - SLEEP_SLOP);
2354
2355	REG_WRITE(ah, AR_SLEEP1,
2356		  SM((CAB_TIMEOUT_VAL << 3), AR_SLEEP1_CAB_TIMEOUT)
2357		  | AR_SLEEP1_ASSUME_DTIM);
2358
2359	if (pCap->hw_caps & ATH9K_HW_CAP_AUTOSLEEP)
2360		beacontimeout = (BEACON_TIMEOUT_VAL << 3);
2361	else
2362		beacontimeout = MIN_BEACON_TIMEOUT_VAL;
2363
2364	REG_WRITE(ah, AR_SLEEP2,
2365		  SM(beacontimeout, AR_SLEEP2_BEACON_TIMEOUT));
2366
2367	REG_WRITE(ah, AR_TIM_PERIOD, beaconintval);
2368	REG_WRITE(ah, AR_DTIM_PERIOD, dtimperiod);
2369
2370	REGWRITE_BUFFER_FLUSH(ah);
2371
2372	REG_SET_BIT(ah, AR_TIMER_MODE,
2373		    AR_TBTT_TIMER_EN | AR_TIM_TIMER_EN |
2374		    AR_DTIM_TIMER_EN);
2375
2376	/* TSF Out of Range Threshold */
2377	REG_WRITE(ah, AR_TSFOOR_THRESHOLD, bs->bs_tsfoor_threshold);
2378}
2379EXPORT_SYMBOL(ath9k_hw_set_sta_beacon_timers);
2380
2381/*******************/
2382/* HW Capabilities */
2383/*******************/
2384
2385static u8 fixup_chainmask(u8 chip_chainmask, u8 eeprom_chainmask)
2386{
2387	eeprom_chainmask &= chip_chainmask;
2388	if (eeprom_chainmask)
2389		return eeprom_chainmask;
2390	else
2391		return chip_chainmask;
2392}
2393
2394/**
2395 * ath9k_hw_dfs_tested - checks if DFS has been tested with used chipset
2396 * @ah: the atheros hardware data structure
2397 *
2398 * We enable DFS support upstream on chipsets which have passed a series
2399 * of tests. The testing requirements are going to be documented. Desired
2400 * test requirements are documented at:
2401 *
2402 * https://wireless.wiki.kernel.org/en/users/Drivers/ath9k/dfs
2403 *
2404 * Once a new chipset gets properly tested an individual commit can be used
2405 * to document the testing for DFS for that chipset.
2406 */
2407static bool ath9k_hw_dfs_tested(struct ath_hw *ah)
2408{
2409
2410	switch (ah->hw_version.macVersion) {
2411	/* for temporary testing DFS with 9280 */
2412	case AR_SREV_VERSION_9280:
2413	/* AR9580 will likely be our first target to get testing on */
2414	case AR_SREV_VERSION_9580:
2415		return true;
2416	default:
2417		return false;
2418	}
2419}
2420
2421static void ath9k_gpio_cap_init(struct ath_hw *ah)
2422{
2423	struct ath9k_hw_capabilities *pCap = &ah->caps;
2424
2425	if (AR_SREV_9271(ah)) {
2426		pCap->num_gpio_pins = AR9271_NUM_GPIO;
2427		pCap->gpio_mask = AR9271_GPIO_MASK;
2428	} else if (AR_DEVID_7010(ah)) {
2429		pCap->num_gpio_pins = AR7010_NUM_GPIO;
2430		pCap->gpio_mask = AR7010_GPIO_MASK;
2431	} else if (AR_SREV_9287(ah)) {
2432		pCap->num_gpio_pins = AR9287_NUM_GPIO;
2433		pCap->gpio_mask = AR9287_GPIO_MASK;
2434	} else if (AR_SREV_9285(ah)) {
2435		pCap->num_gpio_pins = AR9285_NUM_GPIO;
2436		pCap->gpio_mask = AR9285_GPIO_MASK;
2437	} else if (AR_SREV_9280(ah)) {
2438		pCap->num_gpio_pins = AR9280_NUM_GPIO;
2439		pCap->gpio_mask = AR9280_GPIO_MASK;
2440	} else if (AR_SREV_9300(ah)) {
2441		pCap->num_gpio_pins = AR9300_NUM_GPIO;
2442		pCap->gpio_mask = AR9300_GPIO_MASK;
2443	} else if (AR_SREV_9330(ah)) {
2444		pCap->num_gpio_pins = AR9330_NUM_GPIO;
2445		pCap->gpio_mask = AR9330_GPIO_MASK;
2446	} else if (AR_SREV_9340(ah)) {
2447		pCap->num_gpio_pins = AR9340_NUM_GPIO;
2448		pCap->gpio_mask = AR9340_GPIO_MASK;
2449	} else if (AR_SREV_9462(ah)) {
2450		pCap->num_gpio_pins = AR9462_NUM_GPIO;
2451		pCap->gpio_mask = AR9462_GPIO_MASK;
2452	} else if (AR_SREV_9485(ah)) {
2453		pCap->num_gpio_pins = AR9485_NUM_GPIO;
2454		pCap->gpio_mask = AR9485_GPIO_MASK;
2455	} else if (AR_SREV_9531(ah)) {
2456		pCap->num_gpio_pins = AR9531_NUM_GPIO;
2457		pCap->gpio_mask = AR9531_GPIO_MASK;
2458	} else if (AR_SREV_9550(ah)) {
2459		pCap->num_gpio_pins = AR9550_NUM_GPIO;
2460		pCap->gpio_mask = AR9550_GPIO_MASK;
2461	} else if (AR_SREV_9561(ah)) {
2462		pCap->num_gpio_pins = AR9561_NUM_GPIO;
2463		pCap->gpio_mask = AR9561_GPIO_MASK;
2464	} else if (AR_SREV_9565(ah)) {
2465		pCap->num_gpio_pins = AR9565_NUM_GPIO;
2466		pCap->gpio_mask = AR9565_GPIO_MASK;
2467	} else if (AR_SREV_9580(ah)) {
2468		pCap->num_gpio_pins = AR9580_NUM_GPIO;
2469		pCap->gpio_mask = AR9580_GPIO_MASK;
2470	} else {
2471		pCap->num_gpio_pins = AR_NUM_GPIO;
2472		pCap->gpio_mask = AR_GPIO_MASK;
2473	}
2474}
2475
2476int ath9k_hw_fill_cap_info(struct ath_hw *ah)
2477{
2478	struct ath9k_hw_capabilities *pCap = &ah->caps;
2479	struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
2480	struct ath_common *common = ath9k_hw_common(ah);
2481
2482	u16 eeval;
2483	u8 ant_div_ctl1, tx_chainmask, rx_chainmask;
2484
2485	eeval = ah->eep_ops->get_eeprom(ah, EEP_REG_0);
2486	regulatory->current_rd = eeval;
2487
2488	if (ah->opmode != NL80211_IFTYPE_AP &&
2489	    ah->hw_version.subvendorid == AR_SUBVENDOR_ID_NEW_A) {
2490		if (regulatory->current_rd == 0x64 ||
2491		    regulatory->current_rd == 0x65)
2492			regulatory->current_rd += 5;
2493		else if (regulatory->current_rd == 0x41)
2494			regulatory->current_rd = 0x43;
2495		ath_dbg(common, REGULATORY, "regdomain mapped to 0x%x\n",
2496			regulatory->current_rd);
2497	}
2498
2499	eeval = ah->eep_ops->get_eeprom(ah, EEP_OP_MODE);
2500
2501	if (eeval & AR5416_OPFLAGS_11A) {
2502		if (ah->disable_5ghz)
2503			ath_warn(common, "disabling 5GHz band\n");
2504		else
2505			pCap->hw_caps |= ATH9K_HW_CAP_5GHZ;
2506	}
2507
2508	if (eeval & AR5416_OPFLAGS_11G) {
2509		if (ah->disable_2ghz)
2510			ath_warn(common, "disabling 2GHz band\n");
2511		else
2512			pCap->hw_caps |= ATH9K_HW_CAP_2GHZ;
2513	}
2514
2515	if ((pCap->hw_caps & (ATH9K_HW_CAP_2GHZ | ATH9K_HW_CAP_5GHZ)) == 0) {
2516		ath_err(common, "both bands are disabled\n");
2517		return -EINVAL;
2518	}
2519
2520	ath9k_gpio_cap_init(ah);
2521
2522	if (AR_SREV_9485(ah) ||
2523	    AR_SREV_9285(ah) ||
2524	    AR_SREV_9330(ah) ||
2525	    AR_SREV_9565(ah))
2526		pCap->chip_chainmask = 1;
2527	else if (!AR_SREV_9280_20_OR_LATER(ah))
2528		pCap->chip_chainmask = 7;
2529	else if (!AR_SREV_9300_20_OR_LATER(ah) ||
2530		 AR_SREV_9340(ah) ||
2531		 AR_SREV_9462(ah) ||
2532		 AR_SREV_9531(ah))
2533		pCap->chip_chainmask = 3;
2534	else
2535		pCap->chip_chainmask = 7;
2536
2537	pCap->tx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_TX_MASK);
2538	/*
2539	 * For AR9271 we will temporarily use the rx chainmax as read from
2540	 * the EEPROM.
2541	 */
2542	if ((ah->hw_version.devid == AR5416_DEVID_PCI) &&
2543	    !(eeval & AR5416_OPFLAGS_11A) &&
2544	    !(AR_SREV_9271(ah)))
2545		/* CB71: GPIO 0 is pulled down to indicate 3 rx chains */
2546		pCap->rx_chainmask = ath9k_hw_gpio_get(ah, 0) ? 0x5 : 0x7;
2547	else if (AR_SREV_9100(ah))
2548		pCap->rx_chainmask = 0x7;
2549	else
2550		/* Use rx_chainmask from EEPROM. */
2551		pCap->rx_chainmask = ah->eep_ops->get_eeprom(ah, EEP_RX_MASK);
2552
2553	pCap->tx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->tx_chainmask);
2554	pCap->rx_chainmask = fixup_chainmask(pCap->chip_chainmask, pCap->rx_chainmask);
2555	ah->txchainmask = pCap->tx_chainmask;
2556	ah->rxchainmask = pCap->rx_chainmask;
2557
2558	ah->misc_mode |= AR_PCU_MIC_NEW_LOC_ENA;
2559
2560	/* enable key search for every frame in an aggregate */
2561	if (AR_SREV_9300_20_OR_LATER(ah))
2562		ah->misc_mode |= AR_PCU_ALWAYS_PERFORM_KEYSEARCH;
2563
2564	common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
2565
2566	if (ah->hw_version.devid != AR2427_DEVID_PCIE)
2567		pCap->hw_caps |= ATH9K_HW_CAP_HT;
2568	else
2569		pCap->hw_caps &= ~ATH9K_HW_CAP_HT;
2570
2571	if (AR_SREV_9160_10_OR_LATER(ah) || AR_SREV_9100(ah))
2572		pCap->rts_aggr_limit = ATH_AMPDU_LIMIT_MAX;
2573	else
2574		pCap->rts_aggr_limit = (8 * 1024);
2575
2576#ifdef CONFIG_ATH9K_RFKILL
2577	ah->rfsilent = ah->eep_ops->get_eeprom(ah, EEP_RF_SILENT);
2578	if (ah->rfsilent & EEP_RFSILENT_ENABLED) {
2579		ah->rfkill_gpio =
2580			MS(ah->rfsilent, EEP_RFSILENT_GPIO_SEL);
2581		ah->rfkill_polarity =
2582			MS(ah->rfsilent, EEP_RFSILENT_POLARITY);
2583
2584		pCap->hw_caps |= ATH9K_HW_CAP_RFSILENT;
2585	}
2586#endif
2587	if (AR_SREV_9271(ah) || AR_SREV_9300_20_OR_LATER(ah))
2588		pCap->hw_caps |= ATH9K_HW_CAP_AUTOSLEEP;
2589	else
2590		pCap->hw_caps &= ~ATH9K_HW_CAP_AUTOSLEEP;
2591
2592	if (AR_SREV_9280(ah) || AR_SREV_9285(ah))
2593		pCap->hw_caps &= ~ATH9K_HW_CAP_4KB_SPLITTRANS;
2594	else
2595		pCap->hw_caps |= ATH9K_HW_CAP_4KB_SPLITTRANS;
2596
2597	if (AR_SREV_9300_20_OR_LATER(ah)) {
2598		pCap->hw_caps |= ATH9K_HW_CAP_EDMA | ATH9K_HW_CAP_FASTCLOCK;
2599		if (!AR_SREV_9330(ah) && !AR_SREV_9485(ah) &&
2600		    !AR_SREV_9561(ah) && !AR_SREV_9565(ah))
2601			pCap->hw_caps |= ATH9K_HW_CAP_LDPC;
2602
2603		pCap->rx_hp_qdepth = ATH9K_HW_RX_HP_QDEPTH;
2604		pCap->rx_lp_qdepth = ATH9K_HW_RX_LP_QDEPTH;
2605		pCap->rx_status_len = sizeof(struct ar9003_rxs);
2606		pCap->tx_desc_len = sizeof(struct ar9003_txc);
2607		pCap->txs_len = sizeof(struct ar9003_txs);
2608	} else {
2609		pCap->tx_desc_len = sizeof(struct ath_desc);
2610		if (AR_SREV_9280_20(ah))
2611			pCap->hw_caps |= ATH9K_HW_CAP_FASTCLOCK;
2612	}
2613
2614	if (AR_SREV_9300_20_OR_LATER(ah))
2615		pCap->hw_caps |= ATH9K_HW_CAP_RAC_SUPPORTED;
2616
2617	if (AR_SREV_9561(ah))
2618		ah->ent_mode = 0x3BDA000;
2619	else if (AR_SREV_9300_20_OR_LATER(ah))
2620		ah->ent_mode = REG_READ(ah, AR_ENT_OTP);
2621
2622	if (AR_SREV_9287_11_OR_LATER(ah) || AR_SREV_9271(ah))
2623		pCap->hw_caps |= ATH9K_HW_CAP_SGI_20;
2624
2625	if (AR_SREV_9285(ah)) {
2626		if (ah->eep_ops->get_eeprom(ah, EEP_MODAL_VER) >= 3) {
2627			ant_div_ctl1 =
2628				ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2629			if ((ant_div_ctl1 & 0x1) && ((ant_div_ctl1 >> 3) & 0x1)) {
2630				pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2631				ath_info(common, "Enable LNA combining\n");
2632			}
2633		}
2634	}
2635
2636	if (AR_SREV_9300_20_OR_LATER(ah)) {
2637		if (ah->eep_ops->get_eeprom(ah, EEP_CHAIN_MASK_REDUCE))
2638			pCap->hw_caps |= ATH9K_HW_CAP_APM;
2639	}
2640
2641	if (AR_SREV_9330(ah) || AR_SREV_9485(ah) || AR_SREV_9565(ah)) {
2642		ant_div_ctl1 = ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
2643		if ((ant_div_ctl1 >> 0x6) == 0x3) {
2644			pCap->hw_caps |= ATH9K_HW_CAP_ANT_DIV_COMB;
2645			ath_info(common, "Enable LNA combining\n");
2646		}
2647	}
2648
2649	if (ath9k_hw_dfs_tested(ah))
2650		pCap->hw_caps |= ATH9K_HW_CAP_DFS;
2651
2652	tx_chainmask = pCap->tx_chainmask;
2653	rx_chainmask = pCap->rx_chainmask;
2654	while (tx_chainmask || rx_chainmask) {
2655		if (tx_chainmask & BIT(0))
2656			pCap->max_txchains++;
2657		if (rx_chainmask & BIT(0))
2658			pCap->max_rxchains++;
2659
2660		tx_chainmask >>= 1;
2661		rx_chainmask >>= 1;
2662	}
2663
2664	if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
2665		if (!(ah->ent_mode & AR_ENT_OTP_49GHZ_DISABLE))
2666			pCap->hw_caps |= ATH9K_HW_CAP_MCI;
2667
2668		if (AR_SREV_9462_20_OR_LATER(ah))
2669			pCap->hw_caps |= ATH9K_HW_CAP_RTT;
2670	}
2671
2672	if (AR_SREV_9300_20_OR_LATER(ah) &&
2673	    ah->eep_ops->get_eeprom(ah, EEP_PAPRD))
2674			pCap->hw_caps |= ATH9K_HW_CAP_PAPRD;
2675
2676#ifdef CONFIG_ATH9K_WOW
2677	if (AR_SREV_9462_20_OR_LATER(ah) || AR_SREV_9565_11_OR_LATER(ah))
2678		ah->wow.max_patterns = MAX_NUM_PATTERN;
2679	else
2680		ah->wow.max_patterns = MAX_NUM_PATTERN_LEGACY;
2681#endif
2682
2683	return 0;
2684}
2685
2686/****************************/
2687/* GPIO / RFKILL / Antennae */
2688/****************************/
2689
2690static void ath9k_hw_gpio_cfg_output_mux(struct ath_hw *ah, u32 gpio, u32 type)
2691{
2692	int addr;
2693	u32 gpio_shift, tmp;
2694
2695	if (gpio > 11)
2696		addr = AR_GPIO_OUTPUT_MUX3(ah);
2697	else if (gpio > 5)
2698		addr = AR_GPIO_OUTPUT_MUX2(ah);
2699	else
2700		addr = AR_GPIO_OUTPUT_MUX1(ah);
2701
2702	gpio_shift = (gpio % 6) * 5;
2703
2704	if (AR_SREV_9280_20_OR_LATER(ah) ||
2705	    (addr != AR_GPIO_OUTPUT_MUX1(ah))) {
2706		REG_RMW(ah, addr, (type << gpio_shift),
2707			(0x1f << gpio_shift));
2708	} else {
2709		tmp = REG_READ(ah, addr);
2710		tmp = ((tmp & 0x1F0) << 1) | (tmp & ~0x1F0);
2711		tmp &= ~(0x1f << gpio_shift);
2712		tmp |= (type << gpio_shift);
2713		REG_WRITE(ah, addr, tmp);
2714	}
2715}
2716
2717/* BSP should set the corresponding MUX register correctly.
2718 */
2719static void ath9k_hw_gpio_cfg_soc(struct ath_hw *ah, u32 gpio, bool out,
2720				  const char *label)
2721{
2722	int err;
2723
2724	if (ah->caps.gpio_requested & BIT(gpio))
2725		return;
2726
2727	err = devm_gpio_request_one(ah->dev, gpio, out ? GPIOF_OUT_INIT_LOW : GPIOF_IN, label);
2728	if (err) {
2729		ath_err(ath9k_hw_common(ah), "request GPIO%d failed:%d\n",
2730			gpio, err);
2731		return;
2732	}
2733
2734	ah->caps.gpio_requested |= BIT(gpio);
2735}
2736
2737static void ath9k_hw_gpio_cfg_wmac(struct ath_hw *ah, u32 gpio, bool out,
2738				   u32 ah_signal_type)
2739{
2740	u32 gpio_set, gpio_shift = gpio;
2741
2742	if (AR_DEVID_7010(ah)) {
2743		gpio_set = out ?
2744			AR7010_GPIO_OE_AS_OUTPUT : AR7010_GPIO_OE_AS_INPUT;
2745		REG_RMW(ah, AR7010_GPIO_OE, gpio_set << gpio_shift,
2746			AR7010_GPIO_OE_MASK << gpio_shift);
2747	} else if (AR_SREV_SOC(ah)) {
2748		gpio_set = out ? 1 : 0;
2749		REG_RMW(ah, AR_GPIO_OE_OUT(ah), gpio_set << gpio_shift,
2750			gpio_set << gpio_shift);
2751	} else {
2752		gpio_shift = gpio << 1;
2753		gpio_set = out ?
2754			AR_GPIO_OE_OUT_DRV_ALL : AR_GPIO_OE_OUT_DRV_NO;
2755		REG_RMW(ah, AR_GPIO_OE_OUT(ah), gpio_set << gpio_shift,
2756			AR_GPIO_OE_OUT_DRV << gpio_shift);
2757
2758		if (out)
2759			ath9k_hw_gpio_cfg_output_mux(ah, gpio, ah_signal_type);
2760	}
2761}
2762
2763static void ath9k_hw_gpio_request(struct ath_hw *ah, u32 gpio, bool out,
2764				  const char *label, u32 ah_signal_type)
2765{
2766	WARN_ON(gpio >= ah->caps.num_gpio_pins);
2767
2768	if (BIT(gpio) & ah->caps.gpio_mask)
2769		ath9k_hw_gpio_cfg_wmac(ah, gpio, out, ah_signal_type);
2770	else if (AR_SREV_SOC(ah))
2771		ath9k_hw_gpio_cfg_soc(ah, gpio, out, label);
2772	else
2773		WARN_ON(1);
2774}
2775
2776void ath9k_hw_gpio_request_in(struct ath_hw *ah, u32 gpio, const char *label)
2777{
2778	ath9k_hw_gpio_request(ah, gpio, false, label, 0);
2779}
2780EXPORT_SYMBOL(ath9k_hw_gpio_request_in);
2781
2782void ath9k_hw_gpio_request_out(struct ath_hw *ah, u32 gpio, const char *label,
2783			       u32 ah_signal_type)
2784{
2785	ath9k_hw_gpio_request(ah, gpio, true, label, ah_signal_type);
2786}
2787EXPORT_SYMBOL(ath9k_hw_gpio_request_out);
2788
2789void ath9k_hw_gpio_free(struct ath_hw *ah, u32 gpio)
2790{
2791	if (!AR_SREV_SOC(ah))
2792		return;
2793
2794	WARN_ON(gpio >= ah->caps.num_gpio_pins);
2795
2796	if (ah->caps.gpio_requested & BIT(gpio))
2797		ah->caps.gpio_requested &= ~BIT(gpio);
2798}
2799EXPORT_SYMBOL(ath9k_hw_gpio_free);
2800
2801u32 ath9k_hw_gpio_get(struct ath_hw *ah, u32 gpio)
2802{
2803	u32 val = 0xffffffff;
2804
2805#define MS_REG_READ(x, y) \
2806	(MS(REG_READ(ah, AR_GPIO_IN_OUT(ah)), x##_GPIO_IN_VAL) & BIT(y))
2807
2808	WARN_ON(gpio >= ah->caps.num_gpio_pins);
2809
2810	if (BIT(gpio) & ah->caps.gpio_mask) {
2811		if (AR_SREV_9271(ah))
2812			val = MS_REG_READ(AR9271, gpio);
2813		else if (AR_SREV_9287(ah))
2814			val = MS_REG_READ(AR9287, gpio);
2815		else if (AR_SREV_9285(ah))
2816			val = MS_REG_READ(AR9285, gpio);
2817		else if (AR_SREV_9280(ah))
2818			val = MS_REG_READ(AR928X, gpio);
2819		else if (AR_DEVID_7010(ah))
2820			val = REG_READ(ah, AR7010_GPIO_IN) & BIT(gpio);
2821		else if (AR_SREV_9300_20_OR_LATER(ah))
2822			val = REG_READ(ah, AR_GPIO_IN(ah)) & BIT(gpio);
2823		else
2824			val = MS_REG_READ(AR, gpio);
2825	} else if (BIT(gpio) & ah->caps.gpio_requested) {
2826		val = gpio_get_value(gpio) & BIT(gpio);
2827	} else {
2828		WARN_ON(1);
2829	}
2830
2831	return !!val;
2832}
2833EXPORT_SYMBOL(ath9k_hw_gpio_get);
2834
2835void ath9k_hw_set_gpio(struct ath_hw *ah, u32 gpio, u32 val)
2836{
2837	WARN_ON(gpio >= ah->caps.num_gpio_pins);
2838
2839	if (AR_DEVID_7010(ah) || AR_SREV_9271(ah))
2840		val = !val;
2841	else
2842		val = !!val;
2843
2844	if (BIT(gpio) & ah->caps.gpio_mask) {
2845		u32 out_addr = AR_DEVID_7010(ah) ?
2846			AR7010_GPIO_OUT : AR_GPIO_IN_OUT(ah);
2847
2848		REG_RMW(ah, out_addr, val << gpio, BIT(gpio));
2849	} else if (BIT(gpio) & ah->caps.gpio_requested) {
2850		gpio_set_value(gpio, val);
2851	} else {
2852		WARN_ON(1);
2853	}
2854}
2855EXPORT_SYMBOL(ath9k_hw_set_gpio);
2856
2857void ath9k_hw_setantenna(struct ath_hw *ah, u32 antenna)
2858{
2859	REG_WRITE(ah, AR_DEF_ANTENNA, (antenna & 0x7));
2860}
2861EXPORT_SYMBOL(ath9k_hw_setantenna);
2862
2863/*********************/
2864/* General Operation */
2865/*********************/
2866
2867u32 ath9k_hw_getrxfilter(struct ath_hw *ah)
2868{
2869	u32 bits = REG_READ(ah, AR_RX_FILTER);
2870	u32 phybits = REG_READ(ah, AR_PHY_ERR);
2871
2872	if (phybits & AR_PHY_ERR_RADAR)
2873		bits |= ATH9K_RX_FILTER_PHYRADAR;
2874	if (phybits & (AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING))
2875		bits |= ATH9K_RX_FILTER_PHYERR;
2876
2877	return bits;
2878}
2879EXPORT_SYMBOL(ath9k_hw_getrxfilter);
2880
2881void ath9k_hw_setrxfilter(struct ath_hw *ah, u32 bits)
2882{
2883	u32 phybits;
2884
2885	ENABLE_REGWRITE_BUFFER(ah);
2886
2887	REG_WRITE(ah, AR_RX_FILTER, bits);
2888
2889	phybits = 0;
2890	if (bits & ATH9K_RX_FILTER_PHYRADAR)
2891		phybits |= AR_PHY_ERR_RADAR;
2892	if (bits & ATH9K_RX_FILTER_PHYERR)
2893		phybits |= AR_PHY_ERR_OFDM_TIMING | AR_PHY_ERR_CCK_TIMING;
2894	REG_WRITE(ah, AR_PHY_ERR, phybits);
2895
2896	if (phybits)
2897		REG_SET_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2898	else
2899		REG_CLR_BIT(ah, AR_RXCFG, AR_RXCFG_ZLFDMA);
2900
2901	REGWRITE_BUFFER_FLUSH(ah);
2902}
2903EXPORT_SYMBOL(ath9k_hw_setrxfilter);
2904
2905bool ath9k_hw_phy_disable(struct ath_hw *ah)
2906{
2907	if (ath9k_hw_mci_is_enabled(ah))
2908		ar9003_mci_bt_gain_ctrl(ah);
2909
2910	if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_WARM))
2911		return false;
2912
2913	ath9k_hw_init_pll(ah, NULL);
2914	ah->htc_reset_init = true;
2915	return true;
2916}
2917EXPORT_SYMBOL(ath9k_hw_phy_disable);
2918
2919bool ath9k_hw_disable(struct ath_hw *ah)
2920{
2921	if (!ath9k_hw_setpower(ah, ATH9K_PM_AWAKE))
2922		return false;
2923
2924	if (!ath9k_hw_set_reset_reg(ah, ATH9K_RESET_COLD))
2925		return false;
2926
2927	ath9k_hw_init_pll(ah, NULL);
2928	return true;
2929}
2930EXPORT_SYMBOL(ath9k_hw_disable);
2931
2932static int get_antenna_gain(struct ath_hw *ah, struct ath9k_channel *chan)
2933{
2934	enum eeprom_param gain_param;
2935
2936	if (IS_CHAN_2GHZ(chan))
2937		gain_param = EEP_ANTENNA_GAIN_2G;
2938	else
2939		gain_param = EEP_ANTENNA_GAIN_5G;
2940
2941	return ah->eep_ops->get_eeprom(ah, gain_param);
2942}
2943
2944void ath9k_hw_apply_txpower(struct ath_hw *ah, struct ath9k_channel *chan,
2945			    bool test)
2946{
2947	struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2948	struct ieee80211_channel *channel;
2949	int chan_pwr, new_pwr;
2950	u16 ctl = NO_CTL;
2951
2952	if (!chan)
2953		return;
2954
2955	if (!test)
2956		ctl = ath9k_regd_get_ctl(reg, chan);
2957
2958	channel = chan->chan;
2959	chan_pwr = min_t(int, channel->max_power * 2, MAX_COMBINED_POWER);
2960	new_pwr = min_t(int, chan_pwr, reg->power_limit);
2961
2962	ah->eep_ops->set_txpower(ah, chan, ctl,
2963				 get_antenna_gain(ah, chan), new_pwr, test);
2964}
2965
2966void ath9k_hw_set_txpowerlimit(struct ath_hw *ah, u32 limit, bool test)
2967{
2968	struct ath_regulatory *reg = ath9k_hw_regulatory(ah);
2969	struct ath9k_channel *chan = ah->curchan;
2970	struct ieee80211_channel *channel = chan->chan;
2971
2972	reg->power_limit = min_t(u32, limit, MAX_COMBINED_POWER);
2973	if (test)
2974		channel->max_power = MAX_COMBINED_POWER / 2;
2975
2976	ath9k_hw_apply_txpower(ah, chan, test);
2977
2978	if (test)
2979		channel->max_power = DIV_ROUND_UP(reg->max_power_level, 2);
2980}
2981EXPORT_SYMBOL(ath9k_hw_set_txpowerlimit);
2982
2983void ath9k_hw_setopmode(struct ath_hw *ah)
2984{
2985	ath9k_hw_set_operating_mode(ah, ah->opmode);
2986}
2987EXPORT_SYMBOL(ath9k_hw_setopmode);
2988
2989void ath9k_hw_setmcastfilter(struct ath_hw *ah, u32 filter0, u32 filter1)
2990{
2991	REG_WRITE(ah, AR_MCAST_FIL0, filter0);
2992	REG_WRITE(ah, AR_MCAST_FIL1, filter1);
2993}
2994EXPORT_SYMBOL(ath9k_hw_setmcastfilter);
2995
2996void ath9k_hw_write_associd(struct ath_hw *ah)
2997{
2998	struct ath_common *common = ath9k_hw_common(ah);
2999
3000	REG_WRITE(ah, AR_BSS_ID0, get_unaligned_le32(common->curbssid));
3001	REG_WRITE(ah, AR_BSS_ID1, get_unaligned_le16(common->curbssid + 4) |
3002		  ((common->curaid & 0x3fff) << AR_BSS_ID1_AID_S));
3003}
3004EXPORT_SYMBOL(ath9k_hw_write_associd);
3005
3006#define ATH9K_MAX_TSF_READ 10
3007
3008u64 ath9k_hw_gettsf64(struct ath_hw *ah)
3009{
3010	u32 tsf_lower, tsf_upper1, tsf_upper2;
3011	int i;
3012
3013	tsf_upper1 = REG_READ(ah, AR_TSF_U32);
3014	for (i = 0; i < ATH9K_MAX_TSF_READ; i++) {
3015		tsf_lower = REG_READ(ah, AR_TSF_L32);
3016		tsf_upper2 = REG_READ(ah, AR_TSF_U32);
3017		if (tsf_upper2 == tsf_upper1)
3018			break;
3019		tsf_upper1 = tsf_upper2;
3020	}
3021
3022	WARN_ON( i == ATH9K_MAX_TSF_READ );
3023
3024	return (((u64)tsf_upper1 << 32) | tsf_lower);
3025}
3026EXPORT_SYMBOL(ath9k_hw_gettsf64);
3027
3028void ath9k_hw_settsf64(struct ath_hw *ah, u64 tsf64)
3029{
3030	REG_WRITE(ah, AR_TSF_L32, tsf64 & 0xffffffff);
3031	REG_WRITE(ah, AR_TSF_U32, (tsf64 >> 32) & 0xffffffff);
3032}
3033EXPORT_SYMBOL(ath9k_hw_settsf64);
3034
3035void ath9k_hw_reset_tsf(struct ath_hw *ah)
3036{
3037	if (!ath9k_hw_wait(ah, AR_SLP32_MODE, AR_SLP32_TSF_WRITE_STATUS, 0,
3038			   AH_TSF_WRITE_TIMEOUT))
3039		ath_dbg(ath9k_hw_common(ah), RESET,
3040			"AR_SLP32_TSF_WRITE_STATUS limit exceeded\n");
3041
3042	REG_WRITE(ah, AR_RESET_TSF, AR_RESET_TSF_ONCE);
3043}
3044EXPORT_SYMBOL(ath9k_hw_reset_tsf);
3045
3046void ath9k_hw_set_tsfadjust(struct ath_hw *ah, bool set)
3047{
3048	if (set)
3049		ah->misc_mode |= AR_PCU_TX_ADD_TSF;
3050	else
3051		ah->misc_mode &= ~AR_PCU_TX_ADD_TSF;
3052}
3053EXPORT_SYMBOL(ath9k_hw_set_tsfadjust);
3054
3055void ath9k_hw_set11nmac2040(struct ath_hw *ah, struct ath9k_channel *chan)
3056{
3057	u32 macmode;
3058
3059	if (IS_CHAN_HT40(chan) && !ah->config.cwm_ignore_extcca)
3060		macmode = AR_2040_JOINED_RX_CLEAR;
3061	else
3062		macmode = 0;
3063
3064	REG_WRITE(ah, AR_2040_MODE, macmode);
3065}
3066
3067/* HW Generic timers configuration */
3068
3069static const struct ath_gen_timer_configuration gen_tmr_configuration[] =
3070{
3071	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3072	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3073	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3074	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3075	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3076	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3077	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3078	{AR_NEXT_NDP_TIMER, AR_NDP_PERIOD, AR_TIMER_MODE, 0x0080},
3079	{AR_NEXT_NDP2_TIMER, AR_NDP2_PERIOD, AR_NDP2_TIMER_MODE, 0x0001},
3080	{AR_NEXT_NDP2_TIMER + 1*4, AR_NDP2_PERIOD + 1*4,
3081				AR_NDP2_TIMER_MODE, 0x0002},
3082	{AR_NEXT_NDP2_TIMER + 2*4, AR_NDP2_PERIOD + 2*4,
3083				AR_NDP2_TIMER_MODE, 0x0004},
3084	{AR_NEXT_NDP2_TIMER + 3*4, AR_NDP2_PERIOD + 3*4,
3085				AR_NDP2_TIMER_MODE, 0x0008},
3086	{AR_NEXT_NDP2_TIMER + 4*4, AR_NDP2_PERIOD + 4*4,
3087				AR_NDP2_TIMER_MODE, 0x0010},
3088	{AR_NEXT_NDP2_TIMER + 5*4, AR_NDP2_PERIOD + 5*4,
3089				AR_NDP2_TIMER_MODE, 0x0020},
3090	{AR_NEXT_NDP2_TIMER + 6*4, AR_NDP2_PERIOD + 6*4,
3091				AR_NDP2_TIMER_MODE, 0x0040},
3092	{AR_NEXT_NDP2_TIMER + 7*4, AR_NDP2_PERIOD + 7*4,
3093				AR_NDP2_TIMER_MODE, 0x0080}
3094};
3095
3096/* HW generic timer primitives */
3097
3098u32 ath9k_hw_gettsf32(struct ath_hw *ah)
3099{
3100	return REG_READ(ah, AR_TSF_L32);
3101}
3102EXPORT_SYMBOL(ath9k_hw_gettsf32);
3103
3104void ath9k_hw_gen_timer_start_tsf2(struct ath_hw *ah)
3105{
3106	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3107
3108	if (timer_table->tsf2_enabled) {
3109		REG_SET_BIT(ah, AR_DIRECT_CONNECT, AR_DC_AP_STA_EN);
3110		REG_SET_BIT(ah, AR_RESET_TSF, AR_RESET_TSF2_ONCE);
3111	}
3112}
3113
3114struct ath_gen_timer *ath_gen_timer_alloc(struct ath_hw *ah,
3115					  void (*trigger)(void *),
3116					  void (*overflow)(void *),
3117					  void *arg,
3118					  u8 timer_index)
3119{
3120	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3121	struct ath_gen_timer *timer;
3122
3123	if ((timer_index < AR_FIRST_NDP_TIMER) ||
3124	    (timer_index >= ATH_MAX_GEN_TIMER))
3125		return NULL;
3126
3127	if ((timer_index > AR_FIRST_NDP_TIMER) &&
3128	    !AR_SREV_9300_20_OR_LATER(ah))
3129		return NULL;
3130
3131	timer = kzalloc(sizeof(struct ath_gen_timer), GFP_KERNEL);
3132	if (timer == NULL)
3133		return NULL;
3134
3135	/* allocate a hardware generic timer slot */
3136	timer_table->timers[timer_index] = timer;
3137	timer->index = timer_index;
3138	timer->trigger = trigger;
3139	timer->overflow = overflow;
3140	timer->arg = arg;
3141
3142	if ((timer_index > AR_FIRST_NDP_TIMER) && !timer_table->tsf2_enabled) {
3143		timer_table->tsf2_enabled = true;
3144		ath9k_hw_gen_timer_start_tsf2(ah);
3145	}
3146
3147	return timer;
3148}
3149EXPORT_SYMBOL(ath_gen_timer_alloc);
3150
3151void ath9k_hw_gen_timer_start(struct ath_hw *ah,
3152			      struct ath_gen_timer *timer,
3153			      u32 timer_next,
3154			      u32 timer_period)
3155{
3156	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3157	u32 mask = 0;
3158
3159	timer_table->timer_mask |= BIT(timer->index);
3160
3161	/*
3162	 * Program generic timer registers
3163	 */
3164	REG_WRITE(ah, gen_tmr_configuration[timer->index].next_addr,
3165		 timer_next);
3166	REG_WRITE(ah, gen_tmr_configuration[timer->index].period_addr,
3167		  timer_period);
3168	REG_SET_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3169		    gen_tmr_configuration[timer->index].mode_mask);
3170
3171	if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3172		/*
3173		 * Starting from AR9462, each generic timer can select which tsf
3174		 * to use. But we still follow the old rule, 0 - 7 use tsf and
3175		 * 8 - 15  use tsf2.
3176		 */
3177		if ((timer->index < AR_GEN_TIMER_BANK_1_LEN))
3178			REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3179				       (1 << timer->index));
3180		else
3181			REG_SET_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3182				       (1 << timer->index));
3183	}
3184
3185	if (timer->trigger)
3186		mask |= SM(AR_GENTMR_BIT(timer->index),
3187			   AR_IMR_S5_GENTIMER_TRIG);
3188	if (timer->overflow)
3189		mask |= SM(AR_GENTMR_BIT(timer->index),
3190			   AR_IMR_S5_GENTIMER_THRESH);
3191
3192	REG_SET_BIT(ah, AR_IMR_S5, mask);
3193
3194	if ((ah->imask & ATH9K_INT_GENTIMER) == 0) {
3195		ah->imask |= ATH9K_INT_GENTIMER;
3196		ath9k_hw_set_interrupts(ah);
3197	}
3198}
3199EXPORT_SYMBOL(ath9k_hw_gen_timer_start);
3200
3201void ath9k_hw_gen_timer_stop(struct ath_hw *ah, struct ath_gen_timer *timer)
3202{
3203	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3204
3205	/* Clear generic timer enable bits. */
3206	REG_CLR_BIT(ah, gen_tmr_configuration[timer->index].mode_addr,
3207			gen_tmr_configuration[timer->index].mode_mask);
3208
3209	if (AR_SREV_9462(ah) || AR_SREV_9565(ah)) {
3210		/*
3211		 * Need to switch back to TSF if it was using TSF2.
3212		 */
3213		if ((timer->index >= AR_GEN_TIMER_BANK_1_LEN)) {
3214			REG_CLR_BIT(ah, AR_MAC_PCU_GEN_TIMER_TSF_SEL,
3215				    (1 << timer->index));
3216		}
3217	}
3218
3219	/* Disable both trigger and thresh interrupt masks */
3220	REG_CLR_BIT(ah, AR_IMR_S5,
3221		(SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_THRESH) |
3222		SM(AR_GENTMR_BIT(timer->index), AR_IMR_S5_GENTIMER_TRIG)));
3223
3224	timer_table->timer_mask &= ~BIT(timer->index);
3225
3226	if (timer_table->timer_mask == 0) {
3227		ah->imask &= ~ATH9K_INT_GENTIMER;
3228		ath9k_hw_set_interrupts(ah);
3229	}
3230}
3231EXPORT_SYMBOL(ath9k_hw_gen_timer_stop);
3232
3233void ath_gen_timer_free(struct ath_hw *ah, struct ath_gen_timer *timer)
3234{
3235	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3236
3237	/* free the hardware generic timer slot */
3238	timer_table->timers[timer->index] = NULL;
3239	kfree(timer);
3240}
3241EXPORT_SYMBOL(ath_gen_timer_free);
3242
3243/*
3244 * Generic Timer Interrupts handling
3245 */
3246void ath_gen_timer_isr(struct ath_hw *ah)
3247{
3248	struct ath_gen_timer_table *timer_table = &ah->hw_gen_timers;
3249	struct ath_gen_timer *timer;
3250	unsigned long trigger_mask, thresh_mask;
3251	unsigned int index;
3252
3253	/* get hardware generic timer interrupt status */
3254	trigger_mask = ah->intr_gen_timer_trigger;
3255	thresh_mask = ah->intr_gen_timer_thresh;
3256	trigger_mask &= timer_table->timer_mask;
3257	thresh_mask &= timer_table->timer_mask;
3258
3259	for_each_set_bit(index, &thresh_mask, ARRAY_SIZE(timer_table->timers)) {
3260		timer = timer_table->timers[index];
3261		if (!timer)
3262		    continue;
3263		if (!timer->overflow)
3264		    continue;
3265
3266		trigger_mask &= ~BIT(index);
3267		timer->overflow(timer->arg);
3268	}
3269
3270	for_each_set_bit(index, &trigger_mask, ARRAY_SIZE(timer_table->timers)) {
3271		timer = timer_table->timers[index];
3272		if (!timer)
3273		    continue;
3274		if (!timer->trigger)
3275		    continue;
3276		timer->trigger(timer->arg);
3277	}
3278}
3279EXPORT_SYMBOL(ath_gen_timer_isr);
3280
3281/********/
3282/* HTC  */
3283/********/
3284
3285static struct {
3286	u32 version;
3287	const char * name;
3288} ath_mac_bb_names[] = {
3289	/* Devices with external radios */
3290	{ AR_SREV_VERSION_5416_PCI,	"5416" },
3291	{ AR_SREV_VERSION_5416_PCIE,	"5418" },
3292	{ AR_SREV_VERSION_9100,		"9100" },
3293	{ AR_SREV_VERSION_9160,		"9160" },
3294	/* Single-chip solutions */
3295	{ AR_SREV_VERSION_9280,		"9280" },
3296	{ AR_SREV_VERSION_9285,		"9285" },
3297	{ AR_SREV_VERSION_9287,         "9287" },
3298	{ AR_SREV_VERSION_9271,         "9271" },
3299	{ AR_SREV_VERSION_9300,         "9300" },
3300	{ AR_SREV_VERSION_9330,         "9330" },
3301	{ AR_SREV_VERSION_9340,		"9340" },
3302	{ AR_SREV_VERSION_9485,         "9485" },
3303	{ AR_SREV_VERSION_9462,         "9462" },
3304	{ AR_SREV_VERSION_9550,         "9550" },
3305	{ AR_SREV_VERSION_9565,         "9565" },
3306	{ AR_SREV_VERSION_9531,         "9531" },
3307	{ AR_SREV_VERSION_9561,         "9561" },
3308};
3309
3310/* For devices with external radios */
3311static struct {
3312	u16 version;
3313	const char * name;
3314} ath_rf_names[] = {
3315	{ 0,				"5133" },
3316	{ AR_RAD5133_SREV_MAJOR,	"5133" },
3317	{ AR_RAD5122_SREV_MAJOR,	"5122" },
3318	{ AR_RAD2133_SREV_MAJOR,	"2133" },
3319	{ AR_RAD2122_SREV_MAJOR,	"2122" }
3320};
3321
3322/*
3323 * Return the MAC/BB name. "????" is returned if the MAC/BB is unknown.
3324 */
3325static const char *ath9k_hw_mac_bb_name(u32 mac_bb_version)
3326{
3327	int i;
3328
3329	for (i=0; i<ARRAY_SIZE(ath_mac_bb_names); i++) {
3330		if (ath_mac_bb_names[i].version == mac_bb_version) {
3331			return ath_mac_bb_names[i].name;
3332		}
3333	}
3334
3335	return "????";
3336}
3337
3338/*
3339 * Return the RF name. "????" is returned if the RF is unknown.
3340 * Used for devices with external radios.
3341 */
3342static const char *ath9k_hw_rf_name(u16 rf_version)
3343{
3344	int i;
3345
3346	for (i=0; i<ARRAY_SIZE(ath_rf_names); i++) {
3347		if (ath_rf_names[i].version == rf_version) {
3348			return ath_rf_names[i].name;
3349		}
3350	}
3351
3352	return "????";
3353}
3354
3355void ath9k_hw_name(struct ath_hw *ah, char *hw_name, size_t len)
3356{
3357	int used;
3358
3359	/* chipsets >= AR9280 are single-chip */
3360	if (AR_SREV_9280_20_OR_LATER(ah)) {
3361		used = scnprintf(hw_name, len,
3362				 "Atheros AR%s Rev:%x",
3363				 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3364				 ah->hw_version.macRev);
3365	}
3366	else {
3367		used = scnprintf(hw_name, len,
3368				 "Atheros AR%s MAC/BB Rev:%x AR%s RF Rev:%x",
3369				 ath9k_hw_mac_bb_name(ah->hw_version.macVersion),
3370				 ah->hw_version.macRev,
3371				 ath9k_hw_rf_name((ah->hw_version.analog5GhzRev
3372						  & AR_RADIO_SREV_MAJOR)),
3373				 ah->hw_version.phyRev);
3374	}
3375
3376	hw_name[used] = '\0';
3377}
3378EXPORT_SYMBOL(ath9k_hw_name);