qmi.h

  1/* SPDX-License-Identifier: BSD-3-Clause-Clear */
  2/*
  3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
  4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
  5 */
  6
  7#ifndef ATH12K_QMI_H
  8#define ATH12K_QMI_H
  9
 10#include <linux/mutex.h>
 11#include <linux/soc/qcom/qmi.h>
 12
 13#define ATH12K_HOST_VERSION_STRING		"WIN"
 14#define ATH12K_QMI_WLANFW_TIMEOUT_MS		10000
 15#define ATH12K_QMI_MAX_BDF_FILE_NAME_SIZE	64
 16#define ATH12K_QMI_CALDB_ADDRESS		0x4BA00000
 17#define ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01	128
 18#define ATH12K_QMI_WLFW_SERVICE_ID_V01		0x45
 19#define ATH12K_QMI_WLFW_SERVICE_VERS_V01	0x01
 20#define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01	0x02
 21#define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_WCN7850 0x1
 22
 23#define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_QCN9274	0x07
 24#define ATH12K_QMI_WLFW_SERVICE_INS_ID_V01_IPQ5332	0x2
 25#define ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01	32
 26#define ATH12K_QMI_RESP_LEN_MAX			8192
 27#define ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01	52
 28#define ATH12K_QMI_CALDB_SIZE			0x480000
 29#define ATH12K_QMI_BDF_EXT_STR_LENGTH		0x20
 30#define ATH12K_QMI_FW_MEM_REQ_SEGMENT_CNT	3
 31#define ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01 4
 32#define ATH12K_QMI_DEVMEM_CMEM_INDEX	0
 33
 34#define QMI_WLFW_REQUEST_MEM_IND_V01		0x0035
 35#define QMI_WLFW_FW_MEM_READY_IND_V01		0x0037
 36#define QMI_WLFW_FW_READY_IND_V01		0x0038
 37
 38#define QMI_WLANFW_MAX_DATA_SIZE_V01		6144
 39#define ATH12K_FIRMWARE_MODE_OFF		4
 40
 41#define ATH12K_BOARD_ID_DEFAULT	0xFF
 42
 43struct ath12k_base;
 44struct ath12k_hw_group;
 45
 46enum ath12k_qmi_file_type {
 47	ATH12K_QMI_FILE_TYPE_BDF_GOLDEN	= 0,
 48	ATH12K_QMI_FILE_TYPE_CALDATA	= 2,
 49	ATH12K_QMI_FILE_TYPE_EEPROM	= 3,
 50	ATH12K_QMI_MAX_FILE_TYPE	= 4,
 51};
 52
 53enum ath12k_qmi_bdf_type {
 54	ATH12K_QMI_BDF_TYPE_BIN			= 0,
 55	ATH12K_QMI_BDF_TYPE_ELF			= 1,
 56	ATH12K_QMI_BDF_TYPE_REGDB		= 4,
 57	ATH12K_QMI_BDF_TYPE_CALIBRATION		= 5,
 58};
 59
 60enum ath12k_qmi_event_type {
 61	ATH12K_QMI_EVENT_SERVER_ARRIVE,
 62	ATH12K_QMI_EVENT_SERVER_EXIT,
 63	ATH12K_QMI_EVENT_REQUEST_MEM,
 64	ATH12K_QMI_EVENT_FW_MEM_READY,
 65	ATH12K_QMI_EVENT_FW_READY,
 66	ATH12K_QMI_EVENT_REGISTER_DRIVER,
 67	ATH12K_QMI_EVENT_UNREGISTER_DRIVER,
 68	ATH12K_QMI_EVENT_RECOVERY,
 69	ATH12K_QMI_EVENT_FORCE_FW_ASSERT,
 70	ATH12K_QMI_EVENT_POWER_UP,
 71	ATH12K_QMI_EVENT_POWER_DOWN,
 72	ATH12K_QMI_EVENT_HOST_CAP,
 73	ATH12K_QMI_EVENT_MAX,
 74};
 75
 76struct ath12k_qmi_driver_event {
 77	struct list_head list;
 78	enum ath12k_qmi_event_type type;
 79	void *data;
 80};
 81
 82struct ath12k_qmi_ce_cfg {
 83	const struct ce_pipe_config *tgt_ce;
 84	int tgt_ce_len;
 85	const struct service_to_pipe *svc_to_ce_map;
 86	int svc_to_ce_map_len;
 87	const u8 *shadow_reg;
 88	int shadow_reg_len;
 89	u32 *shadow_reg_v3;
 90	int shadow_reg_v3_len;
 91};
 92
 93struct ath12k_qmi_event_msg {
 94	struct list_head list;
 95	enum ath12k_qmi_event_type type;
 96};
 97
 98struct target_mem_chunk {
 99	u32 size;
100	u32 type;
101	u32 prev_size;
102	u32 prev_type;
103	dma_addr_t paddr;
104	union {
105		void __iomem *ioaddr;
106		void *addr;
107	} v;
108};
109
110struct target_info {
111	u32 chip_id;
112	u32 chip_family;
113	u32 board_id;
114	u32 soc_id;
115	u32 fw_version;
116	u32 eeprom_caldata;
117	char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1];
118	char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1];
119	char bdf_ext[ATH12K_QMI_BDF_EXT_STR_LENGTH];
120};
121
122struct m3_mem_region {
123	/* total memory allocated */
124	u32 total_size;
125	/* actual memory being used */
126	u32 size;
127	dma_addr_t paddr;
128	void *vaddr;
129};
130
131struct dev_mem_info {
132	u64 start;
133	u64 size;
134};
135
136struct ath12k_qmi {
137	struct ath12k_base *ab;
138	struct qmi_handle handle;
139	struct sockaddr_qrtr sq;
140	struct work_struct event_work;
141	struct workqueue_struct *event_wq;
142	struct list_head event_list;
143	spinlock_t event_lock; /* spinlock for qmi event list */
144	struct ath12k_qmi_ce_cfg ce_cfg;
145	struct target_mem_chunk target_mem[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
146	u32 mem_seg_count;
147	u32 target_mem_mode;
148	bool target_mem_delayed;
149	u8 cal_done;
150
151	/* protected with struct ath12k_qmi::event_lock */
152	bool block_event;
153
154	u8 num_radios;
155	struct target_info target;
156	struct m3_mem_region m3_mem;
157	unsigned int service_ins_id;
158	struct dev_mem_info dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01];
159};
160
161#define QMI_WLANFW_HOST_CAP_REQ_MSG_V01_MAX_LEN		261
162#define QMI_WLANFW_HOST_CAP_REQ_V01			0x0034
163#define QMI_WLANFW_HOST_CAP_RESP_MSG_V01_MAX_LEN	7
164#define QMI_WLFW_HOST_CAP_RESP_V01			0x0034
165#define QMI_WLFW_MAX_NUM_GPIO_V01			32
166#define QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01		64
167#define QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01		3
168
169struct qmi_wlanfw_host_ddr_range {
170	u64 start;
171	u64 size;
172};
173
174enum ath12k_qmi_target_mem {
175	HOST_DDR_REGION_TYPE = 0x1,
176	BDF_MEM_REGION_TYPE = 0x2,
177	M3_DUMP_REGION_TYPE = 0x3,
178	CALDB_MEM_REGION_TYPE = 0x4,
179	MLO_GLOBAL_MEM_REGION_TYPE = 0x8,
180	PAGEABLE_MEM_REGION_TYPE = 0x9,
181};
182
183enum qmi_wlanfw_host_build_type {
184	WLANFW_HOST_BUILD_TYPE_ENUM_MIN_VAL_V01 = INT_MIN,
185	QMI_WLANFW_HOST_BUILD_TYPE_UNSPECIFIED_V01 = 0,
186	QMI_WLANFW_HOST_BUILD_TYPE_PRIMARY_V01 = 1,
187	QMI_WLANFW_HOST_BUILD_TYPE_SECONDARY_V01 = 2,
188	WLANFW_HOST_BUILD_TYPE_ENUM_MAX_VAL_V01 = INT_MAX,
189};
190
191#define QMI_WLFW_MAX_NUM_MLO_CHIPS_V01 3
192#define QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01 2
193
194struct wlfw_host_mlo_chip_info_s_v01 {
195	u8 chip_id;
196	u8 num_local_links;
197	u8 hw_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01];
198	u8 valid_mlo_link_id[QMI_WLFW_MAX_NUM_MLO_LINKS_PER_CHIP_V01];
199};
200
201enum ath12k_qmi_cnss_feature {
202	CNSS_FEATURE_MIN_ENUM_VAL_V01 = INT_MIN,
203	CNSS_QDSS_CFG_MISS_V01 = 3,
204	CNSS_PCIE_PERST_NO_PULL_V01 = 4,
205	CNSS_MAX_FEATURE_V01 = 64,
206	CNSS_FEATURE_MAX_ENUM_VAL_V01 = INT_MAX,
207};
208
209struct qmi_wlanfw_host_cap_req_msg_v01 {
210	u8 num_clients_valid;
211	u32 num_clients;
212	u8 wake_msi_valid;
213	u32 wake_msi;
214	u8 gpios_valid;
215	u32 gpios_len;
216	u32 gpios[QMI_WLFW_MAX_NUM_GPIO_V01];
217	u8 nm_modem_valid;
218	u8 nm_modem;
219	u8 bdf_support_valid;
220	u8 bdf_support;
221	u8 bdf_cache_support_valid;
222	u8 bdf_cache_support;
223	u8 m3_support_valid;
224	u8 m3_support;
225	u8 m3_cache_support_valid;
226	u8 m3_cache_support;
227	u8 cal_filesys_support_valid;
228	u8 cal_filesys_support;
229	u8 cal_cache_support_valid;
230	u8 cal_cache_support;
231	u8 cal_done_valid;
232	u8 cal_done;
233	u8 mem_bucket_valid;
234	u32 mem_bucket;
235	u8 mem_cfg_mode_valid;
236	u8 mem_cfg_mode;
237	u8 cal_duration_valid;
238	u16 cal_duraiton;
239	u8 platform_name_valid;
240	char platform_name[QMI_WLANFW_MAX_PLATFORM_NAME_LEN_V01 + 1];
241	u8 ddr_range_valid;
242	struct qmi_wlanfw_host_ddr_range ddr_range[QMI_WLANFW_MAX_HOST_DDR_RANGE_SIZE_V01];
243	u8 host_build_type_valid;
244	enum qmi_wlanfw_host_build_type host_build_type;
245	u8 mlo_capable_valid;
246	u8 mlo_capable;
247	u8 mlo_chip_id_valid;
248	u16 mlo_chip_id;
249	u8 mlo_group_id_valid;
250	u8 mlo_group_id;
251	u8 max_mlo_peer_valid;
252	u16 max_mlo_peer;
253	u8 mlo_num_chips_valid;
254	u8 mlo_num_chips;
255	u8 mlo_chip_info_valid;
256	struct wlfw_host_mlo_chip_info_s_v01 mlo_chip_info[QMI_WLFW_MAX_NUM_MLO_CHIPS_V01];
257	u8 feature_list_valid;
258	u64 feature_list;
259
260};
261
262struct qmi_wlanfw_host_cap_resp_msg_v01 {
263	struct qmi_response_type_v01 resp;
264};
265
266#define QMI_WLANFW_PHY_CAP_REQ_MSG_V01_MAX_LEN		0
267#define QMI_WLANFW_PHY_CAP_REQ_V01			0x0057
268#define QMI_WLANFW_PHY_CAP_RESP_MSG_V01_MAX_LEN		18
269#define QMI_WLANFW_PHY_CAP_RESP_V01			0x0057
270
271struct qmi_wlanfw_phy_cap_req_msg_v01 {
272};
273
274struct qmi_wlanfw_phy_cap_resp_msg_v01 {
275	struct qmi_response_type_v01 resp;
276	u8 num_phy_valid;
277	u8 num_phy;
278	u8 board_id_valid;
279	u32 board_id;
280	u8 single_chip_mlo_support_valid;
281	u8 single_chip_mlo_support;
282};
283
284#define QMI_WLANFW_IND_REGISTER_REQ_MSG_V01_MAX_LEN		54
285#define QMI_WLANFW_IND_REGISTER_REQ_V01				0x0020
286#define QMI_WLANFW_IND_REGISTER_RESP_MSG_V01_MAX_LEN		18
287#define QMI_WLANFW_IND_REGISTER_RESP_V01			0x0020
288#define QMI_WLANFW_CLIENT_ID					0x4b4e454c
289
290struct qmi_wlanfw_ind_register_req_msg_v01 {
291	u8 fw_ready_enable_valid;
292	u8 fw_ready_enable;
293	u8 initiate_cal_download_enable_valid;
294	u8 initiate_cal_download_enable;
295	u8 initiate_cal_update_enable_valid;
296	u8 initiate_cal_update_enable;
297	u8 msa_ready_enable_valid;
298	u8 msa_ready_enable;
299	u8 pin_connect_result_enable_valid;
300	u8 pin_connect_result_enable;
301	u8 client_id_valid;
302	u32 client_id;
303	u8 request_mem_enable_valid;
304	u8 request_mem_enable;
305	u8 fw_mem_ready_enable_valid;
306	u8 fw_mem_ready_enable;
307	u8 fw_init_done_enable_valid;
308	u8 fw_init_done_enable;
309	u8 rejuvenate_enable_valid;
310	u32 rejuvenate_enable;
311	u8 xo_cal_enable_valid;
312	u8 xo_cal_enable;
313	u8 cal_done_enable_valid;
314	u8 cal_done_enable;
315};
316
317struct qmi_wlanfw_ind_register_resp_msg_v01 {
318	struct qmi_response_type_v01 resp;
319	u8 fw_status_valid;
320	u64 fw_status;
321};
322
323#define QMI_WLANFW_REQUEST_MEM_IND_MSG_V01_MAX_LEN	1824
324#define QMI_WLANFW_RESPOND_MEM_REQ_MSG_V01_MAX_LEN	888
325#define QMI_WLANFW_RESPOND_MEM_RESP_MSG_V01_MAX_LEN	7
326#define QMI_WLANFW_REQUEST_MEM_IND_V01			0x0035
327#define QMI_WLANFW_RESPOND_MEM_REQ_V01			0x0036
328#define QMI_WLANFW_RESPOND_MEM_RESP_V01			0x0036
329#define QMI_WLANFW_MAX_NUM_MEM_CFG_V01			2
330#define QMI_WLANFW_MAX_STR_LEN_V01                      16
331
332struct qmi_wlanfw_mem_cfg_s_v01 {
333	u64 offset;
334	u32 size;
335	u8 secure_flag;
336};
337
338enum qmi_wlanfw_mem_type_enum_v01 {
339	WLANFW_MEM_TYPE_ENUM_MIN_VAL_V01 = INT_MIN,
340	QMI_WLANFW_MEM_TYPE_MSA_V01 = 0,
341	QMI_WLANFW_MEM_TYPE_DDR_V01 = 1,
342	QMI_WLANFW_MEM_BDF_V01 = 2,
343	QMI_WLANFW_MEM_M3_V01 = 3,
344	QMI_WLANFW_MEM_CAL_V01 = 4,
345	QMI_WLANFW_MEM_DPD_V01 = 5,
346	WLANFW_MEM_TYPE_ENUM_MAX_VAL_V01 = INT_MAX,
347};
348
349struct qmi_wlanfw_mem_seg_s_v01 {
350	u32 size;
351	enum qmi_wlanfw_mem_type_enum_v01 type;
352	u32 mem_cfg_len;
353	struct qmi_wlanfw_mem_cfg_s_v01 mem_cfg[QMI_WLANFW_MAX_NUM_MEM_CFG_V01];
354};
355
356struct qmi_wlanfw_request_mem_ind_msg_v01 {
357	u32 mem_seg_len;
358	struct qmi_wlanfw_mem_seg_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
359};
360
361struct qmi_wlanfw_mem_seg_resp_s_v01 {
362	u64 addr;
363	u32 size;
364	enum qmi_wlanfw_mem_type_enum_v01 type;
365	u8 restore;
366};
367
368struct qmi_wlanfw_respond_mem_req_msg_v01 {
369	u32 mem_seg_len;
370	struct qmi_wlanfw_mem_seg_resp_s_v01 mem_seg[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
371};
372
373struct qmi_wlanfw_respond_mem_resp_msg_v01 {
374	struct qmi_response_type_v01 resp;
375};
376
377struct qmi_wlanfw_fw_mem_ready_ind_msg_v01 {
378	char placeholder;
379};
380
381struct qmi_wlanfw_fw_ready_ind_msg_v01 {
382	char placeholder;
383};
384
385#define QMI_WLANFW_CAP_REQ_MSG_V01_MAX_LEN	0
386#define QMI_WLANFW_CAP_RESP_MSG_V01_MAX_LEN	207
387#define QMI_WLANFW_CAP_REQ_V01			0x0024
388#define QMI_WLANFW_CAP_RESP_V01			0x0024
389
390enum qmi_wlanfw_pipedir_enum_v01 {
391	QMI_WLFW_PIPEDIR_NONE_V01 = 0,
392	QMI_WLFW_PIPEDIR_IN_V01 = 1,
393	QMI_WLFW_PIPEDIR_OUT_V01 = 2,
394	QMI_WLFW_PIPEDIR_INOUT_V01 = 3,
395};
396
397struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01 {
398	u32 pipe_num;
399	u32 pipe_dir;
400	u32 nentries;
401	u32 nbytes_max;
402	u32 flags;
403};
404
405struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01 {
406	u32 service_id;
407	u32 pipe_dir;
408	u32 pipe_num;
409};
410
411struct qmi_wlanfw_shadow_reg_cfg_s_v01 {
412	u16 id;
413	u16 offset;
414};
415
416struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01 {
417	u32 addr;
418};
419
420struct qmi_wlanfw_memory_region_info_s_v01 {
421	u64 region_addr;
422	u32 size;
423	u8 secure_flag;
424};
425
426struct qmi_wlanfw_rf_chip_info_s_v01 {
427	u32 chip_id;
428	u32 chip_family;
429};
430
431struct qmi_wlanfw_rf_board_info_s_v01 {
432	u32 board_id;
433};
434
435struct qmi_wlanfw_soc_info_s_v01 {
436	u32 soc_id;
437};
438
439struct qmi_wlanfw_fw_version_info_s_v01 {
440	u32 fw_version;
441	char fw_build_timestamp[ATH12K_QMI_WLANFW_MAX_TIMESTAMP_LEN_V01 + 1];
442};
443
444struct qmi_wlanfw_dev_mem_info_s_v01 {
445	u64 start;
446	u64 size;
447};
448
449enum qmi_wlanfw_cal_temp_id_enum_v01 {
450	QMI_WLANFW_CAL_TEMP_IDX_0_V01 = 0,
451	QMI_WLANFW_CAL_TEMP_IDX_1_V01 = 1,
452	QMI_WLANFW_CAL_TEMP_IDX_2_V01 = 2,
453	QMI_WLANFW_CAL_TEMP_IDX_3_V01 = 3,
454	QMI_WLANFW_CAL_TEMP_IDX_4_V01 = 4,
455	QMI_WLANFW_CAL_TEMP_ID_MAX_V01 = 0xFF,
456};
457
458enum qmi_wlanfw_rd_card_chain_cap_v01 {
459	WLFW_RD_CARD_CHAIN_CAP_MIN_VAL_V01 = INT_MIN,
460	WLFW_RD_CARD_CHAIN_CAP_UNSPECIFIED_V01 = 0,
461	WLFW_RD_CARD_CHAIN_CAP_1x1_V01 = 1,
462	WLFW_RD_CARD_CHAIN_CAP_2x2_V01 = 2,
463	WLFW_RD_CARD_CHAIN_CAP_MAX_VAL_V01 = INT_MAX,
464};
465
466struct qmi_wlanfw_cap_resp_msg_v01 {
467	struct qmi_response_type_v01 resp;
468	u8 chip_info_valid;
469	struct qmi_wlanfw_rf_chip_info_s_v01 chip_info;
470	u8 board_info_valid;
471	struct qmi_wlanfw_rf_board_info_s_v01 board_info;
472	u8 soc_info_valid;
473	struct qmi_wlanfw_soc_info_s_v01 soc_info;
474	u8 fw_version_info_valid;
475	struct qmi_wlanfw_fw_version_info_s_v01 fw_version_info;
476	u8 fw_build_id_valid;
477	char fw_build_id[ATH12K_QMI_WLANFW_MAX_BUILD_ID_LEN_V01 + 1];
478	u8 num_macs_valid;
479	u8 num_macs;
480	u8 voltage_mv_valid;
481	u32 voltage_mv;
482	u8 time_freq_hz_valid;
483	u32 time_freq_hz;
484	u8 otp_version_valid;
485	u32 otp_version;
486	u8 eeprom_caldata_read_timeout_valid;
487	u32 eeprom_caldata_read_timeout;
488	u8 fw_caps_valid;
489	u64 fw_caps;
490	u8 rd_card_chain_cap_valid;
491	enum qmi_wlanfw_rd_card_chain_cap_v01 rd_card_chain_cap;
492	u8 dev_mem_info_valid;
493	struct qmi_wlanfw_dev_mem_info_s_v01 dev_mem[ATH12K_QMI_WLFW_MAX_DEV_MEM_NUM_V01];
494};
495
496struct qmi_wlanfw_cap_req_msg_v01 {
497	char placeholder;
498};
499
500#define QMI_WLANFW_BDF_DOWNLOAD_REQ_MSG_V01_MAX_LEN	6182
501#define QMI_WLANFW_BDF_DOWNLOAD_RESP_MSG_V01_MAX_LEN	7
502#define QMI_WLANFW_BDF_DOWNLOAD_RESP_V01		0x0025
503#define QMI_WLANFW_BDF_DOWNLOAD_REQ_V01			0x0025
504/* TODO: Need to check with MCL and FW team that data can be pointer and
505 * can be last element in structure
506 */
507struct qmi_wlanfw_bdf_download_req_msg_v01 {
508	u8 valid;
509	u8 file_id_valid;
510	enum qmi_wlanfw_cal_temp_id_enum_v01 file_id;
511	u8 total_size_valid;
512	u32 total_size;
513	u8 seg_id_valid;
514	u32 seg_id;
515	u8 data_valid;
516	u32 data_len;
517	u8 data[QMI_WLANFW_MAX_DATA_SIZE_V01];
518	u8 end_valid;
519	u8 end;
520	u8 bdf_type_valid;
521	u8 bdf_type;
522
523};
524
525struct qmi_wlanfw_bdf_download_resp_msg_v01 {
526	struct qmi_response_type_v01 resp;
527};
528
529#define QMI_WLANFW_M3_INFO_REQ_MSG_V01_MAX_MSG_LEN	18
530#define QMI_WLANFW_M3_INFO_RESP_MSG_V01_MAX_MSG_LEN	7
531#define QMI_WLANFW_M3_INFO_RESP_V01		0x003C
532#define QMI_WLANFW_M3_INFO_REQ_V01		0x003C
533
534struct qmi_wlanfw_m3_info_req_msg_v01 {
535	u64 addr;
536	u32 size;
537};
538
539struct qmi_wlanfw_m3_info_resp_msg_v01 {
540	struct qmi_response_type_v01 resp;
541};
542
543#define QMI_WLANFW_WLAN_MODE_REQ_MSG_V01_MAX_LEN	11
544#define QMI_WLANFW_WLAN_MODE_RESP_MSG_V01_MAX_LEN	7
545#define QMI_WLANFW_WLAN_CFG_REQ_MSG_V01_MAX_LEN		803
546#define QMI_WLANFW_WLAN_CFG_RESP_MSG_V01_MAX_LEN	7
547#define QMI_WLANFW_WLAN_MODE_REQ_V01			0x0022
548#define QMI_WLANFW_WLAN_MODE_RESP_V01			0x0022
549#define QMI_WLANFW_WLAN_CFG_REQ_V01			0x0023
550#define QMI_WLANFW_WLAN_CFG_RESP_V01			0x0023
551#define QMI_WLANFW_MAX_STR_LEN_V01			16
552#define QMI_WLANFW_MAX_NUM_CE_V01			12
553#define QMI_WLANFW_MAX_NUM_SVC_V01			24
554#define QMI_WLANFW_MAX_NUM_SHADOW_REG_V01		24
555#define QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01		60
556
557struct qmi_wlanfw_wlan_mode_req_msg_v01 {
558	u32 mode;
559	u8 hw_debug_valid;
560	u8 hw_debug;
561};
562
563struct qmi_wlanfw_wlan_mode_resp_msg_v01 {
564	struct qmi_response_type_v01 resp;
565};
566
567struct qmi_wlanfw_wlan_cfg_req_msg_v01 {
568	u8 host_version_valid;
569	char host_version[QMI_WLANFW_MAX_STR_LEN_V01 + 1];
570	u8  tgt_cfg_valid;
571	u32  tgt_cfg_len;
572	struct qmi_wlanfw_ce_tgt_pipe_cfg_s_v01
573			tgt_cfg[QMI_WLANFW_MAX_NUM_CE_V01];
574	u8  svc_cfg_valid;
575	u32 svc_cfg_len;
576	struct qmi_wlanfw_ce_svc_pipe_cfg_s_v01
577			svc_cfg[QMI_WLANFW_MAX_NUM_SVC_V01];
578	u8 shadow_reg_valid;
579	u32 shadow_reg_len;
580	struct qmi_wlanfw_shadow_reg_cfg_s_v01
581		shadow_reg[QMI_WLANFW_MAX_NUM_SHADOW_REG_V01];
582	u8 shadow_reg_v3_valid;
583	u32 shadow_reg_v3_len;
584	struct qmi_wlanfw_shadow_reg_v3_cfg_s_v01
585		shadow_reg_v3[QMI_WLANFW_MAX_NUM_SHADOW_REG_V3_V01];
586};
587
588struct qmi_wlanfw_wlan_cfg_resp_msg_v01 {
589	struct qmi_response_type_v01 resp;
590};
591
592#define ATH12K_QMI_WLANFW_WLAN_INI_REQ_V01	0x002F
593#define ATH12K_QMI_WLANFW_WLAN_INI_RESP_V01	0x002F
594#define QMI_WLANFW_WLAN_INI_REQ_MSG_V01_MAX_LEN		7
595#define QMI_WLANFW_WLAN_INI_RESP_MSG_V01_MAX_LEN	7
596
597struct qmi_wlanfw_wlan_ini_req_msg_v01 {
598	/* Must be set to true if enable_fwlog is being passed */
599	u8 enable_fwlog_valid;
600	u8 enable_fwlog;
601};
602
603struct qmi_wlanfw_wlan_ini_resp_msg_v01 {
604	struct qmi_response_type_v01 resp;
605};
606
607enum ath12k_qmi_mem_mode {
608	ATH12K_QMI_MEMORY_MODE_DEFAULT = 0,
609	ATH12K_QMI_MEMORY_MODE_LOW_512_M,
610};
611
612static inline void ath12k_qmi_set_event_block(struct ath12k_qmi *qmi, bool block)
613{
614	lockdep_assert_held(&qmi->event_lock);
615
616	qmi->block_event = block;
617}
618
619static inline bool ath12k_qmi_get_event_block(struct ath12k_qmi *qmi)
620{
621	lockdep_assert_held(&qmi->event_lock);
622
623	return qmi->block_event;
624}
625
626int ath12k_qmi_firmware_start(struct ath12k_base *ab,
627			      u32 mode);
628void ath12k_qmi_firmware_stop(struct ath12k_base *ab);
629void ath12k_qmi_deinit_service(struct ath12k_base *ab);
630int ath12k_qmi_init_service(struct ath12k_base *ab);
631void ath12k_qmi_free_resource(struct ath12k_base *ab);
632void ath12k_qmi_trigger_host_cap(struct ath12k_base *ab);
633void ath12k_qmi_reset_mlo_mem(struct ath12k_hw_group *ag);
634
635#endif