hal_tx.h

  1/* SPDX-License-Identifier: BSD-3-Clause-Clear */
  2/*
  3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
  4 * Copyright (c) 2021-2022, 2024-2025 Qualcomm Innovation Center, Inc.
  5 * All rights reserved.
  6 */
  7
  8#ifndef ATH12K_HAL_TX_H
  9#define ATH12K_HAL_TX_H
 10
 11#include "hal_desc.h"
 12#include "core.h"
 13
 14#define HAL_TX_ADDRX_EN			1
 15#define HAL_TX_ADDRY_EN			2
 16
 17#define HAL_TX_ADDR_SEARCH_DEFAULT	0
 18#define HAL_TX_ADDR_SEARCH_INDEX	1
 19
 20/* TODO: check all these data can be managed with struct ath12k_tx_desc_info for perf */
 21struct hal_tx_info {
 22	u16 meta_data_flags; /* %HAL_TCL_DATA_CMD_INFO0_META_ */
 23	u8 ring_id;
 24	u8 rbm_id;
 25	u32 desc_id;
 26	enum hal_tcl_desc_type type;
 27	enum hal_tcl_encap_type encap_type;
 28	dma_addr_t paddr;
 29	u32 data_len;
 30	u32 pkt_offset;
 31	enum hal_encrypt_type encrypt_type;
 32	u32 flags0; /* %HAL_TCL_DATA_CMD_INFO1_ */
 33	u32 flags1; /* %HAL_TCL_DATA_CMD_INFO2_ */
 34	u16 addr_search_flags; /* %HAL_TCL_DATA_CMD_INFO0_ADDR(X/Y)_ */
 35	u16 bss_ast_hash;
 36	u16 bss_ast_idx;
 37	u8 tid;
 38	u8 search_type; /* %HAL_TX_ADDR_SEARCH_ */
 39	u8 lmac_id;
 40	u8 vdev_id;
 41	u8 dscp_tid_tbl_idx;
 42	bool enable_mesh;
 43	int bank_id;
 44};
 45
 46/* TODO: Check if the actual desc macros can be used instead */
 47#define HAL_TX_STATUS_FLAGS_FIRST_MSDU		BIT(0)
 48#define HAL_TX_STATUS_FLAGS_LAST_MSDU		BIT(1)
 49#define HAL_TX_STATUS_FLAGS_MSDU_IN_AMSDU	BIT(2)
 50#define HAL_TX_STATUS_FLAGS_RATE_STATS_VALID	BIT(3)
 51#define HAL_TX_STATUS_FLAGS_RATE_LDPC		BIT(4)
 52#define HAL_TX_STATUS_FLAGS_RATE_STBC		BIT(5)
 53#define HAL_TX_STATUS_FLAGS_OFDMA		BIT(6)
 54
 55#define HAL_TX_STATUS_DESC_LEN		sizeof(struct hal_wbm_release_ring)
 56
 57/* Tx status parsed from srng desc */
 58struct hal_tx_status {
 59	enum hal_wbm_rel_src_module buf_rel_source;
 60	enum hal_wbm_tqm_rel_reason status;
 61	s8 ack_rssi;
 62	u32 flags; /* %HAL_TX_STATUS_FLAGS_ */
 63	u32 ppdu_id;
 64	u8 try_cnt;
 65	u8 tid;
 66	u16 peer_id;
 67	enum hal_tx_rate_stats_pkt_type pkt_type;
 68	enum hal_tx_rate_stats_sgi sgi;
 69	enum ath12k_supported_bw bw;
 70	u8 mcs;
 71	u16 tones;
 72	u8 ofdma;
 73};
 74
 75#define HAL_TX_PHY_DESC_INFO0_BF_TYPE		GENMASK(17, 16)
 76#define HAL_TX_PHY_DESC_INFO0_PREAMBLE_11B	BIT(20)
 77#define HAL_TX_PHY_DESC_INFO0_PKT_TYPE		GENMASK(24, 21)
 78#define HAL_TX_PHY_DESC_INFO0_BANDWIDTH		GENMASK(30, 28)
 79#define HAL_TX_PHY_DESC_INFO1_MCS		GENMASK(3, 0)
 80#define HAL_TX_PHY_DESC_INFO1_STBC		BIT(6)
 81#define HAL_TX_PHY_DESC_INFO2_NSS		GENMASK(23, 21)
 82#define HAL_TX_PHY_DESC_INFO3_AP_PKT_BW		GENMASK(6, 4)
 83#define HAL_TX_PHY_DESC_INFO3_LTF_SIZE		GENMASK(20, 19)
 84#define HAL_TX_PHY_DESC_INFO3_ACTIVE_CHANNEL	GENMASK(17, 15)
 85
 86struct hal_tx_phy_desc {
 87	__le32 info0;
 88	__le32 info1;
 89	__le32 info2;
 90	__le32 info3;
 91} __packed;
 92
 93#define HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_15_0	GENMASK(15, 0)
 94#define HAL_TX_FES_STAT_PROT_INFO0_STRT_FRM_TS_31_16	GENMASK(31, 16)
 95#define HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_15_0	GENMASK(15, 0)
 96#define HAL_TX_FES_STAT_PROT_INFO1_END_FRM_TS_31_16	GENMASK(31, 16)
 97
 98struct hal_tx_fes_status_prot {
 99	__le64 reserved;
100	__le32 info0;
101	__le32 info1;
102	__le32 reserved1[11];
103} __packed;
104
105#define HAL_TX_FES_STAT_USR_PPDU_INFO0_DURATION		GENMASK(15, 0)
106
107struct hal_tx_fes_status_user_ppdu {
108	__le64 reserved;
109	__le32 info0;
110	__le32 reserved1[3];
111} __packed;
112
113#define HAL_TX_FES_STAT_STRT_INFO0_PROT_TS_LOWER_32	GENMASK(31, 0)
114#define HAL_TX_FES_STAT_STRT_INFO1_PROT_TS_UPPER_32	GENMASK(31, 0)
115
116struct hal_tx_fes_status_start_prot {
117	__le32 info0;
118	__le32 info1;
119	__le64 reserved;
120} __packed;
121
122#define HAL_TX_FES_STATUS_START_INFO0_MEDIUM_PROT_TYPE	GENMASK(29, 27)
123
124struct hal_tx_fes_status_start {
125	__le32 reserved;
126	__le32 info0;
127	__le64 reserved1;
128} __packed;
129
130#define HAL_TX_Q_EXT_INFO0_FRAME_CTRL		GENMASK(15, 0)
131#define HAL_TX_Q_EXT_INFO0_QOS_CTRL		GENMASK(31, 16)
132#define HAL_TX_Q_EXT_INFO1_AMPDU_FLAG		BIT(0)
133
134struct hal_tx_queue_exten {
135	__le32 info0;
136	__le32 info1;
137} __packed;
138
139#define HAL_TX_FES_SETUP_INFO0_NUM_OF_USERS	GENMASK(28, 23)
140
141struct hal_tx_fes_setup {
142	__le32 schedule_id;
143	__le32 info0;
144	__le64 reserved;
145} __packed;
146
147#define HAL_TX_PPDU_SETUP_INFO0_MEDIUM_PROT_TYPE	GENMASK(2, 0)
148#define HAL_TX_PPDU_SETUP_INFO1_PROT_FRAME_ADDR1_31_0	GENMASK(31, 0)
149#define HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR1_47_32	GENMASK(15, 0)
150#define HAL_TX_PPDU_SETUP_INFO2_PROT_FRAME_ADDR2_15_0	GENMASK(31, 16)
151#define HAL_TX_PPDU_SETUP_INFO3_PROT_FRAME_ADDR2_47_16	GENMASK(31, 0)
152#define HAL_TX_PPDU_SETUP_INFO4_PROT_FRAME_ADDR3_31_0	GENMASK(31, 0)
153#define HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR3_47_32	GENMASK(15, 0)
154#define HAL_TX_PPDU_SETUP_INFO5_PROT_FRAME_ADDR4_15_0	GENMASK(31, 16)
155#define HAL_TX_PPDU_SETUP_INFO6_PROT_FRAME_ADDR4_47_16	GENMASK(31, 0)
156
157struct hal_tx_pcu_ppdu_setup_init {
158	__le32 info0;
159	__le32 info1;
160	__le32 info2;
161	__le32 info3;
162	__le32 reserved;
163	__le32 info4;
164	__le32 info5;
165	__le32 info6;
166} __packed;
167
168#define HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_15_0	GENMASK(15, 0)
169#define HAL_TX_FES_STATUS_END_INFO0_START_TIMESTAMP_31_16	GENMASK(31, 16)
170
171struct hal_tx_fes_status_end {
172	__le32 reserved[2];
173	__le32 info0;
174	__le32 reserved1[19];
175} __packed;
176
177#define HAL_TX_BANK_CONFIG_EPD			BIT(0)
178#define HAL_TX_BANK_CONFIG_ENCAP_TYPE		GENMASK(2, 1)
179#define HAL_TX_BANK_CONFIG_ENCRYPT_TYPE		GENMASK(6, 3)
180#define HAL_TX_BANK_CONFIG_SRC_BUFFER_SWAP	BIT(7)
181#define HAL_TX_BANK_CONFIG_LINK_META_SWAP	BIT(8)
182#define HAL_TX_BANK_CONFIG_INDEX_LOOKUP_EN	BIT(9)
183#define HAL_TX_BANK_CONFIG_ADDRX_EN		BIT(10)
184#define HAL_TX_BANK_CONFIG_ADDRY_EN		BIT(11)
185#define HAL_TX_BANK_CONFIG_MESH_EN		GENMASK(13, 12)
186#define HAL_TX_BANK_CONFIG_VDEV_ID_CHECK_EN	BIT(14)
187#define HAL_TX_BANK_CONFIG_PMAC_ID		GENMASK(16, 15)
188/* STA mode will have MCAST_PKT_CTRL instead of DSCP_TID_MAP bitfield */
189#define HAL_TX_BANK_CONFIG_DSCP_TIP_MAP_ID	GENMASK(22, 17)
190
191void ath12k_hal_tx_cmd_desc_setup(struct ath12k_base *ab,
192				  struct hal_tcl_data_cmd *tcl_cmd,
193				  struct hal_tx_info *ti);
194void ath12k_hal_tx_set_dscp_tid_map(struct ath12k_base *ab, int id);
195int ath12k_hal_reo_cmd_send(struct ath12k_base *ab, struct hal_srng *srng,
196			    enum hal_reo_cmd_type type,
197			    struct ath12k_hal_reo_cmd *cmd);
198void ath12k_hal_tx_configure_bank_register(struct ath12k_base *ab, u32 bank_config,
199					   u8 bank_id);
200#endif