hal_rx.h

   1/* SPDX-License-Identifier: BSD-3-Clause-Clear */
   2/*
   3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
   4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
   5 */
   6
   7#ifndef ATH12K_HAL_RX_H
   8#define ATH12K_HAL_RX_H
   9
  10struct hal_rx_wbm_rel_info {
  11	u32 cookie;
  12	enum hal_wbm_rel_src_module err_rel_src;
  13	enum hal_reo_dest_ring_push_reason push_reason;
  14	u32 err_code;
  15	bool first_msdu;
  16	bool last_msdu;
  17	bool continuation;
  18	void *rx_desc;
  19	bool hw_cc_done;
  20};
  21
  22#define HAL_INVALID_PEERID	0x3fff
  23#define VHT_SIG_SU_NSS_MASK 0x7
  24
  25#define HAL_RX_MPDU_INFO_PN_GET_BYTE1(__val) \
  26	le32_get_bits((__val), GENMASK(7, 0))
  27
  28#define HAL_RX_MPDU_INFO_PN_GET_BYTE2(__val) \
  29	le32_get_bits((__val), GENMASK(15, 8))
  30
  31#define HAL_RX_MPDU_INFO_PN_GET_BYTE3(__val) \
  32	le32_get_bits((__val), GENMASK(23, 16))
  33
  34#define HAL_RX_MPDU_INFO_PN_GET_BYTE4(__val) \
  35	le32_get_bits((__val), GENMASK(31, 24))
  36
  37struct hal_rx_mon_status_tlv_hdr {
  38	u32 hdr;
  39	u8 value[];
  40};
  41
  42enum hal_rx_su_mu_coding {
  43	HAL_RX_SU_MU_CODING_BCC,
  44	HAL_RX_SU_MU_CODING_LDPC,
  45	HAL_RX_SU_MU_CODING_MAX,
  46};
  47
  48enum hal_rx_gi {
  49	HAL_RX_GI_0_8_US,
  50	HAL_RX_GI_0_4_US,
  51	HAL_RX_GI_1_6_US,
  52	HAL_RX_GI_3_2_US,
  53	HAL_RX_GI_MAX,
  54};
  55
  56enum hal_rx_bw {
  57	HAL_RX_BW_20MHZ,
  58	HAL_RX_BW_40MHZ,
  59	HAL_RX_BW_80MHZ,
  60	HAL_RX_BW_160MHZ,
  61	HAL_RX_BW_320MHZ,
  62	HAL_RX_BW_MAX,
  63};
  64
  65enum hal_rx_preamble {
  66	HAL_RX_PREAMBLE_11A,
  67	HAL_RX_PREAMBLE_11B,
  68	HAL_RX_PREAMBLE_11N,
  69	HAL_RX_PREAMBLE_11AC,
  70	HAL_RX_PREAMBLE_11AX,
  71	HAL_RX_PREAMBLE_11BA,
  72	HAL_RX_PREAMBLE_11BE,
  73	HAL_RX_PREAMBLE_MAX,
  74};
  75
  76enum hal_rx_reception_type {
  77	HAL_RX_RECEPTION_TYPE_SU,
  78	HAL_RX_RECEPTION_TYPE_MU_MIMO,
  79	HAL_RX_RECEPTION_TYPE_MU_OFDMA,
  80	HAL_RX_RECEPTION_TYPE_MU_OFDMA_MIMO,
  81	HAL_RX_RECEPTION_TYPE_MAX,
  82};
  83
  84enum hal_rx_legacy_rate {
  85	HAL_RX_LEGACY_RATE_1_MBPS,
  86	HAL_RX_LEGACY_RATE_2_MBPS,
  87	HAL_RX_LEGACY_RATE_5_5_MBPS,
  88	HAL_RX_LEGACY_RATE_6_MBPS,
  89	HAL_RX_LEGACY_RATE_9_MBPS,
  90	HAL_RX_LEGACY_RATE_11_MBPS,
  91	HAL_RX_LEGACY_RATE_12_MBPS,
  92	HAL_RX_LEGACY_RATE_18_MBPS,
  93	HAL_RX_LEGACY_RATE_24_MBPS,
  94	HAL_RX_LEGACY_RATE_36_MBPS,
  95	HAL_RX_LEGACY_RATE_48_MBPS,
  96	HAL_RX_LEGACY_RATE_54_MBPS,
  97	HAL_RX_LEGACY_RATE_INVALID,
  98};
  99
 100#define HAL_TLV_STATUS_PPDU_NOT_DONE            0
 101#define HAL_TLV_STATUS_PPDU_DONE                1
 102#define HAL_TLV_STATUS_BUF_DONE                 2
 103#define HAL_TLV_STATUS_PPDU_NON_STD_DONE        3
 104#define HAL_RX_FCS_LEN                          4
 105
 106enum hal_rx_mon_status {
 107	HAL_RX_MON_STATUS_PPDU_NOT_DONE,
 108	HAL_RX_MON_STATUS_PPDU_DONE,
 109	HAL_RX_MON_STATUS_BUF_DONE,
 110	HAL_RX_MON_STATUS_BUF_ADDR,
 111	HAL_RX_MON_STATUS_MPDU_START,
 112	HAL_RX_MON_STATUS_MPDU_END,
 113	HAL_RX_MON_STATUS_MSDU_END,
 114};
 115
 116#define HAL_RX_MAX_MPDU				1024
 117#define HAL_RX_NUM_WORDS_PER_PPDU_BITMAP	(HAL_RX_MAX_MPDU >> 5)
 118
 119struct hal_rx_user_status {
 120	u32 mcs:4,
 121	nss:3,
 122	ofdma_info_valid:1,
 123	ul_ofdma_ru_start_index:7,
 124	ul_ofdma_ru_width:7,
 125	ul_ofdma_ru_size:8;
 126	u32 ul_ofdma_user_v0_word0;
 127	u32 ul_ofdma_user_v0_word1;
 128	u32 ast_index;
 129	u32 tid;
 130	u16 tcp_msdu_count;
 131	u16 tcp_ack_msdu_count;
 132	u16 udp_msdu_count;
 133	u16 other_msdu_count;
 134	u16 frame_control;
 135	u8 frame_control_info_valid;
 136	u8 data_sequence_control_info_valid;
 137	u16 first_data_seq_ctrl;
 138	u32 preamble_type;
 139	u16 ht_flags;
 140	u16 vht_flags;
 141	u16 he_flags;
 142	u8 rs_flags;
 143	u8 ldpc;
 144	u32 mpdu_cnt_fcs_ok;
 145	u32 mpdu_cnt_fcs_err;
 146	u32 mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP];
 147	u32 mpdu_ok_byte_count;
 148	u32 mpdu_err_byte_count;
 149	bool ampdu_present;
 150	u16 ampdu_id;
 151};
 152
 153#define HAL_MAX_UL_MU_USERS	37
 154
 155struct hal_rx_u_sig_info {
 156	bool ul_dl;
 157	u8 bw;
 158	u8 ppdu_type_comp_mode;
 159	u8 eht_sig_mcs;
 160	u8 num_eht_sig_sym;
 161	struct ieee80211_radiotap_eht_usig usig;
 162};
 163
 164#define HAL_RX_MON_MAX_AGGR_SIZE	128
 165
 166struct hal_rx_tlv_aggr_info {
 167	bool in_progress;
 168	u16 cur_len;
 169	u16 tlv_tag;
 170	u8 buf[HAL_RX_MON_MAX_AGGR_SIZE];
 171};
 172
 173struct hal_rx_radiotap_eht {
 174	__le32 known;
 175	__le32 data[9];
 176};
 177
 178#define EHT_MAX_USER_INFO	4
 179
 180struct hal_rx_eht_info {
 181	u8 num_user_info;
 182	struct hal_rx_radiotap_eht eht;
 183	u32 user_info[EHT_MAX_USER_INFO];
 184};
 185
 186struct hal_rx_mon_ppdu_info {
 187	u32 ppdu_id;
 188	u32 last_ppdu_id;
 189	u64 ppdu_ts;
 190	u32 num_mpdu_fcs_ok;
 191	u32 num_mpdu_fcs_err;
 192	u32 preamble_type;
 193	u32 mpdu_len;
 194	u16 chan_num;
 195	u16 freq;
 196	u16 tcp_msdu_count;
 197	u16 tcp_ack_msdu_count;
 198	u16 udp_msdu_count;
 199	u16 other_msdu_count;
 200	u16 peer_id;
 201	u8 rate;
 202	u8 mcs;
 203	u8 nss;
 204	u8 bw;
 205	u8 vht_flag_values1;
 206	u8 vht_flag_values2;
 207	u8 vht_flag_values3[4];
 208	u8 vht_flag_values4;
 209	u8 vht_flag_values5;
 210	u16 vht_flag_values6;
 211	u8 is_stbc;
 212	u8 gi;
 213	u8 sgi;
 214	u8 ldpc;
 215	u8 beamformed;
 216	u8 rssi_comb;
 217	u16 tid;
 218	u8 fc_valid;
 219	u16 ht_flags;
 220	u16 vht_flags;
 221	u16 he_flags;
 222	u16 he_mu_flags;
 223	u8 dcm;
 224	u8 ru_alloc;
 225	u8 reception_type;
 226	u64 tsft;
 227	u64 rx_duration;
 228	u16 frame_control;
 229	u32 ast_index;
 230	u8 rs_fcs_err;
 231	u8 rs_flags;
 232	u8 cck_flag;
 233	u8 ofdm_flag;
 234	u8 ulofdma_flag;
 235	u8 frame_control_info_valid;
 236	u16 he_per_user_1;
 237	u16 he_per_user_2;
 238	u8 he_per_user_position;
 239	u8 he_per_user_known;
 240	u16 he_flags1;
 241	u16 he_flags2;
 242	u8 he_RU[4];
 243	u16 he_data1;
 244	u16 he_data2;
 245	u16 he_data3;
 246	u16 he_data4;
 247	u16 he_data5;
 248	u16 he_data6;
 249	u32 ppdu_len;
 250	u32 prev_ppdu_id;
 251	u32 device_id;
 252	u16 first_data_seq_ctrl;
 253	u8 monitor_direct_used;
 254	u8 data_sequence_control_info_valid;
 255	u8 ltf_size;
 256	u8 rxpcu_filter_pass;
 257	s8 rssi_chain[8][8];
 258	u32 num_users;
 259	u32 mpdu_fcs_ok_bitmap[HAL_RX_NUM_WORDS_PER_PPDU_BITMAP];
 260	u8 addr1[ETH_ALEN];
 261	u8 addr2[ETH_ALEN];
 262	u8 addr3[ETH_ALEN];
 263	u8 addr4[ETH_ALEN];
 264	struct hal_rx_user_status userstats[HAL_MAX_UL_MU_USERS];
 265	u8 userid;
 266	bool first_msdu_in_mpdu;
 267	bool is_ampdu;
 268	u8 medium_prot_type;
 269	bool ppdu_continuation;
 270	bool eht_usig;
 271	struct hal_rx_u_sig_info u_sig_info;
 272	bool is_eht;
 273	struct hal_rx_eht_info eht_info;
 274	struct hal_rx_tlv_aggr_info tlv_aggr;
 275};
 276
 277#define HAL_RX_PPDU_START_INFO0_PPDU_ID			GENMASK(15, 0)
 278#define HAL_RX_PPDU_START_INFO1_CHAN_NUM		GENMASK(15, 0)
 279#define HAL_RX_PPDU_START_INFO1_CHAN_FREQ		GENMASK(31, 16)
 280
 281struct hal_rx_ppdu_start {
 282	__le32 info0;
 283	__le32 info1;
 284	__le32 ppdu_start_ts_31_0;
 285	__le32 ppdu_start_ts_63_32;
 286	__le32 rsvd[2];
 287} __packed;
 288
 289#define HAL_RX_PPDU_END_USER_STATS_INFO0_PEER_ID		GENMASK(13, 0)
 290#define HAL_RX_PPDU_END_USER_STATS_INFO0_DEVICE_ID		GENMASK(15, 14)
 291#define HAL_RX_PPDU_END_USER_STATS_INFO0_MPDU_CNT_FCS_ERR	GENMASK(26, 16)
 292
 293#define HAL_RX_PPDU_END_USER_STATS_INFO1_MPDU_CNT_FCS_OK	GENMASK(10, 0)
 294#define HAL_RX_PPDU_END_USER_STATS_INFO1_FC_VALID		BIT(11)
 295#define HAL_RX_PPDU_END_USER_STATS_INFO1_QOS_CTRL_VALID		BIT(12)
 296#define HAL_RX_PPDU_END_USER_STATS_INFO1_HT_CTRL_VALID		BIT(13)
 297#define HAL_RX_PPDU_END_USER_STATS_INFO1_PKT_TYPE              GENMASK(24, 21)
 298
 299#define HAL_RX_PPDU_END_USER_STATS_INFO2_AST_INDEX		GENMASK(15, 0)
 300#define HAL_RX_PPDU_END_USER_STATS_INFO2_FRAME_CTRL		GENMASK(31, 16)
 301
 302#define HAL_RX_PPDU_END_USER_STATS_INFO3_QOS_CTRL		GENMASK(31, 16)
 303
 304#define HAL_RX_PPDU_END_USER_STATS_INFO4_UDP_MSDU_CNT		GENMASK(15, 0)
 305#define HAL_RX_PPDU_END_USER_STATS_INFO4_TCP_MSDU_CNT		GENMASK(31, 16)
 306
 307#define HAL_RX_PPDU_END_USER_STATS_INFO5_OTHER_MSDU_CNT		GENMASK(15, 0)
 308#define HAL_RX_PPDU_END_USER_STATS_INFO5_TCP_ACK_MSDU_CNT	GENMASK(31, 16)
 309
 310#define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_BITMAP		GENMASK(15, 0)
 311#define HAL_RX_PPDU_END_USER_STATS_INFO6_TID_EOSP_BITMAP	GENMASK(31, 16)
 312
 313#define HAL_RX_PPDU_END_USER_STATS_INFO7_MPDU_OK_BYTE_COUNT    GENMASK(24, 0)
 314#define HAL_RX_PPDU_END_USER_STATS_INFO8_MPDU_ERR_BYTE_COUNT   GENMASK(24, 0)
 315
 316struct hal_rx_ppdu_end_user_stats {
 317	__le32 rsvd0[2];
 318	__le32 info0;
 319	__le32 info1;
 320	__le32 info2;
 321	__le32 info3;
 322	__le32 ht_ctrl;
 323	__le32 rsvd1[2];
 324	__le32 info4;
 325	__le32 info5;
 326	__le32 usr_resp_ref;
 327	__le32 info6;
 328	__le32 rsvd3[4];
 329	__le32 info7;
 330	__le32 rsvd4;
 331	__le32 info8;
 332	__le32 rsvd5[2];
 333	__le32 usr_resp_ref_ext;
 334	__le32 rsvd6;
 335} __packed;
 336
 337struct hal_rx_ppdu_end_user_stats_ext {
 338	__le32 info0;
 339	__le32 info1;
 340	__le32 info2;
 341	__le32 info3;
 342	__le32 info4;
 343	__le32 info5;
 344	__le32 info6;
 345	__le32 rsvd;
 346} __packed;
 347
 348#define HAL_RX_HT_SIG_INFO_INFO0_MCS		GENMASK(6, 0)
 349#define HAL_RX_HT_SIG_INFO_INFO0_BW		BIT(7)
 350
 351#define HAL_RX_HT_SIG_INFO_INFO1_STBC		GENMASK(5, 4)
 352#define HAL_RX_HT_SIG_INFO_INFO1_FEC_CODING	BIT(6)
 353#define HAL_RX_HT_SIG_INFO_INFO1_GI		BIT(7)
 354
 355struct hal_rx_ht_sig_info {
 356	__le32 info0;
 357	__le32 info1;
 358} __packed;
 359
 360#define HAL_RX_LSIG_B_INFO_INFO0_RATE	GENMASK(3, 0)
 361#define HAL_RX_LSIG_B_INFO_INFO0_LEN	GENMASK(15, 4)
 362
 363struct hal_rx_lsig_b_info {
 364	__le32 info0;
 365} __packed;
 366
 367#define HAL_RX_LSIG_A_INFO_INFO0_RATE		GENMASK(3, 0)
 368#define HAL_RX_LSIG_A_INFO_INFO0_LEN		GENMASK(16, 5)
 369#define HAL_RX_LSIG_A_INFO_INFO0_PKT_TYPE	GENMASK(27, 24)
 370
 371struct hal_rx_lsig_a_info {
 372	__le32 info0;
 373} __packed;
 374
 375#define HAL_RX_VHT_SIG_A_INFO_INFO0_BW		GENMASK(1, 0)
 376#define HAL_RX_VHT_SIG_A_INFO_INFO0_STBC	BIT(3)
 377#define HAL_RX_VHT_SIG_A_INFO_INFO0_GROUP_ID	GENMASK(9, 4)
 378#define HAL_RX_VHT_SIG_A_INFO_INFO0_NSTS	GENMASK(21, 10)
 379
 380#define HAL_RX_VHT_SIG_A_INFO_INFO1_GI_SETTING		GENMASK(1, 0)
 381#define HAL_RX_VHT_SIG_A_INFO_INFO1_SU_MU_CODING	BIT(2)
 382#define HAL_RX_VHT_SIG_A_INFO_INFO1_MCS			GENMASK(7, 4)
 383#define HAL_RX_VHT_SIG_A_INFO_INFO1_BEAMFORMED		BIT(8)
 384
 385struct hal_rx_vht_sig_a_info {
 386	__le32 info0;
 387	__le32 info1;
 388} __packed;
 389
 390enum hal_rx_vht_sig_a_gi_setting {
 391	HAL_RX_VHT_SIG_A_NORMAL_GI = 0,
 392	HAL_RX_VHT_SIG_A_SHORT_GI = 1,
 393	HAL_RX_VHT_SIG_A_SHORT_GI_AMBIGUITY = 3,
 394};
 395
 396#define HE_GI_0_8 0
 397#define HE_GI_0_4 1
 398#define HE_GI_1_6 2
 399#define HE_GI_3_2 3
 400
 401#define HE_LTF_1_X 0
 402#define HE_LTF_2_X 1
 403#define HE_LTF_4_X 2
 404
 405#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_MCS	GENMASK(6, 3)
 406#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DCM		BIT(7)
 407#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_TRANSMIT_BW	GENMASK(20, 19)
 408#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_CP_LTF_SIZE	GENMASK(22, 21)
 409#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_NSTS		GENMASK(25, 23)
 410#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BSS_COLOR		GENMASK(13, 8)
 411#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_SPATIAL_REUSE	GENMASK(18, 15)
 412#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_FORMAT_IND	BIT(0)
 413#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_BEAM_CHANGE	BIT(1)
 414#define HAL_RX_HE_SIG_A_SU_INFO_INFO0_DL_UL_FLAG	BIT(2)
 415
 416#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXOP_DURATION	GENMASK(6, 0)
 417#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_CODING		BIT(7)
 418#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_LDPC_EXTRA	BIT(8)
 419#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_STBC		BIT(9)
 420#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_TXBF		BIT(10)
 421#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_FACTOR	GENMASK(12, 11)
 422#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_PKT_EXT_PE_DISAM	BIT(13)
 423#define HAL_RX_HE_SIG_A_SU_INFO_INFO1_DOPPLER_IND	BIT(15)
 424
 425struct hal_rx_he_sig_a_su_info {
 426	__le32 info0;
 427	__le32 info1;
 428} __packed;
 429
 430#define HAL_RX_HE_SIG_A_MU_DL_INFO0_UL_FLAG		BIT(1)
 431#define HAL_RX_HE_SIG_A_MU_DL_INFO0_MCS_OF_SIGB		GENMASK(3, 1)
 432#define HAL_RX_HE_SIG_A_MU_DL_INFO0_DCM_OF_SIGB		BIT(4)
 433#define HAL_RX_HE_SIG_A_MU_DL_INFO0_BSS_COLOR		GENMASK(10, 5)
 434#define HAL_RX_HE_SIG_A_MU_DL_INFO0_SPATIAL_REUSE	GENMASK(14, 11)
 435#define HAL_RX_HE_SIG_A_MU_DL_INFO0_TRANSMIT_BW		GENMASK(17, 15)
 436#define HAL_RX_HE_SIG_A_MU_DL_INFO0_NUM_SIGB_SYMB	GENMASK(21, 18)
 437#define HAL_RX_HE_SIG_A_MU_DL_INFO0_COMP_MODE_SIGB	BIT(22)
 438#define HAL_RX_HE_SIG_A_MU_DL_INFO0_CP_LTF_SIZE		GENMASK(24, 23)
 439#define HAL_RX_HE_SIG_A_MU_DL_INFO0_DOPPLER_INDICATION	BIT(25)
 440
 441#define HAL_RX_HE_SIG_A_MU_DL_INFO1_TXOP_DURATION	GENMASK(6, 0)
 442#define HAL_RX_HE_SIG_A_MU_DL_INFO1_NUM_LTF_SYMB	GENMASK(10, 8)
 443#define HAL_RX_HE_SIG_A_MU_DL_INFO1_LDPC_EXTRA		BIT(11)
 444#define HAL_RX_HE_SIG_A_MU_DL_INFO1_STBC		BIT(12)
 445#define HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_FACTOR	GENMASK(14, 13)
 446#define HAL_RX_HE_SIG_A_MU_DL_INFO1_PKT_EXT_PE_DISAM	BIT(15)
 447
 448struct hal_rx_he_sig_a_mu_dl_info {
 449	__le32 info0;
 450	__le32 info1;
 451} __packed;
 452
 453#define HAL_RX_HE_SIG_B1_MU_INFO_INFO0_RU_ALLOCATION	GENMASK(7, 0)
 454
 455struct hal_rx_he_sig_b1_mu_info {
 456	__le32 info0;
 457} __packed;
 458
 459#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_ID           GENMASK(10, 0)
 460#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_MCS		GENMASK(18, 15)
 461#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_CODING	BIT(20)
 462#define HAL_RX_HE_SIG_B2_MU_INFO_INFO0_STA_NSTS		GENMASK(31, 29)
 463
 464struct hal_rx_he_sig_b2_mu_info {
 465	__le32 info0;
 466} __packed;
 467
 468#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_ID	GENMASK(10, 0)
 469#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_NSTS	GENMASK(13, 11)
 470#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_TXBF	BIT(14)
 471#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_MCS	GENMASK(18, 15)
 472#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_DCM	BIT(19)
 473#define HAL_RX_HE_SIG_B2_OFDMA_INFO_INFO0_STA_CODING	BIT(20)
 474
 475struct hal_rx_he_sig_b2_ofdma_info {
 476	__le32 info0;
 477} __packed;
 478
 479enum hal_rx_ul_reception_type {
 480	HAL_RECEPTION_TYPE_ULOFMDA,
 481	HAL_RECEPTION_TYPE_ULMIMO,
 482	HAL_RECEPTION_TYPE_OTHER,
 483	HAL_RECEPTION_TYPE_FRAMELESS
 484};
 485
 486#define HAL_RX_RSSI_LEGACY_INFO_INFO0_RECEPTION		GENMASK(3, 0)
 487#define HAL_RX_RSSI_LEGACY_INFO_INFO0_RX_BW		GENMASK(7, 5)
 488#define HAL_RX_RSSI_LEGACY_INFO_INFO1_RSSI_COMB		GENMASK(15, 8)
 489#define HAL_RX_RSSI_LEGACY_INFO_INFO2_RSSI_COMB_PPDU	GENMASK(7, 0)
 490
 491struct hal_rx_phyrx_rssi_legacy_info {
 492	__le32 info0;
 493	__le32 rsvd0[39];
 494	__le32 info1;
 495	__le32 info2;
 496} __packed;
 497
 498#define HAL_RX_MPDU_START_INFO0_PPDU_ID			GENMASK(31, 16)
 499#define HAL_RX_MPDU_START_INFO1_PEERID			GENMASK(29, 16)
 500#define HAL_RX_MPDU_START_INFO1_DEVICE_ID		GENMASK(31, 30)
 501#define HAL_RX_MPDU_START_INFO2_MPDU_LEN		GENMASK(13, 0)
 502struct hal_rx_mpdu_start {
 503	__le32 rsvd0[9];
 504	__le32 info0;
 505	__le32 info1;
 506	__le32 rsvd1[2];
 507	__le32 info2;
 508	__le32 rsvd2[16];
 509} __packed;
 510
 511struct hal_rx_msdu_end {
 512	__le32 info0;
 513	__le32 rsvd0[9];
 514	__le16 info00;
 515	__le16 info01;
 516	__le32 rsvd00[8];
 517	__le32 info1;
 518	__le32 rsvd1[10];
 519	__le32 info2;
 520	__le32 rsvd2;
 521} __packed;
 522
 523#define HAL_RX_PPDU_END_DURATION	GENMASK(23, 0)
 524struct hal_rx_ppdu_end_duration {
 525	__le32 rsvd0[9];
 526	__le32 info0;
 527	__le32 rsvd1[18];
 528} __packed;
 529
 530struct hal_rx_rxpcu_classification_overview {
 531	u32 rsvd0;
 532} __packed;
 533
 534struct hal_rx_msdu_desc_info {
 535	u32 msdu_flags;
 536	u16 msdu_len; /* 14 bits for length */
 537};
 538
 539#define HAL_RX_NUM_MSDU_DESC 6
 540struct hal_rx_msdu_list {
 541	struct hal_rx_msdu_desc_info msdu_info[HAL_RX_NUM_MSDU_DESC];
 542	u64 paddr[HAL_RX_NUM_MSDU_DESC];
 543	u32 sw_cookie[HAL_RX_NUM_MSDU_DESC];
 544	u8 rbm[HAL_RX_NUM_MSDU_DESC];
 545};
 546
 547#define HAL_RX_FBM_ACK_INFO0_ADDR1_31_0		GENMASK(31, 0)
 548#define HAL_RX_FBM_ACK_INFO1_ADDR1_47_32	GENMASK(15, 0)
 549#define HAL_RX_FBM_ACK_INFO1_ADDR2_15_0		GENMASK(31, 16)
 550#define HAL_RX_FBM_ACK_INFO2_ADDR2_47_16	GENMASK(31, 0)
 551
 552struct hal_rx_frame_bitmap_ack {
 553	__le32 reserved;
 554	__le32 info0;
 555	__le32 info1;
 556	__le32 info2;
 557	__le32 reserved1[10];
 558} __packed;
 559
 560#define HAL_RX_RESP_REQ_INFO0_PPDU_ID		GENMASK(15, 0)
 561#define HAL_RX_RESP_REQ_INFO0_RECEPTION_TYPE	BIT(16)
 562#define HAL_RX_RESP_REQ_INFO1_DURATION		GENMASK(15, 0)
 563#define HAL_RX_RESP_REQ_INFO1_RATE_MCS		GENMASK(24, 21)
 564#define HAL_RX_RESP_REQ_INFO1_SGI		GENMASK(26, 25)
 565#define HAL_RX_RESP_REQ_INFO1_STBC		BIT(27)
 566#define HAL_RX_RESP_REQ_INFO1_LDPC		BIT(28)
 567#define HAL_RX_RESP_REQ_INFO1_IS_AMPDU		BIT(29)
 568#define HAL_RX_RESP_REQ_INFO2_NUM_USER		GENMASK(6, 0)
 569#define HAL_RX_RESP_REQ_INFO3_ADDR1_31_0	GENMASK(31, 0)
 570#define HAL_RX_RESP_REQ_INFO4_ADDR1_47_32	GENMASK(15, 0)
 571#define HAL_RX_RESP_REQ_INFO4_ADDR1_15_0	GENMASK(31, 16)
 572#define HAL_RX_RESP_REQ_INFO5_ADDR1_47_16	GENMASK(31, 0)
 573
 574struct hal_rx_resp_req_info {
 575	__le32 info0;
 576	__le32 reserved[1];
 577	__le32 info1;
 578	__le32 info2;
 579	__le32 reserved1[2];
 580	__le32 info3;
 581	__le32 info4;
 582	__le32 info5;
 583	__le32 reserved2[5];
 584} __packed;
 585
 586#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0 0xDDBEEF
 587#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1 0xADBEEF
 588#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2 0xBDBEEF
 589#define REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3 0xCDBEEF
 590
 591#define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VALID		BIT(30)
 592#define HAL_RX_UL_OFDMA_USER_INFO_V0_W0_VER		BIT(31)
 593#define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_NSS		GENMASK(2, 0)
 594#define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_MCS		GENMASK(6, 3)
 595#define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_LDPC		BIT(7)
 596#define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_DCM		BIT(8)
 597#define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_START	GENMASK(15, 9)
 598#define HAL_RX_UL_OFDMA_USER_INFO_V0_W1_RU_SIZE		GENMASK(18, 16)
 599
 600/* HE Radiotap data1 Mask */
 601#define HE_SU_FORMAT_TYPE 0x0000
 602#define HE_EXT_SU_FORMAT_TYPE 0x0001
 603#define HE_MU_FORMAT_TYPE  0x0002
 604#define HE_TRIG_FORMAT_TYPE  0x0003
 605#define HE_BEAM_CHANGE_KNOWN 0x0008
 606#define HE_DL_UL_KNOWN 0x0010
 607#define HE_MCS_KNOWN 0x0020
 608#define HE_DCM_KNOWN 0x0040
 609#define HE_CODING_KNOWN 0x0080
 610#define HE_LDPC_EXTRA_SYMBOL_KNOWN 0x0100
 611#define HE_STBC_KNOWN 0x0200
 612#define HE_DATA_BW_RU_KNOWN 0x4000
 613#define HE_DOPPLER_KNOWN 0x8000
 614#define HE_BSS_COLOR_KNOWN 0x0004
 615
 616/* HE Radiotap data2 Mask */
 617#define HE_GI_KNOWN 0x0002
 618#define HE_TXBF_KNOWN 0x0010
 619#define HE_PE_DISAMBIGUITY_KNOWN 0x0020
 620#define HE_TXOP_KNOWN 0x0040
 621#define HE_LTF_SYMBOLS_KNOWN 0x0004
 622#define HE_PRE_FEC_PADDING_KNOWN 0x0008
 623#define HE_MIDABLE_PERIODICITY_KNOWN 0x0080
 624
 625/* HE radiotap data3 shift values */
 626#define HE_BEAM_CHANGE_SHIFT 6
 627#define HE_DL_UL_SHIFT 7
 628#define HE_TRANSMIT_MCS_SHIFT 8
 629#define HE_DCM_SHIFT 12
 630#define HE_CODING_SHIFT 13
 631#define HE_LDPC_EXTRA_SYMBOL_SHIFT 14
 632#define HE_STBC_SHIFT 15
 633
 634/* HE radiotap data4 shift values */
 635#define HE_STA_ID_SHIFT 4
 636
 637/* HE radiotap data5 */
 638#define HE_GI_SHIFT 4
 639#define HE_LTF_SIZE_SHIFT 6
 640#define HE_LTF_SYM_SHIFT 8
 641#define HE_TXBF_SHIFT 14
 642#define HE_PE_DISAMBIGUITY_SHIFT 15
 643#define HE_PRE_FEC_PAD_SHIFT 12
 644
 645/* HE radiotap data6 */
 646#define HE_DOPPLER_SHIFT 4
 647#define HE_TXOP_SHIFT 8
 648
 649/* HE radiotap HE-MU flags1 */
 650#define HE_SIG_B_MCS_KNOWN 0x0010
 651#define HE_SIG_B_DCM_KNOWN 0x0040
 652#define HE_SIG_B_SYM_NUM_KNOWN 0x8000
 653#define HE_RU_0_KNOWN 0x0100
 654#define HE_RU_1_KNOWN 0x0200
 655#define HE_RU_2_KNOWN 0x0400
 656#define HE_RU_3_KNOWN 0x0800
 657#define HE_DCM_FLAG_1_SHIFT 5
 658#define HE_SPATIAL_REUSE_MU_KNOWN 0x0100
 659#define HE_SIG_B_COMPRESSION_FLAG_1_KNOWN 0x4000
 660
 661/* HE radiotap HE-MU flags2 */
 662#define HE_SIG_B_COMPRESSION_FLAG_2_SHIFT 3
 663#define HE_BW_KNOWN 0x0004
 664#define HE_NUM_SIG_B_SYMBOLS_SHIFT 4
 665#define HE_SIG_B_COMPRESSION_FLAG_2_KNOWN 0x0100
 666#define HE_NUM_SIG_B_FLAG_2_SHIFT 9
 667#define HE_LTF_FLAG_2_SYMBOLS_SHIFT 12
 668#define HE_LTF_KNOWN 0x8000
 669
 670/* HE radiotap per_user_1 */
 671#define HE_STA_SPATIAL_SHIFT 11
 672#define HE_TXBF_SHIFT 14
 673#define HE_RESERVED_SET_TO_1_SHIFT 19
 674#define HE_STA_CODING_SHIFT 20
 675
 676/* HE radiotap per_user_2 */
 677#define HE_STA_MCS_SHIFT 4
 678#define HE_STA_DCM_SHIFT 5
 679
 680/* HE radiotap per user known */
 681#define HE_USER_FIELD_POSITION_KNOWN 0x01
 682#define HE_STA_ID_PER_USER_KNOWN 0x02
 683#define HE_STA_NSTS_KNOWN 0x04
 684#define HE_STA_TX_BF_KNOWN 0x08
 685#define HE_STA_SPATIAL_CONFIG_KNOWN 0x10
 686#define HE_STA_MCS_KNOWN 0x20
 687#define HE_STA_DCM_KNOWN 0x40
 688#define HE_STA_CODING_KNOWN 0x80
 689
 690#define HAL_RX_MPDU_ERR_FCS			BIT(0)
 691#define HAL_RX_MPDU_ERR_DECRYPT			BIT(1)
 692#define HAL_RX_MPDU_ERR_TKIP_MIC		BIT(2)
 693#define HAL_RX_MPDU_ERR_AMSDU_ERR		BIT(3)
 694#define HAL_RX_MPDU_ERR_OVERFLOW		BIT(4)
 695#define HAL_RX_MPDU_ERR_MSDU_LEN		BIT(5)
 696#define HAL_RX_MPDU_ERR_MPDU_LEN		BIT(6)
 697#define HAL_RX_MPDU_ERR_UNENCRYPTED_FRAME	BIT(7)
 698
 699#define HAL_RX_CMN_USR_INFO0_CP_SETTING			GENMASK(17, 16)
 700#define HAL_RX_CMN_USR_INFO0_LTF_SIZE			GENMASK(19, 18)
 701
 702struct hal_phyrx_common_user_info {
 703	__le32 rsvd[2];
 704	__le32 info0;
 705	__le32 rsvd1;
 706} __packed;
 707
 708#define HAL_RX_EHT_SIG_NDP_CMN_INFO0_SPATIAL_REUSE	GENMASK(3, 0)
 709#define HAL_RX_EHT_SIG_NDP_CMN_INFO0_GI_LTF		GENMASK(5, 4)
 710#define HAL_RX_EHT_SIG_NDP_CMN_INFO0_NUM_LTF_SYM	GENMASK(8, 6)
 711#define HAL_RX_EHT_SIG_NDP_CMN_INFO0_NSS		GENMASK(10, 7)
 712#define HAL_RX_EHT_SIG_NDP_CMN_INFO0_BEAMFORMED		BIT(11)
 713#define HAL_RX_EHT_SIG_NDP_CMN_INFO0_DISREGARD		GENMASK(13, 12)
 714#define HAL_RX_EHT_SIG_NDP_CMN_INFO0_CRC		GENMASK(17, 14)
 715
 716struct hal_eht_sig_ndp_cmn_eb {
 717	__le32 info0;
 718} __packed;
 719
 720#define HAL_RX_EHT_SIG_OVERFLOW_INFO0_SPATIAL_REUSE		GENMASK(3, 0)
 721#define HAL_RX_EHT_SIG_OVERFLOW_INFO0_GI_LTF			GENMASK(5, 4)
 722#define HAL_RX_EHT_SIG_OVERFLOW_INFO0_NUM_LTF_SYM		GENMASK(8, 6)
 723#define HAL_RX_EHT_SIG_OVERFLOW_INFO0_LDPC_EXTA_SYM		BIT(9)
 724#define HAL_RX_EHT_SIG_OVERFLOW_INFO0_PRE_FEC_PAD_FACTOR	GENMASK(11, 10)
 725#define HAL_RX_EHT_SIG_OVERFLOW_INFO0_DISAMBIGUITY		BIT(12)
 726#define HAL_RX_EHT_SIG_OVERFLOW_INFO0_DISREGARD			GENMASK(16, 13)
 727
 728struct hal_eht_sig_usig_overflow {
 729	__le32 info0;
 730} __packed;
 731
 732#define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_STA_ID	GENMASK(10, 0)
 733#define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_MCS	GENMASK(14, 11)
 734#define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_VALIDATE	BIT(15)
 735#define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_NSS	GENMASK(19, 16)
 736#define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_BEAMFORMED	BIT(20)
 737#define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_CODING	BIT(21)
 738#define HAL_RX_EHT_SIG_NON_MUMIMO_USER_INFO0_CRC	GENMASK(25, 22)
 739
 740struct hal_eht_sig_non_mu_mimo {
 741	__le32 info0;
 742} __packed;
 743
 744#define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_STA_ID		GENMASK(10, 0)
 745#define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_MCS		GENMASK(14, 11)
 746#define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_CODING		BIT(15)
 747#define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_SPATIAL_CODING	GENMASK(22, 16)
 748#define HAL_RX_EHT_SIG_MUMIMO_USER_INFO0_CRC		GENMASK(26, 23)
 749
 750struct hal_eht_sig_mu_mimo {
 751	__le32 info0;
 752} __packed;
 753
 754union hal_eht_sig_user_field {
 755	struct hal_eht_sig_mu_mimo mu_mimo;
 756	struct hal_eht_sig_non_mu_mimo n_mu_mimo;
 757};
 758
 759#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_SPATIAL_REUSE		GENMASK(3, 0)
 760#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_GI_LTF			GENMASK(5, 4)
 761#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_NUM_LTF_SYM		GENMASK(8, 6)
 762#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_LDPC_EXTA_SYM		BIT(9)
 763#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_PRE_FEC_PAD_FACTOR	GENMASK(11, 10)
 764#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_DISAMBIGUITY		BIT(12)
 765#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_DISREGARD		GENMASK(16, 13)
 766#define HAL_RX_EHT_SIG_NON_OFDMA_INFO0_NUM_USERS		GENMASK(19, 17)
 767
 768struct hal_eht_sig_non_ofdma_cmn_eb {
 769	__le32 info0;
 770	union hal_eht_sig_user_field user_field;
 771} __packed;
 772
 773#define HAL_RX_EHT_SIG_OFDMA_EB1_SPATIAL_REUSE		GENMASK_ULL(3, 0)
 774#define HAL_RX_EHT_SIG_OFDMA_EB1_GI_LTF			GENMASK_ULL(5, 4)
 775#define HAL_RX_EHT_SIG_OFDMA_EB1_NUM_LFT_SYM		GENMASK_ULL(8, 6)
 776#define HAL_RX_EHT_SIG_OFDMA_EB1_LDPC_EXTRA_SYM		BIT(9)
 777#define HAL_RX_EHT_SIG_OFDMA_EB1_PRE_FEC_PAD_FACTOR	GENMASK_ULL(11, 10)
 778#define HAL_RX_EHT_SIG_OFDMA_EB1_PRE_DISAMBIGUITY	BIT(12)
 779#define HAL_RX_EHT_SIG_OFDMA_EB1_DISREGARD		GENMASK_ULL(16, 13)
 780#define HAL_RX_EHT_SIG_OFDMA_EB1_RU_ALLOC_1_1		GENMASK_ULL(25, 17)
 781#define HAL_RX_EHT_SIG_OFDMA_EB1_RU_ALLOC_1_2		GENMASK_ULL(34, 26)
 782#define HAL_RX_EHT_SIG_OFDMA_EB1_CRC			GENMASK_ULL(30, 27)
 783
 784struct hal_eht_sig_ofdma_cmn_eb1 {
 785	__le64 info0;
 786} __packed;
 787
 788#define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_1		GENMASK_ULL(8, 0)
 789#define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_2		GENMASK_ULL(17, 9)
 790#define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_3		GENMASK_ULL(26, 18)
 791#define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_4		GENMASK_ULL(35, 27)
 792#define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_5		GENMASK_ULL(44, 36)
 793#define HAL_RX_EHT_SIG_OFDMA_EB2_RU_ALLOC_2_6		GENMASK_ULL(53, 45)
 794#define HAL_RX_EHT_SIG_OFDMA_EB2_MCS			GNEMASK_ULL(57, 54)
 795
 796struct hal_eht_sig_ofdma_cmn_eb2 {
 797	__le64 info0;
 798} __packed;
 799
 800struct hal_eht_sig_ofdma_cmn_eb {
 801	struct hal_eht_sig_ofdma_cmn_eb1 eb1;
 802	struct hal_eht_sig_ofdma_cmn_eb2 eb2;
 803	union hal_eht_sig_user_field user_field;
 804} __packed;
 805
 806enum hal_eht_bw {
 807	HAL_EHT_BW_20,
 808	HAL_EHT_BW_40,
 809	HAL_EHT_BW_80,
 810	HAL_EHT_BW_160,
 811	HAL_EHT_BW_320_1,
 812	HAL_EHT_BW_320_2,
 813};
 814
 815#define HAL_RX_USIG_CMN_INFO0_PHY_VERSION	GENMASK(2, 0)
 816#define HAL_RX_USIG_CMN_INFO0_BW		GENMASK(5, 3)
 817#define HAL_RX_USIG_CMN_INFO0_UL_DL		BIT(6)
 818#define HAL_RX_USIG_CMN_INFO0_BSS_COLOR		GENMASK(12, 7)
 819#define HAL_RX_USIG_CMN_INFO0_TXOP		GENMASK(19, 13)
 820#define HAL_RX_USIG_CMN_INFO0_DISREGARD		GENMASK(25, 20)
 821#define HAL_RX_USIG_CMN_INFO0_VALIDATE		BIT(26)
 822
 823struct hal_mon_usig_cmn {
 824	__le32 info0;
 825} __packed;
 826
 827#define HAL_RX_USIG_TB_INFO0_PPDU_TYPE_COMP_MODE	GENMASK(1, 0)
 828#define HAL_RX_USIG_TB_INFO0_VALIDATE			BIT(2)
 829#define HAL_RX_USIG_TB_INFO0_SPATIAL_REUSE_1		GENMASK(6, 3)
 830#define HAL_RX_USIG_TB_INFO0_SPATIAL_REUSE_2		GENMASK(10, 7)
 831#define HAL_RX_USIG_TB_INFO0_DISREGARD_1		GENMASK(15, 11)
 832#define HAL_RX_USIG_TB_INFO0_CRC			GENMASK(19, 16)
 833#define HAL_RX_USIG_TB_INFO0_TAIL			GENMASK(25, 20)
 834#define HAL_RX_USIG_TB_INFO0_RX_INTEG_CHECK_PASS	BIT(31)
 835
 836struct hal_mon_usig_tb {
 837	__le32 info0;
 838} __packed;
 839
 840#define HAL_RX_USIG_MU_INFO0_PPDU_TYPE_COMP_MODE	GENMASK(1, 0)
 841#define HAL_RX_USIG_MU_INFO0_VALIDATE_1			BIT(2)
 842#define HAL_RX_USIG_MU_INFO0_PUNC_CH_INFO		GENMASK(7, 3)
 843#define HAL_RX_USIG_MU_INFO0_VALIDATE_2			BIT(8)
 844#define HAL_RX_USIG_MU_INFO0_EHT_SIG_MCS		GENMASK(10, 9)
 845#define HAL_RX_USIG_MU_INFO0_NUM_EHT_SIG_SYM		GENMASK(15, 11)
 846#define HAL_RX_USIG_MU_INFO0_CRC			GENMASK(20, 16)
 847#define HAL_RX_USIG_MU_INFO0_TAIL			GENMASK(26, 21)
 848#define HAL_RX_USIG_MU_INFO0_RX_INTEG_CHECK_PASS	BIT(31)
 849
 850struct hal_mon_usig_mu {
 851	__le32 info0;
 852} __packed;
 853
 854union hal_mon_usig_non_cmn {
 855	struct hal_mon_usig_tb tb;
 856	struct hal_mon_usig_mu mu;
 857};
 858
 859struct hal_mon_usig_hdr {
 860	struct hal_mon_usig_cmn cmn;
 861	union hal_mon_usig_non_cmn non_cmn;
 862} __packed;
 863
 864#define HAL_RX_USR_INFO0_PHY_PPDU_ID		GENMASK(15, 0)
 865#define HAL_RX_USR_INFO0_USR_RSSI		GENMASK(23, 16)
 866#define HAL_RX_USR_INFO0_PKT_TYPE		GENMASK(27, 24)
 867#define HAL_RX_USR_INFO0_STBC			BIT(28)
 868#define HAL_RX_USR_INFO0_RECEPTION_TYPE		GENMASK(31, 29)
 869
 870#define HAL_RX_USR_INFO1_MCS			GENMASK(3, 0)
 871#define HAL_RX_USR_INFO1_SGI			GENMASK(5, 4)
 872#define HAL_RX_USR_INFO1_HE_RANGING_NDP		BIT(6)
 873#define HAL_RX_USR_INFO1_MIMO_SS_BITMAP		GENMASK(15, 8)
 874#define HAL_RX_USR_INFO1_RX_BW			GENMASK(18, 16)
 875#define HAL_RX_USR_INFO1_DL_OFMDA_USR_IDX	GENMASK(31, 24)
 876
 877#define HAL_RX_USR_INFO2_DL_OFDMA_CONTENT_CHAN	BIT(0)
 878#define HAL_RX_USR_INFO2_NSS			GENMASK(10, 8)
 879#define HAL_RX_USR_INFO2_STREAM_OFFSET		GENMASK(13, 11)
 880#define HAL_RX_USR_INFO2_STA_DCM		BIT(14)
 881#define HAL_RX_USR_INFO2_LDPC			BIT(15)
 882#define HAL_RX_USR_INFO2_RU_TYPE_80_0		GENMASK(19, 16)
 883#define HAL_RX_USR_INFO2_RU_TYPE_80_1		GENMASK(23, 20)
 884#define HAL_RX_USR_INFO2_RU_TYPE_80_2		GENMASK(27, 24)
 885#define HAL_RX_USR_INFO2_RU_TYPE_80_3		GENMASK(31, 28)
 886
 887#define HAL_RX_USR_INFO3_RU_START_IDX_80_0	GENMASK(5, 0)
 888#define HAL_RX_USR_INFO3_RU_START_IDX_80_1	GENMASK(13, 8)
 889#define HAL_RX_USR_INFO3_RU_START_IDX_80_2	GENMASK(21, 16)
 890#define HAL_RX_USR_INFO3_RU_START_IDX_80_3	GENMASK(29, 24)
 891
 892struct hal_receive_user_info {
 893	__le32 info0;
 894	__le32 info1;
 895	__le32 info2;
 896	__le32 info3;
 897	__le32 user_fd_rssi_seg0;
 898	__le32 user_fd_rssi_seg1;
 899	__le32 user_fd_rssi_seg2;
 900	__le32 user_fd_rssi_seg3;
 901} __packed;
 902
 903enum hal_mon_reception_type {
 904	HAL_RECEPTION_TYPE_SU,
 905	HAL_RECEPTION_TYPE_DL_MU_MIMO,
 906	HAL_RECEPTION_TYPE_DL_MU_OFMA,
 907	HAL_RECEPTION_TYPE_DL_MU_OFDMA_MIMO,
 908	HAL_RECEPTION_TYPE_UL_MU_MIMO,
 909	HAL_RECEPTION_TYPE_UL_MU_OFDMA,
 910	HAL_RECEPTION_TYPE_UL_MU_OFDMA_MIMO,
 911};
 912
 913/* Different allowed RU in 11BE */
 914#define HAL_EHT_RU_26		0ULL
 915#define HAL_EHT_RU_52		1ULL
 916#define HAL_EHT_RU_78		2ULL
 917#define HAL_EHT_RU_106		3ULL
 918#define HAL_EHT_RU_132		4ULL
 919#define HAL_EHT_RU_242		5ULL
 920#define HAL_EHT_RU_484		6ULL
 921#define HAL_EHT_RU_726		7ULL
 922#define HAL_EHT_RU_996		8ULL
 923#define HAL_EHT_RU_996x2	9ULL
 924#define HAL_EHT_RU_996x3	10ULL
 925#define HAL_EHT_RU_996x4	11ULL
 926#define HAL_EHT_RU_NONE		15ULL
 927#define HAL_EHT_RU_INVALID	31ULL
 928/* MRUs spanning above 80Mhz
 929 * HAL_EHT_RU_996_484 = HAL_EHT_RU_484 + HAL_EHT_RU_996 + 4 (reserved)
 930 */
 931#define HAL_EHT_RU_996_484	18ULL
 932#define HAL_EHT_RU_996x2_484	28ULL
 933#define HAL_EHT_RU_996x3_484	40ULL
 934#define HAL_EHT_RU_996_484_242	23ULL
 935
 936#define NUM_RU_BITS_PER80	16
 937#define NUM_RU_BITS_PER20	4
 938
 939/* Different per_80Mhz band in 320Mhz bandwidth */
 940#define HAL_80_0	0
 941#define HAL_80_1	1
 942#define HAL_80_2	2
 943#define HAL_80_3	3
 944
 945#define HAL_RU_80MHZ(num_band)		((num_band) * NUM_RU_BITS_PER80)
 946#define HAL_RU_20MHZ(idx_per_80)	((idx_per_80) * NUM_RU_BITS_PER20)
 947
 948#define HAL_RU_SHIFT(num_band, idx_per_80)	\
 949		(HAL_RU_80MHZ(num_band) + HAL_RU_20MHZ(idx_per_80))
 950
 951#define HAL_RU(ru, num_band, idx_per_80)	\
 952		((u64)(ru) << HAL_RU_SHIFT(num_band, idx_per_80))
 953
 954/* MRU-996+484 */
 955#define HAL_EHT_RU_996_484_0	(HAL_RU(HAL_EHT_RU_484, HAL_80_0, 1) |	\
 956				 HAL_RU(HAL_EHT_RU_996, HAL_80_1, 0))
 957#define HAL_EHT_RU_996_484_1	(HAL_RU(HAL_EHT_RU_484, HAL_80_0, 0) |	\
 958				 HAL_RU(HAL_EHT_RU_996, HAL_80_1, 0))
 959#define HAL_EHT_RU_996_484_2	(HAL_RU(HAL_EHT_RU_996, HAL_80_0, 0) |	\
 960				 HAL_RU(HAL_EHT_RU_484, HAL_80_1, 1))
 961#define HAL_EHT_RU_996_484_3	(HAL_RU(HAL_EHT_RU_996, HAL_80_0, 0) |	\
 962				 HAL_RU(HAL_EHT_RU_484, HAL_80_1, 0))
 963#define HAL_EHT_RU_996_484_4	(HAL_RU(HAL_EHT_RU_484, HAL_80_2, 1) |	\
 964				 HAL_RU(HAL_EHT_RU_996, HAL_80_3, 0))
 965#define HAL_EHT_RU_996_484_5	(HAL_RU(HAL_EHT_RU_484, HAL_80_2, 0) |	\
 966				 HAL_RU(HAL_EHT_RU_996, HAL_80_3, 0))
 967#define HAL_EHT_RU_996_484_6	(HAL_RU(HAL_EHT_RU_996, HAL_80_2, 0) |	\
 968				 HAL_RU(HAL_EHT_RU_484, HAL_80_3, 1))
 969#define HAL_EHT_RU_996_484_7	(HAL_RU(HAL_EHT_RU_996, HAL_80_2, 0) |	\
 970				 HAL_RU(HAL_EHT_RU_484, HAL_80_3, 0))
 971
 972/* MRU-996x2+484 */
 973#define HAL_EHT_RU_996x2_484_0	(HAL_RU(HAL_EHT_RU_484, HAL_80_0, 1) |	\
 974				 HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) |	\
 975				 HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0))
 976#define HAL_EHT_RU_996x2_484_1	(HAL_RU(HAL_EHT_RU_484, HAL_80_0, 0) |	\
 977				 HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) |	\
 978				 HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0))
 979#define HAL_EHT_RU_996x2_484_2	(HAL_RU(HAL_EHT_RU_996x2, HAL_80_0, 0) |	\
 980				 HAL_RU(HAL_EHT_RU_484, HAL_80_1, 1) |	\
 981				 HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0))
 982#define HAL_EHT_RU_996x2_484_3	(HAL_RU(HAL_EHT_RU_996x2, HAL_80_0, 0) |	\
 983				 HAL_RU(HAL_EHT_RU_484, HAL_80_1, 0) |	\
 984				 HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0))
 985#define HAL_EHT_RU_996x2_484_4	(HAL_RU(HAL_EHT_RU_996x2, HAL_80_0, 0) |	\
 986				 HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) |	\
 987				 HAL_RU(HAL_EHT_RU_484, HAL_80_2, 1))
 988#define HAL_EHT_RU_996x2_484_5	(HAL_RU(HAL_EHT_RU_996x2, HAL_80_0, 0) |	\
 989				 HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) |	\
 990				 HAL_RU(HAL_EHT_RU_484, HAL_80_2, 0))
 991#define HAL_EHT_RU_996x2_484_6	(HAL_RU(HAL_EHT_RU_484, HAL_80_1, 1) |	\
 992				 HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0) |	\
 993				 HAL_RU(HAL_EHT_RU_996x2, HAL_80_3, 0))
 994#define HAL_EHT_RU_996x2_484_7	(HAL_RU(HAL_EHT_RU_484, HAL_80_1, 0) |	\
 995				 HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0) |	\
 996				 HAL_RU(HAL_EHT_RU_996x2, HAL_80_3, 0))
 997#define HAL_EHT_RU_996x2_484_8	(HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) |	\
 998				 HAL_RU(HAL_EHT_RU_484, HAL_80_2, 1) |	\
 999				 HAL_RU(HAL_EHT_RU_996x2, HAL_80_3, 0))
1000#define HAL_EHT_RU_996x2_484_9	(HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) |	\
1001				 HAL_RU(HAL_EHT_RU_484, HAL_80_2, 0) |	\
1002				 HAL_RU(HAL_EHT_RU_996x2, HAL_80_3, 0))
1003#define HAL_EHT_RU_996x2_484_10	(HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) |	\
1004				 HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0) |	\
1005				 HAL_RU(HAL_EHT_RU_484, HAL_80_3, 1))
1006#define HAL_EHT_RU_996x2_484_11	(HAL_RU(HAL_EHT_RU_996x2, HAL_80_1, 0) |	\
1007				 HAL_RU(HAL_EHT_RU_996x2, HAL_80_2, 0) |	\
1008				 HAL_RU(HAL_EHT_RU_484, HAL_80_3, 0))
1009
1010/* MRU-996x3+484 */
1011#define HAL_EHT_RU_996x3_484_0	(HAL_RU(HAL_EHT_RU_484, HAL_80_0, 1) |	\
1012				 HAL_RU(HAL_EHT_RU_996x3, HAL_80_1, 0) |	\
1013				 HAL_RU(HAL_EHT_RU_996x3, HAL_80_2, 0) |	\
1014				 HAL_RU(HAL_EHT_RU_996x3, HAL_80_3, 0))
1015#define HAL_EHT_RU_996x3_484_1	(HAL_RU(HAL_EHT_RU_484, HAL_80_0, 0) |	\
1016				 HAL_RU(HAL_EHT_RU_996x3, HAL_80_1, 0) |	\
1017				 HAL_RU(HAL_EHT_RU_996x3, HAL_80_2, 0) |	\
1018				 HAL_RU(HAL_EHT_RU_996x3, HAL_80_3, 0))
1019#define HAL_EHT_RU_996x3_484_2	(HAL_RU(HAL_EHT_RU_996x3, HAL_80_0, 0) |	\
1020				 HAL_RU(HAL_EHT_RU_484, HAL_80_1, 1) |	\
1021				 HAL_RU(HAL_EHT_RU_996x3, HAL_80_2, 0) |	\
1022				 HAL_RU(HAL_EHT_RU_996x3, HAL_80_3, 0))
1023#define HAL_EHT_RU_996x3_484_3	(HAL_RU(HAL_EHT_RU_996x3, HAL_80_0, 0) |	\
1024				 HAL_RU(HAL_EHT_RU_484, HAL_80_1, 0) |	\
1025				 HAL_RU(HAL_EHT_RU_996x3, HAL_80_2, 0) |	\
1026				 HAL_RU(HAL_EHT_RU_996x3, HAL_80_3, 0))
1027#define HAL_EHT_RU_996x3_484_4	(HAL_RU(HAL_EHT_RU_996x3, HAL_80_0, 0) |	\
1028				 HAL_RU(HAL_EHT_RU_996x3, HAL_80_1, 0) |	\
1029				 HAL_RU(HAL_EHT_RU_484, HAL_80_2, 1) |	\
1030				 HAL_RU(HAL_EHT_RU_996x3, HAL_80_3, 0))
1031#define HAL_EHT_RU_996x3_484_5	(HAL_RU(HAL_EHT_RU_996x3, HAL_80_0, 0) |	\
1032				 HAL_RU(HAL_EHT_RU_996x3, HAL_80_1, 0) |	\
1033				 HAL_RU(HAL_EHT_RU_484, HAL_80_2, 0) |	\
1034				 HAL_RU(HAL_EHT_RU_996x3, HAL_80_3, 0))
1035#define HAL_EHT_RU_996x3_484_6	(HAL_RU(HAL_EHT_RU_996x3, HAL_80_0, 0) |	\
1036				 HAL_RU(HAL_EHT_RU_996x3, HAL_80_1, 0) |	\
1037				 HAL_RU(HAL_EHT_RU_996x3, HAL_80_2, 0) |	\
1038				 HAL_RU(HAL_EHT_RU_484, HAL_80_3, 1))
1039#define HAL_EHT_RU_996x3_484_7	(HAL_RU(HAL_EHT_RU_996x3, HAL_80_0, 0) |	\
1040				 HAL_RU(HAL_EHT_RU_996x3, HAL_80_1, 0) |	\
1041				 HAL_RU(HAL_EHT_RU_996x3, HAL_80_2, 0) |	\
1042				 HAL_RU(HAL_EHT_RU_484, HAL_80_3, 0))
1043
1044#define HAL_RU_PER80(ru_per80, num_80mhz, ru_idx_per80mhz) \
1045			(HAL_RU(ru_per80, num_80mhz, ru_idx_per80mhz))
1046
1047#define RU_INVALID		0
1048#define RU_26			1
1049#define RU_52			2
1050#define RU_106			4
1051#define RU_242			9
1052#define RU_484			18
1053#define RU_996			37
1054#define RU_2X996		74
1055#define RU_3X996		111
1056#define RU_4X996		148
1057#define RU_52_26		(RU_52 + RU_26)
1058#define RU_106_26		(RU_106 + RU_26)
1059#define RU_484_242		(RU_484 + RU_242)
1060#define RU_996_484		(RU_996 + RU_484)
1061#define RU_996_484_242		(RU_996 + RU_484_242)
1062#define RU_2X996_484		(RU_2X996 + RU_484)
1063#define RU_3X996_484		(RU_3X996 + RU_484)
1064
1065enum ath12k_eht_ru_size {
1066	ATH12K_EHT_RU_26,
1067	ATH12K_EHT_RU_52,
1068	ATH12K_EHT_RU_106,
1069	ATH12K_EHT_RU_242,
1070	ATH12K_EHT_RU_484,
1071	ATH12K_EHT_RU_996,
1072	ATH12K_EHT_RU_996x2,
1073	ATH12K_EHT_RU_996x4,
1074	ATH12K_EHT_RU_52_26,
1075	ATH12K_EHT_RU_106_26,
1076	ATH12K_EHT_RU_484_242,
1077	ATH12K_EHT_RU_996_484,
1078	ATH12K_EHT_RU_996_484_242,
1079	ATH12K_EHT_RU_996x2_484,
1080	ATH12K_EHT_RU_996x3,
1081	ATH12K_EHT_RU_996x3_484,
1082
1083	/* Keep last */
1084	ATH12K_EHT_RU_INVALID,
1085};
1086
1087#define HAL_RX_RU_ALLOC_TYPE_MAX	ATH12K_EHT_RU_INVALID
1088
1089static inline
1090enum nl80211_he_ru_alloc ath12k_he_ru_tones_to_nl80211_he_ru_alloc(u16 ru_tones)
1091{
1092	enum nl80211_he_ru_alloc ret;
1093
1094	switch (ru_tones) {
1095	case RU_52:
1096		ret = NL80211_RATE_INFO_HE_RU_ALLOC_52;
1097		break;
1098	case RU_106:
1099		ret = NL80211_RATE_INFO_HE_RU_ALLOC_106;
1100		break;
1101	case RU_242:
1102		ret = NL80211_RATE_INFO_HE_RU_ALLOC_242;
1103		break;
1104	case RU_484:
1105		ret = NL80211_RATE_INFO_HE_RU_ALLOC_484;
1106		break;
1107	case RU_996:
1108		ret = NL80211_RATE_INFO_HE_RU_ALLOC_996;
1109		break;
1110	case RU_2X996:
1111		ret = NL80211_RATE_INFO_HE_RU_ALLOC_2x996;
1112		break;
1113	case RU_26:
1114		fallthrough;
1115	default:
1116		ret = NL80211_RATE_INFO_HE_RU_ALLOC_26;
1117		break;
1118	}
1119	return ret;
1120}
1121
1122void ath12k_hal_reo_status_queue_stats(struct ath12k_base *ab,
1123				       struct hal_tlv_64_hdr *tlv,
1124				       struct hal_reo_status *status);
1125void ath12k_hal_reo_flush_queue_status(struct ath12k_base *ab,
1126				       struct hal_tlv_64_hdr *tlv,
1127				       struct hal_reo_status *status);
1128void ath12k_hal_reo_flush_cache_status(struct ath12k_base *ab,
1129				       struct hal_tlv_64_hdr *tlv,
1130				       struct hal_reo_status *status);
1131void ath12k_hal_reo_unblk_cache_status(struct ath12k_base *ab,
1132				       struct hal_tlv_64_hdr *tlv,
1133				       struct hal_reo_status *status);
1134void ath12k_hal_reo_flush_timeout_list_status(struct ath12k_base *ab,
1135					      struct hal_tlv_64_hdr *tlv,
1136					      struct hal_reo_status *status);
1137void ath12k_hal_reo_desc_thresh_reached_status(struct ath12k_base *ab,
1138					       struct hal_tlv_64_hdr *tlv,
1139					       struct hal_reo_status *status);
1140void ath12k_hal_reo_update_rx_reo_queue_status(struct ath12k_base *ab,
1141					       struct hal_tlv_64_hdr *tlv,
1142					       struct hal_reo_status *status);
1143void ath12k_hal_rx_msdu_link_info_get(struct hal_rx_msdu_link *link, u32 *num_msdus,
1144				      u32 *msdu_cookies,
1145				      enum hal_rx_buf_return_buf_manager *rbm);
1146void ath12k_hal_rx_msdu_link_desc_set(struct ath12k_base *ab,
1147				      struct hal_wbm_release_ring *desc,
1148				      struct ath12k_buffer_addr *buf_addr_info,
1149				      enum hal_wbm_rel_bm_act action);
1150void ath12k_hal_rx_buf_addr_info_set(struct ath12k_buffer_addr *binfo,
1151				     dma_addr_t paddr, u32 cookie, u8 manager);
1152void ath12k_hal_rx_buf_addr_info_get(struct ath12k_buffer_addr *binfo,
1153				     dma_addr_t *paddr,
1154				     u32 *cookie, u8 *rbm);
1155int ath12k_hal_desc_reo_parse_err(struct ath12k_base *ab,
1156				  struct hal_reo_dest_ring *desc,
1157				  dma_addr_t *paddr, u32 *desc_bank);
1158int ath12k_hal_wbm_desc_parse_err(struct ath12k_base *ab, void *desc,
1159				  struct hal_rx_wbm_rel_info *rel_info);
1160void ath12k_hal_rx_reo_ent_paddr_get(struct ath12k_base *ab,
1161				     struct ath12k_buffer_addr *buff_addr,
1162				     dma_addr_t *paddr, u32 *cookie);
1163void ath12k_hal_rx_reo_ent_buf_paddr_get(void *rx_desc, dma_addr_t *paddr, u32 *sw_cookie,
1164					 struct ath12k_buffer_addr **pp_buf_addr,
1165					 u8 *rbm, u32 *msdu_cnt);
1166void ath12k_hal_rx_msdu_list_get(struct ath12k *ar,
1167				 struct hal_rx_msdu_link *link_desc,
1168				 struct hal_rx_msdu_list *msdu_list,
1169				 u16 *num_msdus);
1170
1171#endif