FILE
hal_rx.c
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linux-6.19.14/drivers/net/wireless/ath/ath12k/hal_rx.c
1// SPDX-License-Identifier: BSD-3-Clause-Clear 2/* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 5 */ 6 7#include "debug.h" 8#include "hal.h" 9#include "hal_tx.h" 10#include "hal_rx.h" 11#include "hal_desc.h" 12#include "hif.h" 13 14static void ath12k_hal_reo_set_desc_hdr(struct hal_desc_header *hdr, 15 u8 owner, u8 buffer_type, u32 magic) 16{ 17 hdr->info0 = le32_encode_bits(owner, HAL_DESC_HDR_INFO0_OWNER) | 18 le32_encode_bits(buffer_type, HAL_DESC_HDR_INFO0_BUF_TYPE); 19 20 /* Magic pattern in reserved bits for debugging */ 21 hdr->info0 |= le32_encode_bits(magic, HAL_DESC_HDR_INFO0_DBG_RESERVED); 22} 23 24static int ath12k_hal_reo_cmd_queue_stats(struct hal_tlv_64_hdr *tlv, 25 struct ath12k_hal_reo_cmd *cmd) 26{ 27 struct hal_reo_get_queue_stats *desc; 28 29 tlv->tl = le64_encode_bits(HAL_REO_GET_QUEUE_STATS, HAL_TLV_HDR_TAG) | 30 le64_encode_bits(sizeof(*desc), HAL_TLV_HDR_LEN); 31 32 desc = (struct hal_reo_get_queue_stats *)tlv->value; 33 memset_startat(desc, 0, queue_addr_lo); 34 35 desc->cmd.info0 &= ~cpu_to_le32(HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED); 36 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS) 37 desc->cmd.info0 |= cpu_to_le32(HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED); 38 39 desc->queue_addr_lo = cpu_to_le32(cmd->addr_lo); 40 desc->info0 = le32_encode_bits(cmd->addr_hi, 41 HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI); 42 if (cmd->flag & HAL_REO_CMD_FLG_STATS_CLEAR) 43 desc->info0 |= cpu_to_le32(HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS); 44 45 return le32_get_bits(desc->cmd.info0, HAL_REO_CMD_HDR_INFO0_CMD_NUMBER); 46} 47 48static int ath12k_hal_reo_cmd_flush_cache(struct ath12k_hal *hal, 49 struct hal_tlv_64_hdr *tlv, 50 struct ath12k_hal_reo_cmd *cmd) 51{ 52 struct hal_reo_flush_cache *desc; 53 u8 avail_slot = ffz(hal->avail_blk_resource); 54 55 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER) { 56 if (avail_slot >= HAL_MAX_AVAIL_BLK_RES) 57 return -ENOSPC; 58 59 hal->current_blk_index = avail_slot; 60 } 61 62 tlv->tl = le64_encode_bits(HAL_REO_FLUSH_CACHE, HAL_TLV_HDR_TAG) | 63 le64_encode_bits(sizeof(*desc), HAL_TLV_HDR_LEN); 64 65 desc = (struct hal_reo_flush_cache *)tlv->value; 66 memset_startat(desc, 0, cache_addr_lo); 67 68 desc->cmd.info0 &= ~cpu_to_le32(HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED); 69 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS) 70 desc->cmd.info0 |= cpu_to_le32(HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED); 71 72 desc->cache_addr_lo = cpu_to_le32(cmd->addr_lo); 73 desc->info0 = le32_encode_bits(cmd->addr_hi, 74 HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI); 75 76 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_FWD_ALL_MPDUS) 77 desc->info0 |= cpu_to_le32(HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS); 78 79 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_BLOCK_LATER) { 80 desc->info0 |= cpu_to_le32(HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE); 81 desc->info0 |= 82 le32_encode_bits(avail_slot, 83 HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX); 84 } 85 86 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_NO_INVAL) 87 desc->info0 |= cpu_to_le32(HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE); 88 89 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_ALL) 90 desc->info0 |= cpu_to_le32(HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL); 91 92 if (cmd->flag & HAL_REO_CMD_FLG_FLUSH_QUEUE_1K_DESC) 93 desc->info0 |= cpu_to_le32(HAL_REO_FLUSH_CACHE_INFO0_FLUSH_QUEUE_1K_DESC); 94 95 return le32_get_bits(desc->cmd.info0, HAL_REO_CMD_HDR_INFO0_CMD_NUMBER); 96} 97 98static int ath12k_hal_reo_cmd_update_rx_queue(struct hal_tlv_64_hdr *tlv, 99 struct ath12k_hal_reo_cmd *cmd) 100{ 101 struct hal_reo_update_rx_queue *desc; 102 103 tlv->tl = le64_encode_bits(HAL_REO_UPDATE_RX_REO_QUEUE, HAL_TLV_HDR_TAG) | 104 le64_encode_bits(sizeof(*desc), HAL_TLV_HDR_LEN); 105 106 desc = (struct hal_reo_update_rx_queue *)tlv->value; 107 memset_startat(desc, 0, queue_addr_lo); 108 109 desc->cmd.info0 &= ~cpu_to_le32(HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED); 110 if (cmd->flag & HAL_REO_CMD_FLG_NEED_STATUS) 111 desc->cmd.info0 |= cpu_to_le32(HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED); 112 113 desc->queue_addr_lo = cpu_to_le32(cmd->addr_lo); 114 desc->info0 = 115 le32_encode_bits(cmd->addr_hi, 116 HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI) | 117 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_RX_QUEUE_NUM), 118 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM) | 119 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_VLD), 120 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD) | 121 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_ALDC), 122 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT) | 123 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_DIS_DUP_DETECTION), 124 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION) | 125 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_SOFT_REORDER_EN), 126 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN) | 127 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_AC), 128 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC) | 129 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_BAR), 130 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR) | 131 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_RETRY), 132 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY) | 133 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_CHECK_2K_MODE), 134 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE) | 135 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_OOR_MODE), 136 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE) | 137 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_BA_WINDOW_SIZE), 138 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE) | 139 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_CHECK), 140 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK) | 141 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_EVEN_PN), 142 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN) | 143 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_UNEVEN_PN), 144 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN) | 145 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_HANDLE_ENABLE), 146 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE) | 147 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_SIZE), 148 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE) | 149 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_IGNORE_AMPDU_FLG), 150 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG) | 151 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_SVLD), 152 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD) | 153 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_SSN), 154 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN) | 155 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_SEQ_2K_ERR), 156 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR) | 157 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_PN_VALID), 158 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID) | 159 le32_encode_bits(!!(cmd->upd0 & HAL_REO_CMD_UPD0_PN), 160 HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN); 161 162 desc->info1 = 163 le32_encode_bits(cmd->rx_queue_num, 164 HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER) | 165 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_VLD), 166 HAL_REO_UPD_RX_QUEUE_INFO1_VLD) | 167 le32_encode_bits(u32_get_bits(cmd->upd1, HAL_REO_CMD_UPD1_ALDC), 168 HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER) | 169 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_DIS_DUP_DETECTION), 170 HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION) | 171 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_SOFT_REORDER_EN), 172 HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN) | 173 le32_encode_bits(u32_get_bits(cmd->upd1, HAL_REO_CMD_UPD1_AC), 174 HAL_REO_UPD_RX_QUEUE_INFO1_AC) | 175 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_BAR), 176 HAL_REO_UPD_RX_QUEUE_INFO1_BAR) | 177 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_CHECK_2K_MODE), 178 HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE) | 179 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_RETRY), 180 HAL_REO_UPD_RX_QUEUE_INFO1_RETRY) | 181 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_OOR_MODE), 182 HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE) | 183 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_PN_CHECK), 184 HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK) | 185 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_EVEN_PN), 186 HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN) | 187 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_UNEVEN_PN), 188 HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN) | 189 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_PN_HANDLE_ENABLE), 190 HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE) | 191 le32_encode_bits(!!(cmd->upd1 & HAL_REO_CMD_UPD1_IGNORE_AMPDU_FLG), 192 HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG); 193 194 if (cmd->pn_size == 24) 195 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_24; 196 else if (cmd->pn_size == 48) 197 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_48; 198 else if (cmd->pn_size == 128) 199 cmd->pn_size = HAL_RX_REO_QUEUE_PN_SIZE_128; 200 201 if (cmd->ba_window_size < 1) 202 cmd->ba_window_size = 1; 203 204 if (cmd->ba_window_size == 1) 205 cmd->ba_window_size++; 206 207 desc->info2 = 208 le32_encode_bits(cmd->ba_window_size - 1, 209 HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE) | 210 le32_encode_bits(cmd->pn_size, HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE) | 211 le32_encode_bits(!!(cmd->upd2 & HAL_REO_CMD_UPD2_SVLD), 212 HAL_REO_UPD_RX_QUEUE_INFO2_SVLD) | 213 le32_encode_bits(u32_get_bits(cmd->upd2, HAL_REO_CMD_UPD2_SSN), 214 HAL_REO_UPD_RX_QUEUE_INFO2_SSN) | 215 le32_encode_bits(!!(cmd->upd2 & HAL_REO_CMD_UPD2_SEQ_2K_ERR), 216 HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR) | 217 le32_encode_bits(!!(cmd->upd2 & HAL_REO_CMD_UPD2_PN_ERR), 218 HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR); 219 220 return le32_get_bits(desc->cmd.info0, HAL_REO_CMD_HDR_INFO0_CMD_NUMBER); 221} 222 223int ath12k_hal_reo_cmd_send(struct ath12k_base *ab, struct hal_srng *srng, 224 enum hal_reo_cmd_type type, 225 struct ath12k_hal_reo_cmd *cmd) 226{ 227 struct hal_tlv_64_hdr *reo_desc; 228 int ret; 229 230 spin_lock_bh(&srng->lock); 231 232 ath12k_hal_srng_access_begin(ab, srng); 233 reo_desc = ath12k_hal_srng_src_get_next_entry(ab, srng); 234 if (!reo_desc) { 235 ret = -ENOBUFS; 236 goto out; 237 } 238 239 switch (type) { 240 case HAL_REO_CMD_GET_QUEUE_STATS: 241 ret = ath12k_hal_reo_cmd_queue_stats(reo_desc, cmd); 242 break; 243 case HAL_REO_CMD_FLUSH_CACHE: 244 ret = ath12k_hal_reo_cmd_flush_cache(&ab->hal, reo_desc, cmd); 245 break; 246 case HAL_REO_CMD_UPDATE_RX_QUEUE: 247 ret = ath12k_hal_reo_cmd_update_rx_queue(reo_desc, cmd); 248 break; 249 case HAL_REO_CMD_FLUSH_QUEUE: 250 case HAL_REO_CMD_UNBLOCK_CACHE: 251 case HAL_REO_CMD_FLUSH_TIMEOUT_LIST: 252 ath12k_warn(ab, "Unsupported reo command %d\n", type); 253 ret = -EOPNOTSUPP; 254 break; 255 default: 256 ath12k_warn(ab, "Unknown reo command %d\n", type); 257 ret = -EINVAL; 258 break; 259 } 260 261out: 262 ath12k_hal_srng_access_end(ab, srng); 263 spin_unlock_bh(&srng->lock); 264 265 return ret; 266} 267 268void ath12k_hal_rx_buf_addr_info_set(struct ath12k_buffer_addr *binfo, 269 dma_addr_t paddr, u32 cookie, u8 manager) 270{ 271 u32 paddr_lo, paddr_hi; 272 273 paddr_lo = lower_32_bits(paddr); 274 paddr_hi = upper_32_bits(paddr); 275 binfo->info0 = le32_encode_bits(paddr_lo, BUFFER_ADDR_INFO0_ADDR); 276 binfo->info1 = le32_encode_bits(paddr_hi, BUFFER_ADDR_INFO1_ADDR) | 277 le32_encode_bits(cookie, BUFFER_ADDR_INFO1_SW_COOKIE) | 278 le32_encode_bits(manager, BUFFER_ADDR_INFO1_RET_BUF_MGR); 279} 280 281void ath12k_hal_rx_buf_addr_info_get(struct ath12k_buffer_addr *binfo, 282 dma_addr_t *paddr, 283 u32 *cookie, u8 *rbm) 284{ 285 *paddr = (((u64)le32_get_bits(binfo->info1, BUFFER_ADDR_INFO1_ADDR)) << 32) | 286 le32_get_bits(binfo->info0, BUFFER_ADDR_INFO0_ADDR); 287 *cookie = le32_get_bits(binfo->info1, BUFFER_ADDR_INFO1_SW_COOKIE); 288 *rbm = le32_get_bits(binfo->info1, BUFFER_ADDR_INFO1_RET_BUF_MGR); 289} 290 291void ath12k_hal_rx_msdu_link_info_get(struct hal_rx_msdu_link *link, u32 *num_msdus, 292 u32 *msdu_cookies, 293 enum hal_rx_buf_return_buf_manager *rbm) 294{ 295 struct hal_rx_msdu_details *msdu; 296 u32 val; 297 int i; 298 299 *num_msdus = HAL_NUM_RX_MSDUS_PER_LINK_DESC; 300 301 msdu = &link->msdu_link[0]; 302 *rbm = le32_get_bits(msdu->buf_addr_info.info1, 303 BUFFER_ADDR_INFO1_RET_BUF_MGR); 304 305 for (i = 0; i < *num_msdus; i++) { 306 msdu = &link->msdu_link[i]; 307 308 val = le32_get_bits(msdu->buf_addr_info.info0, 309 BUFFER_ADDR_INFO0_ADDR); 310 if (val == 0) { 311 *num_msdus = i; 312 break; 313 } 314 *msdu_cookies = le32_get_bits(msdu->buf_addr_info.info1, 315 BUFFER_ADDR_INFO1_SW_COOKIE); 316 msdu_cookies++; 317 } 318} 319 320int ath12k_hal_desc_reo_parse_err(struct ath12k_base *ab, 321 struct hal_reo_dest_ring *desc, 322 dma_addr_t *paddr, u32 *desc_bank) 323{ 324 enum hal_reo_dest_ring_push_reason push_reason; 325 enum hal_reo_dest_ring_error_code err_code; 326 u32 cookie; 327 328 push_reason = le32_get_bits(desc->info0, 329 HAL_REO_DEST_RING_INFO0_PUSH_REASON); 330 err_code = le32_get_bits(desc->info0, 331 HAL_REO_DEST_RING_INFO0_ERROR_CODE); 332 ab->device_stats.reo_error[err_code]++; 333 334 if (push_reason != HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED && 335 push_reason != HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION) { 336 ath12k_warn(ab, "expected error push reason code, received %d\n", 337 push_reason); 338 return -EINVAL; 339 } 340 341 ath12k_hal_rx_reo_ent_paddr_get(ab, &desc->buf_addr_info, paddr, &cookie); 342 *desc_bank = u32_get_bits(cookie, DP_LINK_DESC_BANK_MASK); 343 344 return 0; 345} 346 347int ath12k_hal_wbm_desc_parse_err(struct ath12k_base *ab, void *desc, 348 struct hal_rx_wbm_rel_info *rel_info) 349{ 350 struct hal_wbm_release_ring *wbm_desc = desc; 351 struct hal_wbm_release_ring_cc_rx *wbm_cc_desc = desc; 352 enum hal_wbm_rel_desc_type type; 353 enum hal_wbm_rel_src_module rel_src; 354 bool hw_cc_done; 355 u64 desc_va; 356 u32 val; 357 358 type = le32_get_bits(wbm_desc->info0, HAL_WBM_RELEASE_INFO0_DESC_TYPE); 359 /* We expect only WBM_REL buffer type */ 360 if (type != HAL_WBM_REL_DESC_TYPE_REL_MSDU) { 361 WARN_ON(1); 362 return -EINVAL; 363 } 364 365 rel_src = le32_get_bits(wbm_desc->info0, 366 HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE); 367 if (rel_src != HAL_WBM_REL_SRC_MODULE_RXDMA && 368 rel_src != HAL_WBM_REL_SRC_MODULE_REO) 369 return -EINVAL; 370 371 /* The format of wbm rel ring desc changes based on the 372 * hw cookie conversion status 373 */ 374 hw_cc_done = le32_get_bits(wbm_desc->info0, 375 HAL_WBM_RELEASE_RX_INFO0_CC_STATUS); 376 377 if (!hw_cc_done) { 378 val = le32_get_bits(wbm_desc->buf_addr_info.info1, 379 BUFFER_ADDR_INFO1_RET_BUF_MGR); 380 if (val != HAL_RX_BUF_RBM_SW3_BM) { 381 ab->device_stats.invalid_rbm++; 382 return -EINVAL; 383 } 384 385 rel_info->cookie = le32_get_bits(wbm_desc->buf_addr_info.info1, 386 BUFFER_ADDR_INFO1_SW_COOKIE); 387 388 rel_info->rx_desc = NULL; 389 } else { 390 val = le32_get_bits(wbm_cc_desc->info0, 391 HAL_WBM_RELEASE_RX_CC_INFO0_RBM); 392 if (val != HAL_RX_BUF_RBM_SW3_BM) { 393 ab->device_stats.invalid_rbm++; 394 return -EINVAL; 395 } 396 397 rel_info->cookie = le32_get_bits(wbm_cc_desc->info1, 398 HAL_WBM_RELEASE_RX_CC_INFO1_COOKIE); 399 400 desc_va = ((u64)le32_to_cpu(wbm_cc_desc->buf_va_hi) << 32 | 401 le32_to_cpu(wbm_cc_desc->buf_va_lo)); 402 rel_info->rx_desc = 403 (struct ath12k_rx_desc_info *)((unsigned long)desc_va); 404 } 405 406 rel_info->err_rel_src = rel_src; 407 rel_info->hw_cc_done = hw_cc_done; 408 409 rel_info->first_msdu = le32_get_bits(wbm_desc->info3, 410 HAL_WBM_RELEASE_INFO3_FIRST_MSDU); 411 rel_info->last_msdu = le32_get_bits(wbm_desc->info3, 412 HAL_WBM_RELEASE_INFO3_LAST_MSDU); 413 rel_info->continuation = le32_get_bits(wbm_desc->info3, 414 HAL_WBM_RELEASE_INFO3_CONTINUATION); 415 416 if (rel_info->err_rel_src == HAL_WBM_REL_SRC_MODULE_REO) { 417 rel_info->push_reason = 418 le32_get_bits(wbm_desc->info0, 419 HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON); 420 rel_info->err_code = 421 le32_get_bits(wbm_desc->info0, 422 HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE); 423 } else { 424 rel_info->push_reason = 425 le32_get_bits(wbm_desc->info0, 426 HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON); 427 rel_info->err_code = 428 le32_get_bits(wbm_desc->info0, 429 HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE); 430 } 431 432 return 0; 433} 434 435void ath12k_hal_rx_reo_ent_paddr_get(struct ath12k_base *ab, 436 struct ath12k_buffer_addr *buff_addr, 437 dma_addr_t *paddr, u32 *cookie) 438{ 439 *paddr = ((u64)(le32_get_bits(buff_addr->info1, 440 BUFFER_ADDR_INFO1_ADDR)) << 32) | 441 le32_get_bits(buff_addr->info0, BUFFER_ADDR_INFO0_ADDR); 442 443 *cookie = le32_get_bits(buff_addr->info1, BUFFER_ADDR_INFO1_SW_COOKIE); 444} 445 446void ath12k_hal_rx_reo_ent_buf_paddr_get(void *rx_desc, dma_addr_t *paddr, 447 u32 *sw_cookie, 448 struct ath12k_buffer_addr **pp_buf_addr, 449 u8 *rbm, u32 *msdu_cnt) 450{ 451 struct hal_reo_entrance_ring *reo_ent_ring = 452 (struct hal_reo_entrance_ring *)rx_desc; 453 struct ath12k_buffer_addr *buf_addr_info; 454 struct rx_mpdu_desc *rx_mpdu_desc_info_details; 455 456 rx_mpdu_desc_info_details = 457 (struct rx_mpdu_desc *)&reo_ent_ring->rx_mpdu_info; 458 459 *msdu_cnt = le32_get_bits(rx_mpdu_desc_info_details->info0, 460 RX_MPDU_DESC_INFO0_MSDU_COUNT); 461 462 buf_addr_info = (struct ath12k_buffer_addr *)&reo_ent_ring->buf_addr_info; 463 464 *paddr = (((u64)le32_get_bits(buf_addr_info->info1, 465 BUFFER_ADDR_INFO1_ADDR)) << 32) | 466 le32_get_bits(buf_addr_info->info0, 467 BUFFER_ADDR_INFO0_ADDR); 468 469 *sw_cookie = le32_get_bits(buf_addr_info->info1, 470 BUFFER_ADDR_INFO1_SW_COOKIE); 471 *rbm = le32_get_bits(buf_addr_info->info1, 472 BUFFER_ADDR_INFO1_RET_BUF_MGR); 473 474 *pp_buf_addr = (void *)buf_addr_info; 475} 476 477void ath12k_hal_rx_msdu_list_get(struct ath12k *ar, 478 struct hal_rx_msdu_link *link_desc, 479 struct hal_rx_msdu_list *msdu_list, 480 u16 *num_msdus) 481{ 482 struct hal_rx_msdu_details *msdu_details = NULL; 483 struct rx_msdu_desc *msdu_desc_info = NULL; 484 u32 last = 0, first = 0; 485 u8 tmp = 0; 486 int i; 487 488 last = u32_encode_bits(last, RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU); 489 first = u32_encode_bits(first, RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU); 490 msdu_details = &link_desc->msdu_link[0]; 491 492 for (i = 0; i < HAL_RX_NUM_MSDU_DESC; i++) { 493 if (!i && le32_get_bits(msdu_details[i].buf_addr_info.info0, 494 BUFFER_ADDR_INFO0_ADDR) == 0) 495 break; 496 if (le32_get_bits(msdu_details[i].buf_addr_info.info0, 497 BUFFER_ADDR_INFO0_ADDR) == 0) { 498 msdu_desc_info = &msdu_details[i - 1].rx_msdu_info; 499 msdu_desc_info->info0 |= cpu_to_le32(last); 500 break; 501 } 502 msdu_desc_info = &msdu_details[i].rx_msdu_info; 503 504 if (!i) 505 msdu_desc_info->info0 |= cpu_to_le32(first); 506 else if (i == (HAL_RX_NUM_MSDU_DESC - 1)) 507 msdu_desc_info->info0 |= cpu_to_le32(last); 508 msdu_list->msdu_info[i].msdu_flags = le32_to_cpu(msdu_desc_info->info0); 509 msdu_list->msdu_info[i].msdu_len = 510 HAL_RX_MSDU_PKT_LENGTH_GET(msdu_desc_info->info0); 511 msdu_list->sw_cookie[i] = 512 le32_get_bits(msdu_details[i].buf_addr_info.info1, 513 BUFFER_ADDR_INFO1_SW_COOKIE); 514 tmp = le32_get_bits(msdu_details[i].buf_addr_info.info1, 515 BUFFER_ADDR_INFO1_RET_BUF_MGR); 516 msdu_list->paddr[i] = 517 ((u64)(le32_get_bits(msdu_details[i].buf_addr_info.info1, 518 BUFFER_ADDR_INFO1_ADDR)) << 32) | 519 le32_get_bits(msdu_details[i].buf_addr_info.info0, 520 BUFFER_ADDR_INFO0_ADDR); 521 msdu_list->rbm[i] = tmp; 522 } 523 *num_msdus = i; 524} 525 526void ath12k_hal_rx_msdu_link_desc_set(struct ath12k_base *ab, 527 struct hal_wbm_release_ring *desc, 528 struct ath12k_buffer_addr *buf_addr_info, 529 enum hal_wbm_rel_bm_act action) 530{ 531 desc->buf_addr_info = *buf_addr_info; 532 desc->info0 |= le32_encode_bits(HAL_WBM_REL_SRC_MODULE_SW, 533 HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE) | 534 le32_encode_bits(action, HAL_WBM_RELEASE_INFO0_BM_ACTION) | 535 le32_encode_bits(HAL_WBM_REL_DESC_TYPE_MSDU_LINK, 536 HAL_WBM_RELEASE_INFO0_DESC_TYPE); 537} 538 539void ath12k_hal_reo_status_queue_stats(struct ath12k_base *ab, struct hal_tlv_64_hdr *tlv, 540 struct hal_reo_status *status) 541{ 542 struct hal_reo_get_queue_stats_status *desc = 543 (struct hal_reo_get_queue_stats_status *)tlv->value; 544 545 status->uniform_hdr.cmd_num = 546 le32_get_bits(desc->hdr.info0, 547 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM); 548 status->uniform_hdr.cmd_status = 549 le32_get_bits(desc->hdr.info0, 550 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS); 551 552 ath12k_dbg(ab, ATH12K_DBG_HAL, "Queue stats status:\n"); 553 ath12k_dbg(ab, ATH12K_DBG_HAL, "header: cmd_num %d status %d\n", 554 status->uniform_hdr.cmd_num, 555 status->uniform_hdr.cmd_status); 556 ath12k_dbg(ab, ATH12K_DBG_HAL, "ssn %u cur_idx %u\n", 557 le32_get_bits(desc->info0, 558 HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN), 559 le32_get_bits(desc->info0, 560 HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX)); 561 ath12k_dbg(ab, ATH12K_DBG_HAL, "pn = [%08x, %08x, %08x, %08x]\n", 562 desc->pn[0], desc->pn[1], desc->pn[2], desc->pn[3]); 563 ath12k_dbg(ab, ATH12K_DBG_HAL, "last_rx: enqueue_tstamp %08x dequeue_tstamp %08x\n", 564 desc->last_rx_enqueue_timestamp, 565 desc->last_rx_dequeue_timestamp); 566 ath12k_dbg(ab, ATH12K_DBG_HAL, "rx_bitmap [%08x %08x %08x %08x %08x %08x %08x %08x]\n", 567 desc->rx_bitmap[0], desc->rx_bitmap[1], desc->rx_bitmap[2], 568 desc->rx_bitmap[3], desc->rx_bitmap[4], desc->rx_bitmap[5], 569 desc->rx_bitmap[6], desc->rx_bitmap[7]); 570 ath12k_dbg(ab, ATH12K_DBG_HAL, "count: cur_mpdu %u cur_msdu %u\n", 571 le32_get_bits(desc->info1, 572 HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT), 573 le32_get_bits(desc->info1, 574 HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT)); 575 ath12k_dbg(ab, ATH12K_DBG_HAL, "fwd_timeout %u fwd_bar %u dup_count %u\n", 576 le32_get_bits(desc->info2, 577 HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT), 578 le32_get_bits(desc->info2, 579 HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT), 580 le32_get_bits(desc->info2, 581 HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT)); 582 ath12k_dbg(ab, ATH12K_DBG_HAL, "frames_in_order %u bar_rcvd %u\n", 583 le32_get_bits(desc->info3, 584 HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT), 585 le32_get_bits(desc->info3, 586 HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT)); 587 ath12k_dbg(ab, ATH12K_DBG_HAL, "num_mpdus %d num_msdus %d total_bytes %d\n", 588 desc->num_mpdu_frames, desc->num_msdu_frames, 589 desc->total_bytes); 590 ath12k_dbg(ab, ATH12K_DBG_HAL, "late_rcvd %u win_jump_2k %u hole_cnt %u\n", 591 le32_get_bits(desc->info4, 592 HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU), 593 le32_get_bits(desc->info2, 594 HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_WINDOW_JMP2K), 595 le32_get_bits(desc->info4, 596 HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT)); 597 ath12k_dbg(ab, ATH12K_DBG_HAL, "looping count %u\n", 598 le32_get_bits(desc->info5, 599 HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT)); 600} 601 602void ath12k_hal_reo_flush_queue_status(struct ath12k_base *ab, struct hal_tlv_64_hdr *tlv, 603 struct hal_reo_status *status) 604{ 605 struct hal_reo_flush_queue_status *desc = 606 (struct hal_reo_flush_queue_status *)tlv->value; 607 608 status->uniform_hdr.cmd_num = 609 le32_get_bits(desc->hdr.info0, 610 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM); 611 status->uniform_hdr.cmd_status = 612 le32_get_bits(desc->hdr.info0, 613 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS); 614 status->u.flush_queue.err_detected = 615 le32_get_bits(desc->info0, 616 HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED); 617} 618 619void ath12k_hal_reo_flush_cache_status(struct ath12k_base *ab, struct hal_tlv_64_hdr *tlv, 620 struct hal_reo_status *status) 621{ 622 struct ath12k_hal *hal = &ab->hal; 623 struct hal_reo_flush_cache_status *desc = 624 (struct hal_reo_flush_cache_status *)tlv->value; 625 626 status->uniform_hdr.cmd_num = 627 le32_get_bits(desc->hdr.info0, 628 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM); 629 status->uniform_hdr.cmd_status = 630 le32_get_bits(desc->hdr.info0, 631 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS); 632 633 status->u.flush_cache.err_detected = 634 le32_get_bits(desc->info0, 635 HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR); 636 status->u.flush_cache.err_code = 637 le32_get_bits(desc->info0, 638 HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE); 639 if (!status->u.flush_cache.err_code) 640 hal->avail_blk_resource |= BIT(hal->current_blk_index); 641 642 status->u.flush_cache.cache_controller_flush_status_hit = 643 le32_get_bits(desc->info0, 644 HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT); 645 646 status->u.flush_cache.cache_controller_flush_status_desc_type = 647 le32_get_bits(desc->info0, 648 HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE); 649 status->u.flush_cache.cache_controller_flush_status_client_id = 650 le32_get_bits(desc->info0, 651 HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID); 652 status->u.flush_cache.cache_controller_flush_status_err = 653 le32_get_bits(desc->info0, 654 HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR); 655 status->u.flush_cache.cache_controller_flush_status_cnt = 656 le32_get_bits(desc->info0, 657 HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT); 658} 659 660void ath12k_hal_reo_unblk_cache_status(struct ath12k_base *ab, struct hal_tlv_64_hdr *tlv, 661 struct hal_reo_status *status) 662{ 663 struct ath12k_hal *hal = &ab->hal; 664 struct hal_reo_unblock_cache_status *desc = 665 (struct hal_reo_unblock_cache_status *)tlv->value; 666 667 status->uniform_hdr.cmd_num = 668 le32_get_bits(desc->hdr.info0, 669 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM); 670 status->uniform_hdr.cmd_status = 671 le32_get_bits(desc->hdr.info0, 672 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS); 673 674 status->u.unblock_cache.err_detected = 675 le32_get_bits(desc->info0, 676 HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR); 677 status->u.unblock_cache.unblock_type = 678 le32_get_bits(desc->info0, 679 HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE); 680 681 if (!status->u.unblock_cache.err_detected && 682 status->u.unblock_cache.unblock_type == 683 HAL_REO_STATUS_UNBLOCK_BLOCKING_RESOURCE) 684 hal->avail_blk_resource &= ~BIT(hal->current_blk_index); 685} 686 687void ath12k_hal_reo_flush_timeout_list_status(struct ath12k_base *ab, 688 struct hal_tlv_64_hdr *tlv, 689 struct hal_reo_status *status) 690{ 691 struct hal_reo_flush_timeout_list_status *desc = 692 (struct hal_reo_flush_timeout_list_status *)tlv->value; 693 694 status->uniform_hdr.cmd_num = 695 le32_get_bits(desc->hdr.info0, 696 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM); 697 status->uniform_hdr.cmd_status = 698 le32_get_bits(desc->hdr.info0, 699 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS); 700 701 status->u.timeout_list.err_detected = 702 le32_get_bits(desc->info0, 703 HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR); 704 status->u.timeout_list.list_empty = 705 le32_get_bits(desc->info0, 706 HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY); 707 708 status->u.timeout_list.release_desc_cnt = 709 le32_get_bits(desc->info1, 710 HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT); 711 status->u.timeout_list.fwd_buf_cnt = 712 le32_get_bits(desc->info0, 713 HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT); 714} 715 716void ath12k_hal_reo_desc_thresh_reached_status(struct ath12k_base *ab, 717 struct hal_tlv_64_hdr *tlv, 718 struct hal_reo_status *status) 719{ 720 struct hal_reo_desc_thresh_reached_status *desc = 721 (struct hal_reo_desc_thresh_reached_status *)tlv->value; 722 723 status->uniform_hdr.cmd_num = 724 le32_get_bits(desc->hdr.info0, 725 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM); 726 status->uniform_hdr.cmd_status = 727 le32_get_bits(desc->hdr.info0, 728 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS); 729 730 status->u.desc_thresh_reached.threshold_idx = 731 le32_get_bits(desc->info0, 732 HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX); 733 734 status->u.desc_thresh_reached.link_desc_counter0 = 735 le32_get_bits(desc->info1, 736 HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0); 737 738 status->u.desc_thresh_reached.link_desc_counter1 = 739 le32_get_bits(desc->info2, 740 HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1); 741 742 status->u.desc_thresh_reached.link_desc_counter2 = 743 le32_get_bits(desc->info3, 744 HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2); 745 746 status->u.desc_thresh_reached.link_desc_counter_sum = 747 le32_get_bits(desc->info4, 748 HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM); 749} 750 751void ath12k_hal_reo_update_rx_reo_queue_status(struct ath12k_base *ab, 752 struct hal_tlv_64_hdr *tlv, 753 struct hal_reo_status *status) 754{ 755 struct hal_reo_status_hdr *desc = 756 (struct hal_reo_status_hdr *)tlv->value; 757 758 status->uniform_hdr.cmd_num = 759 le32_get_bits(desc->info0, 760 HAL_REO_STATUS_HDR_INFO0_STATUS_NUM); 761 status->uniform_hdr.cmd_status = 762 le32_get_bits(desc->info0, 763 HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS); 764} 765 766u32 ath12k_hal_reo_qdesc_size(u32 ba_window_size, u8 tid) 767{ 768 u32 num_ext_desc, num_1k_desc = 0; 769 770 if (ba_window_size <= 1) { 771 if (tid != HAL_DESC_REO_NON_QOS_TID) 772 num_ext_desc = 1; 773 else 774 num_ext_desc = 0; 775 776 } else if (ba_window_size <= 105) { 777 num_ext_desc = 1; 778 } else if (ba_window_size <= 210) { 779 num_ext_desc = 2; 780 } else if (ba_window_size <= 256) { 781 num_ext_desc = 3; 782 } else { 783 num_ext_desc = 10; 784 num_1k_desc = 1; 785 } 786 787 return sizeof(struct hal_rx_reo_queue) + 788 (num_ext_desc * sizeof(struct hal_rx_reo_queue_ext)) + 789 (num_1k_desc * sizeof(struct hal_rx_reo_queue_1k)); 790} 791 792void ath12k_hal_reo_qdesc_setup(struct hal_rx_reo_queue *qdesc, 793 int tid, u32 ba_window_size, 794 u32 start_seq, enum hal_pn_type type) 795{ 796 struct hal_rx_reo_queue_ext *ext_desc; 797 798 ath12k_hal_reo_set_desc_hdr(&qdesc->desc_hdr, HAL_DESC_REO_OWNED, 799 HAL_DESC_REO_QUEUE_DESC, 800 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_0); 801 802 qdesc->rx_queue_num = le32_encode_bits(tid, HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER); 803 804 qdesc->info0 = 805 le32_encode_bits(1, HAL_RX_REO_QUEUE_INFO0_VLD) | 806 le32_encode_bits(1, HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER) | 807 le32_encode_bits(ath12k_tid_to_ac(tid), HAL_RX_REO_QUEUE_INFO0_AC); 808 809 if (ba_window_size < 1) 810 ba_window_size = 1; 811 812 if (ba_window_size == 1 && tid != HAL_DESC_REO_NON_QOS_TID) 813 ba_window_size++; 814 815 if (ba_window_size == 1) 816 qdesc->info0 |= le32_encode_bits(1, HAL_RX_REO_QUEUE_INFO0_RETRY); 817 818 qdesc->info0 |= le32_encode_bits(ba_window_size - 1, 819 HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE); 820 switch (type) { 821 case HAL_PN_TYPE_NONE: 822 case HAL_PN_TYPE_WAPI_EVEN: 823 case HAL_PN_TYPE_WAPI_UNEVEN: 824 break; 825 case HAL_PN_TYPE_WPA: 826 qdesc->info0 |= 827 le32_encode_bits(1, HAL_RX_REO_QUEUE_INFO0_PN_CHECK) | 828 le32_encode_bits(HAL_RX_REO_QUEUE_PN_SIZE_48, 829 HAL_RX_REO_QUEUE_INFO0_PN_SIZE); 830 break; 831 } 832 833 /* TODO: Set Ignore ampdu flags based on BA window size and/or 834 * AMPDU capabilities 835 */ 836 qdesc->info0 |= le32_encode_bits(1, HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG); 837 838 qdesc->info1 |= le32_encode_bits(0, HAL_RX_REO_QUEUE_INFO1_SVLD); 839 840 if (start_seq <= 0xfff) 841 qdesc->info1 = le32_encode_bits(start_seq, 842 HAL_RX_REO_QUEUE_INFO1_SSN); 843 844 if (tid == HAL_DESC_REO_NON_QOS_TID) 845 return; 846 847 ext_desc = qdesc->ext_desc; 848 849 /* TODO: HW queue descriptors are currently allocated for max BA 850 * window size for all QOS TIDs so that same descriptor can be used 851 * later when ADDBA request is received. This should be changed to 852 * allocate HW queue descriptors based on BA window size being 853 * negotiated (0 for non BA cases), and reallocate when BA window 854 * size changes and also send WMI message to FW to change the REO 855 * queue descriptor in Rx peer entry as part of dp_rx_tid_update. 856 */ 857 memset(ext_desc, 0, 3 * sizeof(*ext_desc)); 858 ath12k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED, 859 HAL_DESC_REO_QUEUE_EXT_DESC, 860 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_1); 861 ext_desc++; 862 ath12k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED, 863 HAL_DESC_REO_QUEUE_EXT_DESC, 864 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_2); 865 ext_desc++; 866 ath12k_hal_reo_set_desc_hdr(&ext_desc->desc_hdr, HAL_DESC_REO_OWNED, 867 HAL_DESC_REO_QUEUE_EXT_DESC, 868 REO_QUEUE_DESC_MAGIC_DEBUG_PATTERN_3); 869} 870 871void ath12k_hal_reo_init_cmd_ring(struct ath12k_base *ab, 872 struct hal_srng *srng) 873{ 874 struct hal_srng_params params; 875 struct hal_tlv_64_hdr *tlv; 876 struct hal_reo_get_queue_stats *desc; 877 int i, cmd_num = 1; 878 int entry_size; 879 u8 *entry; 880 881 memset(¶ms, 0, sizeof(params)); 882 883 entry_size = ath12k_hal_srng_get_entrysize(ab, HAL_REO_CMD); 884 ath12k_hal_srng_get_params(ab, srng, ¶ms); 885 entry = (u8 *)params.ring_base_vaddr; 886 887 for (i = 0; i < params.num_entries; i++) { 888 tlv = (struct hal_tlv_64_hdr *)entry; 889 desc = (struct hal_reo_get_queue_stats *)tlv->value; 890 desc->cmd.info0 = le32_encode_bits(cmd_num++, 891 HAL_REO_CMD_HDR_INFO0_CMD_NUMBER); 892 entry += entry_size; 893 } 894} 895 896void ath12k_hal_reo_hw_setup(struct ath12k_base *ab, u32 ring_hash_map) 897{ 898 u32 reo_base = HAL_SEQ_WCSS_UMAC_REO_REG; 899 u32 val; 900 901 val = ath12k_hif_read32(ab, reo_base + HAL_REO1_GEN_ENABLE); 902 903 val |= u32_encode_bits(1, HAL_REO1_GEN_ENABLE_AGING_LIST_ENABLE) | 904 u32_encode_bits(1, HAL_REO1_GEN_ENABLE_AGING_FLUSH_ENABLE); 905 ath12k_hif_write32(ab, reo_base + HAL_REO1_GEN_ENABLE, val); 906 907 val = ath12k_hif_read32(ab, reo_base + HAL_REO1_MISC_CTRL_ADDR(ab)); 908 909 val &= ~(HAL_REO1_MISC_CTL_FRAG_DST_RING | 910 HAL_REO1_MISC_CTL_BAR_DST_RING); 911 val |= u32_encode_bits(HAL_SRNG_RING_ID_REO2SW0, 912 HAL_REO1_MISC_CTL_FRAG_DST_RING); 913 val |= u32_encode_bits(HAL_SRNG_RING_ID_REO2SW0, 914 HAL_REO1_MISC_CTL_BAR_DST_RING); 915 ath12k_hif_write32(ab, reo_base + HAL_REO1_MISC_CTRL_ADDR(ab), val); 916 917 ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_0(ab), 918 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_USEC); 919 ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_1(ab), 920 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_USEC); 921 ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_2(ab), 922 HAL_DEFAULT_BE_BK_VI_REO_TIMEOUT_USEC); 923 ath12k_hif_write32(ab, reo_base + HAL_REO1_AGING_THRESH_IX_3(ab), 924 HAL_DEFAULT_VO_REO_TIMEOUT_USEC); 925 926 ath12k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_2, 927 ring_hash_map); 928 ath12k_hif_write32(ab, reo_base + HAL_REO1_DEST_RING_CTRL_IX_3, 929 ring_hash_map); 930} 931 932void ath12k_hal_reo_shared_qaddr_cache_clear(struct ath12k_base *ab) 933{ 934 u32 val; 935 936 lockdep_assert_held(&ab->base_lock); 937 val = ath12k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + 938 HAL_REO1_QDESC_ADDR(ab)); 939 940 val |= u32_encode_bits(1, HAL_REO_QDESC_ADDR_READ_CLEAR_QDESC_ARRAY); 941 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + 942 HAL_REO1_QDESC_ADDR(ab), val); 943 944 val &= ~HAL_REO_QDESC_ADDR_READ_CLEAR_QDESC_ARRAY; 945 ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_REO_REG + 946 HAL_REO1_QDESC_ADDR(ab), val); 947}
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