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hal_desc.h
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linux-6.19.14/drivers/net/wireless/ath/ath12k/hal_desc.h
1/* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2/* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2022, 2024-2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6#include "core.h" 7 8#ifndef ATH12K_HAL_DESC_H 9#define ATH12K_HAL_DESC_H 10 11#define BUFFER_ADDR_INFO0_ADDR GENMASK(31, 0) 12 13#define BUFFER_ADDR_INFO1_ADDR GENMASK(7, 0) 14#define BUFFER_ADDR_INFO1_RET_BUF_MGR GENMASK(11, 8) 15#define BUFFER_ADDR_INFO1_SW_COOKIE GENMASK(31, 12) 16 17struct ath12k_buffer_addr { 18 __le32 info0; 19 __le32 info1; 20} __packed; 21 22/* ath12k_buffer_addr 23 * 24 * buffer_addr_31_0 25 * Address (lower 32 bits) of the MSDU buffer or MSDU_EXTENSION 26 * descriptor or Link descriptor 27 * 28 * buffer_addr_39_32 29 * Address (upper 8 bits) of the MSDU buffer or MSDU_EXTENSION 30 * descriptor or Link descriptor 31 * 32 * return_buffer_manager (RBM) 33 * Consumer: WBM 34 * Producer: SW/FW 35 * Indicates to which buffer manager the buffer or MSDU_EXTENSION 36 * descriptor or link descriptor that is being pointed to shall be 37 * returned after the frame has been processed. It is used by WBM 38 * for routing purposes. 39 * 40 * Values are defined in enum %HAL_RX_BUF_RBM_ 41 * 42 * sw_buffer_cookie 43 * Cookie field exclusively used by SW. HW ignores the contents, 44 * accept that it passes the programmed value on to other 45 * descriptors together with the physical address. 46 * 47 * Field can be used by SW to for example associate the buffers 48 * physical address with the virtual address. 49 * 50 * NOTE1: 51 * The three most significant bits can have a special meaning 52 * in case this struct is embedded in a TX_MPDU_DETAILS STRUCT, 53 * and field transmit_bw_restriction is set 54 * 55 * In case of NON punctured transmission: 56 * Sw_buffer_cookie[19:17] = 3'b000: 20 MHz TX only 57 * Sw_buffer_cookie[19:17] = 3'b001: 40 MHz TX only 58 * Sw_buffer_cookie[19:17] = 3'b010: 80 MHz TX only 59 * Sw_buffer_cookie[19:17] = 3'b011: 160 MHz TX only 60 * Sw_buffer_cookie[19:17] = 3'b101: 240 MHz TX only 61 * Sw_buffer_cookie[19:17] = 3'b100: 320 MHz TX only 62 * Sw_buffer_cookie[19:18] = 2'b11: reserved 63 * 64 * In case of punctured transmission: 65 * Sw_buffer_cookie[19:16] = 4'b0000: pattern 0 only 66 * Sw_buffer_cookie[19:16] = 4'b0001: pattern 1 only 67 * Sw_buffer_cookie[19:16] = 4'b0010: pattern 2 only 68 * Sw_buffer_cookie[19:16] = 4'b0011: pattern 3 only 69 * Sw_buffer_cookie[19:16] = 4'b0100: pattern 4 only 70 * Sw_buffer_cookie[19:16] = 4'b0101: pattern 5 only 71 * Sw_buffer_cookie[19:16] = 4'b0110: pattern 6 only 72 * Sw_buffer_cookie[19:16] = 4'b0111: pattern 7 only 73 * Sw_buffer_cookie[19:16] = 4'b1000: pattern 8 only 74 * Sw_buffer_cookie[19:16] = 4'b1001: pattern 9 only 75 * Sw_buffer_cookie[19:16] = 4'b1010: pattern 10 only 76 * Sw_buffer_cookie[19:16] = 4'b1011: pattern 11 only 77 * Sw_buffer_cookie[19:18] = 2'b11: reserved 78 * 79 * Note: a punctured transmission is indicated by the presence 80 * of TLV TX_PUNCTURE_SETUP embedded in the scheduler TLV 81 * 82 * Sw_buffer_cookie[20:17]: Tid: The TID field in the QoS control 83 * field 84 * 85 * Sw_buffer_cookie[16]: Mpdu_qos_control_valid: This field 86 * indicates MPDUs with a QoS control field. 87 * 88 */ 89 90enum hal_tlv_tag { 91 HAL_MACTX_CBF_START = 0 /* 0x0 */, 92 HAL_PHYRX_DATA = 1 /* 0x1 */, 93 HAL_PHYRX_CBF_DATA_RESP = 2 /* 0x2 */, 94 HAL_PHYRX_ABORT_REQUEST = 3 /* 0x3 */, 95 HAL_PHYRX_USER_ABORT_NOTIFICATION = 4 /* 0x4 */, 96 HAL_MACTX_DATA_RESP = 5 /* 0x5 */, 97 HAL_MACTX_CBF_DATA = 6 /* 0x6 */, 98 HAL_MACTX_CBF_DONE = 7 /* 0x7 */, 99 HAL_PHYRX_LMR_DATA_RESP = 8 /* 0x8 */, 100 HAL_RXPCU_TO_UCODE_START = 9 /* 0x9 */, 101 HAL_RXPCU_TO_UCODE_DELIMITER_FOR_FULL_MPDU = 10 /* 0xa */, 102 HAL_RXPCU_TO_UCODE_FULL_MPDU_DATA = 11 /* 0xb */, 103 HAL_RXPCU_TO_UCODE_FCS_STATUS = 12 /* 0xc */, 104 HAL_RXPCU_TO_UCODE_MPDU_DELIMITER = 13 /* 0xd */, 105 HAL_RXPCU_TO_UCODE_DELIMITER_FOR_MPDU_HEADER = 14 /* 0xe */, 106 HAL_RXPCU_TO_UCODE_MPDU_HEADER_DATA = 15 /* 0xf */, 107 HAL_RXPCU_TO_UCODE_END = 16 /* 0x10 */, 108 HAL_MACRX_CBF_READ_REQUEST = 32 /* 0x20 */, 109 HAL_MACRX_CBF_DATA_REQUEST = 33 /* 0x21 */, 110 HAL_MACRXXPECT_NDP_RECEPTION = 34 /* 0x22 */, 111 HAL_MACRX_FREEZE_CAPTURE_CHANNEL = 35 /* 0x23 */, 112 HAL_MACRX_NDP_TIMEOUT = 36 /* 0x24 */, 113 HAL_MACRX_ABORT_ACK = 37 /* 0x25 */, 114 HAL_MACRX_REQ_IMPLICIT_FB = 38 /* 0x26 */, 115 HAL_MACRX_CHAIN_MASK = 39 /* 0x27 */, 116 HAL_MACRX_NAP_USER = 40 /* 0x28 */, 117 HAL_MACRX_ABORT_REQUEST = 41 /* 0x29 */, 118 HAL_PHYTX_OTHER_TRANSMIT_INFO16 = 42 /* 0x2a */, 119 HAL_PHYTX_ABORT_ACK = 43 /* 0x2b */, 120 HAL_PHYTX_ABORT_REQUEST = 44 /* 0x2c */, 121 HAL_PHYTX_PKT_END = 45 /* 0x2d */, 122 HAL_PHYTX_PPDU_HEADER_INFO_REQUEST = 46 /* 0x2e */, 123 HAL_PHYTX_REQUEST_CTRL_INFO = 47 /* 0x2f */, 124 HAL_PHYTX_DATA_REQUEST = 48 /* 0x30 */, 125 HAL_PHYTX_BF_CV_LOADING_DONE = 49 /* 0x31 */, 126 HAL_PHYTX_NAP_ACK = 50 /* 0x32 */, 127 HAL_PHYTX_NAP_DONE = 51 /* 0x33 */, 128 HAL_PHYTX_OFF_ACK = 52 /* 0x34 */, 129 HAL_PHYTX_ON_ACK = 53 /* 0x35 */, 130 HAL_PHYTX_SYNTH_OFF_ACK = 54 /* 0x36 */, 131 HAL_PHYTX_DEBUG16 = 55 /* 0x37 */, 132 HAL_MACTX_ABORT_REQUEST = 56 /* 0x38 */, 133 HAL_MACTX_ABORT_ACK = 57 /* 0x39 */, 134 HAL_MACTX_PKT_END = 58 /* 0x3a */, 135 HAL_MACTX_PRE_PHY_DESC = 59 /* 0x3b */, 136 HAL_MACTX_BF_PARAMS_COMMON = 60 /* 0x3c */, 137 HAL_MACTX_BF_PARAMS_PER_USER = 61 /* 0x3d */, 138 HAL_MACTX_PREFETCH_CV = 62 /* 0x3e */, 139 HAL_MACTX_USER_DESC_COMMON = 63 /* 0x3f */, 140 HAL_MACTX_USER_DESC_PER_USER = 64 /* 0x40 */, 141 HAL_XAMPLE_USER_TLV_16 = 65 /* 0x41 */, 142 HAL_XAMPLE_TLV_16 = 66 /* 0x42 */, 143 HAL_MACTX_PHY_OFF = 67 /* 0x43 */, 144 HAL_MACTX_PHY_ON = 68 /* 0x44 */, 145 HAL_MACTX_SYNTH_OFF = 69 /* 0x45 */, 146 HAL_MACTXXPECT_CBF_COMMON = 70 /* 0x46 */, 147 HAL_MACTXXPECT_CBF_PER_USER = 71 /* 0x47 */, 148 HAL_MACTX_PHY_DESC = 72 /* 0x48 */, 149 HAL_MACTX_L_SIG_A = 73 /* 0x49 */, 150 HAL_MACTX_L_SIG_B = 74 /* 0x4a */, 151 HAL_MACTX_HT_SIG = 75 /* 0x4b */, 152 HAL_MACTX_VHT_SIG_A = 76 /* 0x4c */, 153 HAL_MACTX_VHT_SIG_B_SU20 = 77 /* 0x4d */, 154 HAL_MACTX_VHT_SIG_B_SU40 = 78 /* 0x4e */, 155 HAL_MACTX_VHT_SIG_B_SU80 = 79 /* 0x4f */, 156 HAL_MACTX_VHT_SIG_B_SU160 = 80 /* 0x50 */, 157 HAL_MACTX_VHT_SIG_B_MU20 = 81 /* 0x51 */, 158 HAL_MACTX_VHT_SIG_B_MU40 = 82 /* 0x52 */, 159 HAL_MACTX_VHT_SIG_B_MU80 = 83 /* 0x53 */, 160 HAL_MACTX_VHT_SIG_B_MU160 = 84 /* 0x54 */, 161 HAL_MACTX_SERVICE = 85 /* 0x55 */, 162 HAL_MACTX_HE_SIG_A_SU = 86 /* 0x56 */, 163 HAL_MACTX_HE_SIG_A_MU_DL = 87 /* 0x57 */, 164 HAL_MACTX_HE_SIG_A_MU_UL = 88 /* 0x58 */, 165 HAL_MACTX_HE_SIG_B1_MU = 89 /* 0x59 */, 166 HAL_MACTX_HE_SIG_B2_MU = 90 /* 0x5a */, 167 HAL_MACTX_HE_SIG_B2_OFDMA = 91 /* 0x5b */, 168 HAL_MACTX_DELETE_CV = 92 /* 0x5c */, 169 HAL_MACTX_MU_UPLINK_COMMON = 93 /* 0x5d */, 170 HAL_MACTX_MU_UPLINK_USER_SETUP = 94 /* 0x5e */, 171 HAL_MACTX_OTHER_TRANSMIT_INFO = 95 /* 0x5f */, 172 HAL_MACTX_PHY_NAP = 96 /* 0x60 */, 173 HAL_MACTX_DEBUG = 97 /* 0x61 */, 174 HAL_PHYRX_ABORT_ACK = 98 /* 0x62 */, 175 HAL_PHYRX_GENERATED_CBF_DETAILS = 99 /* 0x63 */, 176 HAL_PHYRX_RSSI_LEGACY = 100 /* 0x64 */, 177 HAL_PHYRX_RSSI_HT = 101 /* 0x65 */, 178 HAL_PHYRX_USER_INFO = 102 /* 0x66 */, 179 HAL_PHYRX_PKT_END = 103 /* 0x67 */, 180 HAL_PHYRX_DEBUG = 104 /* 0x68 */, 181 HAL_PHYRX_CBF_TRANSFER_DONE = 105 /* 0x69 */, 182 HAL_PHYRX_CBF_TRANSFER_ABORT = 106 /* 0x6a */, 183 HAL_PHYRX_L_SIG_A = 107 /* 0x6b */, 184 HAL_PHYRX_L_SIG_B = 108 /* 0x6c */, 185 HAL_PHYRX_HT_SIG = 109 /* 0x6d */, 186 HAL_PHYRX_VHT_SIG_A = 110 /* 0x6e */, 187 HAL_PHYRX_VHT_SIG_B_SU20 = 111 /* 0x6f */, 188 HAL_PHYRX_VHT_SIG_B_SU40 = 112 /* 0x70 */, 189 HAL_PHYRX_VHT_SIG_B_SU80 = 113 /* 0x71 */, 190 HAL_PHYRX_VHT_SIG_B_SU160 = 114 /* 0x72 */, 191 HAL_PHYRX_VHT_SIG_B_MU20 = 115 /* 0x73 */, 192 HAL_PHYRX_VHT_SIG_B_MU40 = 116 /* 0x74 */, 193 HAL_PHYRX_VHT_SIG_B_MU80 = 117 /* 0x75 */, 194 HAL_PHYRX_VHT_SIG_B_MU160 = 118 /* 0x76 */, 195 HAL_PHYRX_HE_SIG_A_SU = 119 /* 0x77 */, 196 HAL_PHYRX_HE_SIG_A_MU_DL = 120 /* 0x78 */, 197 HAL_PHYRX_HE_SIG_A_MU_UL = 121 /* 0x79 */, 198 HAL_PHYRX_HE_SIG_B1_MU = 122 /* 0x7a */, 199 HAL_PHYRX_HE_SIG_B2_MU = 123 /* 0x7b */, 200 HAL_PHYRX_HE_SIG_B2_OFDMA = 124 /* 0x7c */, 201 HAL_PHYRX_OTHER_RECEIVE_INFO = 125 /* 0x7d */, 202 HAL_PHYRX_COMMON_USER_INFO = 126 /* 0x7e */, 203 HAL_PHYRX_DATA_DONE = 127 /* 0x7f */, 204 HAL_COEX_TX_REQ = 128 /* 0x80 */, 205 HAL_DUMMY = 129 /* 0x81 */, 206 HALXAMPLE_TLV_32_NAME = 130 /* 0x82 */, 207 HAL_MPDU_LIMIT = 131 /* 0x83 */, 208 HAL_NA_LENGTH_END = 132 /* 0x84 */, 209 HAL_OLE_BUF_STATUS = 133 /* 0x85 */, 210 HAL_PCU_PPDU_SETUP_DONE = 134 /* 0x86 */, 211 HAL_PCU_PPDU_SETUP_END = 135 /* 0x87 */, 212 HAL_PCU_PPDU_SETUP_INIT = 136 /* 0x88 */, 213 HAL_PCU_PPDU_SETUP_START = 137 /* 0x89 */, 214 HAL_PDG_FES_SETUP = 138 /* 0x8a */, 215 HAL_PDG_RESPONSE = 139 /* 0x8b */, 216 HAL_PDG_TX_REQ = 140 /* 0x8c */, 217 HAL_SCH_WAIT_INSTR = 141 /* 0x8d */, 218 HAL_TQM_FLOWMPTY_STATUS = 143 /* 0x8f */, 219 HAL_TQM_FLOW_NOTMPTY_STATUS = 144 /* 0x90 */, 220 HAL_TQM_GEN_MPDU_LENGTH_LIST = 145 /* 0x91 */, 221 HAL_TQM_GEN_MPDU_LENGTH_LIST_STATUS = 146 /* 0x92 */, 222 HAL_TQM_GEN_MPDUS = 147 /* 0x93 */, 223 HAL_TQM_GEN_MPDUS_STATUS = 148 /* 0x94 */, 224 HAL_TQM_REMOVE_MPDU = 149 /* 0x95 */, 225 HAL_TQM_REMOVE_MPDU_STATUS = 150 /* 0x96 */, 226 HAL_TQM_REMOVE_MSDU = 151 /* 0x97 */, 227 HAL_TQM_REMOVE_MSDU_STATUS = 152 /* 0x98 */, 228 HAL_TQM_UPDATE_TX_MPDU_COUNT = 153 /* 0x99 */, 229 HAL_TQM_WRITE_CMD = 154 /* 0x9a */, 230 HAL_OFDMA_TRIGGER_DETAILS = 155 /* 0x9b */, 231 HAL_TX_DATA = 156 /* 0x9c */, 232 HAL_TX_FES_SETUP = 157 /* 0x9d */, 233 HAL_RX_PACKET = 158 /* 0x9e */, 234 HALXPECTED_RESPONSE = 159 /* 0x9f */, 235 HAL_TX_MPDU_END = 160 /* 0xa0 */, 236 HAL_TX_MPDU_START = 161 /* 0xa1 */, 237 HAL_TX_MSDU_END = 162 /* 0xa2 */, 238 HAL_TX_MSDU_START = 163 /* 0xa3 */, 239 HAL_TX_SW_MODE_SETUP = 164 /* 0xa4 */, 240 HAL_TXPCU_BUFFER_STATUS = 165 /* 0xa5 */, 241 HAL_TXPCU_USER_BUFFER_STATUS = 166 /* 0xa6 */, 242 HAL_DATA_TO_TIME_CONFIG = 167 /* 0xa7 */, 243 HALXAMPLE_USER_TLV_32 = 168 /* 0xa8 */, 244 HAL_MPDU_INFO = 169 /* 0xa9 */, 245 HAL_PDG_USER_SETUP = 170 /* 0xaa */, 246 HAL_TX_11AH_SETUP = 171 /* 0xab */, 247 HAL_REO_UPDATE_RX_REO_QUEUE_STATUS = 172 /* 0xac */, 248 HAL_TX_PEER_ENTRY = 173 /* 0xad */, 249 HAL_TX_RAW_OR_NATIVE_FRAME_SETUP = 174 /* 0xae */, 250 HALXAMPLE_USER_TLV_44 = 175 /* 0xaf */, 251 HAL_TX_FLUSH = 176 /* 0xb0 */, 252 HAL_TX_FLUSH_REQ = 177 /* 0xb1 */, 253 HAL_TQM_WRITE_CMD_STATUS = 178 /* 0xb2 */, 254 HAL_TQM_GET_MPDU_QUEUE_STATS = 179 /* 0xb3 */, 255 HAL_TQM_GET_MSDU_FLOW_STATS = 180 /* 0xb4 */, 256 HALXAMPLE_USER_CTLV_44 = 181 /* 0xb5 */, 257 HAL_TX_FES_STATUS_START = 182 /* 0xb6 */, 258 HAL_TX_FES_STATUS_USER_PPDU = 183 /* 0xb7 */, 259 HAL_TX_FES_STATUS_USER_RESPONSE = 184 /* 0xb8 */, 260 HAL_TX_FES_STATUS_END = 185 /* 0xb9 */, 261 HAL_RX_TRIG_INFO = 186 /* 0xba */, 262 HAL_RXPCU_TX_SETUP_CLEAR = 187 /* 0xbb */, 263 HAL_RX_FRAME_BITMAP_REQ = 188 /* 0xbc */, 264 HAL_RX_FRAME_BITMAP_ACK = 189 /* 0xbd */, 265 HAL_COEX_RX_STATUS = 190 /* 0xbe */, 266 HAL_RX_START_PARAM = 191 /* 0xbf */, 267 HAL_RX_PPDU_START = 192 /* 0xc0 */, 268 HAL_RX_PPDU_END = 193 /* 0xc1 */, 269 HAL_RX_MPDU_START = 194 /* 0xc2 */, 270 HAL_RX_MPDU_END = 195 /* 0xc3 */, 271 HAL_RX_MSDU_START = 196 /* 0xc4 */, 272 HAL_RX_MSDU_END = 197 /* 0xc5 */, 273 HAL_RX_ATTENTION = 198 /* 0xc6 */, 274 HAL_RECEIVED_RESPONSE_INFO = 199 /* 0xc7 */, 275 HAL_RX_PHY_SLEEP = 200 /* 0xc8 */, 276 HAL_RX_HEADER = 201 /* 0xc9 */, 277 HAL_RX_PEER_ENTRY = 202 /* 0xca */, 278 HAL_RX_FLUSH = 203 /* 0xcb */, 279 HAL_RX_RESPONSE_REQUIRED_INFO = 204 /* 0xcc */, 280 HAL_RX_FRAMELESS_BAR_DETAILS = 205 /* 0xcd */, 281 HAL_TQM_GET_MPDU_QUEUE_STATS_STATUS = 206 /* 0xce */, 282 HAL_TQM_GET_MSDU_FLOW_STATS_STATUS = 207 /* 0xcf */, 283 HAL_TX_CBF_INFO = 208 /* 0xd0 */, 284 HAL_PCU_PPDU_SETUP_USER = 209 /* 0xd1 */, 285 HAL_RX_MPDU_PCU_START = 210 /* 0xd2 */, 286 HAL_RX_PM_INFO = 211 /* 0xd3 */, 287 HAL_RX_USER_PPDU_END = 212 /* 0xd4 */, 288 HAL_RX_PRE_PPDU_START = 213 /* 0xd5 */, 289 HAL_RX_PREAMBLE = 214 /* 0xd6 */, 290 HAL_TX_FES_SETUP_COMPLETE = 215 /* 0xd7 */, 291 HAL_TX_LAST_MPDU_FETCHED = 216 /* 0xd8 */, 292 HAL_TXDMA_STOP_REQUEST = 217 /* 0xd9 */, 293 HAL_RXPCU_SETUP = 218 /* 0xda */, 294 HAL_RXPCU_USER_SETUP = 219 /* 0xdb */, 295 HAL_TX_FES_STATUS_ACK_OR_BA = 220 /* 0xdc */, 296 HAL_TQM_ACKED_MPDU = 221 /* 0xdd */, 297 HAL_COEX_TX_RESP = 222 /* 0xde */, 298 HAL_COEX_TX_STATUS = 223 /* 0xdf */, 299 HAL_MACTX_COEX_PHY_CTRL = 224 /* 0xe0 */, 300 HAL_COEX_STATUS_BROADCAST = 225 /* 0xe1 */, 301 HAL_RESPONSE_START_STATUS = 226 /* 0xe2 */, 302 HAL_RESPONSEND_STATUS = 227 /* 0xe3 */, 303 HAL_CRYPTO_STATUS = 228 /* 0xe4 */, 304 HAL_RECEIVED_TRIGGER_INFO = 229 /* 0xe5 */, 305 HAL_COEX_TX_STOP_CTRL = 230 /* 0xe6 */, 306 HAL_RX_PPDU_ACK_REPORT = 231 /* 0xe7 */, 307 HAL_RX_PPDU_NO_ACK_REPORT = 232 /* 0xe8 */, 308 HAL_SCH_COEX_STATUS = 233 /* 0xe9 */, 309 HAL_SCHEDULER_COMMAND_STATUS = 234 /* 0xea */, 310 HAL_SCHEDULER_RX_PPDU_NO_RESPONSE_STATUS = 235 /* 0xeb */, 311 HAL_TX_FES_STATUS_PROT = 236 /* 0xec */, 312 HAL_TX_FES_STATUS_START_PPDU = 237 /* 0xed */, 313 HAL_TX_FES_STATUS_START_PROT = 238 /* 0xee */, 314 HAL_TXPCU_PHYTX_DEBUG32 = 239 /* 0xef */, 315 HAL_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 = 240 /* 0xf0 */, 316 HAL_TX_MPDU_COUNT_TRANSFERND = 241 /* 0xf1 */, 317 HAL_WHO_ANCHOR_OFFSET = 242 /* 0xf2 */, 318 HAL_WHO_ANCHOR_VALUE = 243 /* 0xf3 */, 319 HAL_WHO_CCE_INFO = 244 /* 0xf4 */, 320 HAL_WHO_COMMIT = 245 /* 0xf5 */, 321 HAL_WHO_COMMIT_DONE = 246 /* 0xf6 */, 322 HAL_WHO_FLUSH = 247 /* 0xf7 */, 323 HAL_WHO_L2_LLC = 248 /* 0xf8 */, 324 HAL_WHO_L2_PAYLOAD = 249 /* 0xf9 */, 325 HAL_WHO_L3_CHECKSUM = 250 /* 0xfa */, 326 HAL_WHO_L3_INFO = 251 /* 0xfb */, 327 HAL_WHO_L4_CHECKSUM = 252 /* 0xfc */, 328 HAL_WHO_L4_INFO = 253 /* 0xfd */, 329 HAL_WHO_MSDU = 254 /* 0xfe */, 330 HAL_WHO_MSDU_MISC = 255 /* 0xff */, 331 HAL_WHO_PACKET_DATA = 256 /* 0x100 */, 332 HAL_WHO_PACKET_HDR = 257 /* 0x101 */, 333 HAL_WHO_PPDU_END = 258 /* 0x102 */, 334 HAL_WHO_PPDU_START = 259 /* 0x103 */, 335 HAL_WHO_TSO = 260 /* 0x104 */, 336 HAL_WHO_WMAC_HEADER_PV0 = 261 /* 0x105 */, 337 HAL_WHO_WMAC_HEADER_PV1 = 262 /* 0x106 */, 338 HAL_WHO_WMAC_IV = 263 /* 0x107 */, 339 HAL_MPDU_INFO_END = 264 /* 0x108 */, 340 HAL_MPDU_INFO_BITMAP = 265 /* 0x109 */, 341 HAL_TX_QUEUE_EXTENSION = 266 /* 0x10a */, 342 HAL_SCHEDULER_SELFGEN_RESPONSE_STATUS = 267 /* 0x10b */, 343 HAL_TQM_UPDATE_TX_MPDU_COUNT_STATUS = 268 /* 0x10c */, 344 HAL_TQM_ACKED_MPDU_STATUS = 269 /* 0x10d */, 345 HAL_TQM_ADD_MSDU_STATUS = 270 /* 0x10e */, 346 HAL_TQM_LIST_GEN_DONE = 271 /* 0x10f */, 347 HAL_WHO_TERMINATE = 272 /* 0x110 */, 348 HAL_TX_LAST_MPDU_END = 273 /* 0x111 */, 349 HAL_TX_CV_DATA = 274 /* 0x112 */, 350 HAL_PPDU_TX_END = 275 /* 0x113 */, 351 HAL_PROT_TX_END = 276 /* 0x114 */, 352 HAL_MPDU_INFO_GLOBAL_END = 277 /* 0x115 */, 353 HAL_TQM_SCH_INSTR_GLOBAL_END = 278 /* 0x116 */, 354 HAL_RX_PPDU_END_USER_STATS = 279 /* 0x117 */, 355 HAL_RX_PPDU_END_USER_STATS_EXT = 280 /* 0x118 */, 356 HAL_REO_GET_QUEUE_STATS = 281 /* 0x119 */, 357 HAL_REO_FLUSH_QUEUE = 282 /* 0x11a */, 358 HAL_REO_FLUSH_CACHE = 283 /* 0x11b */, 359 HAL_REO_UNBLOCK_CACHE = 284 /* 0x11c */, 360 HAL_REO_GET_QUEUE_STATS_STATUS = 285 /* 0x11d */, 361 HAL_REO_FLUSH_QUEUE_STATUS = 286 /* 0x11e */, 362 HAL_REO_FLUSH_CACHE_STATUS = 287 /* 0x11f */, 363 HAL_REO_UNBLOCK_CACHE_STATUS = 288 /* 0x120 */, 364 HAL_TQM_FLUSH_CACHE = 289 /* 0x121 */, 365 HAL_TQM_UNBLOCK_CACHE = 290 /* 0x122 */, 366 HAL_TQM_FLUSH_CACHE_STATUS = 291 /* 0x123 */, 367 HAL_TQM_UNBLOCK_CACHE_STATUS = 292 /* 0x124 */, 368 HAL_RX_PPDU_END_STATUS_DONE = 293 /* 0x125 */, 369 HAL_RX_STATUS_BUFFER_DONE = 294 /* 0x126 */, 370 HAL_TX_DATA_SYNC = 297 /* 0x129 */, 371 HAL_PHYRX_CBF_READ_REQUEST_ACK = 298 /* 0x12a */, 372 HAL_TQM_GET_MPDU_HEAD_INFO = 299 /* 0x12b */, 373 HAL_TQM_SYNC_CMD = 300 /* 0x12c */, 374 HAL_TQM_GET_MPDU_HEAD_INFO_STATUS = 301 /* 0x12d */, 375 HAL_TQM_SYNC_CMD_STATUS = 302 /* 0x12e */, 376 HAL_TQM_THRESHOLD_DROP_NOTIFICATION_STATUS = 303 /* 0x12f */, 377 HAL_TQM_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 304 /* 0x130 */, 378 HAL_REO_FLUSH_TIMEOUT_LIST = 305 /* 0x131 */, 379 HAL_REO_FLUSH_TIMEOUT_LIST_STATUS = 306 /* 0x132 */, 380 HAL_REO_DESCRIPTOR_THRESHOLD_REACHED_STATUS = 307 /* 0x133 */, 381 HAL_SCHEDULER_RX_SIFS_RESPONSE_TRIGGER_STATUS = 308 /* 0x134 */, 382 HALXAMPLE_USER_TLV_32_NAME = 309 /* 0x135 */, 383 HAL_RX_PPDU_START_USER_INFO = 310 /* 0x136 */, 384 HAL_RX_RING_MASK = 311 /* 0x137 */, 385 HAL_COEX_MAC_NAP = 312 /* 0x138 */, 386 HAL_RXPCU_PPDU_END_INFO = 313 /* 0x139 */, 387 HAL_WHO_MESH_CONTROL = 314 /* 0x13a */, 388 HAL_PDG_SW_MODE_BW_START = 315 /* 0x13b */, 389 HAL_PDG_SW_MODE_BW_END = 316 /* 0x13c */, 390 HAL_PDG_WAIT_FOR_MAC_REQUEST = 317 /* 0x13d */, 391 HAL_PDG_WAIT_FOR_PHY_REQUEST = 318 /* 0x13e */, 392 HAL_SCHEDULER_END = 319 /* 0x13f */, 393 HAL_RX_PPDU_START_DROPPED = 320 /* 0x140 */, 394 HAL_RX_PPDU_END_DROPPED = 321 /* 0x141 */, 395 HAL_RX_PPDU_END_STATUS_DONE_DROPPED = 322 /* 0x142 */, 396 HAL_RX_MPDU_START_DROPPED = 323 /* 0x143 */, 397 HAL_RX_MSDU_START_DROPPED = 324 /* 0x144 */, 398 HAL_RX_MSDU_END_DROPPED = 325 /* 0x145 */, 399 HAL_RX_MPDU_END_DROPPED = 326 /* 0x146 */, 400 HAL_RX_ATTENTION_DROPPED = 327 /* 0x147 */, 401 HAL_TXPCU_USER_SETUP = 328 /* 0x148 */, 402 HAL_RXPCU_USER_SETUP_EXT = 329 /* 0x149 */, 403 HAL_CMD_PART_0_END = 330 /* 0x14a */, 404 HAL_MACTX_SYNTH_ON = 331 /* 0x14b */, 405 HAL_SCH_CRITICAL_TLV_REFERENCE = 332 /* 0x14c */, 406 HAL_TQM_MPDU_GLOBAL_START = 333 /* 0x14d */, 407 HALXAMPLE_TLV_32 = 334 /* 0x14e */, 408 HAL_TQM_UPDATE_TX_MSDU_FLOW = 335 /* 0x14f */, 409 HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD = 336 /* 0x150 */, 410 HAL_TQM_UPDATE_TX_MSDU_FLOW_STATUS = 337 /* 0x151 */, 411 HAL_TQM_UPDATE_TX_MPDU_QUEUE_HEAD_STATUS = 338 /* 0x152 */, 412 HAL_REO_UPDATE_RX_REO_QUEUE = 339 /* 0x153 */, 413 HAL_TQM_MPDU_QUEUEMPTY_STATUS = 340 /* 0x154 */, 414 HAL_TQM_2_SCH_MPDU_AVAILABLE = 341 /* 0x155 */, 415 HAL_PDG_TRIG_RESPONSE = 342 /* 0x156 */, 416 HAL_TRIGGER_RESPONSE_TX_DONE = 343 /* 0x157 */, 417 HAL_ABORT_FROM_PHYRX_DETAILS = 344 /* 0x158 */, 418 HAL_SCH_TQM_CMD_WRAPPER = 345 /* 0x159 */, 419 HAL_MPDUS_AVAILABLE = 346 /* 0x15a */, 420 HAL_RECEIVED_RESPONSE_INFO_PART2 = 347 /* 0x15b */, 421 HAL_PHYRX_TX_START_TIMING = 348 /* 0x15c */, 422 HAL_TXPCU_PREAMBLE_DONE = 349 /* 0x15d */, 423 HAL_NDP_PREAMBLE_DONE = 350 /* 0x15e */, 424 HAL_SCH_TQM_CMD_WRAPPER_RBO_DROP = 351 /* 0x15f */, 425 HAL_SCH_TQM_CMD_WRAPPER_CONT_DROP = 352 /* 0x160 */, 426 HAL_MACTX_CLEAR_PREV_TX_INFO = 353 /* 0x161 */, 427 HAL_TX_PUNCTURE_SETUP = 354 /* 0x162 */, 428 HAL_R2R_STATUS_END = 355 /* 0x163 */, 429 HAL_MACTX_PREFETCH_CV_COMMON = 356 /* 0x164 */, 430 HAL_END_OF_FLUSH_MARKER = 357 /* 0x165 */, 431 HAL_MACTX_MU_UPLINK_COMMON_PUNC = 358 /* 0x166 */, 432 HAL_MACTX_MU_UPLINK_USER_SETUP_PUNC = 359 /* 0x167 */, 433 HAL_RECEIVED_RESPONSE_USER_7_0 = 360 /* 0x168 */, 434 HAL_RECEIVED_RESPONSE_USER_15_8 = 361 /* 0x169 */, 435 HAL_RECEIVED_RESPONSE_USER_23_16 = 362 /* 0x16a */, 436 HAL_RECEIVED_RESPONSE_USER_31_24 = 363 /* 0x16b */, 437 HAL_RECEIVED_RESPONSE_USER_36_32 = 364 /* 0x16c */, 438 HAL_TX_LOOPBACK_SETUP = 365 /* 0x16d */, 439 HAL_PHYRX_OTHER_RECEIVE_INFO_RU_DETAILS = 366 /* 0x16e */, 440 HAL_SCH_WAIT_INSTR_TX_PATH = 367 /* 0x16f */, 441 HAL_MACTX_OTHER_TRANSMIT_INFO_TX2TX = 368 /* 0x170 */, 442 HAL_MACTX_OTHER_TRANSMIT_INFOMUPHY_SETUP = 369 /* 0x171 */, 443 HAL_PHYRX_OTHER_RECEIVE_INFOVM_DETAILS = 370 /* 0x172 */, 444 HAL_TX_WUR_DATA = 371 /* 0x173 */, 445 HAL_RX_PPDU_END_START = 372 /* 0x174 */, 446 HAL_RX_PPDU_END_MIDDLE = 373 /* 0x175 */, 447 HAL_RX_PPDU_END_LAST = 374 /* 0x176 */, 448 HAL_MACTX_BACKOFF_BASED_TRANSMISSION = 375 /* 0x177 */, 449 HAL_MACTX_OTHER_TRANSMIT_INFO_DL_OFDMA_TX = 376 /* 0x178 */, 450 HAL_SRP_INFO = 377 /* 0x179 */, 451 HAL_OBSS_SR_INFO = 378 /* 0x17a */, 452 HAL_SCHEDULER_SW_MSG_STATUS = 379 /* 0x17b */, 453 HAL_HWSCH_RXPCU_MAC_INFO_ANNOUNCEMENT = 380 /* 0x17c */, 454 HAL_RXPCU_SETUP_COMPLETE = 381 /* 0x17d */, 455 HAL_SNOOP_PPDU_START = 382 /* 0x17e */, 456 HAL_SNOOP_MPDU_USR_DBG_INFO = 383 /* 0x17f */, 457 HAL_SNOOP_MSDU_USR_DBG_INFO = 384 /* 0x180 */, 458 HAL_SNOOP_MSDU_USR_DATA = 385 /* 0x181 */, 459 HAL_SNOOP_MPDU_USR_STAT_INFO = 386 /* 0x182 */, 460 HAL_SNOOP_PPDU_END = 387 /* 0x183 */, 461 HAL_SNOOP_SPARE = 388 /* 0x184 */, 462 HAL_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_COMMON = 390 /* 0x186 */, 463 HAL_PHYRX_OTHER_RECEIVE_INFO_MU_RSSI_USER = 391 /* 0x187 */, 464 HAL_MACTX_OTHER_TRANSMIT_INFO_SCH_DETAILS = 392 /* 0x188 */, 465 HAL_PHYRX_OTHER_RECEIVE_INFO_108PVM_DETAILS = 393 /* 0x189 */, 466 HAL_SCH_TLV_WRAPPER = 394 /* 0x18a */, 467 HAL_SCHEDULER_STATUS_WRAPPER = 395 /* 0x18b */, 468 HAL_MPDU_INFO_6X = 396 /* 0x18c */, 469 HAL_MACTX_11AZ_USER_DESC_PER_USER = 397 /* 0x18d */, 470 HAL_MACTX_U_SIGHT_SU_MU = 398 /* 0x18e */, 471 HAL_MACTX_U_SIGHT_TB = 399 /* 0x18f */, 472 HAL_PHYRX_U_SIGHT_SU_MU = 403 /* 0x193 */, 473 HAL_PHYRX_U_SIGHT_TB = 404 /* 0x194 */, 474 HAL_MACRX_LMR_READ_REQUEST = 408 /* 0x198 */, 475 HAL_MACRX_LMR_DATA_REQUEST = 409 /* 0x199 */, 476 HAL_PHYRX_LMR_TRANSFER_DONE = 410 /* 0x19a */, 477 HAL_PHYRX_LMR_TRANSFER_ABORT = 411 /* 0x19b */, 478 HAL_PHYRX_LMR_READ_REQUEST_ACK = 412 /* 0x19c */, 479 HAL_MACRX_SECURE_LTF_SEQ_PTR = 413 /* 0x19d */, 480 HAL_PHYRX_USER_INFO_MU_UL = 414 /* 0x19e */, 481 HAL_MPDU_QUEUE_OVERVIEW = 415 /* 0x19f */, 482 HAL_SCHEDULER_NAV_INFO = 416 /* 0x1a0 */, 483 HAL_LMR_PEER_ENTRY = 418 /* 0x1a2 */, 484 HAL_LMR_MPDU_START = 419 /* 0x1a3 */, 485 HAL_LMR_DATA = 420 /* 0x1a4 */, 486 HAL_LMR_MPDU_END = 421 /* 0x1a5 */, 487 HAL_REO_GET_QUEUE_1K_STATS_STATUS = 422 /* 0x1a6 */, 488 HAL_RX_FRAME_1K_BITMAP_ACK = 423 /* 0x1a7 */, 489 HAL_TX_FES_STATUS_1K_BA = 424 /* 0x1a8 */, 490 HAL_TQM_ACKED_1K_MPDU = 425 /* 0x1a9 */, 491 HAL_MACRX_INBSS_OBSS_IND = 426 /* 0x1aa */, 492 HAL_PHYRX_LOCATION = 427 /* 0x1ab */, 493 HAL_MLO_TX_NOTIFICATION_SU = 428 /* 0x1ac */, 494 HAL_MLO_TX_NOTIFICATION_MU = 429 /* 0x1ad */, 495 HAL_MLO_TX_REQ_SU = 430 /* 0x1ae */, 496 HAL_MLO_TX_REQ_MU = 431 /* 0x1af */, 497 HAL_MLO_TX_RESP = 432 /* 0x1b0 */, 498 HAL_MLO_RX_NOTIFICATION = 433 /* 0x1b1 */, 499 HAL_MLO_BKOFF_TRUNC_REQ = 434 /* 0x1b2 */, 500 HAL_MLO_TBTT_NOTIFICATION = 435 /* 0x1b3 */, 501 HAL_MLO_MESSAGE = 436 /* 0x1b4 */, 502 HAL_MLO_TS_SYNC_MSG = 437 /* 0x1b5 */, 503 HAL_MLO_FES_SETUP = 438 /* 0x1b6 */, 504 HAL_MLO_PDG_FES_SETUP_SU = 439 /* 0x1b7 */, 505 HAL_MLO_PDG_FES_SETUP_MU = 440 /* 0x1b8 */, 506 HAL_MPDU_INFO_1K_BITMAP = 441 /* 0x1b9 */, 507 HAL_MON_BUF_ADDR = 442 /* 0x1ba */, 508 HAL_TX_FRAG_STATE = 443 /* 0x1bb */, 509 HAL_MACTXHT_SIG_USR_OFDMA = 446 /* 0x1be */, 510 HAL_PHYRXHT_SIG_CMN_PUNC = 448 /* 0x1c0 */, 511 HAL_PHYRXHT_SIG_CMN_OFDMA = 450 /* 0x1c2 */, 512 HAL_PHYRXHT_SIG_USR_OFDMA = 454 /* 0x1c6 */, 513 HAL_PHYRX_PKT_END_PART1 = 456 /* 0x1c8 */, 514 HAL_MACTXXPECT_NDP_RECEPTION = 457 /* 0x1c9 */, 515 HAL_MACTX_SECURE_LTF_SEQ_PTR = 458 /* 0x1ca */, 516 HAL_MLO_PDG_BKOFF_TRUNC_NOTIFY = 460 /* 0x1cc */, 517 HAL_PHYRX_11AZ_INTEGRITY_DATA = 461 /* 0x1cd */, 518 HAL_PHYTX_LOCATION = 462 /* 0x1ce */, 519 HAL_PHYTX_11AZ_INTEGRITY_DATA = 463 /* 0x1cf */, 520 HAL_MACTXHT_SIG_USR_SU = 466 /* 0x1d2 */, 521 HAL_MACTXHT_SIG_USR_MU_MIMO = 467 /* 0x1d3 */, 522 HAL_PHYRXHT_SIG_USR_SU = 468 /* 0x1d4 */, 523 HAL_PHYRXHT_SIG_USR_MU_MIMO = 469 /* 0x1d5 */, 524 HAL_PHYRX_GENERIC_U_SIG = 470 /* 0x1d6 */, 525 HAL_PHYRX_GENERIC_EHT_SIG = 471 /* 0x1d7 */, 526 HAL_OVERWRITE_RESP_START = 472 /* 0x1d8 */, 527 HAL_OVERWRITE_RESP_PREAMBLE_INFO = 473 /* 0x1d9 */, 528 HAL_OVERWRITE_RESP_FRAME_INFO = 474 /* 0x1da */, 529 HAL_OVERWRITE_RESP_END = 475 /* 0x1db */, 530 HAL_RXPCUARLY_RX_INDICATION = 476 /* 0x1dc */, 531 HAL_MON_DROP = 477 /* 0x1dd */, 532 HAL_MACRX_MU_UPLINK_COMMON_SNIFF = 478 /* 0x1de */, 533 HAL_MACRX_MU_UPLINK_USER_SETUP_SNIFF = 479 /* 0x1df */, 534 HAL_MACRX_MU_UPLINK_USER_SEL_SNIFF = 480 /* 0x1e0 */, 535 HAL_MACRX_MU_UPLINK_FCS_STATUS_SNIFF = 481 /* 0x1e1 */, 536 HAL_MACTX_PREFETCH_CV_DMA = 482 /* 0x1e2 */, 537 HAL_MACTX_PREFETCH_CV_PER_USER = 483 /* 0x1e3 */, 538 HAL_PHYRX_OTHER_RECEIVE_INFO_ALL_SIGB_DETAILS = 484 /* 0x1e4 */, 539 HAL_MACTX_BF_PARAMS_UPDATE_COMMON = 485 /* 0x1e5 */, 540 HAL_MACTX_BF_PARAMS_UPDATE_PER_USER = 486 /* 0x1e6 */, 541 HAL_RANGING_USER_DETAILS = 487 /* 0x1e7 */, 542 HAL_PHYTX_CV_CORR_STATUS = 488 /* 0x1e8 */, 543 HAL_PHYTX_CV_CORR_COMMON = 489 /* 0x1e9 */, 544 HAL_PHYTX_CV_CORR_USER = 490 /* 0x1ea */, 545 HAL_MACTX_CV_CORR_COMMON = 491 /* 0x1eb */, 546 HAL_MACTX_CV_CORR_MAC_INFO_GROUP = 492 /* 0x1ec */, 547 HAL_BW_PUNCTUREVAL_WRAPPER = 493 /* 0x1ed */, 548 HAL_MACTX_RX_NOTIFICATION_FOR_PHY = 494 /* 0x1ee */, 549 HAL_MACTX_TX_NOTIFICATION_FOR_PHY = 495 /* 0x1ef */, 550 HAL_MACTX_MU_UPLINK_COMMON_PER_BW = 496 /* 0x1f0 */, 551 HAL_MACTX_MU_UPLINK_USER_SETUP_PER_BW = 497 /* 0x1f1 */, 552 HAL_RX_PPDU_END_USER_STATS_EXT2 = 498 /* 0x1f2 */, 553 HAL_FW2SW_MON = 499 /* 0x1f3 */, 554 HAL_WSI_DIRECT_MESSAGE = 500 /* 0x1f4 */, 555 HAL_MACTXMLSR_PRE_SWITCH = 501 /* 0x1f5 */, 556 HAL_MACTXMLSR_SWITCH = 502 /* 0x1f6 */, 557 HAL_MACTXMLSR_SWITCH_BACK = 503 /* 0x1f7 */, 558 HAL_PHYTXMLSR_SWITCH_ACK = 504 /* 0x1f8 */, 559 HAL_PHYTXMLSR_SWITCH_BACK_ACK = 505 /* 0x1f9 */, 560 HAL_SPARE_REUSE_TAG_0 = 506 /* 0x1fa */, 561 HAL_SPARE_REUSE_TAG_1 = 507 /* 0x1fb */, 562 HAL_SPARE_REUSE_TAG_2 = 508 /* 0x1fc */, 563 HAL_SPARE_REUSE_TAG_3 = 509 /* 0x1fd */, 564 /* FIXME: Assign correct value for HAL_TCL_DATA_CMD */ 565 HAL_TCL_DATA_CMD = 510, 566 HAL_TLV_BASE = 511 /* 0x1ff */, 567}; 568 569#define HAL_TLV_HDR_TAG GENMASK(9, 1) 570#define HAL_TLV_HDR_LEN GENMASK(25, 10) 571#define HAL_TLV_USR_ID GENMASK(31, 26) 572 573#define HAL_TLV_ALIGN 4 574 575struct hal_tlv_hdr { 576 __le32 tl; 577 u8 value[]; 578} __packed; 579 580#define HAL_TLV_64_HDR_TAG GENMASK(9, 1) 581#define HAL_TLV_64_HDR_LEN GENMASK(21, 10) 582#define HAL_TLV_64_USR_ID GENMASK(31, 26) 583#define HAL_TLV_64_ALIGN 8 584 585struct hal_tlv_64_hdr { 586 __le64 tl; 587 u8 value[]; 588} __packed; 589 590#define RX_MPDU_DESC_INFO0_MSDU_COUNT GENMASK(7, 0) 591#define RX_MPDU_DESC_INFO0_FRAG_FLAG BIT(8) 592#define RX_MPDU_DESC_INFO0_MPDU_RETRY BIT(9) 593#define RX_MPDU_DESC_INFO0_AMPDU_FLAG BIT(10) 594#define RX_MPDU_DESC_INFO0_BAR_FRAME BIT(11) 595#define RX_MPDU_DESC_INFO0_VALID_PN BIT(12) 596#define RX_MPDU_DESC_INFO0_RAW_MPDU BIT(13) 597#define RX_MPDU_DESC_INFO0_MORE_FRAG_FLAG BIT(14) 598#define RX_MPDU_DESC_INFO0_SRC_INFO GENMASK(26, 15) 599#define RX_MPDU_DESC_INFO0_MPDU_QOS_CTRL_VALID BIT(27) 600#define RX_MPDU_DESC_INFO0_TID GENMASK(31, 28) 601 602/* Peer Metadata classification */ 603 604/* Version 0 */ 605#define RX_MPDU_DESC_META_DATA_V0_PEER_ID GENMASK(15, 0) 606#define RX_MPDU_DESC_META_DATA_V0_VDEV_ID GENMASK(23, 16) 607 608/* Version 1 */ 609#define RX_MPDU_DESC_META_DATA_V1_PEER_ID GENMASK(13, 0) 610#define RX_MPDU_DESC_META_DATA_V1_LOGICAL_LINK_ID GENMASK(15, 14) 611#define RX_MPDU_DESC_META_DATA_V1_VDEV_ID GENMASK(23, 16) 612#define RX_MPDU_DESC_META_DATA_V1_LMAC_ID GENMASK(25, 24) 613#define RX_MPDU_DESC_META_DATA_V1_DEVICE_ID GENMASK(28, 26) 614 615/* Version 1A */ 616#define RX_MPDU_DESC_META_DATA_V1A_PEER_ID GENMASK(13, 0) 617#define RX_MPDU_DESC_META_DATA_V1A_VDEV_ID GENMASK(21, 14) 618#define RX_MPDU_DESC_META_DATA_V1A_LOGICAL_LINK_ID GENMASK(25, 22) 619#define RX_MPDU_DESC_META_DATA_V1A_DEVICE_ID GENMASK(28, 26) 620 621/* Version 1B */ 622#define RX_MPDU_DESC_META_DATA_V1B_PEER_ID GENMASK(13, 0) 623#define RX_MPDU_DESC_META_DATA_V1B_VDEV_ID GENMASK(21, 14) 624#define RX_MPDU_DESC_META_DATA_V1B_HW_LINK_ID GENMASK(25, 22) 625#define RX_MPDU_DESC_META_DATA_V1B_DEVICE_ID GENMASK(28, 26) 626 627struct rx_mpdu_desc { 628 __le32 info0; /* %RX_MPDU_DESC_INFO */ 629 __le32 peer_meta_data; 630} __packed; 631 632/* rx_mpdu_desc 633 * Producer: RXDMA 634 * Consumer: REO/SW/FW 635 * 636 * msdu_count 637 * The number of MSDUs within the MPDU 638 * 639 * fragment_flag 640 * When set, this MPDU is a fragment and REO should forward this 641 * fragment MPDU to the REO destination ring without any reorder 642 * checks, pn checks or bitmap update. This implies that REO is 643 * forwarding the pointer to the MSDU link descriptor. 644 * 645 * mpdu_retry_bit 646 * The retry bit setting from the MPDU header of the received frame 647 * 648 * ampdu_flag 649 * Indicates the MPDU was received as part of an A-MPDU. 650 * 651 * bar_frame 652 * Indicates the received frame is a BAR frame. After processing, 653 * this frame shall be pushed to SW or deleted. 654 * 655 * valid_pn 656 * When not set, REO will not perform a PN sequence number check. 657 * 658 * raw_mpdu 659 * Field only valid when first_msdu_in_mpdu_flag is set. Indicates 660 * the contents in the MSDU buffer contains a 'RAW' MPDU. This 661 * 'RAW' MPDU might be spread out over multiple MSDU buffers. 662 * 663 * more_fragment_flag 664 * The More Fragment bit setting from the MPDU header of the 665 * received frame 666 * 667 * src_info 668 * Source (Virtual) device/interface info associated with this peer. 669 * This field gets passed on by REO to PPE in the EDMA descriptor. 670 * 671 * mpdu_qos_control_valid 672 * When set, the MPDU has a QoS control field 673 * 674 * tid 675 * Field only valid when mpdu_qos_control_valid is set 676 */ 677 678enum hal_rx_msdu_desc_reo_dest_ind { 679 HAL_RX_MSDU_DESC_REO_DEST_IND_TCL, 680 HAL_RX_MSDU_DESC_REO_DEST_IND_SW1, 681 HAL_RX_MSDU_DESC_REO_DEST_IND_SW2, 682 HAL_RX_MSDU_DESC_REO_DEST_IND_SW3, 683 HAL_RX_MSDU_DESC_REO_DEST_IND_SW4, 684 HAL_RX_MSDU_DESC_REO_DEST_IND_RELEASE, 685 HAL_RX_MSDU_DESC_REO_DEST_IND_FW, 686 HAL_RX_MSDU_DESC_REO_DEST_IND_SW5, 687 HAL_RX_MSDU_DESC_REO_DEST_IND_SW6, 688 HAL_RX_MSDU_DESC_REO_DEST_IND_SW7, 689 HAL_RX_MSDU_DESC_REO_DEST_IND_SW8, 690}; 691 692#define RX_MSDU_DESC_INFO0_FIRST_MSDU_IN_MPDU BIT(0) 693#define RX_MSDU_DESC_INFO0_LAST_MSDU_IN_MPDU BIT(1) 694#define RX_MSDU_DESC_INFO0_MSDU_CONTINUATION BIT(2) 695#define RX_MSDU_DESC_INFO0_MSDU_LENGTH GENMASK(16, 3) 696#define RX_MSDU_DESC_INFO0_MSDU_DROP BIT(17) 697#define RX_MSDU_DESC_INFO0_VALID_SA BIT(18) 698#define RX_MSDU_DESC_INFO0_VALID_DA BIT(19) 699#define RX_MSDU_DESC_INFO0_DA_MCBC BIT(20) 700#define RX_MSDU_DESC_INFO0_L3_HDR_PAD_MSB BIT(21) 701#define RX_MSDU_DESC_INFO0_TCP_UDP_CHKSUM_FAIL BIT(22) 702#define RX_MSDU_DESC_INFO0_IP_CHKSUM_FAIL BIT(23) 703#define RX_MSDU_DESC_INFO0_FROM_DS BIT(24) 704#define RX_MSDU_DESC_INFO0_TO_DS BIT(25) 705#define RX_MSDU_DESC_INFO0_INTRA_BSS BIT(26) 706#define RX_MSDU_DESC_INFO0_DST_CHIP_ID GENMASK(28, 27) 707#define RX_MSDU_DESC_INFO0_DECAP_FORMAT GENMASK(30, 29) 708 709#define HAL_RX_MSDU_PKT_LENGTH_GET(val) \ 710 (le32_get_bits((val), RX_MSDU_DESC_INFO0_MSDU_LENGTH)) 711 712struct rx_msdu_desc { 713 __le32 info0; 714} __packed; 715 716/* rx_msdu_desc 717 * 718 * first_msdu_in_mpdu 719 * Indicates first msdu in mpdu. 720 * 721 * last_msdu_in_mpdu 722 * Indicates last msdu in mpdu. This flag can be true only when 723 * 'Msdu_continuation' set to 0. This implies that when an msdu 724 * is spread out over multiple buffers and thus msdu_continuation 725 * is set, only for the very last buffer of the msdu, can the 726 * 'last_msdu_in_mpdu' be set. 727 * 728 * When both first_msdu_in_mpdu and last_msdu_in_mpdu are set, 729 * the MPDU that this MSDU belongs to only contains a single MSDU. 730 * 731 * msdu_continuation 732 * When set, this MSDU buffer was not able to hold the entire MSDU. 733 * The next buffer will therefore contain additional information 734 * related to this MSDU. 735 * 736 * msdu_length 737 * Field is only valid in combination with the 'first_msdu_in_mpdu' 738 * being set. Full MSDU length in bytes after decapsulation. This 739 * field is still valid for MPDU frames without A-MSDU. It still 740 * represents MSDU length after decapsulation Or in case of RAW 741 * MPDUs, it indicates the length of the entire MPDU (without FCS 742 * field). 743 * 744 * msdu_drop 745 * Indicates that REO shall drop this MSDU and not forward it to 746 * any other ring. 747 * 748 * valid_sa 749 * Indicates OLE found a valid SA entry for this MSDU. 750 * 751 * valid_da 752 * When set, OLE found a valid DA entry for this MSDU. 753 * 754 * da_mcbc 755 * Field Only valid if valid_da is set. Indicates the DA address 756 * is a Multicast or Broadcast address for this MSDU. 757 * 758 * l3_header_padding_msb 759 * Passed on from 'RX_MSDU_END' TLV (only the MSB is reported as 760 * the LSB is always zero). Number of bytes padded to make sure 761 * that the L3 header will always start of a Dword boundary 762 * 763 * tcp_udp_checksum_fail 764 * Passed on from 'RX_ATTENTION' TLV 765 * Indicates that the computed checksum did not match the checksum 766 * in the TCP/UDP header. 767 * 768 * ip_checksum_fail 769 * Passed on from 'RX_ATTENTION' TLV 770 * Indicates that the computed checksum did not match the checksum 771 * in the IP header. 772 * 773 * from_DS 774 * Set if the 'from DS' bit is set in the frame control. 775 * 776 * to_DS 777 * Set if the 'to DS' bit is set in the frame control. 778 * 779 * intra_bss 780 * This packet needs intra-BSS routing by SW as the 'vdev_id' 781 * for the destination is the same as the 'vdev_id' that this 782 * MSDU was got in. 783 * 784 * dest_chip_id 785 * If intra_bss is set, copied by RXOLE/RXDMA from 'ADDR_SEARCH_ENTRY' 786 * to support intra-BSS routing with multi-chip multi-link operation. 787 * This indicates into which chip's TCL the packet should be queued. 788 * 789 * decap_format 790 * Indicates the format after decapsulation: 791 */ 792 793#define RX_MSDU_EXT_DESC_INFO0_REO_DEST_IND GENMASK(4, 0) 794#define RX_MSDU_EXT_DESC_INFO0_SERVICE_CODE GENMASK(13, 5) 795#define RX_MSDU_EXT_DESC_INFO0_PRIORITY_VALID BIT(14) 796#define RX_MSDU_EXT_DESC_INFO0_DATA_OFFSET GENMASK(26, 15) 797#define RX_MSDU_EXT_DESC_INFO0_SRC_LINK_ID GENMASK(29, 27) 798 799struct rx_msdu_ext_desc { 800 __le32 info0; 801} __packed; 802 803/* rx_msdu_ext_desc 804 * 805 * reo_destination_indication 806 * The ID of the REO exit ring where the MSDU frame shall push 807 * after (MPDU level) reordering has finished. 808 * 809 * service_code 810 * Opaque service code between PPE and Wi-Fi 811 * 812 * priority_valid 813 * 814 * data_offset 815 * The offset to Rx packet data within the buffer (including 816 * Rx DMA offset programming and L3 header padding inserted 817 * by Rx OLE). 818 * 819 * src_link_id 820 * Set to the link ID of the PMAC that received the frame 821 */ 822 823enum hal_reo_dest_ring_buffer_type { 824 HAL_REO_DEST_RING_BUFFER_TYPE_MSDU, 825 HAL_REO_DEST_RING_BUFFER_TYPE_LINK_DESC, 826}; 827 828enum hal_reo_dest_ring_push_reason { 829 HAL_REO_DEST_RING_PUSH_REASON_ERR_DETECTED, 830 HAL_REO_DEST_RING_PUSH_REASON_ROUTING_INSTRUCTION, 831}; 832 833enum hal_reo_dest_ring_error_code { 834 HAL_REO_DEST_RING_ERROR_CODE_DESC_ADDR_ZERO, 835 HAL_REO_DEST_RING_ERROR_CODE_DESC_INVALID, 836 HAL_REO_DEST_RING_ERROR_CODE_AMPDU_IN_NON_BA, 837 HAL_REO_DEST_RING_ERROR_CODE_NON_BA_DUPLICATE, 838 HAL_REO_DEST_RING_ERROR_CODE_BA_DUPLICATE, 839 HAL_REO_DEST_RING_ERROR_CODE_FRAME_2K_JUMP, 840 HAL_REO_DEST_RING_ERROR_CODE_BAR_2K_JUMP, 841 HAL_REO_DEST_RING_ERROR_CODE_FRAME_OOR, 842 HAL_REO_DEST_RING_ERROR_CODE_BAR_OOR, 843 HAL_REO_DEST_RING_ERROR_CODE_NO_BA_SESSION, 844 HAL_REO_DEST_RING_ERROR_CODE_FRAME_SN_EQUALS_SSN, 845 HAL_REO_DEST_RING_ERROR_CODE_PN_CHECK_FAILED, 846 HAL_REO_DEST_RING_ERROR_CODE_2K_ERR_FLAG_SET, 847 HAL_REO_DEST_RING_ERROR_CODE_PN_ERR_FLAG_SET, 848 HAL_REO_DEST_RING_ERROR_CODE_DESC_BLOCKED, 849 HAL_REO_DEST_RING_ERROR_CODE_MAX, 850}; 851 852#define HAL_REO_DEST_RING_INFO0_BUFFER_TYPE BIT(0) 853#define HAL_REO_DEST_RING_INFO0_PUSH_REASON GENMASK(2, 1) 854#define HAL_REO_DEST_RING_INFO0_ERROR_CODE GENMASK(7, 3) 855#define HAL_REO_DEST_RING_INFO0_MSDU_DATA_SIZE GENMASK(11, 8) 856#define HAL_REO_DEST_RING_INFO0_SW_EXCEPTION BIT(12) 857#define HAL_REO_DEST_RING_INFO0_SRC_LINK_ID GENMASK(15, 13) 858#define HAL_REO_DEST_RING_INFO0_SIGNATURE GENMASK(19, 16) 859#define HAL_REO_DEST_RING_INFO0_RING_ID GENMASK(27, 20) 860#define HAL_REO_DEST_RING_INFO0_LOOPING_COUNT GENMASK(31, 28) 861 862struct hal_reo_dest_ring { 863 struct ath12k_buffer_addr buf_addr_info; 864 struct rx_mpdu_desc rx_mpdu_info; 865 struct rx_msdu_desc rx_msdu_info; 866 __le32 buf_va_lo; 867 __le32 buf_va_hi; 868 __le32 info0; /* %HAL_REO_DEST_RING_INFO0_ */ 869} __packed; 870 871/* hal_reo_dest_ring 872 * 873 * Producer: RXDMA 874 * Consumer: REO/SW/FW 875 * 876 * buf_addr_info 877 * Details of the physical address of a buffer or MSDU 878 * link descriptor. 879 * 880 * rx_mpdu_info 881 * General information related to the MPDU that is passed 882 * on from REO entrance ring to the REO destination ring. 883 * 884 * rx_msdu_info 885 * General information related to the MSDU that is passed 886 * on from RXDMA all the way to the REO destination ring. 887 * 888 * buf_va_lo 889 * Field only valid if Reo_dest_buffer_type is set to MSDU_buf_address 890 * Lower 32 bits of the 64-bit virtual address corresponding 891 * to Buf_or_link_desc_addr_info 892 * 893 * buf_va_hi 894 * Address (upper 32 bits) of the REO queue descriptor. 895 * Upper 32 bits of the 64-bit virtual address corresponding 896 * to Buf_or_link_desc_addr_info 897 * 898 * buffer_type 899 * Indicates the type of address provided in the buf_addr_info. 900 * Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_. 901 * 902 * push_reason 903 * Reason for pushing this frame to this exit ring. Values are 904 * defined in enum %HAL_REO_DEST_RING_PUSH_REASON_. 905 * 906 * error_code 907 * Valid only when 'push_reason' is set. All error codes are 908 * defined in enum %HAL_REO_DEST_RING_ERROR_CODE_. 909 * 910 * captured_msdu_data_size 911 * The number of following REO_DESTINATION STRUCTs that have 912 * been replaced with msdu_data extracted from the msdu_buffer 913 * and copied into the ring for easy FW/SW access. 914 * 915 * sw_exception 916 * This field has the same setting as the SW_exception field 917 * in the corresponding REO_entrance_ring descriptor. 918 * When set, the REO entrance descriptor is generated by FW, 919 * and the MPDU was processed in the following way: 920 * - NO re-order function is needed. 921 * - MPDU delinking is determined by the setting of Entrance 922 * ring field: SW_excection_mpdu_delink 923 * - Destination ring selection is based on the setting of 924 * the Entrance ring field SW_exception_destination _ring_valid 925 * 926 * src_link_id 927 * Set to the link ID of the PMAC that received the frame 928 * 929 * signature 930 * Set to value 0x8 when msdu capture mode is enabled for this ring 931 * 932 * ring_id 933 * The buffer pointer ring id. 934 * 0 - Idle ring 935 * 1 - N refers to other rings. 936 * 937 * looping_count 938 * Indicates the number of times the producer of entries into 939 * this ring has looped around the ring. 940 */ 941 942#define HAL_REO_TO_PPE_RING_INFO0_DATA_LENGTH GENMASK(15, 0) 943#define HAL_REO_TO_PPE_RING_INFO0_DATA_OFFSET GENMASK(23, 16) 944#define HAL_REO_TO_PPE_RING_INFO0_POOL_ID GENMASK(28, 24) 945#define HAL_REO_TO_PPE_RING_INFO0_PREHEADER BIT(29) 946#define HAL_REO_TO_PPE_RING_INFO0_TSO_EN BIT(30) 947#define HAL_REO_TO_PPE_RING_INFO0_MORE BIT(31) 948 949struct hal_reo_to_ppe_ring { 950 __le32 buffer_addr; 951 __le32 info0; /* %HAL_REO_TO_PPE_RING_INFO0_ */ 952} __packed; 953 954/* hal_reo_to_ppe_ring 955 * 956 * Producer: REO 957 * Consumer: PPE 958 * 959 * buf_addr_info 960 * Details of the physical address of a buffer or MSDU 961 * link descriptor. 962 * 963 * data_length 964 * Length of valid data in bytes 965 * 966 * data_offset 967 * Offset to the data from buffer pointer. Can be used to 968 * strip header in the data for tunnel termination etc. 969 * 970 * pool_id 971 * REO has global configuration register for this field. 972 * It may have several free buffer pools, each 973 * RX-Descriptor ring can fetch free buffer from specific 974 * buffer pool; pool id will indicate which pool the buffer 975 * will be released to; POOL_ID Zero returned to SW 976 * 977 * preheader 978 * Disabled: 0 (Default) 979 * Enabled: 1 980 * 981 * tso_en 982 * Disabled: 0 (Default) 983 * Enabled: 1 984 * 985 * more 986 * More Segments followed 987 */ 988 989enum hal_reo_entr_rxdma_push_reason { 990 HAL_REO_ENTR_RING_RXDMA_PUSH_REASON_ERR_DETECTED, 991 HAL_REO_ENTR_RING_RXDMA_PUSH_REASON_ROUTING_INSTRUCTION, 992 HAL_REO_ENTR_RING_RXDMA_PUSH_REASON_RX_FLUSH, 993}; 994 995enum hal_reo_entr_rxdma_ecode { 996 HAL_REO_ENTR_RING_RXDMA_ECODE_OVERFLOW_ERR, 997 HAL_REO_ENTR_RING_RXDMA_ECODE_MPDU_LEN_ERR, 998 HAL_REO_ENTR_RING_RXDMA_ECODE_FCS_ERR, 999 HAL_REO_ENTR_RING_RXDMA_ECODE_DECRYPT_ERR, 1000 HAL_REO_ENTR_RING_RXDMA_ECODE_TKIP_MIC_ERR, 1001 HAL_REO_ENTR_RING_RXDMA_ECODE_UNECRYPTED_ERR, 1002 HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LEN_ERR, 1003 HAL_REO_ENTR_RING_RXDMA_ECODE_MSDU_LIMIT_ERR, 1004 HAL_REO_ENTR_RING_RXDMA_ECODE_WIFI_PARSE_ERR, 1005 HAL_REO_ENTR_RING_RXDMA_ECODE_AMSDU_PARSE_ERR, 1006 HAL_REO_ENTR_RING_RXDMA_ECODE_SA_TIMEOUT_ERR, 1007 HAL_REO_ENTR_RING_RXDMA_ECODE_DA_TIMEOUT_ERR, 1008 HAL_REO_ENTR_RING_RXDMA_ECODE_FLOW_TIMEOUT_ERR, 1009 HAL_REO_ENTR_RING_RXDMA_ECODE_FLUSH_REQUEST_ERR, 1010 HAL_REO_ENTR_RING_RXDMA_ECODE_AMSDU_FRAG_ERR, 1011 HAL_REO_ENTR_RING_RXDMA_ECODE_MULTICAST_ECHO_ERR, 1012 HAL_REO_ENTR_RING_RXDMA_ECODE_AMSDU_MISMATCH_ERR, 1013 HAL_REO_ENTR_RING_RXDMA_ECODE_UNAUTH_WDS_ERR, 1014 HAL_REO_ENTR_RING_RXDMA_ECODE_GRPCAST_AMSDU_WDS_ERR, 1015 HAL_REO_ENTR_RING_RXDMA_ECODE_MAX, 1016}; 1017 1018enum hal_rx_reo_dest_ring { 1019 HAL_RX_REO_DEST_RING_TCL, 1020 HAL_RX_REO_DEST_RING_SW1, 1021 HAL_RX_REO_DEST_RING_SW2, 1022 HAL_RX_REO_DEST_RING_SW3, 1023 HAL_RX_REO_DEST_RING_SW4, 1024 HAL_RX_REO_DEST_RING_RELEASE, 1025 HAL_RX_REO_DEST_RING_FW, 1026 HAL_RX_REO_DEST_RING_SW5, 1027 HAL_RX_REO_DEST_RING_SW6, 1028 HAL_RX_REO_DEST_RING_SW7, 1029 HAL_RX_REO_DEST_RING_SW8, 1030}; 1031 1032#define HAL_REO_ENTR_RING_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 1033#define HAL_REO_ENTR_RING_INFO0_MPDU_BYTE_COUNT GENMASK(21, 8) 1034#define HAL_REO_ENTR_RING_INFO0_DEST_IND GENMASK(26, 22) 1035#define HAL_REO_ENTR_RING_INFO0_FRAMELESS_BAR BIT(27) 1036 1037#define HAL_REO_ENTR_RING_INFO1_RXDMA_PUSH_REASON GENMASK(1, 0) 1038#define HAL_REO_ENTR_RING_INFO1_RXDMA_ERROR_CODE GENMASK(6, 2) 1039#define HAL_REO_ENTR_RING_INFO1_MPDU_FRAG_NUM GENMASK(10, 7) 1040#define HAL_REO_ENTR_RING_INFO1_SW_EXCEPTION BIT(11) 1041#define HAL_REO_ENTR_RING_INFO1_SW_EXCEPT_MPDU_DELINK BIT(12) 1042#define HAL_REO_ENTR_RING_INFO1_SW_EXCEPTION_RING_VLD BIT(13) 1043#define HAL_REO_ENTR_RING_INFO1_SW_EXCEPTION_RING GENMASK(18, 14) 1044#define HAL_REO_ENTR_RING_INFO1_MPDU_SEQ_NUM GENMASK(30, 19) 1045 1046#define HAL_REO_ENTR_RING_INFO2_PHY_PPDU_ID GENMASK(15, 0) 1047#define HAL_REO_ENTR_RING_INFO2_SRC_LINK_ID GENMASK(18, 16) 1048#define HAL_REO_ENTR_RING_INFO2_RING_ID GENMASK(27, 20) 1049#define HAL_REO_ENTR_RING_INFO2_LOOPING_COUNT GENMASK(31, 28) 1050 1051struct hal_reo_entrance_ring { 1052 struct ath12k_buffer_addr buf_addr_info; 1053 struct rx_mpdu_desc rx_mpdu_info; 1054 __le32 queue_addr_lo; 1055 __le32 info0; /* %HAL_REO_ENTR_RING_INFO0_ */ 1056 __le32 info1; /* %HAL_REO_ENTR_RING_INFO1_ */ 1057 __le32 info2; /* %HAL_REO_DEST_RING_INFO2_ */ 1058 1059} __packed; 1060 1061/* hal_reo_entrance_ring 1062 * 1063 * Producer: RXDMA 1064 * Consumer: REO 1065 * 1066 * buf_addr_info 1067 * Details of the physical address of a buffer or MSDU 1068 * link descriptor. 1069 * 1070 * rx_mpdu_info 1071 * General information related to the MPDU that is passed 1072 * on from REO entrance ring to the REO destination ring. 1073 * 1074 * queue_addr_lo 1075 * Address (lower 32 bits) of the REO queue descriptor. 1076 * 1077 * queue_addr_hi 1078 * Address (upper 8 bits) of the REO queue descriptor. 1079 * 1080 * mpdu_byte_count 1081 * An approximation of the number of bytes received in this MPDU. 1082 * Used to keeps stats on the amount of data flowing 1083 * through a queue. 1084 * 1085 * reo_destination_indication 1086 * The id of the reo exit ring where the msdu frame shall push 1087 * after (MPDU level) reordering has finished. Values are defined 1088 * in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_. 1089 * 1090 * frameless_bar 1091 * Indicates that this REO entrance ring struct contains BAR info 1092 * from a multi TID BAR frame. The original multi TID BAR frame 1093 * itself contained all the REO info for the first TID, but all 1094 * the subsequent TID info and their linkage to the REO descriptors 1095 * is passed down as 'frameless' BAR info. 1096 * 1097 * The only fields valid in this descriptor when this bit is set 1098 * are queue_addr_lo, queue_addr_hi, mpdu_sequence_number, 1099 * bar_frame and peer_meta_data. 1100 * 1101 * rxdma_push_reason 1102 * Reason for pushing this frame to this exit ring. Values are 1103 * defined in enum %HAL_REO_ENTR_RING_RXDMA_PUSH_REASON_. 1104 * 1105 * rxdma_error_code 1106 * Valid only when 'push_reason' is set. All error codes are 1107 * defined in enum %HAL_REO_ENTR_RING_RXDMA_ECODE_. 1108 * 1109 * mpdu_fragment_number 1110 * Field only valid when Reo_level_mpdu_frame_info. 1111 * Rx_mpdu_desc_info_details.Fragment_flag is set. 1112 * 1113 * sw_exception 1114 * When not set, REO is performing all its default MPDU processing 1115 * operations, 1116 * When set, this REO entrance descriptor is generated by FW, and 1117 * should be processed as an exception. This implies: 1118 * NO re-order function is needed. 1119 * MPDU delinking is determined by the setting of field 1120 * SW_excection_mpdu_delink 1121 * 1122 * sw_exception_mpdu_delink 1123 * Field only valid when SW_exception is set. 1124 * 1'b0: REO should NOT delink the MPDU, and thus pass this 1125 * MPDU on to the destination ring as is. This implies that 1126 * in the REO_DESTINATION_RING struct field 1127 * Buf_or_link_desc_addr_info should point to an MSDU link 1128 * descriptor 1129 * 1'b1: REO should perform the normal MPDU delink into MSDU operations. 1130 * 1131 * sw_exception_dest_ring 1132 * Field only valid when fields SW_exception and SW 1133 * exception_destination_ring_valid are set. values are defined 1134 * in %HAL_RX_REO_DEST_RING_. 1135 * 1136 * mpdu_seq_number 1137 * The field can have two different meanings based on the setting 1138 * of sub-field Reo level mpdu frame info. 1139 * Rx_mpdu_desc_info_details. BAR_frame 1140 * 'BAR_frame' is NOT set: 1141 * The MPDU sequence number of the received frame. 1142 * 'BAR_frame' is set. 1143 * The MPDU Start sequence number from the BAR frame 1144 * 1145 * phy_ppdu_id 1146 * A PPDU counter value that PHY increments for every PPDU received 1147 * 1148 * src_link_id 1149 * Set to the link ID of the PMAC that received the frame 1150 * 1151 * ring_id 1152 * The buffer pointer ring id. 1153 * 0 - Idle ring 1154 * 1 - N refers to other rings. 1155 * 1156 * looping_count 1157 * Indicates the number of times the producer of entries into 1158 * this ring has looped around the ring. 1159 */ 1160 1161#define HAL_REO_CMD_HDR_INFO0_CMD_NUMBER GENMASK(15, 0) 1162#define HAL_REO_CMD_HDR_INFO0_STATUS_REQUIRED BIT(16) 1163 1164struct hal_reo_cmd_hdr { 1165 __le32 info0; 1166} __packed; 1167 1168#define HAL_REO_GET_QUEUE_STATS_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 1169#define HAL_REO_GET_QUEUE_STATS_INFO0_CLEAR_STATS BIT(8) 1170 1171struct hal_reo_get_queue_stats { 1172 struct hal_reo_cmd_hdr cmd; 1173 __le32 queue_addr_lo; 1174 __le32 info0; 1175 __le32 rsvd0[6]; 1176 __le32 tlv64_pad; 1177} __packed; 1178 1179/* hal_reo_get_queue_stats 1180 * Producer: SW 1181 * Consumer: REO 1182 * 1183 * cmd 1184 * Details for command execution tracking purposes. 1185 * 1186 * queue_addr_lo 1187 * Address (lower 32 bits) of the REO queue descriptor. 1188 * 1189 * queue_addr_hi 1190 * Address (upper 8 bits) of the REO queue descriptor. 1191 * 1192 * clear_stats 1193 * Clear stats settings. When set, Clear the stats after 1194 * generating the status. 1195 * 1196 * Following stats will be cleared. 1197 * Timeout_count 1198 * Forward_due_to_bar_count 1199 * Duplicate_count 1200 * Frames_in_order_count 1201 * BAR_received_count 1202 * MPDU_Frames_processed_count 1203 * MSDU_Frames_processed_count 1204 * Total_processed_byte_count 1205 * Late_receive_MPDU_count 1206 * window_jump_2k 1207 * Hole_count 1208 */ 1209 1210#define HAL_REO_FLUSH_QUEUE_INFO0_DESC_ADDR_HI GENMASK(7, 0) 1211#define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_DESC_ADDR BIT(8) 1212#define HAL_REO_FLUSH_QUEUE_INFO0_BLOCK_RESRC_IDX GENMASK(10, 9) 1213 1214struct hal_reo_flush_queue { 1215 struct hal_reo_cmd_hdr cmd; 1216 __le32 desc_addr_lo; 1217 __le32 info0; 1218 __le32 rsvd0[6]; 1219} __packed; 1220 1221#define HAL_REO_FLUSH_CACHE_INFO0_CACHE_ADDR_HI GENMASK(7, 0) 1222#define HAL_REO_FLUSH_CACHE_INFO0_FWD_ALL_MPDUS BIT(8) 1223#define HAL_REO_FLUSH_CACHE_INFO0_RELEASE_BLOCK_IDX BIT(9) 1224#define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_RESRC_IDX GENMASK(11, 10) 1225#define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_WO_INVALIDATE BIT(12) 1226#define HAL_REO_FLUSH_CACHE_INFO0_BLOCK_CACHE_USAGE BIT(13) 1227#define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_ALL BIT(14) 1228#define HAL_REO_FLUSH_CACHE_INFO0_FLUSH_QUEUE_1K_DESC BIT(15) 1229 1230struct hal_reo_flush_cache { 1231 struct hal_reo_cmd_hdr cmd; 1232 __le32 cache_addr_lo; 1233 __le32 info0; 1234 __le32 rsvd0[6]; 1235} __packed; 1236 1237#define HAL_TCL_DATA_CMD_INFO0_CMD_TYPE BIT(0) 1238#define HAL_TCL_DATA_CMD_INFO0_DESC_TYPE BIT(1) 1239#define HAL_TCL_DATA_CMD_INFO0_BANK_ID GENMASK(7, 2) 1240#define HAL_TCL_DATA_CMD_INFO0_TX_NOTIFY_FRAME GENMASK(10, 8) 1241#define HAL_TCL_DATA_CMD_INFO0_HDR_LEN_READ_SEL BIT(11) 1242#define HAL_TCL_DATA_CMD_INFO0_BUF_TIMESTAMP GENMASK(30, 12) 1243#define HAL_TCL_DATA_CMD_INFO0_BUF_TIMESTAMP_VLD BIT(31) 1244 1245#define HAL_TCL_DATA_CMD_INFO1_CMD_NUM GENMASK(31, 16) 1246 1247#define HAL_TCL_DATA_CMD_INFO2_DATA_LEN GENMASK(15, 0) 1248#define HAL_TCL_DATA_CMD_INFO2_IP4_CKSUM_EN BIT(16) 1249#define HAL_TCL_DATA_CMD_INFO2_UDP4_CKSUM_EN BIT(17) 1250#define HAL_TCL_DATA_CMD_INFO2_UDP6_CKSUM_EN BIT(18) 1251#define HAL_TCL_DATA_CMD_INFO2_TCP4_CKSUM_EN BIT(19) 1252#define HAL_TCL_DATA_CMD_INFO2_TCP6_CKSUM_EN BIT(20) 1253#define HAL_TCL_DATA_CMD_INFO2_TO_FW BIT(21) 1254#define HAL_TCL_DATA_CMD_INFO2_PKT_OFFSET GENMASK(31, 23) 1255 1256#define HAL_TCL_DATA_CMD_INFO3_TID_OVERWRITE BIT(0) 1257#define HAL_TCL_DATA_CMD_INFO3_FLOW_OVERRIDE_EN BIT(1) 1258#define HAL_TCL_DATA_CMD_INFO3_CLASSIFY_INFO_SEL GENMASK(3, 2) 1259#define HAL_TCL_DATA_CMD_INFO3_TID GENMASK(7, 4) 1260#define HAL_TCL_DATA_CMD_INFO3_FLOW_OVERRIDE BIT(8) 1261#define HAL_TCL_DATA_CMD_INFO3_PMAC_ID GENMASK(10, 9) 1262#define HAL_TCL_DATA_CMD_INFO3_MSDU_COLOR GENMASK(12, 11) 1263#define HAL_TCL_DATA_CMD_INFO3_VDEV_ID GENMASK(31, 24) 1264 1265#define HAL_TCL_DATA_CMD_INFO4_SEARCH_INDEX GENMASK(19, 0) 1266#define HAL_TCL_DATA_CMD_INFO4_CACHE_SET_NUM GENMASK(23, 20) 1267#define HAL_TCL_DATA_CMD_INFO4_IDX_LOOKUP_OVERRIDE BIT(24) 1268 1269#define HAL_TCL_DATA_CMD_INFO5_RING_ID GENMASK(27, 20) 1270#define HAL_TCL_DATA_CMD_INFO5_LOOPING_COUNT GENMASK(31, 28) 1271 1272enum hal_encrypt_type { 1273 HAL_ENCRYPT_TYPE_WEP_40, 1274 HAL_ENCRYPT_TYPE_WEP_104, 1275 HAL_ENCRYPT_TYPE_TKIP_NO_MIC, 1276 HAL_ENCRYPT_TYPE_WEP_128, 1277 HAL_ENCRYPT_TYPE_TKIP_MIC, 1278 HAL_ENCRYPT_TYPE_WAPI, 1279 HAL_ENCRYPT_TYPE_CCMP_128, 1280 HAL_ENCRYPT_TYPE_OPEN, 1281 HAL_ENCRYPT_TYPE_CCMP_256, 1282 HAL_ENCRYPT_TYPE_GCMP_128, 1283 HAL_ENCRYPT_TYPE_AES_GCMP_256, 1284 HAL_ENCRYPT_TYPE_WAPI_GCM_SM4, 1285}; 1286 1287enum hal_tcl_encap_type { 1288 HAL_TCL_ENCAP_TYPE_RAW, 1289 HAL_TCL_ENCAP_TYPE_NATIVE_WIFI, 1290 HAL_TCL_ENCAP_TYPE_ETHERNET, 1291 HAL_TCL_ENCAP_TYPE_802_3 = 3, 1292 HAL_TCL_ENCAP_TYPE_MAX 1293}; 1294 1295enum hal_tcl_desc_type { 1296 HAL_TCL_DESC_TYPE_BUFFER, 1297 HAL_TCL_DESC_TYPE_EXT_DESC, 1298 HAL_TCL_DESC_TYPE_MAX, 1299}; 1300 1301enum hal_wbm_htt_tx_comp_status { 1302 HAL_WBM_REL_HTT_TX_COMP_STATUS_OK, 1303 HAL_WBM_REL_HTT_TX_COMP_STATUS_DROP, 1304 HAL_WBM_REL_HTT_TX_COMP_STATUS_TTL, 1305 HAL_WBM_REL_HTT_TX_COMP_STATUS_REINJ, 1306 HAL_WBM_REL_HTT_TX_COMP_STATUS_INSPECT, 1307 HAL_WBM_REL_HTT_TX_COMP_STATUS_MEC_NOTIFY, 1308 HAL_WBM_REL_HTT_TX_COMP_STATUS_VDEVID_MISMATCH, 1309 HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX, 1310}; 1311 1312struct hal_tcl_data_cmd { 1313 struct ath12k_buffer_addr buf_addr_info; 1314 __le32 info0; 1315 __le32 info1; 1316 __le32 info2; 1317 __le32 info3; 1318 __le32 info4; 1319 __le32 info5; 1320} __packed; 1321 1322/* hal_tcl_data_cmd 1323 * 1324 * buf_addr_info 1325 * Details of the physical address of a buffer or MSDU 1326 * link descriptor. 1327 * 1328 * tcl_cmd_type 1329 * used to select the type of TCL Command descriptor 1330 * 1331 * desc_type 1332 * Indicates the type of address provided in the buf_addr_info. 1333 * Values are defined in enum %HAL_REO_DEST_RING_BUFFER_TYPE_. 1334 * 1335 * bank_id 1336 * used to select one of the TCL register banks for fields removed 1337 * from 'TCL_DATA_CMD' that do not change often within one virtual 1338 * device or a set of virtual devices: 1339 * 1340 * tx_notify_frame 1341 * TCL copies this value to 'TQM_ENTRANCE_RING' field FW_tx_notify_frame. 1342 * 1343 * hdr_length_read_sel 1344 * used to select the per 'encap_type' register set for MSDU header 1345 * read length 1346 * 1347 * buffer_timestamp 1348 * buffer_timestamp_valid 1349 * Frame system entrance timestamp. It shall be filled by first 1350 * module (SW, TCL or TQM) that sees the frames first. 1351 * 1352 * cmd_num 1353 * This number can be used to match against status. 1354 * 1355 * data_length 1356 * MSDU length in case of direct descriptor. Length of link 1357 * extension descriptor in case of Link extension descriptor. 1358 * 1359 * *_checksum_en 1360 * Enable checksum replacement for ipv4, udp_over_ipv4, ipv6, 1361 * udp_over_ipv6, tcp_over_ipv4 and tcp_over_ipv6. 1362 * 1363 * to_fw 1364 * Forward packet to FW along with classification result. The 1365 * packet will not be forward to TQM when this bit is set. 1366 * 1'b0: Use classification result to forward the packet. 1367 * 1'b1: Override classification result & forward packet only to fw 1368 * 1369 * packet_offset 1370 * Packet offset from Metadata in case of direct buffer descriptor. 1371 * 1372 * hlos_tid_overwrite 1373 * 1374 * When set, TCL shall ignore the IP DSCP and VLAN PCP 1375 * fields and use HLOS_TID as the final TID. Otherwise TCL 1376 * shall consider the DSCP and PCP fields as well as HLOS_TID 1377 * and choose a final TID based on the configured priority 1378 * 1379 * flow_override_enable 1380 * TCL uses this to select the flow pointer from the peer table, 1381 * which can be overridden by SW for pre-encrypted raw WiFi packets 1382 * that cannot be parsed for UDP or for other MLO 1383 * 0 - FP_PARSE_IP: Use the flow-pointer based on parsing the IPv4 1384 * or IPv6 header. 1385 * 1 - FP_USE_OVERRIDE: Use the who_classify_info_sel and 1386 * flow_override fields to select the flow-pointer 1387 * 1388 * who_classify_info_sel 1389 * Field only valid when flow_override_enable is set to FP_USE_OVERRIDE. 1390 * This field is used to select one of the 'WHO_CLASSIFY_INFO's in the 1391 * peer table in case more than 2 flows are mapped to a single TID. 1392 * 0: To choose Flow 0 and 1 of any TID use this value. 1393 * 1: To choose Flow 2 and 3 of any TID use this value. 1394 * 2: To choose Flow 4 and 5 of any TID use this value. 1395 * 3: To choose Flow 6 and 7 of any TID use this value. 1396 * 1397 * If who_classify_info sel is not in sync with the num_tx_classify_info 1398 * field from address search, then TCL will set 'who_classify_info_sel' 1399 * to 0 use flows 0 and 1. 1400 * 1401 * hlos_tid 1402 * HLOS MSDU priority 1403 * Field is used when HLOS_TID_overwrite is set. 1404 * 1405 * flow_override 1406 * Field only valid when flow_override_enable is set to FP_USE_OVERRIDE 1407 * TCL uses this to select the flow pointer from the peer table, 1408 * which can be overridden by SW for pre-encrypted raw WiFi packets 1409 * that cannot be parsed for UDP or for other MLO 1410 * 0 - FP_USE_NON_UDP: Use the non-UDP flow pointer (flow 0) 1411 * 1 - FP_USE_UDP: Use the UDP flow pointer (flow 1) 1412 * 1413 * pmac_id 1414 * TCL uses this PMAC_ID in address search, i.e, while 1415 * finding matching entry for the packet in AST corresponding 1416 * to given PMAC_ID 1417 * 1418 * If PMAC ID is all 1s (=> value 3), it indicates wildcard 1419 * match for any PMAC 1420 * 1421 * vdev_id 1422 * Virtual device ID to check against the address search entry to 1423 * avoid security issues from transmitting packets from an incorrect 1424 * virtual device 1425 * 1426 * search_index 1427 * The index that will be used for index based address or 1428 * flow search. The field is valid when 'search_type' is 1 or 2. 1429 * 1430 * cache_set_num 1431 * 1432 * Cache set number that should be used to cache the index 1433 * based search results, for address and flow search. This 1434 * value should be equal to LSB four bits of the hash value of 1435 * match data, in case of search index points to an entry which 1436 * may be used in content based search also. The value can be 1437 * anything when the entry pointed by search index will not be 1438 * used for content based search. 1439 * 1440 * index_loop_override 1441 * When set, address search and packet routing is forced to use 1442 * 'search_index' instead of following the register configuration 1443 * selected by Bank_id. 1444 * 1445 * ring_id 1446 * The buffer pointer ring ID. 1447 * 0 refers to the IDLE ring 1448 * 1 - N refers to other rings 1449 * 1450 * looping_count 1451 * 1452 * A count value that indicates the number of times the 1453 * producer of entries into the Ring has looped around the 1454 * ring. 1455 * 1456 * At initialization time, this value is set to 0. On the 1457 * first loop, this value is set to 1. After the max value is 1458 * reached allowed by the number of bits for this field, the 1459 * count value continues with 0 again. 1460 * 1461 * In case SW is the consumer of the ring entries, it can 1462 * use this field to figure out up to where the producer of 1463 * entries has created new entries. This eliminates the need to 1464 * check where the head pointer' of the ring is located once 1465 * the SW starts processing an interrupt indicating that new 1466 * entries have been put into this ring... 1467 * 1468 * Also note that SW if it wants only needs to look at the 1469 * LSB bit of this count value. 1470 */ 1471 1472#define HAL_TCL_DESC_LEN sizeof(struct hal_tcl_data_cmd) 1473 1474#define HAL_TX_MSDU_EXT_INFO0_BUF_PTR_LO GENMASK(31, 0) 1475 1476#define HAL_TX_MSDU_EXT_INFO1_BUF_PTR_HI GENMASK(7, 0) 1477#define HAL_TX_MSDU_EXT_INFO1_EXTN_OVERRIDE BIT(8) 1478#define HAL_TX_MSDU_EXT_INFO1_ENCAP_TYPE GENMASK(10, 9) 1479#define HAL_TX_MSDU_EXT_INFO1_ENCRYPT_TYPE GENMASK(14, 11) 1480#define HAL_TX_MSDU_EXT_INFO1_BUF_LEN GENMASK(31, 16) 1481 1482struct hal_tx_msdu_ext_desc { 1483 __le32 rsvd0[6]; 1484 __le32 info0; 1485 __le32 info1; 1486 __le32 rsvd1[10]; 1487}; 1488 1489struct hal_tcl_gse_cmd { 1490 __le32 ctrl_buf_addr_lo; 1491 __le32 info0; 1492 __le32 meta_data[2]; 1493 __le32 rsvd0[2]; 1494 __le32 info1; 1495} __packed; 1496 1497/* hal_tcl_gse_cmd 1498 * 1499 * ctrl_buf_addr_lo, ctrl_buf_addr_hi 1500 * Address of a control buffer containing additional info needed 1501 * for this command execution. 1502 * 1503 * meta_data 1504 * Meta data to be returned in the status descriptor 1505 */ 1506 1507enum hal_tcl_cache_op_res { 1508 HAL_TCL_CACHE_OP_RES_DONE, 1509 HAL_TCL_CACHE_OP_RES_NOT_FOUND, 1510 HAL_TCL_CACHE_OP_RES_TIMEOUT, 1511}; 1512 1513struct hal_tcl_status_ring { 1514 __le32 info0; 1515 __le32 msdu_byte_count; 1516 __le32 msdu_timestamp; 1517 __le32 meta_data[2]; 1518 __le32 info1; 1519 __le32 rsvd0; 1520 __le32 info2; 1521} __packed; 1522 1523/* hal_tcl_status_ring 1524 * 1525 * msdu_cnt 1526 * msdu_byte_count 1527 * MSDU count of Entry and MSDU byte count for entry 1. 1528 * 1529 */ 1530 1531#define HAL_CE_SRC_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0) 1532#define HAL_CE_SRC_DESC_ADDR_INFO_HASH_EN BIT(8) 1533#define HAL_CE_SRC_DESC_ADDR_INFO_BYTE_SWAP BIT(9) 1534#define HAL_CE_SRC_DESC_ADDR_INFO_DEST_SWAP BIT(10) 1535#define HAL_CE_SRC_DESC_ADDR_INFO_GATHER BIT(11) 1536#define HAL_CE_SRC_DESC_ADDR_INFO_LEN GENMASK(31, 16) 1537 1538#define HAL_CE_SRC_DESC_META_INFO_DATA GENMASK(15, 0) 1539 1540#define HAL_CE_SRC_DESC_FLAGS_RING_ID GENMASK(27, 20) 1541#define HAL_CE_SRC_DESC_FLAGS_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT 1542 1543struct hal_ce_srng_src_desc { 1544 __le32 buffer_addr_low; 1545 __le32 buffer_addr_info; /* %HAL_CE_SRC_DESC_ADDR_INFO_ */ 1546 __le32 meta_info; /* %HAL_CE_SRC_DESC_META_INFO_ */ 1547 __le32 flags; /* %HAL_CE_SRC_DESC_FLAGS_ */ 1548} __packed; 1549 1550/* hal_ce_srng_src_desc 1551 * 1552 * buffer_addr_lo 1553 * LSB 32 bits of the 40 Bit Pointer to the source buffer 1554 * 1555 * buffer_addr_hi 1556 * MSB 8 bits of the 40 Bit Pointer to the source buffer 1557 * 1558 * toeplitz_en 1559 * Enable generation of 32-bit Toeplitz-LFSR hash for 1560 * data transfer. In case of gather field in first source 1561 * ring entry of the gather copy cycle in taken into account. 1562 * 1563 * src_swap 1564 * Treats source memory organization as big-endian. For 1565 * each dword read (4 bytes), the byte 0 is swapped with byte 3 1566 * and byte 1 is swapped with byte 2. 1567 * In case of gather field in first source ring entry of 1568 * the gather copy cycle in taken into account. 1569 * 1570 * dest_swap 1571 * Treats destination memory organization as big-endian. 1572 * For each dword write (4 bytes), the byte 0 is swapped with 1573 * byte 3 and byte 1 is swapped with byte 2. 1574 * In case of gather field in first source ring entry of 1575 * the gather copy cycle in taken into account. 1576 * 1577 * gather 1578 * Enables gather of multiple copy engine source 1579 * descriptors to one destination. 1580 * 1581 * ce_res_0 1582 * Reserved 1583 * 1584 * 1585 * length 1586 * Length of the buffer in units of octets of the current 1587 * descriptor 1588 * 1589 * fw_metadata 1590 * Meta data used by FW. 1591 * In case of gather field in first source ring entry of 1592 * the gather copy cycle in taken into account. 1593 * 1594 * ce_res_1 1595 * Reserved 1596 * 1597 * ce_res_2 1598 * Reserved 1599 * 1600 * ring_id 1601 * The buffer pointer ring ID. 1602 * 0 refers to the IDLE ring 1603 * 1 - N refers to other rings 1604 * Helps with debugging when dumping ring contents. 1605 * 1606 * looping_count 1607 * A count value that indicates the number of times the 1608 * producer of entries into the Ring has looped around the 1609 * ring. 1610 * 1611 * At initialization time, this value is set to 0. On the 1612 * first loop, this value is set to 1. After the max value is 1613 * reached allowed by the number of bits for this field, the 1614 * count value continues with 0 again. 1615 * 1616 * In case SW is the consumer of the ring entries, it can 1617 * use this field to figure out up to where the producer of 1618 * entries has created new entries. This eliminates the need to 1619 * check where the head pointer' of the ring is located once 1620 * the SW starts processing an interrupt indicating that new 1621 * entries have been put into this ring... 1622 * 1623 * Also note that SW if it wants only needs to look at the 1624 * LSB bit of this count value. 1625 */ 1626 1627#define HAL_CE_DEST_DESC_ADDR_INFO_ADDR_HI GENMASK(7, 0) 1628#define HAL_CE_DEST_DESC_ADDR_INFO_RING_ID GENMASK(27, 20) 1629#define HAL_CE_DEST_DESC_ADDR_INFO_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT 1630 1631struct hal_ce_srng_dest_desc { 1632 __le32 buffer_addr_low; 1633 __le32 buffer_addr_info; /* %HAL_CE_DEST_DESC_ADDR_INFO_ */ 1634} __packed; 1635 1636/* hal_ce_srng_dest_desc 1637 * 1638 * dst_buffer_low 1639 * LSB 32 bits of the 40 Bit Pointer to the Destination 1640 * buffer 1641 * 1642 * dst_buffer_high 1643 * MSB 8 bits of the 40 Bit Pointer to the Destination 1644 * buffer 1645 * 1646 * ce_res_4 1647 * Reserved 1648 * 1649 * ring_id 1650 * The buffer pointer ring ID. 1651 * 0 refers to the IDLE ring 1652 * 1 - N refers to other rings 1653 * Helps with debugging when dumping ring contents. 1654 * 1655 * looping_count 1656 * A count value that indicates the number of times the 1657 * producer of entries into the Ring has looped around the 1658 * ring. 1659 * 1660 * At initialization time, this value is set to 0. On the 1661 * first loop, this value is set to 1. After the max value is 1662 * reached allowed by the number of bits for this field, the 1663 * count value continues with 0 again. 1664 * 1665 * In case SW is the consumer of the ring entries, it can 1666 * use this field to figure out up to where the producer of 1667 * entries has created new entries. This eliminates the need to 1668 * check where the head pointer' of the ring is located once 1669 * the SW starts processing an interrupt indicating that new 1670 * entries have been put into this ring... 1671 * 1672 * Also note that SW if it wants only needs to look at the 1673 * LSB bit of this count value. 1674 */ 1675 1676#define HAL_CE_DST_STATUS_DESC_FLAGS_HASH_EN BIT(8) 1677#define HAL_CE_DST_STATUS_DESC_FLAGS_BYTE_SWAP BIT(9) 1678#define HAL_CE_DST_STATUS_DESC_FLAGS_DEST_SWAP BIT(10) 1679#define HAL_CE_DST_STATUS_DESC_FLAGS_GATHER BIT(11) 1680#define HAL_CE_DST_STATUS_DESC_FLAGS_LEN GENMASK(31, 16) 1681 1682#define HAL_CE_DST_STATUS_DESC_META_INFO_DATA GENMASK(15, 0) 1683#define HAL_CE_DST_STATUS_DESC_META_INFO_RING_ID GENMASK(27, 20) 1684#define HAL_CE_DST_STATUS_DESC_META_INFO_LOOP_CNT HAL_SRNG_DESC_LOOP_CNT 1685 1686struct hal_ce_srng_dst_status_desc { 1687 __le32 flags; /* %HAL_CE_DST_STATUS_DESC_FLAGS_ */ 1688 __le32 toeplitz_hash0; 1689 __le32 toeplitz_hash1; 1690 __le32 meta_info; /* HAL_CE_DST_STATUS_DESC_META_INFO_ */ 1691} __packed; 1692 1693/* hal_ce_srng_dst_status_desc 1694 * 1695 * ce_res_5 1696 * Reserved 1697 * 1698 * toeplitz_en 1699 * 1700 * src_swap 1701 * Source memory buffer swapped 1702 * 1703 * dest_swap 1704 * Destination memory buffer swapped 1705 * 1706 * gather 1707 * Gather of multiple copy engine source descriptors to one 1708 * destination enabled 1709 * 1710 * ce_res_6 1711 * Reserved 1712 * 1713 * length 1714 * Sum of all the Lengths of the source descriptor in the 1715 * gather chain 1716 * 1717 * toeplitz_hash_0 1718 * 32 LS bits of 64 bit Toeplitz LFSR hash result 1719 * 1720 * toeplitz_hash_1 1721 * 32 MS bits of 64 bit Toeplitz LFSR hash result 1722 * 1723 * fw_metadata 1724 * Meta data used by FW 1725 * In case of gather field in first source ring entry of 1726 * the gather copy cycle in taken into account. 1727 * 1728 * ce_res_7 1729 * Reserved 1730 * 1731 * ring_id 1732 * The buffer pointer ring ID. 1733 * 0 refers to the IDLE ring 1734 * 1 - N refers to other rings 1735 * Helps with debugging when dumping ring contents. 1736 * 1737 * looping_count 1738 * A count value that indicates the number of times the 1739 * producer of entries into the Ring has looped around the 1740 * ring. 1741 * 1742 * At initialization time, this value is set to 0. On the 1743 * first loop, this value is set to 1. After the max value is 1744 * reached allowed by the number of bits for this field, the 1745 * count value continues with 0 again. 1746 * 1747 * In case SW is the consumer of the ring entries, it can 1748 * use this field to figure out up to where the producer of 1749 * entries has created new entries. This eliminates the need to 1750 * check where the head pointer' of the ring is located once 1751 * the SW starts processing an interrupt indicating that new 1752 * entries have been put into this ring... 1753 * 1754 * Also note that SW if it wants only needs to look at the 1755 * LSB bit of this count value. 1756 */ 1757 1758#define HAL_TX_RATE_STATS_INFO0_VALID BIT(0) 1759#define HAL_TX_RATE_STATS_INFO0_BW GENMASK(3, 1) 1760#define HAL_TX_RATE_STATS_INFO0_PKT_TYPE GENMASK(7, 4) 1761#define HAL_TX_RATE_STATS_INFO0_STBC BIT(8) 1762#define HAL_TX_RATE_STATS_INFO0_LDPC BIT(9) 1763#define HAL_TX_RATE_STATS_INFO0_SGI GENMASK(11, 10) 1764#define HAL_TX_RATE_STATS_INFO0_MCS GENMASK(15, 12) 1765#define HAL_TX_RATE_STATS_INFO0_OFDMA_TX BIT(16) 1766#define HAL_TX_RATE_STATS_INFO0_TONES_IN_RU GENMASK(28, 17) 1767 1768enum hal_tx_rate_stats_bw { 1769 HAL_TX_RATE_STATS_BW_20, 1770 HAL_TX_RATE_STATS_BW_40, 1771 HAL_TX_RATE_STATS_BW_80, 1772 HAL_TX_RATE_STATS_BW_160, 1773}; 1774 1775enum hal_tx_rate_stats_pkt_type { 1776 HAL_TX_RATE_STATS_PKT_TYPE_11A, 1777 HAL_TX_RATE_STATS_PKT_TYPE_11B, 1778 HAL_TX_RATE_STATS_PKT_TYPE_11N, 1779 HAL_TX_RATE_STATS_PKT_TYPE_11AC, 1780 HAL_TX_RATE_STATS_PKT_TYPE_11AX, 1781 HAL_TX_RATE_STATS_PKT_TYPE_11BA, 1782 HAL_TX_RATE_STATS_PKT_TYPE_11BE, 1783}; 1784 1785enum hal_tx_rate_stats_sgi { 1786 HAL_TX_RATE_STATS_SGI_08US, 1787 HAL_TX_RATE_STATS_SGI_04US, 1788 HAL_TX_RATE_STATS_SGI_16US, 1789 HAL_TX_RATE_STATS_SGI_32US, 1790}; 1791 1792struct hal_tx_rate_stats { 1793 __le32 info0; 1794 __le32 tsf; 1795} __packed; 1796 1797struct hal_wbm_link_desc { 1798 struct ath12k_buffer_addr buf_addr_info; 1799} __packed; 1800 1801/* hal_wbm_link_desc 1802 * 1803 * Producer: WBM 1804 * Consumer: WBM 1805 * 1806 * buf_addr_info 1807 * Details of the physical address of a buffer or MSDU 1808 * link descriptor. 1809 */ 1810 1811enum hal_wbm_rel_src_module { 1812 HAL_WBM_REL_SRC_MODULE_TQM, 1813 HAL_WBM_REL_SRC_MODULE_RXDMA, 1814 HAL_WBM_REL_SRC_MODULE_REO, 1815 HAL_WBM_REL_SRC_MODULE_FW, 1816 HAL_WBM_REL_SRC_MODULE_SW, 1817 HAL_WBM_REL_SRC_MODULE_MAX, 1818}; 1819 1820enum hal_wbm_rel_desc_type { 1821 HAL_WBM_REL_DESC_TYPE_REL_MSDU, 1822 HAL_WBM_REL_DESC_TYPE_MSDU_LINK, 1823 HAL_WBM_REL_DESC_TYPE_MPDU_LINK, 1824 HAL_WBM_REL_DESC_TYPE_MSDU_EXT, 1825 HAL_WBM_REL_DESC_TYPE_QUEUE_EXT, 1826}; 1827 1828/* hal_wbm_rel_desc_type 1829 * 1830 * msdu_buffer 1831 * The address points to an MSDU buffer 1832 * 1833 * msdu_link_descriptor 1834 * The address points to an Tx MSDU link descriptor 1835 * 1836 * mpdu_link_descriptor 1837 * The address points to an MPDU link descriptor 1838 * 1839 * msdu_ext_descriptor 1840 * The address points to an MSDU extension descriptor 1841 * 1842 * queue_ext_descriptor 1843 * The address points to an TQM queue extension descriptor. WBM should 1844 * treat this is the same way as a link descriptor. 1845 */ 1846 1847enum hal_wbm_rel_bm_act { 1848 HAL_WBM_REL_BM_ACT_PUT_IN_IDLE, 1849 HAL_WBM_REL_BM_ACT_REL_MSDU, 1850}; 1851 1852/* hal_wbm_rel_bm_act 1853 * 1854 * put_in_idle_list 1855 * Put the buffer or descriptor back in the idle list. In case of MSDU or 1856 * MDPU link descriptor, BM does not need to check to release any 1857 * individual MSDU buffers. 1858 * 1859 * release_msdu_list 1860 * This BM action can only be used in combination with desc_type being 1861 * msdu_link_descriptor. Field first_msdu_index points out which MSDU 1862 * pointer in the MSDU link descriptor is the first of an MPDU that is 1863 * released. BM shall release all the MSDU buffers linked to this first 1864 * MSDU buffer pointer. All related MSDU buffer pointer entries shall be 1865 * set to value 0, which represents the 'NULL' pointer. When all MSDU 1866 * buffer pointers in the MSDU link descriptor are 'NULL', the MSDU link 1867 * descriptor itself shall also be released. 1868 */ 1869#define HAL_WBM_COMPL_RX_INFO0_REL_SRC_MODULE GENMASK(2, 0) 1870#define HAL_WBM_COMPL_RX_INFO0_BM_ACTION GENMASK(5, 3) 1871#define HAL_WBM_COMPL_RX_INFO0_DESC_TYPE GENMASK(8, 6) 1872#define HAL_WBM_COMPL_RX_INFO0_RBM GENMASK(12, 9) 1873#define HAL_WBM_COMPL_RX_INFO0_RXDMA_PUSH_REASON GENMASK(18, 17) 1874#define HAL_WBM_COMPL_RX_INFO0_RXDMA_ERROR_CODE GENMASK(23, 19) 1875#define HAL_WBM_COMPL_RX_INFO0_REO_PUSH_REASON GENMASK(25, 24) 1876#define HAL_WBM_COMPL_RX_INFO0_REO_ERROR_CODE GENMASK(30, 26) 1877#define HAL_WBM_COMPL_RX_INFO0_WBM_INTERNAL_ERROR BIT(31) 1878 1879#define HAL_WBM_COMPL_RX_INFO1_PHY_ADDR_HI GENMASK(7, 0) 1880#define HAL_WBM_COMPL_RX_INFO1_SW_COOKIE GENMASK(27, 8) 1881#define HAL_WBM_COMPL_RX_INFO1_LOOPING_COUNT GENMASK(31, 28) 1882 1883struct hal_wbm_completion_ring_rx { 1884 __le32 addr_lo; 1885 __le32 addr_hi; 1886 __le32 info0; 1887 struct rx_mpdu_desc rx_mpdu_info; 1888 struct rx_msdu_desc rx_msdu_info; 1889 __le32 phy_addr_lo; 1890 __le32 info1; 1891} __packed; 1892 1893#define HAL_WBM_COMPL_TX_INFO0_REL_SRC_MODULE GENMASK(2, 0) 1894#define HAL_WBM_COMPL_TX_INFO0_DESC_TYPE GENMASK(8, 6) 1895#define HAL_WBM_COMPL_TX_INFO0_RBM GENMASK(12, 9) 1896#define HAL_WBM_COMPL_TX_INFO0_TQM_RELEASE_REASON GENMASK(16, 13) 1897#define HAL_WBM_COMPL_TX_INFO0_RBM_OVERRIDE_VLD BIT(17) 1898#define HAL_WBM_COMPL_TX_INFO0_SW_COOKIE_LO GENMASK(29, 18) 1899#define HAL_WBM_COMPL_TX_INFO0_CC_DONE BIT(30) 1900#define HAL_WBM_COMPL_TX_INFO0_WBM_INTERNAL_ERROR BIT(31) 1901 1902#define HAL_WBM_COMPL_TX_INFO1_TQM_STATUS_NUMBER GENMASK(23, 0) 1903#define HAL_WBM_COMPL_TX_INFO1_TRANSMIT_COUNT GENMASK(30, 24) 1904#define HAL_WBM_COMPL_TX_INFO1_SW_REL_DETAILS_VALID BIT(31) 1905 1906#define HAL_WBM_COMPL_TX_INFO2_ACK_FRAME_RSSI GENMASK(7, 0) 1907#define HAL_WBM_COMPL_TX_INFO2_FIRST_MSDU BIT(8) 1908#define HAL_WBM_COMPL_TX_INFO2_LAST_MSDU BIT(9) 1909#define HAL_WBM_COMPL_TX_INFO2_FW_TX_NOTIF_FRAME GENMASK(12, 10) 1910#define HAL_WBM_COMPL_TX_INFO2_BUFFER_TIMESTAMP GENMASK(31, 13) 1911 1912#define HAL_WBM_COMPL_TX_INFO3_PEER_ID GENMASK(15, 0) 1913#define HAL_WBM_COMPL_TX_INFO3_TID GENMASK(19, 16) 1914#define HAL_WBM_COMPL_TX_INFO3_SW_COOKIE_HI GENMASK(27, 20) 1915#define HAL_WBM_COMPL_TX_INFO3_LOOPING_COUNT GENMASK(31, 28) 1916 1917struct hal_wbm_completion_ring_tx { 1918 __le32 buf_va_lo; 1919 __le32 buf_va_hi; 1920 __le32 info0; 1921 __le32 info1; 1922 __le32 info2; 1923 struct hal_tx_rate_stats rate_stats; 1924 __le32 info3; 1925} __packed; 1926 1927#define HAL_WBM_RELEASE_TX_INFO0_REL_SRC_MODULE GENMASK(2, 0) 1928#define HAL_WBM_RELEASE_TX_INFO0_BM_ACTION GENMASK(5, 3) 1929#define HAL_WBM_RELEASE_TX_INFO0_DESC_TYPE GENMASK(8, 6) 1930#define HAL_WBM_RELEASE_TX_INFO0_FIRST_MSDU_IDX GENMASK(12, 9) 1931#define HAL_WBM_RELEASE_TX_INFO0_TQM_RELEASE_REASON GENMASK(18, 13) 1932#define HAL_WBM_RELEASE_TX_INFO0_RBM_OVERRIDE_VLD BIT(17) 1933#define HAL_WBM_RELEASE_TX_INFO0_SW_BUFFER_COOKIE_11_0 GENMASK(29, 18) 1934#define HAL_WBM_RELEASE_TX_INFO0_WBM_INTERNAL_ERROR BIT(31) 1935 1936#define HAL_WBM_RELEASE_TX_INFO1_TQM_STATUS_NUMBER GENMASK(23, 0) 1937#define HAL_WBM_RELEASE_TX_INFO1_TRANSMIT_COUNT GENMASK(30, 24) 1938#define HAL_WBM_RELEASE_TX_INFO1_SW_REL_DETAILS_VALID BIT(31) 1939 1940#define HAL_WBM_RELEASE_TX_INFO2_ACK_FRAME_RSSI GENMASK(7, 0) 1941#define HAL_WBM_RELEASE_TX_INFO2_FIRST_MSDU BIT(8) 1942#define HAL_WBM_RELEASE_TX_INFO2_LAST_MSDU BIT(9) 1943#define HAL_WBM_RELEASE_TX_INFO2_FW_TX_NOTIF_FRAME GENMASK(12, 10) 1944#define HAL_WBM_RELEASE_TX_INFO2_BUFFER_TIMESTAMP GENMASK(31, 13) 1945 1946#define HAL_WBM_RELEASE_TX_INFO3_PEER_ID GENMASK(15, 0) 1947#define HAL_WBM_RELEASE_TX_INFO3_TID GENMASK(19, 16) 1948#define HAL_WBM_RELEASE_TX_INFO3_SW_BUFFER_COOKIE_19_12 GENMASK(27, 20) 1949#define HAL_WBM_RELEASE_TX_INFO3_LOOPING_COUNT GENMASK(31, 28) 1950 1951struct hal_wbm_release_ring_tx { 1952 struct ath12k_buffer_addr buf_addr_info; 1953 __le32 info0; 1954 __le32 info1; 1955 __le32 info2; 1956 struct hal_tx_rate_stats rate_stats; 1957 __le32 info3; 1958} __packed; 1959 1960#define HAL_WBM_RELEASE_RX_INFO0_REL_SRC_MODULE GENMASK(2, 0) 1961#define HAL_WBM_RELEASE_RX_INFO0_BM_ACTION GENMASK(5, 3) 1962#define HAL_WBM_RELEASE_RX_INFO0_DESC_TYPE GENMASK(8, 6) 1963#define HAL_WBM_RELEASE_RX_INFO0_FIRST_MSDU_IDX GENMASK(12, 9) 1964#define HAL_WBM_RELEASE_RX_INFO0_CC_STATUS BIT(16) 1965#define HAL_WBM_RELEASE_RX_INFO0_RXDMA_PUSH_REASON GENMASK(18, 17) 1966#define HAL_WBM_RELEASE_RX_INFO0_RXDMA_ERROR_CODE GENMASK(23, 19) 1967#define HAL_WBM_RELEASE_RX_INFO0_REO_PUSH_REASON GENMASK(25, 24) 1968#define HAL_WBM_RELEASE_RX_INFO0_REO_ERROR_CODE GENMASK(30, 26) 1969#define HAL_WBM_RELEASE_RX_INFO0_WBM_INTERNAL_ERROR BIT(31) 1970 1971#define HAL_WBM_RELEASE_RX_INFO2_RING_ID GENMASK(27, 20) 1972#define HAL_WBM_RELEASE_RX_INFO2_LOOPING_COUNT GENMASK(31, 28) 1973 1974struct hal_wbm_release_ring_rx { 1975 struct ath12k_buffer_addr buf_addr_info; 1976 __le32 info0; 1977 struct rx_mpdu_desc rx_mpdu_info; 1978 struct rx_msdu_desc rx_msdu_info; 1979 __le32 info1; 1980 __le32 info2; 1981} __packed; 1982 1983#define HAL_WBM_RELEASE_RX_CC_INFO0_RBM GENMASK(12, 9) 1984#define HAL_WBM_RELEASE_RX_CC_INFO1_COOKIE GENMASK(27, 8) 1985/* Used when hw cc is success */ 1986struct hal_wbm_release_ring_cc_rx { 1987 __le32 buf_va_lo; 1988 __le32 buf_va_hi; 1989 __le32 info0; 1990 struct rx_mpdu_desc rx_mpdu_info; 1991 struct rx_msdu_desc rx_msdu_info; 1992 __le32 buf_pa_lo; 1993 __le32 info1; 1994} __packed; 1995 1996#define HAL_WBM_RELEASE_INFO0_REL_SRC_MODULE GENMASK(2, 0) 1997#define HAL_WBM_RELEASE_INFO0_BM_ACTION GENMASK(5, 3) 1998#define HAL_WBM_RELEASE_INFO0_DESC_TYPE GENMASK(8, 6) 1999#define HAL_WBM_RELEASE_INFO0_RXDMA_PUSH_REASON GENMASK(18, 17) 2000#define HAL_WBM_RELEASE_INFO0_RXDMA_ERROR_CODE GENMASK(23, 19) 2001#define HAL_WBM_RELEASE_INFO0_REO_PUSH_REASON GENMASK(25, 24) 2002#define HAL_WBM_RELEASE_INFO0_REO_ERROR_CODE GENMASK(30, 26) 2003#define HAL_WBM_RELEASE_INFO0_WBM_INTERNAL_ERROR BIT(31) 2004 2005#define HAL_WBM_RELEASE_INFO3_FIRST_MSDU BIT(0) 2006#define HAL_WBM_RELEASE_INFO3_LAST_MSDU BIT(1) 2007#define HAL_WBM_RELEASE_INFO3_CONTINUATION BIT(2) 2008 2009#define HAL_WBM_RELEASE_INFO5_LOOPING_COUNT GENMASK(31, 28) 2010#define HAL_ENCRYPT_TYPE_MAX 12 2011 2012struct hal_wbm_release_ring { 2013 struct ath12k_buffer_addr buf_addr_info; 2014 __le32 info0; 2015 __le32 info1; 2016 __le32 info2; 2017 __le32 info3; 2018 __le32 info4; 2019 __le32 info5; 2020} __packed; 2021 2022/* hal_wbm_release_ring 2023 * 2024 * Producer: SW/TQM/RXDMA/REO/SWITCH 2025 * Consumer: WBM/SW/FW 2026 * 2027 * HTT tx status is overlaid on wbm_release ring on 4-byte words 2, 3, 4 and 5 2028 * for software based completions. 2029 * 2030 * buf_addr_info 2031 * Details of the physical address of the buffer or link descriptor. 2032 * 2033 * release_source_module 2034 * Indicates which module initiated the release of this buffer/descriptor. 2035 * Values are defined in enum %HAL_WBM_REL_SRC_MODULE_. 2036 * 2037 * buffer_or_desc_type 2038 * Field only valid when WBM is marked as the return_buffer_manager in 2039 * the Released_Buffer_address_info. Indicates that type of buffer or 2040 * descriptor is being released. Values are in enum %HAL_WBM_REL_DESC_TYPE. 2041 * 2042 * wbm_internal_error 2043 * Is set when WBM got a buffer pointer but the action was to push it to 2044 * the idle link descriptor ring or do link related activity OR 2045 * Is set when WBM got a link buffer pointer but the action was to push it 2046 * to the buffer descriptor ring. 2047 * 2048 * looping_count 2049 * A count value that indicates the number of times the 2050 * producer of entries into the Buffer Manager Ring has looped 2051 * around the ring. 2052 * 2053 * At initialization time, this value is set to 0. On the 2054 * first loop, this value is set to 1. After the max value is 2055 * reached allowed by the number of bits for this field, the 2056 * count value continues with 0 again. 2057 * 2058 * In case SW is the consumer of the ring entries, it can 2059 * use this field to figure out up to where the producer of 2060 * entries has created new entries. This eliminates the need to 2061 * check where the head pointer' of the ring is located once 2062 * the SW starts processing an interrupt indicating that new 2063 * entries have been put into this ring... 2064 * 2065 * Also note that SW if it wants only needs to look at the 2066 * LSB bit of this count value. 2067 */ 2068 2069/** 2070 * enum hal_wbm_tqm_rel_reason - TQM release reason code 2071 * @HAL_WBM_TQM_REL_REASON_FRAME_ACKED: ACK or BACK received for the frame 2072 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU: Command remove_mpdus initiated by SW 2073 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX: Command remove transmitted_mpdus 2074 * initiated by sw. 2075 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX: Command remove untransmitted_mpdus 2076 * initiated by sw. 2077 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES: Command remove aged msdus or 2078 * mpdus. 2079 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1: Remove command initiated by 2080 * fw with fw_reason1. 2081 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2: Remove command initiated by 2082 * fw with fw_reason2. 2083 * @HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3: Remove command initiated by 2084 * fw with fw_reason3. 2085 * @HAL_WBM_TQM_REL_REASON_CMD_DISABLE_QUEUE: Remove command initiated by 2086 * fw with disable queue. 2087 * @HAL_WBM_TQM_REL_REASON_CMD_TILL_NONMATCHING: Remove command initiated by 2088 * fw to remove all mpdu until 1st non-match. 2089 * @HAL_WBM_TQM_REL_REASON_DROP_THRESHOLD: Dropped due to drop threshold 2090 * criteria 2091 * @HAL_WBM_TQM_REL_REASON_DROP_LINK_DESC_UNAVAIL: Dropped due to link desc 2092 * not available 2093 * @HAL_WBM_TQM_REL_REASON_DROP_OR_INVALID_MSDU: Dropped due drop bit set or 2094 * null flow 2095 * @HAL_WBM_TQM_REL_REASON_MULTICAST_DROP: Dropped due mcast drop set for VDEV 2096 * @HAL_WBM_TQM_REL_REASON_VDEV_MISMATCH_DROP: Dropped due to being set with 2097 * 'TCL_drop_reason' 2098 */ 2099enum hal_wbm_tqm_rel_reason { 2100 HAL_WBM_TQM_REL_REASON_FRAME_ACKED, 2101 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_MPDU, 2102 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_TX, 2103 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_NOTX, 2104 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_AGED_FRAMES, 2105 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON1, 2106 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON2, 2107 HAL_WBM_TQM_REL_REASON_CMD_REMOVE_RESEAON3, 2108 HAL_WBM_TQM_REL_REASON_CMD_DISABLE_QUEUE, 2109 HAL_WBM_TQM_REL_REASON_CMD_TILL_NONMATCHING, 2110 HAL_WBM_TQM_REL_REASON_DROP_THRESHOLD, 2111 HAL_WBM_TQM_REL_REASON_DROP_LINK_DESC_UNAVAIL, 2112 HAL_WBM_TQM_REL_REASON_DROP_OR_INVALID_MSDU, 2113 HAL_WBM_TQM_REL_REASON_MULTICAST_DROP, 2114 HAL_WBM_TQM_REL_REASON_VDEV_MISMATCH_DROP, 2115}; 2116 2117struct hal_wbm_buffer_ring { 2118 struct ath12k_buffer_addr buf_addr_info; 2119}; 2120 2121enum hal_mon_end_reason { 2122 HAL_MON_STATUS_BUFFER_FULL, 2123 HAL_MON_FLUSH_DETECTED, 2124 HAL_MON_END_OF_PPDU, 2125 HAL_MON_PPDU_TRUNCATED, 2126}; 2127 2128#define HAL_SW_MONITOR_RING_INFO0_RXDMA_PUSH_REASON GENMASK(1, 0) 2129#define HAL_SW_MONITOR_RING_INFO0_RXDMA_ERROR_CODE GENMASK(6, 2) 2130#define HAL_SW_MONITOR_RING_INFO0_MPDU_FRAGMENT_NUMBER GENMASK(10, 7) 2131#define HAL_SW_MONITOR_RING_INFO0_FRAMELESS_BAR BIT(11) 2132#define HAL_SW_MONITOR_RING_INFO0_STATUS_BUF_COUNT GENMASK(15, 12) 2133#define HAL_SW_MONITOR_RING_INFO0_END_OF_PPDU BIT(16) 2134 2135#define HAL_SW_MONITOR_RING_INFO1_PHY_PPDU_ID GENMASK(15, 0) 2136#define HAL_SW_MONITOR_RING_INFO1_RING_ID GENMASK(27, 20) 2137#define HAL_SW_MONITOR_RING_INFO1_LOOPING_COUNT GENMASK(31, 28) 2138 2139struct hal_sw_monitor_ring { 2140 struct ath12k_buffer_addr buf_addr_info; 2141 struct rx_mpdu_desc rx_mpdu_info; 2142 struct ath12k_buffer_addr status_buff_addr_info; 2143 __le32 info0; /* %HAL_SW_MONITOR_RING_INFO0 */ 2144 __le32 info1; /* %HAL_SW_MONITOR_RING_INFO1 */ 2145} __packed; 2146 2147/* hal_sw_monitor_ring 2148 * 2149 * Producer: RXDMA 2150 * Consumer: REO/SW/FW 2151 * buf_addr_info 2152 * Details of the physical address of a buffer or MSDU 2153 * link descriptor. 2154 * 2155 * rx_mpdu_info 2156 * Details related to the MPDU being pushed to SW, valid 2157 * only if end_of_ppdu is set to 0. 2158 * 2159 * status_buff_addr_info 2160 * Details of the physical address of the first status 2161 * buffer used for the PPDU (either the PPDU that included the 2162 * MPDU being pushed to SW if end_of_ppdu = 0, or the PPDU 2163 * whose end is indicated through end_of_ppdu = 1) 2164 * 2165 * rxdma_push_reason 2166 * Indicates why RXDMA pushed the frame to this ring 2167 * 2168 * <enum 0 rxdma_error_detected> RXDMA detected an error an 2169 * pushed this frame to this queue 2170 * 2171 * <enum 1 rxdma_routing_instruction> RXDMA pushed the 2172 * frame to this queue per received routing instructions. No 2173 * error within RXDMA was detected 2174 * 2175 * <enum 2 rxdma_rx_flush> RXDMA received an RX_FLUSH. As a 2176 * result the MSDU link descriptor might not have the 2177 * last_msdu_in_mpdu_flag set, but instead WBM might just see a 2178 * NULL pointer in the MSDU link descriptor. This is to be 2179 * considered a normal condition for this scenario. 2180 * 2181 * rxdma_error_code 2182 * Field only valid when rxdma_push_reason is set to 2183 * 'rxdma_error_detected.' 2184 * 2185 * <enum 0 rxdma_overflow_err>MPDU frame is not complete 2186 * due to a FIFO overflow error in RXPCU. 2187 * 2188 * <enum 1 rxdma_mpdu_length_err>MPDU frame is not complete 2189 * due to receiving incomplete MPDU from the PHY 2190 * 2191 * <enum 3 rxdma_decrypt_err>CRYPTO reported a decryption 2192 * error or CRYPTO received an encrypted frame, but did not get 2193 * a valid corresponding key id in the peer entry. 2194 * 2195 * <enum 4 rxdma_tkip_mic_err>CRYPTO reported a TKIP MIC 2196 * error 2197 * 2198 * <enum 5 rxdma_unecrypted_err>CRYPTO reported an 2199 * unencrypted frame error when encrypted was expected 2200 * 2201 * <enum 6 rxdma_msdu_len_err>RX OLE reported an MSDU 2202 * length error 2203 * 2204 * <enum 7 rxdma_msdu_limit_err>RX OLE reported that max 2205 * number of MSDUs allowed in an MPDU got exceeded 2206 * 2207 * <enum 8 rxdma_wifi_parse_err>RX OLE reported a parsing 2208 * error 2209 * 2210 * <enum 9 rxdma_amsdu_parse_err>RX OLE reported an A-MSDU 2211 * parsing error 2212 * 2213 * <enum 10 rxdma_sa_timeout_err>RX OLE reported a timeout 2214 * during SA search 2215 * 2216 * <enum 11 rxdma_da_timeout_err>RX OLE reported a timeout 2217 * during DA search 2218 * 2219 * <enum 12 rxdma_flow_timeout_err>RX OLE reported a 2220 * timeout during flow search 2221 * 2222 * <enum 13 rxdma_flush_request>RXDMA received a flush 2223 * request 2224 * 2225 * <enum 14 rxdma_amsdu_fragment_err>Rx PCU reported A-MSDU 2226 * present as well as a fragmented MPDU. 2227 * 2228 * mpdu_fragment_number 2229 * Field only valid when Reo_level_mpdu_frame_info. 2230 * Rx_mpdu_desc_info_details.Fragment_flag is set and 2231 * end_of_ppdu is set to 0. 2232 * 2233 * The fragment number from the 802.11 header. 2234 * 2235 * Note that the sequence number is embedded in the field: 2236 * Reo_level_mpdu_frame_info. Rx_mpdu_desc_info_details. 2237 * Mpdu_sequence_number 2238 * 2239 * frameless_bar 2240 * When set, this SW monitor ring struct contains BAR info 2241 * from a multi TID BAR frame. The original multi TID BAR frame 2242 * itself contained all the REO info for the first TID, but all 2243 * the subsequent TID info and their linkage to the REO 2244 * descriptors is passed down as 'frameless' BAR info. 2245 * 2246 * The only fields valid in this descriptor when this bit 2247 * is within the 2248 * 2249 * Reo_level_mpdu_frame_info: 2250 * Within Rx_mpdu_desc_info_details: 2251 * Mpdu_Sequence_number 2252 * BAR_frame 2253 * Peer_meta_data 2254 * All other fields shall be set to 0. 2255 * 2256 * status_buf_count 2257 * A count of status buffers used so far for the PPDU 2258 * (either the PPDU that included the MPDU being pushed to SW 2259 * if end_of_ppdu = 0, or the PPDU whose end is indicated 2260 * through end_of_ppdu = 1) 2261 * 2262 * end_of_ppdu 2263 * Some hw RXDMA can be configured to generate a separate 2264 * 'SW_MONITOR_RING' descriptor at the end of a PPDU (either 2265 * through an 'RX_PPDU_END' TLV or through an 'RX_FLUSH') to 2266 * demarcate PPDUs. 2267 * 2268 * For such a descriptor, this bit is set to 1 and fields 2269 * Reo_level_mpdu_frame_info, mpdu_fragment_number and 2270 * Frameless_bar are all set to 0. 2271 * 2272 * Otherwise this bit is set to 0. 2273 * 2274 * phy_ppdu_id 2275 * A PPDU counter value that PHY increments for every PPDU 2276 * received 2277 * 2278 * The counter value wraps around. Some hw RXDMA can be 2279 * configured to copy this from the RX_PPDU_START TLV for every 2280 * output descriptor. 2281 * 2282 * ring_id 2283 * For debugging. 2284 * This field is filled in by the SRNG module. 2285 * It help to identify the ring that is being looked 2286 * 2287 * looping_count 2288 * For debugging. 2289 * This field is filled in by the SRNG module. 2290 * 2291 * A count value that indicates the number of times the 2292 * producer of entries into this Ring has looped around the 2293 * ring. 2294 * At initialization time, this value is set to 0. On the 2295 * first loop, this value is set to 1. After the max value is 2296 * reached allowed by the number of bits for this field, the 2297 * count value continues with 0 again. 2298 * 2299 * In case SW is the consumer of the ring entries, it can 2300 * use this field to figure out up to where the producer of 2301 * entries has created new entries. This eliminates the need to 2302 * check where the head pointer' of the ring is located once 2303 * the SW starts processing an interrupt indicating that new 2304 * entries have been put into this ring... 2305 */ 2306 2307enum hal_desc_owner { 2308 HAL_DESC_OWNER_WBM, 2309 HAL_DESC_OWNER_SW, 2310 HAL_DESC_OWNER_TQM, 2311 HAL_DESC_OWNER_RXDMA, 2312 HAL_DESC_OWNER_REO, 2313 HAL_DESC_OWNER_SWITCH, 2314}; 2315 2316enum hal_desc_buf_type { 2317 HAL_DESC_BUF_TYPE_TX_MSDU_LINK, 2318 HAL_DESC_BUF_TYPE_TX_MPDU_LINK, 2319 HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_HEAD, 2320 HAL_DESC_BUF_TYPE_TX_MPDU_QUEUE_EXT, 2321 HAL_DESC_BUF_TYPE_TX_FLOW, 2322 HAL_DESC_BUF_TYPE_TX_BUFFER, 2323 HAL_DESC_BUF_TYPE_RX_MSDU_LINK, 2324 HAL_DESC_BUF_TYPE_RX_MPDU_LINK, 2325 HAL_DESC_BUF_TYPE_RX_REO_QUEUE, 2326 HAL_DESC_BUF_TYPE_RX_REO_QUEUE_EXT, 2327 HAL_DESC_BUF_TYPE_RX_BUFFER, 2328 HAL_DESC_BUF_TYPE_IDLE_LINK, 2329}; 2330 2331#define HAL_DESC_REO_OWNED 4 2332#define HAL_DESC_REO_QUEUE_DESC 8 2333#define HAL_DESC_REO_QUEUE_EXT_DESC 9 2334#define HAL_DESC_REO_NON_QOS_TID 16 2335 2336#define HAL_DESC_HDR_INFO0_OWNER GENMASK(3, 0) 2337#define HAL_DESC_HDR_INFO0_BUF_TYPE GENMASK(7, 4) 2338#define HAL_DESC_HDR_INFO0_DBG_RESERVED GENMASK(31, 8) 2339 2340struct hal_desc_header { 2341 __le32 info0; 2342} __packed; 2343 2344struct hal_rx_mpdu_link_ptr { 2345 struct ath12k_buffer_addr addr_info; 2346} __packed; 2347 2348struct hal_rx_msdu_details { 2349 struct ath12k_buffer_addr buf_addr_info; 2350 struct rx_msdu_desc rx_msdu_info; 2351 struct rx_msdu_ext_desc rx_msdu_ext_info; 2352} __packed; 2353 2354#define HAL_RX_MSDU_LNK_INFO0_RX_QUEUE_NUMBER GENMASK(15, 0) 2355#define HAL_RX_MSDU_LNK_INFO0_FIRST_MSDU_LNK BIT(16) 2356 2357struct hal_rx_msdu_link { 2358 struct hal_desc_header desc_hdr; 2359 struct ath12k_buffer_addr buf_addr_info; 2360 __le32 info0; 2361 __le32 pn[4]; 2362 struct hal_rx_msdu_details msdu_link[6]; 2363} __packed; 2364 2365struct hal_rx_reo_queue_ext { 2366 struct hal_desc_header desc_hdr; 2367 __le32 rsvd; 2368 struct hal_rx_mpdu_link_ptr mpdu_link[15]; 2369} __packed; 2370 2371/* hal_rx_reo_queue_ext 2372 * Consumer: REO 2373 * Producer: REO 2374 * 2375 * descriptor_header 2376 * Details about which module owns this struct. 2377 * 2378 * mpdu_link 2379 * Pointer to the next MPDU_link descriptor in the MPDU queue. 2380 */ 2381 2382enum hal_rx_reo_queue_pn_size { 2383 HAL_RX_REO_QUEUE_PN_SIZE_24, 2384 HAL_RX_REO_QUEUE_PN_SIZE_48, 2385 HAL_RX_REO_QUEUE_PN_SIZE_128, 2386}; 2387 2388#define HAL_RX_REO_QUEUE_RX_QUEUE_NUMBER GENMASK(15, 0) 2389 2390#define HAL_RX_REO_QUEUE_INFO0_VLD BIT(0) 2391#define HAL_RX_REO_QUEUE_INFO0_ASSOC_LNK_DESC_COUNTER GENMASK(2, 1) 2392#define HAL_RX_REO_QUEUE_INFO0_DIS_DUP_DETECTION BIT(3) 2393#define HAL_RX_REO_QUEUE_INFO0_SOFT_REORDER_EN BIT(4) 2394#define HAL_RX_REO_QUEUE_INFO0_AC GENMASK(6, 5) 2395#define HAL_RX_REO_QUEUE_INFO0_BAR BIT(7) 2396#define HAL_RX_REO_QUEUE_INFO0_RETRY BIT(8) 2397#define HAL_RX_REO_QUEUE_INFO0_CHECK_2K_MODE BIT(9) 2398#define HAL_RX_REO_QUEUE_INFO0_OOR_MODE BIT(10) 2399#define HAL_RX_REO_QUEUE_INFO0_BA_WINDOW_SIZE GENMASK(20, 11) 2400#define HAL_RX_REO_QUEUE_INFO0_PN_CHECK BIT(21) 2401#define HAL_RX_REO_QUEUE_INFO0_EVEN_PN BIT(22) 2402#define HAL_RX_REO_QUEUE_INFO0_UNEVEN_PN BIT(23) 2403#define HAL_RX_REO_QUEUE_INFO0_PN_HANDLE_ENABLE BIT(24) 2404#define HAL_RX_REO_QUEUE_INFO0_PN_SIZE GENMASK(26, 25) 2405#define HAL_RX_REO_QUEUE_INFO0_IGNORE_AMPDU_FLG BIT(27) 2406 2407#define HAL_RX_REO_QUEUE_INFO1_SVLD BIT(0) 2408#define HAL_RX_REO_QUEUE_INFO1_SSN GENMASK(12, 1) 2409#define HAL_RX_REO_QUEUE_INFO1_CURRENT_IDX GENMASK(22, 13) 2410#define HAL_RX_REO_QUEUE_INFO1_SEQ_2K_ERR BIT(23) 2411#define HAL_RX_REO_QUEUE_INFO1_PN_ERR BIT(24) 2412#define HAL_RX_REO_QUEUE_INFO1_PN_VALID BIT(31) 2413 2414#define HAL_RX_REO_QUEUE_INFO2_MPDU_COUNT GENMASK(6, 0) 2415#define HAL_RX_REO_QUEUE_INFO2_MSDU_COUNT (31, 7) 2416 2417#define HAL_RX_REO_QUEUE_INFO3_TIMEOUT_COUNT GENMASK(9, 4) 2418#define HAL_RX_REO_QUEUE_INFO3_FWD_DUE_TO_BAR_CNT GENMASK(15, 10) 2419#define HAL_RX_REO_QUEUE_INFO3_DUPLICATE_COUNT GENMASK(31, 16) 2420 2421#define HAL_RX_REO_QUEUE_INFO4_FRAME_IN_ORD_COUNT GENMASK(23, 0) 2422#define HAL_RX_REO_QUEUE_INFO4_BAR_RECVD_COUNT GENMASK(31, 24) 2423 2424#define HAL_RX_REO_QUEUE_INFO5_LATE_RX_MPDU_COUNT GENMASK(11, 0) 2425#define HAL_RX_REO_QUEUE_INFO5_WINDOW_JUMP_2K GENMASK(15, 12) 2426#define HAL_RX_REO_QUEUE_INFO5_HOLE_COUNT GENMASK(31, 16) 2427 2428struct hal_rx_reo_queue { 2429 struct hal_desc_header desc_hdr; 2430 __le32 rx_queue_num; 2431 __le32 info0; 2432 __le32 info1; 2433 __le32 pn[4]; 2434 __le32 last_rx_enqueue_timestamp; 2435 __le32 last_rx_dequeue_timestamp; 2436 __le32 next_aging_queue[2]; 2437 __le32 prev_aging_queue[2]; 2438 __le32 rx_bitmap[9]; 2439 __le32 info2; 2440 __le32 info3; 2441 __le32 info4; 2442 __le32 processed_mpdus; 2443 __le32 processed_msdus; 2444 __le32 processed_total_bytes; 2445 __le32 info5; 2446 __le32 rsvd[2]; 2447 struct hal_rx_reo_queue_ext ext_desc[]; 2448} __packed; 2449 2450/* hal_rx_reo_queue 2451 * 2452 * descriptor_header 2453 * Details about which module owns this struct. Note that sub field 2454 * Buffer_type shall be set to receive_reo_queue_descriptor. 2455 * 2456 * receive_queue_number 2457 * Indicates the MPDU queue ID to which this MPDU link descriptor belongs. 2458 * 2459 * vld 2460 * Valid bit indicating a session is established and the queue descriptor 2461 * is valid. 2462 * associated_link_descriptor_counter 2463 * Indicates which of the 3 link descriptor counters shall be incremented 2464 * or decremented when link descriptors are added or removed from this 2465 * flow queue. 2466 * disable_duplicate_detection 2467 * When set, do not perform any duplicate detection. 2468 * soft_reorder_enable 2469 * When set, REO has been instructed to not perform the actual re-ordering 2470 * of frames for this queue, but just to insert the reorder opcodes. 2471 * ac 2472 * Indicates the access category of the queue descriptor. 2473 * bar 2474 * Indicates if BAR has been received. 2475 * retry 2476 * Retry bit is checked if this bit is set. 2477 * chk_2k_mode 2478 * Indicates what type of operation is expected from Reo when the received 2479 * frame SN falls within the 2K window. 2480 * oor_mode 2481 * Indicates what type of operation is expected when the received frame 2482 * falls within the OOR window. 2483 * ba_window_size 2484 * Indicates the negotiated (window size + 1). Max of 256 bits. 2485 * 2486 * A value 255 means 256 bitmap, 63 means 64 bitmap, 0 (means non-BA 2487 * session, with window size of 0). The 3 values here are the main values 2488 * validated, but other values should work as well. 2489 * 2490 * A BA window size of 0 (=> one frame entry bitmat), means that there is 2491 * no additional rx_reo_queue_ext desc. following rx_reo_queue in memory. 2492 * A BA window size of 1 - 105, means that there is 1 rx_reo_queue_ext. 2493 * A BA window size of 106 - 210, means that there are 2 rx_reo_queue_ext. 2494 * A BA window size of 211 - 256, means that there are 3 rx_reo_queue_ext. 2495 * pn_check_needed, pn_shall_be_even, pn_shall_be_uneven, pn_handling_enable, 2496 * pn_size 2497 * REO shall perform the PN increment check, even number check, uneven 2498 * number check, PN error check and size of the PN field check. 2499 * ignore_ampdu_flag 2500 * REO shall ignore the ampdu_flag on entrance descriptor for this queue. 2501 * 2502 * svld 2503 * Sequence number in next field is valid one. 2504 * ssn 2505 * Starting Sequence number of the session. 2506 * current_index 2507 * Points to last forwarded packet 2508 * seq_2k_error_detected_flag 2509 * REO has detected a 2k error jump in the sequence number and from that 2510 * moment forward, all new frames are forwarded directly to FW, without 2511 * duplicate detect, reordering, etc. 2512 * pn_error_detected_flag 2513 * REO has detected a PN error. 2514 */ 2515 2516#define HAL_REO_UPD_RX_QUEUE_INFO0_QUEUE_ADDR_HI GENMASK(7, 0) 2517#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RX_QUEUE_NUM BIT(8) 2518#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_VLD BIT(9) 2519#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_ASSOC_LNK_DESC_CNT BIT(10) 2520#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_DIS_DUP_DETECTION BIT(11) 2521#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SOFT_REORDER_EN BIT(12) 2522#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_AC BIT(13) 2523#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BAR BIT(14) 2524#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_RETRY BIT(15) 2525#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_CHECK_2K_MODE BIT(16) 2526#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_OOR_MODE BIT(17) 2527#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_BA_WINDOW_SIZE BIT(18) 2528#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_CHECK BIT(19) 2529#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_EVEN_PN BIT(20) 2530#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_UNEVEN_PN BIT(21) 2531#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_HANDLE_ENABLE BIT(22) 2532#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_SIZE BIT(23) 2533#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_IGNORE_AMPDU_FLG BIT(24) 2534#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SVLD BIT(25) 2535#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SSN BIT(26) 2536#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_SEQ_2K_ERR BIT(27) 2537#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_ERR BIT(28) 2538#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN_VALID BIT(29) 2539#define HAL_REO_UPD_RX_QUEUE_INFO0_UPD_PN BIT(30) 2540 2541#define HAL_REO_UPD_RX_QUEUE_INFO1_RX_QUEUE_NUMBER GENMASK(15, 0) 2542#define HAL_REO_UPD_RX_QUEUE_INFO1_VLD BIT(16) 2543#define HAL_REO_UPD_RX_QUEUE_INFO1_ASSOC_LNK_DESC_COUNTER GENMASK(18, 17) 2544#define HAL_REO_UPD_RX_QUEUE_INFO1_DIS_DUP_DETECTION BIT(19) 2545#define HAL_REO_UPD_RX_QUEUE_INFO1_SOFT_REORDER_EN BIT(20) 2546#define HAL_REO_UPD_RX_QUEUE_INFO1_AC GENMASK(22, 21) 2547#define HAL_REO_UPD_RX_QUEUE_INFO1_BAR BIT(23) 2548#define HAL_REO_UPD_RX_QUEUE_INFO1_RETRY BIT(24) 2549#define HAL_REO_UPD_RX_QUEUE_INFO1_CHECK_2K_MODE BIT(25) 2550#define HAL_REO_UPD_RX_QUEUE_INFO1_OOR_MODE BIT(26) 2551#define HAL_REO_UPD_RX_QUEUE_INFO1_PN_CHECK BIT(27) 2552#define HAL_REO_UPD_RX_QUEUE_INFO1_EVEN_PN BIT(28) 2553#define HAL_REO_UPD_RX_QUEUE_INFO1_UNEVEN_PN BIT(29) 2554#define HAL_REO_UPD_RX_QUEUE_INFO1_PN_HANDLE_ENABLE BIT(30) 2555#define HAL_REO_UPD_RX_QUEUE_INFO1_IGNORE_AMPDU_FLG BIT(31) 2556 2557#define HAL_REO_UPD_RX_QUEUE_INFO2_BA_WINDOW_SIZE GENMASK(9, 0) 2558#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_SIZE GENMASK(11, 10) 2559#define HAL_REO_UPD_RX_QUEUE_INFO2_SVLD BIT(12) 2560#define HAL_REO_UPD_RX_QUEUE_INFO2_SSN GENMASK(24, 13) 2561#define HAL_REO_UPD_RX_QUEUE_INFO2_SEQ_2K_ERR BIT(25) 2562#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_ERR BIT(26) 2563#define HAL_REO_UPD_RX_QUEUE_INFO2_PN_VALID BIT(27) 2564 2565struct hal_reo_update_rx_queue { 2566 struct hal_reo_cmd_hdr cmd; 2567 __le32 queue_addr_lo; 2568 __le32 info0; 2569 __le32 info1; 2570 __le32 info2; 2571 __le32 pn[4]; 2572} __packed; 2573 2574struct hal_rx_reo_queue_1k { 2575 struct hal_desc_header desc_hdr; 2576 __le32 rx_bitmap_1023_288[23]; 2577 __le32 reserved[8]; 2578} __packed; 2579 2580#define HAL_REO_UNBLOCK_CACHE_INFO0_UNBLK_CACHE BIT(0) 2581#define HAL_REO_UNBLOCK_CACHE_INFO0_RESOURCE_IDX GENMASK(2, 1) 2582 2583struct hal_reo_unblock_cache { 2584 struct hal_reo_cmd_hdr cmd; 2585 __le32 info0; 2586 __le32 rsvd[7]; 2587} __packed; 2588 2589enum hal_reo_exec_status { 2590 HAL_REO_EXEC_STATUS_SUCCESS, 2591 HAL_REO_EXEC_STATUS_BLOCKED, 2592 HAL_REO_EXEC_STATUS_FAILED, 2593 HAL_REO_EXEC_STATUS_RESOURCE_BLOCKED, 2594}; 2595 2596#define HAL_REO_STATUS_HDR_INFO0_STATUS_NUM GENMASK(15, 0) 2597#define HAL_REO_STATUS_HDR_INFO0_EXEC_TIME GENMASK(25, 16) 2598#define HAL_REO_STATUS_HDR_INFO0_EXEC_STATUS GENMASK(27, 26) 2599 2600struct hal_reo_status_hdr { 2601 __le32 info0; 2602 __le32 timestamp; 2603} __packed; 2604 2605/* hal_reo_status_hdr 2606 * Producer: REO 2607 * Consumer: SW 2608 * 2609 * status_num 2610 * The value in this field is equal to value of the reo command 2611 * number. This field helps to correlate the statuses with the REO 2612 * commands. 2613 * 2614 * execution_time (in us) 2615 * The amount of time REO took to execute the command. Note that 2616 * this time does not include the duration of the command waiting 2617 * in the command ring, before the execution started. 2618 * 2619 * execution_status 2620 * Execution status of the command. Values are defined in 2621 * enum %HAL_REO_EXEC_STATUS_. 2622 */ 2623#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_SSN GENMASK(11, 0) 2624#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO0_CUR_IDX GENMASK(21, 12) 2625 2626#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MPDU_COUNT GENMASK(6, 0) 2627#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO1_MSDU_COUNT GENMASK(31, 7) 2628 2629#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_WINDOW_JMP2K GENMASK(3, 0) 2630#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_TIMEOUT_COUNT GENMASK(9, 4) 2631#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_FDTB_COUNT GENMASK(15, 10) 2632#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO2_DUPLICATE_COUNT GENMASK(31, 16) 2633 2634#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_FIO_COUNT GENMASK(23, 0) 2635#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO3_BAR_RCVD_CNT GENMASK(31, 24) 2636 2637#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_LATE_RX_MPDU GENMASK(11, 0) 2638#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO4_HOLE_COUNT GENMASK(27, 12) 2639 2640#define HAL_REO_GET_QUEUE_STATS_STATUS_INFO5_LOOPING_CNT GENMASK(31, 28) 2641 2642struct hal_reo_get_queue_stats_status { 2643 struct hal_reo_status_hdr hdr; 2644 __le32 info0; 2645 __le32 pn[4]; 2646 __le32 last_rx_enqueue_timestamp; 2647 __le32 last_rx_dequeue_timestamp; 2648 __le32 rx_bitmap[9]; 2649 __le32 info1; 2650 __le32 info2; 2651 __le32 info3; 2652 __le32 num_mpdu_frames; 2653 __le32 num_msdu_frames; 2654 __le32 total_bytes; 2655 __le32 info4; 2656 __le32 info5; 2657} __packed; 2658 2659/* hal_reo_get_queue_stats_status 2660 * Producer: REO 2661 * Consumer: SW 2662 * 2663 * status_hdr 2664 * Details that can link this status with the original command. It 2665 * also contains info on how long REO took to execute this command. 2666 * 2667 * ssn 2668 * Starting Sequence number of the session, this changes whenever 2669 * window moves (can be filled by SW then maintained by REO). 2670 * 2671 * current_index 2672 * Points to last forwarded packet. 2673 * 2674 * pn 2675 * Bits of the PN number. 2676 * 2677 * last_rx_enqueue_timestamp 2678 * last_rx_dequeue_timestamp 2679 * Timestamp of arrival of the last MPDU for this queue and 2680 * Timestamp of forwarding an MPDU accordingly. 2681 * 2682 * rx_bitmap 2683 * When a bit is set, the corresponding frame is currently held 2684 * in the re-order queue. The bitmap is Fully managed by HW. 2685 * 2686 * current_mpdu_count 2687 * current_msdu_count 2688 * The number of MPDUs and MSDUs in the queue. 2689 * 2690 * timeout_count 2691 * The number of times REO started forwarding frames even though 2692 * there is a hole in the bitmap. Forwarding reason is timeout. 2693 * 2694 * forward_due_to_bar_count 2695 * The number of times REO started forwarding frames even though 2696 * there is a hole in the bitmap. Fwd reason is reception of BAR. 2697 * 2698 * duplicate_count 2699 * The number of duplicate frames that have been detected. 2700 * 2701 * frames_in_order_count 2702 * The number of frames that have been received in order (without 2703 * a hole that prevented them from being forwarded immediately). 2704 * 2705 * bar_received_count 2706 * The number of times a BAR frame is received. 2707 * 2708 * mpdu_frames_processed_count 2709 * msdu_frames_processed_count 2710 * The total number of MPDU/MSDU frames that have been processed. 2711 * 2712 * total_bytes 2713 * An approximation of the number of bytes received for this queue. 2714 * 2715 * late_receive_mpdu_count 2716 * The number of MPDUs received after the window had already moved 2717 * on. The 'late' sequence window is defined as 2718 * (Window SSN - 256) - (Window SSN - 1). 2719 * 2720 * window_jump_2k 2721 * The number of times the window moved more than 2K 2722 * 2723 * hole_count 2724 * The number of times a hole was created in the receive bitmap. 2725 * 2726 * looping_count 2727 * A count value that indicates the number of times the producer of 2728 * entries into this Ring has looped around the ring. 2729 */ 2730 2731#define HAL_REO_STATUS_LOOP_CNT GENMASK(31, 28) 2732 2733#define HAL_REO_FLUSH_QUEUE_INFO0_ERR_DETECTED BIT(0) 2734#define HAL_REO_FLUSH_QUEUE_INFO0_RSVD GENMASK(31, 1) 2735#define HAL_REO_FLUSH_QUEUE_INFO1_RSVD GENMASK(27, 0) 2736 2737struct hal_reo_flush_queue_status { 2738 struct hal_reo_status_hdr hdr; 2739 __le32 info0; 2740 __le32 rsvd0[21]; 2741 __le32 info1; 2742} __packed; 2743 2744/* hal_reo_flush_queue_status 2745 * Producer: REO 2746 * Consumer: SW 2747 * 2748 * status_hdr 2749 * Details that can link this status with the original command. It 2750 * also contains info on how long REO took to execute this command. 2751 * 2752 * error_detected 2753 * Status of blocking resource 2754 * 2755 * 0 - No error has been detected while executing this command 2756 * 1 - Error detected. The resource to be used for blocking was 2757 * already in use. 2758 * 2759 * looping_count 2760 * A count value that indicates the number of times the producer of 2761 * entries into this Ring has looped around the ring. 2762 */ 2763 2764#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_IS_ERR BIT(0) 2765#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_BLOCK_ERR_CODE GENMASK(2, 1) 2766#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_STATUS_HIT BIT(8) 2767#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_DESC_TYPE GENMASK(11, 9) 2768#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_CLIENT_ID GENMASK(15, 12) 2769#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_ERR GENMASK(17, 16) 2770#define HAL_REO_FLUSH_CACHE_STATUS_INFO0_FLUSH_COUNT GENMASK(25, 18) 2771 2772struct hal_reo_flush_cache_status { 2773 struct hal_reo_status_hdr hdr; 2774 __le32 info0; 2775 __le32 rsvd0[21]; 2776 __le32 info1; 2777} __packed; 2778 2779/* hal_reo_flush_cache_status 2780 * Producer: REO 2781 * Consumer: SW 2782 * 2783 * status_hdr 2784 * Details that can link this status with the original command. It 2785 * also contains info on how long REO took to execute this command. 2786 * 2787 * error_detected 2788 * Status for blocking resource handling 2789 * 2790 * 0 - No error has been detected while executing this command 2791 * 1 - An error in the blocking resource management was detected 2792 * 2793 * block_error_details 2794 * only valid when error_detected is set 2795 * 2796 * 0 - No blocking related errors found 2797 * 1 - Blocking resource is already in use 2798 * 2 - Resource requested to be unblocked, was not blocked 2799 * 2800 * cache_controller_flush_status_hit 2801 * The status that the cache controller returned on executing the 2802 * flush command. 2803 * 2804 * 0 - miss; 1 - hit 2805 * 2806 * cache_controller_flush_status_desc_type 2807 * Flush descriptor type 2808 * 2809 * cache_controller_flush_status_client_id 2810 * Module who made the flush request 2811 * 2812 * In REO, this is always 0 2813 * 2814 * cache_controller_flush_status_error 2815 * Error condition 2816 * 2817 * 0 - No error found 2818 * 1 - HW interface is still busy 2819 * 2 - Line currently locked. Used for one line flush command 2820 * 3 - At least one line is still locked. 2821 * Used for cache flush command. 2822 * 2823 * cache_controller_flush_count 2824 * The number of lines that were actually flushed out 2825 * 2826 * looping_count 2827 * A count value that indicates the number of times the producer of 2828 * entries into this Ring has looped around the ring. 2829 */ 2830 2831#define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_IS_ERR BIT(0) 2832#define HAL_REO_UNBLOCK_CACHE_STATUS_INFO0_TYPE BIT(1) 2833 2834struct hal_reo_unblock_cache_status { 2835 struct hal_reo_status_hdr hdr; 2836 __le32 info0; 2837 __le32 rsvd0[21]; 2838 __le32 info1; 2839} __packed; 2840 2841/* hal_reo_unblock_cache_status 2842 * Producer: REO 2843 * Consumer: SW 2844 * 2845 * status_hdr 2846 * Details that can link this status with the original command. It 2847 * also contains info on how long REO took to execute this command. 2848 * 2849 * error_detected 2850 * 0 - No error has been detected while executing this command 2851 * 1 - The blocking resource was not in use, and therefore it could 2852 * not be unblocked. 2853 * 2854 * unblock_type 2855 * Reference to the type of unblock command 2856 * 0 - Unblock a blocking resource 2857 * 1 - The entire cache usage is unblock 2858 * 2859 * looping_count 2860 * A count value that indicates the number of times the producer of 2861 * entries into this Ring has looped around the ring. 2862 */ 2863 2864#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_IS_ERR BIT(0) 2865#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO0_LIST_EMPTY BIT(1) 2866 2867#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_REL_DESC_COUNT GENMASK(15, 0) 2868#define HAL_REO_FLUSH_TIMEOUT_STATUS_INFO1_FWD_BUF_COUNT GENMASK(31, 16) 2869 2870struct hal_reo_flush_timeout_list_status { 2871 struct hal_reo_status_hdr hdr; 2872 __le32 info0; 2873 __le32 info1; 2874 __le32 rsvd0[20]; 2875 __le32 info2; 2876} __packed; 2877 2878/* hal_reo_flush_timeout_list_status 2879 * Producer: REO 2880 * Consumer: SW 2881 * 2882 * status_hdr 2883 * Details that can link this status with the original command. It 2884 * also contains info on how long REO took to execute this command. 2885 * 2886 * error_detected 2887 * 0 - No error has been detected while executing this command 2888 * 1 - Command not properly executed and returned with error 2889 * 2890 * timeout_list_empty 2891 * When set, REO has depleted the timeout list and all entries are 2892 * gone. 2893 * 2894 * release_desc_count 2895 * Producer: SW; Consumer: REO 2896 * The number of link descriptor released 2897 * 2898 * forward_buf_count 2899 * Producer: SW; Consumer: REO 2900 * The number of buffers forwarded to the REO destination rings 2901 * 2902 * looping_count 2903 * A count value that indicates the number of times the producer of 2904 * entries into this Ring has looped around the ring. 2905 */ 2906 2907#define HAL_REO_DESC_THRESH_STATUS_INFO0_THRESH_INDEX GENMASK(1, 0) 2908#define HAL_REO_DESC_THRESH_STATUS_INFO1_LINK_DESC_COUNTER0 GENMASK(23, 0) 2909#define HAL_REO_DESC_THRESH_STATUS_INFO2_LINK_DESC_COUNTER1 GENMASK(23, 0) 2910#define HAL_REO_DESC_THRESH_STATUS_INFO3_LINK_DESC_COUNTER2 GENMASK(23, 0) 2911#define HAL_REO_DESC_THRESH_STATUS_INFO4_LINK_DESC_COUNTER_SUM GENMASK(25, 0) 2912 2913struct hal_reo_desc_thresh_reached_status { 2914 struct hal_reo_status_hdr hdr; 2915 __le32 info0; 2916 __le32 info1; 2917 __le32 info2; 2918 __le32 info3; 2919 __le32 info4; 2920 __le32 rsvd0[17]; 2921 __le32 info5; 2922} __packed; 2923 2924/* hal_reo_desc_thresh_reached_status 2925 * Producer: REO 2926 * Consumer: SW 2927 * 2928 * status_hdr 2929 * Details that can link this status with the original command. It 2930 * also contains info on how long REO took to execute this command. 2931 * 2932 * threshold_index 2933 * The index of the threshold register whose value got reached 2934 * 2935 * link_descriptor_counter0 2936 * link_descriptor_counter1 2937 * link_descriptor_counter2 2938 * link_descriptor_counter_sum 2939 * Value of the respective counters at generation of this message 2940 * 2941 * looping_count 2942 * A count value that indicates the number of times the producer of 2943 * entries into this Ring has looped around the ring. 2944 */ 2945 2946#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_DATA_LENGTH GENMASK(13, 0) 2947#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_L4_CSUM_STATUS BIT(14) 2948#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_L3_CSUM_STATUS BIT(15) 2949#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_PID GENMASK(27, 24) 2950#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_QDISC BIT(28) 2951#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_MULTICAST BIT(29) 2952#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_MORE BIT(30) 2953#define HAL_TCL_ENTRANCE_FROM_PPE_RING_INFO0_VALID_TOGGLE BIT(31) 2954 2955struct hal_tcl_entrance_from_ppe_ring { 2956 __le32 buffer_addr; 2957 __le32 info0; 2958} __packed; 2959 2960struct hal_mon_buf_ring { 2961 __le32 paddr_lo; 2962 __le32 paddr_hi; 2963 __le64 cookie; 2964}; 2965 2966/* hal_mon_buf_ring 2967 * Producer : SW 2968 * Consumer : Monitor 2969 * 2970 * paddr_lo 2971 * Lower 32-bit physical address of the buffer pointer from the source ring. 2972 * paddr_hi 2973 * bit range 7-0 : upper 8 bit of the physical address. 2974 * bit range 31-8 : reserved. 2975 * cookie 2976 * Consumer: RxMon/TxMon 64 bit cookie of the buffers. 2977 */ 2978 2979#define HAL_MON_DEST_COOKIE_BUF_ID GENMASK(17, 0) 2980 2981#define HAL_MON_DEST_INFO0_END_OFFSET GENMASK(11, 0) 2982#define HAL_MON_DEST_INFO0_END_REASON GENMASK(17, 16) 2983#define HAL_MON_DEST_INFO0_INITIATOR BIT(18) 2984#define HAL_MON_DEST_INFO0_EMPTY_DESC BIT(19) 2985#define HAL_MON_DEST_INFO0_RING_ID GENMASK(27, 20) 2986#define HAL_MON_DEST_INFO0_LOOPING_COUNT GENMASK(31, 28) 2987 2988struct hal_mon_dest_desc { 2989 __le32 cookie; 2990 __le32 reserved; 2991 __le32 ppdu_id; 2992 __le32 info0; 2993}; 2994 2995/* hal_mon_dest_ring 2996 * Producer : TxMon/RxMon 2997 * Consumer : SW 2998 * cookie 2999 * bit 0 -17 buf_id to track the skb's vaddr. 3000 * ppdu_id 3001 * Phy ppdu_id 3002 * end_offset 3003 * The offset into status buffer where DMA ended, ie., offset to the last 3004 * TLV + last TLV size. 3005 * flush_detected 3006 * Indicates whether 'tx_flush' or 'rx_flush' occurred. 3007 * end_of_ppdu 3008 * Indicates end of ppdu. 3009 * pmac_id 3010 * Indicates PMAC that received from frame. 3011 * empty_descriptor 3012 * This descriptor is written on flush or end of ppdu or end of status 3013 * buffer. 3014 * ring_id 3015 * updated by SRNG. 3016 * looping_count 3017 * updated by SRNG. 3018 */ 3019 3020#define HAL_TX_MSDU_METADATA_INFO0_ENCRYPT_FLAG BIT(8) 3021#define HAL_TX_MSDU_METADATA_INFO0_ENCRYPT_TYPE GENMASK(16, 15) 3022#define HAL_TX_MSDU_METADATA_INFO0_HOST_TX_DESC_POOL BIT(31) 3023 3024struct hal_tx_msdu_metadata { 3025 __le32 info0; 3026 __le32 rsvd0[6]; 3027} __packed; 3028 3029/* hal_tx_msdu_metadata 3030 * valid_encrypt_type 3031 * if set, encrypt type is valid 3032 * encrypt_type 3033 * 0 = NO_ENCRYPT, 3034 * 1 = ENCRYPT, 3035 * 2 ~ 3 - Reserved 3036 * host_tx_desc_pool 3037 * If set, Firmware allocates tx_descriptors 3038 * in WAL_BUFFERID_TX_HOST_DATA_EXP,instead 3039 * of WAL_BUFFERID_TX_TCL_DATA_EXP. 3040 * Use cases: 3041 * Any time firmware uses TQM-BYPASS for Data 3042 * TID, firmware expect host to set this bit. 3043 */ 3044 3045#endif /* ATH12K_HAL_DESC_H */
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