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dp.h
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linux-6.19.14/drivers/net/wireless/ath/ath12k/dp.h
1/* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2/* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7#ifndef ATH12K_DP_H 8#define ATH12K_DP_H 9 10#include "hal_desc.h" 11#include "hal_rx.h" 12#include "hw.h" 13 14#define MAX_RXDMA_PER_PDEV 2 15 16struct ath12k_base; 17struct ath12k_peer; 18struct ath12k_dp; 19struct ath12k_vif; 20struct ath12k_link_vif; 21struct hal_tcl_status_ring; 22struct ath12k_ext_irq_grp; 23 24#define DP_MON_PURGE_TIMEOUT_MS 100 25#define DP_MON_SERVICE_BUDGET 128 26 27struct dp_srng { 28 u32 *vaddr_unaligned; 29 u32 *vaddr; 30 dma_addr_t paddr_unaligned; 31 dma_addr_t paddr; 32 int size; 33 u32 ring_id; 34}; 35 36struct dp_rxdma_mon_ring { 37 struct dp_srng refill_buf_ring; 38 struct idr bufs_idr; 39 /* Protects bufs_idr */ 40 spinlock_t idr_lock; 41 int bufs_max; 42}; 43 44struct dp_rxdma_ring { 45 struct dp_srng refill_buf_ring; 46 int bufs_max; 47}; 48 49#define ATH12K_TX_COMPL_NEXT(ab, x) (((x) + 1) % DP_TX_COMP_RING_SIZE(ab)) 50 51struct dp_tx_ring { 52 u8 tcl_data_ring_id; 53 struct dp_srng tcl_data_ring; 54 struct dp_srng tcl_comp_ring; 55 struct hal_wbm_completion_ring_tx *tx_status; 56 int tx_status_head; 57 int tx_status_tail; 58}; 59 60struct ath12k_pdev_mon_stats { 61 u32 status_ppdu_state; 62 u32 status_ppdu_start; 63 u32 status_ppdu_end; 64 u32 status_ppdu_compl; 65 u32 status_ppdu_start_mis; 66 u32 status_ppdu_end_mis; 67 u32 status_ppdu_done; 68 u32 dest_ppdu_done; 69 u32 dest_mpdu_done; 70 u32 dest_mpdu_drop; 71 u32 dup_mon_linkdesc_cnt; 72 u32 dup_mon_buf_cnt; 73 u32 dest_mon_stuck; 74 u32 dest_mon_not_reaped; 75}; 76 77enum dp_mon_status_buf_state { 78 DP_MON_STATUS_MATCH, 79 DP_MON_STATUS_NO_DMA, 80 DP_MON_STATUS_LAG, 81 DP_MON_STATUS_LEAD, 82 DP_MON_STATUS_REPLINISH, 83}; 84 85struct dp_link_desc_bank { 86 void *vaddr_unaligned; 87 void *vaddr; 88 dma_addr_t paddr_unaligned; 89 dma_addr_t paddr; 90 u32 size; 91}; 92 93/* Size to enforce scatter idle list mode */ 94#define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000 95#define DP_LINK_DESC_BANKS_MAX 8 96 97#define DP_LINK_DESC_START 0x4000 98#define DP_LINK_DESC_SHIFT 3 99 100#define DP_LINK_DESC_COOKIE_SET(id, page) \ 101 ((((id) + DP_LINK_DESC_START) << DP_LINK_DESC_SHIFT) | (page)) 102 103#define DP_LINK_DESC_BANK_MASK GENMASK(2, 0) 104 105#define DP_RX_DESC_COOKIE_INDEX_MAX 0x3ffff 106#define DP_RX_DESC_COOKIE_POOL_ID_MAX 0x1c0000 107#define DP_RX_DESC_COOKIE_MAX \ 108 (DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX) 109#define DP_NOT_PPDU_ID_WRAP_AROUND 20000 110 111enum ath12k_dp_ppdu_state { 112 DP_PPDU_STATUS_START, 113 DP_PPDU_STATUS_DONE, 114}; 115 116struct dp_mon_mpdu { 117 struct list_head list; 118 struct sk_buff *head; 119 struct sk_buff *tail; 120 u32 err_bitmap; 121 u8 decap_format; 122}; 123 124#define DP_MON_MAX_STATUS_BUF 32 125 126struct ath12k_mon_data { 127 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 128 struct hal_rx_mon_ppdu_info mon_ppdu_info; 129 130 u32 mon_ppdu_status; 131 u32 mon_last_buf_cookie; 132 u64 mon_last_linkdesc_paddr; 133 u16 chan_noise_floor; 134 u32 err_bitmap; 135 u8 decap_format; 136 137 struct ath12k_pdev_mon_stats rx_mon_stats; 138 enum dp_mon_status_buf_state buf_state; 139 /* lock for monitor data */ 140 spinlock_t mon_lock; 141 struct sk_buff_head rx_status_q; 142 struct dp_mon_mpdu *mon_mpdu; 143 struct list_head dp_rx_mon_mpdu_list; 144 struct dp_mon_tx_ppdu_info *tx_prot_ppdu_info; 145 struct dp_mon_tx_ppdu_info *tx_data_ppdu_info; 146}; 147 148struct ath12k_pdev_dp { 149 u32 mac_id; 150 atomic_t num_tx_pending; 151 wait_queue_head_t tx_empty_waitq; 152 struct dp_srng rxdma_mon_dst_ring[MAX_RXDMA_PER_PDEV]; 153 struct dp_srng tx_mon_dst_ring[MAX_RXDMA_PER_PDEV]; 154 155 struct ieee80211_rx_status rx_status; 156 struct ath12k_mon_data mon_data; 157}; 158 159#define DP_NUM_CLIENTS_MAX 64 160#define DP_AVG_TIDS_PER_CLIENT 2 161#define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT) 162#define DP_AVG_MSDUS_PER_FLOW 128 163#define DP_AVG_FLOWS_PER_TID 2 164#define DP_AVG_MPDUS_PER_TID_MAX 128 165#define DP_AVG_MSDUS_PER_MPDU 4 166 167#define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */ 168 169#define DP_BA_WIN_SZ_MAX 1024 170 171#define DP_TCL_NUM_RING_MAX 4 172 173#define DP_IDLE_SCATTER_BUFS_MAX 16 174 175#define DP_WBM_RELEASE_RING_SIZE 64 176#define DP_TCL_DATA_RING_SIZE 512 177#define DP_TX_COMP_RING_SIZE(ab) \ 178 ((ab)->profile_param->dp_params.tx_comp_ring_size) 179#define DP_TX_IDR_SIZE(ab) DP_TX_COMP_RING_SIZE(ab) 180#define DP_TCL_CMD_RING_SIZE 32 181#define DP_TCL_STATUS_RING_SIZE 32 182#define DP_REO_DST_RING_MAX 8 183#define DP_REO_DST_RING_SIZE 2048 184#define DP_REO_REINJECT_RING_SIZE 32 185#define DP_RX_RELEASE_RING_SIZE 1024 186#define DP_REO_EXCEPTION_RING_SIZE 128 187#define DP_REO_CMD_RING_SIZE 256 188#define DP_REO_STATUS_RING_SIZE 2048 189#define DP_RXDMA_BUF_RING_SIZE 4096 190#define DP_RX_MAC_BUF_RING_SIZE 2048 191#define DP_RXDMA_REFILL_RING_SIZE 2048 192#define DP_RXDMA_ERR_DST_RING_SIZE 1024 193#define DP_RXDMA_MON_STATUS_RING_SIZE 1024 194#define DP_RXDMA_MONITOR_BUF_RING_SIZE(ab) \ 195 ((ab)->profile_param->dp_params.rxdma_monitor_buf_ring_size) 196#define DP_RXDMA_MONITOR_DST_RING_SIZE(ab) \ 197 ((ab)->profile_param->dp_params.rxdma_monitor_dst_ring_size) 198#define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096 199#define DP_TX_MONITOR_BUF_RING_SIZE 4096 200#define DP_TX_MONITOR_DEST_RING_SIZE 2048 201 202#define DP_TX_MONITOR_BUF_SIZE 2048 203#define DP_TX_MONITOR_BUF_SIZE_MIN 48 204#define DP_TX_MONITOR_BUF_SIZE_MAX 8192 205 206#define DP_RX_BUFFER_SIZE 2048 207#define DP_RX_BUFFER_SIZE_LITE 1024 208#define DP_RX_BUFFER_ALIGN_SIZE 128 209 210#define RX_MON_STATUS_BASE_BUF_SIZE 2048 211#define RX_MON_STATUS_BUF_ALIGN 128 212#define RX_MON_STATUS_BUF_RESERVATION 128 213#define RX_MON_STATUS_BUF_SIZE (RX_MON_STATUS_BASE_BUF_SIZE - \ 214 (RX_MON_STATUS_BUF_RESERVATION + \ 215 RX_MON_STATUS_BUF_ALIGN + \ 216 SKB_DATA_ALIGN(sizeof(struct skb_shared_info)))) 217 218#define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0) 219#define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(19, 18) 220 221#define DP_HW2SW_MACID(mac_id) ({ typeof(mac_id) x = (mac_id); x ? x - 1 : 0; }) 222#define DP_SW2HW_MACID(mac_id) ((mac_id) + 1) 223 224#define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0) 225#define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2) 226#define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19) 227 228#define ATH12K_SHADOW_DP_TIMER_INTERVAL 20 229#define ATH12K_SHADOW_CTRL_TIMER_INTERVAL 10 230 231#define ATH12K_NUM_POOL_TX_DESC(ab) \ 232 ((ab)->profile_param->dp_params.num_pool_tx_desc) 233/* TODO: revisit this count during testing */ 234#define ATH12K_RX_DESC_COUNT(ab) \ 235 ((ab)->profile_param->dp_params.rx_desc_count) 236 237#define ATH12K_PAGE_SIZE PAGE_SIZE 238 239/* Total 1024 entries in PPT, i.e 4K/4 considering 4K aligned 240 * SPT pages which makes lower 12bits 0 241 */ 242#define ATH12K_MAX_PPT_ENTRIES 1024 243 244/* Total 512 entries in a SPT, i.e 4K Page/8 */ 245#define ATH12K_MAX_SPT_ENTRIES 512 246 247#define ATH12K_NUM_RX_SPT_PAGES(ab) ((ATH12K_RX_DESC_COUNT(ab)) / \ 248 ATH12K_MAX_SPT_ENTRIES) 249 250#define ATH12K_TX_SPT_PAGES_PER_POOL(ab) (ATH12K_NUM_POOL_TX_DESC(ab) / \ 251 ATH12K_MAX_SPT_ENTRIES) 252#define ATH12K_NUM_TX_SPT_PAGES(ab) (ATH12K_TX_SPT_PAGES_PER_POOL(ab) * \ 253 ATH12K_HW_MAX_QUEUES) 254 255#define ATH12K_TX_SPT_PAGE_OFFSET 0 256#define ATH12K_RX_SPT_PAGE_OFFSET(ab) ATH12K_NUM_TX_SPT_PAGES(ab) 257 258/* The SPT pages are divided for RX and TX, first block for RX 259 * and remaining for TX 260 */ 261#define ATH12K_NUM_TX_SPT_PAGE_START(ab) ATH12K_NUM_RX_SPT_PAGES(ab) 262 263#define ATH12K_DP_RX_DESC_MAGIC 0xBABABABA 264 265/* 4K aligned address have last 12 bits set to 0, this check is done 266 * so that two spt pages address can be stored per 8bytes 267 * of CMEM (PPT) 268 */ 269#define ATH12K_SPT_4K_ALIGN_CHECK 0xFFF 270#define ATH12K_SPT_4K_ALIGN_OFFSET 12 271#define ATH12K_PPT_ADDR_OFFSET(ppt_index) (4 * (ppt_index)) 272 273/* To indicate HW of CMEM address, b0-31 are cmem base received via QMI */ 274#define ATH12K_CMEM_ADDR_MSB 0x10 275 276/* Of 20 bits cookie, b0-b8 is to indicate SPT offset and b9-19 for PPT */ 277#define ATH12K_CC_SPT_MSB 8 278#define ATH12K_CC_PPT_MSB 19 279#define ATH12K_CC_PPT_SHIFT 9 280#define ATH12K_DP_CC_COOKIE_SPT GENMASK(8, 0) 281#define ATH12K_DP_CC_COOKIE_PPT GENMASK(19, 9) 282 283#define DP_REO_QREF_NUM GENMASK(31, 16) 284#define DP_MAX_PEER_ID 2047 285 286/* Total size of the LUT is based on 2K peers, each having reference 287 * for 17tids, note each entry is of type ath12k_reo_queue_ref 288 * hence total size is 2048 * 17 * 8 = 278528 289 */ 290#define DP_REOQ_LUT_SIZE 278528 291 292/* Invalid TX Bank ID value */ 293#define DP_INVALID_BANK_ID -1 294 295#define MAX_TQM_RELEASE_REASON 15 296#define MAX_FW_TX_STATUS 7 297 298struct ath12k_dp_tx_bank_profile { 299 u8 is_configured; 300 u32 num_users; 301 u32 bank_config; 302}; 303 304struct ath12k_hp_update_timer { 305 struct timer_list timer; 306 bool started; 307 bool init; 308 u32 tx_num; 309 u32 timer_tx_num; 310 u32 ring_id; 311 u32 interval; 312 struct ath12k_base *ab; 313}; 314 315struct ath12k_rx_desc_info { 316 struct list_head list; 317 struct sk_buff *skb; 318 u32 cookie; 319 u32 magic; 320 u8 in_use : 1, 321 device_id : 3, 322 reserved : 4; 323}; 324 325struct ath12k_tx_desc_info { 326 struct list_head list; 327 struct sk_buff *skb; 328 struct sk_buff *skb_ext_desc; 329 u32 desc_id; /* Cookie */ 330 u8 mac_id; 331 u8 pool_id; 332}; 333 334struct ath12k_tx_desc_params { 335 struct sk_buff *skb; 336 struct sk_buff *skb_ext_desc; 337 u8 mac_id; 338}; 339 340struct ath12k_spt_info { 341 dma_addr_t paddr; 342 u64 *vaddr; 343}; 344 345struct ath12k_reo_queue_ref { 346 u32 info0; 347 u32 info1; 348} __packed; 349 350struct ath12k_reo_q_addr_lut { 351 u32 *vaddr_unaligned; 352 u32 *vaddr; 353 dma_addr_t paddr_unaligned; 354 dma_addr_t paddr; 355 u32 size; 356}; 357 358struct ath12k_link_stats { 359 u32 tx_enqueued; 360 u32 tx_completed; 361 u32 tx_bcast_mcast; 362 u32 tx_dropped; 363 u32 tx_encap_type[HAL_TCL_ENCAP_TYPE_MAX]; 364 u32 tx_encrypt_type[HAL_ENCRYPT_TYPE_MAX]; 365 u32 tx_desc_type[HAL_TCL_DESC_TYPE_MAX]; 366}; 367 368struct ath12k_dp { 369 struct ath12k_base *ab; 370 u32 mon_dest_ring_stuck_cnt; 371 u8 num_bank_profiles; 372 /* protects the access and update of bank_profiles */ 373 spinlock_t tx_bank_lock; 374 struct ath12k_dp_tx_bank_profile *bank_profiles; 375 enum ath12k_htc_ep_id eid; 376 struct completion htt_tgt_version_received; 377 u8 htt_tgt_ver_major; 378 u8 htt_tgt_ver_minor; 379 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 380 enum hal_rx_buf_return_buf_manager idle_link_rbm; 381 struct dp_srng wbm_idle_ring; 382 struct dp_srng wbm_desc_rel_ring; 383 struct dp_srng reo_reinject_ring; 384 struct dp_srng rx_rel_ring; 385 struct dp_srng reo_except_ring; 386 struct dp_srng reo_cmd_ring; 387 struct dp_srng reo_status_ring; 388 enum ath12k_peer_metadata_version peer_metadata_ver; 389 struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX]; 390 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX]; 391 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX]; 392 struct list_head reo_cmd_update_rx_queue_list; 393 struct list_head reo_cmd_cache_flush_list; 394 u32 reo_cmd_cache_flush_count; 395 /* protects access to below fields, 396 * - reo_cmd_update_rx_queue_list 397 * - reo_cmd_cache_flush_list 398 * - reo_cmd_cache_flush_count 399 */ 400 spinlock_t reo_rxq_flush_lock; 401 struct list_head reo_cmd_list; 402 /* protects access to below fields, 403 * - reo_cmd_list 404 */ 405 spinlock_t reo_cmd_lock; 406 struct ath12k_hp_update_timer reo_cmd_timer; 407 struct ath12k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX]; 408 struct ath12k_spt_info *spt_info; 409 u32 num_spt_pages; 410 u32 rx_ppt_base; 411 struct ath12k_rx_desc_info **rxbaddr; 412 struct ath12k_tx_desc_info **txbaddr; 413 struct list_head rx_desc_free_list; 414 /* protects the free desc list */ 415 spinlock_t rx_desc_lock; 416 417 struct list_head tx_desc_free_list[ATH12K_HW_MAX_QUEUES]; 418 struct list_head tx_desc_used_list[ATH12K_HW_MAX_QUEUES]; 419 /* protects the free and used desc lists */ 420 spinlock_t tx_desc_lock[ATH12K_HW_MAX_QUEUES]; 421 422 struct dp_rxdma_ring rx_refill_buf_ring; 423 struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV]; 424 struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV]; 425 struct dp_rxdma_mon_ring rxdma_mon_buf_ring; 426 struct dp_rxdma_mon_ring tx_mon_buf_ring; 427 struct dp_rxdma_mon_ring rx_mon_status_refill_ring[MAX_RXDMA_PER_PDEV]; 428 struct ath12k_reo_q_addr_lut reoq_lut; 429 struct ath12k_reo_q_addr_lut ml_reoq_lut; 430}; 431 432/* HTT definitions */ 433#define HTT_TAG_TCL_METADATA_VERSION 5 434 435#define HTT_TCL_META_DATA_TYPE GENMASK(1, 0) 436#define HTT_TCL_META_DATA_VALID_HTT BIT(2) 437 438/* vdev meta data */ 439#define HTT_TCL_META_DATA_VDEV_ID GENMASK(10, 3) 440#define HTT_TCL_META_DATA_PDEV_ID GENMASK(12, 11) 441#define HTT_TCL_META_DATA_HOST_INSPECTED_MISSION BIT(13) 442 443/* peer meta data */ 444#define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 3) 445 446/* Global sequence number */ 447#define HTT_TCL_META_DATA_TYPE_GLOBAL_SEQ_NUM 3 448#define HTT_TCL_META_DATA_GLOBAL_SEQ_HOST_INSPECTED BIT(2) 449#define HTT_TCL_META_DATA_GLOBAL_SEQ_NUM GENMASK(14, 3) 450#define HTT_TX_MLO_MCAST_HOST_REINJECT_BASE_VDEV_ID 128 451 452/* HTT tx completion is overlaid in wbm_release_ring */ 453#define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(16, 13) 454#define HTT_TX_WBM_COMP_INFO1_REINJECT_REASON GENMASK(3, 0) 455#define HTT_TX_WBM_COMP_INFO1_EXCEPTION_FRAME BIT(4) 456 457#define HTT_TX_WBM_COMP_INFO2_ACK_RSSI GENMASK(31, 24) 458 459struct htt_tx_wbm_completion { 460 __le32 rsvd0[2]; 461 __le32 info0; 462 __le32 info1; 463 __le32 info2; 464 __le32 info3; 465 __le32 info4; 466 __le32 rsvd1; 467 468} __packed; 469 470enum htt_h2t_msg_type { 471 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 472 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, 473 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, 474 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10, 475 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, 476 HTT_H2T_MSG_TYPE_VDEV_TXRX_STATS_CFG = 0x1a, 477 HTT_H2T_MSG_TYPE_TX_MONITOR_CFG = 0x1b, 478}; 479 480#define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0) 481#define HTT_OPTION_TCL_METADATA_VER_V1 1 482#define HTT_OPTION_TCL_METADATA_VER_V2 2 483#define HTT_OPTION_TAG GENMASK(7, 0) 484#define HTT_OPTION_LEN GENMASK(15, 8) 485#define HTT_OPTION_VALUE GENMASK(31, 16) 486#define HTT_TCL_METADATA_VER_SZ 4 487 488struct htt_ver_req_cmd { 489 __le32 ver_reg_info; 490 __le32 tcl_metadata_version; 491} __packed; 492 493enum htt_srng_ring_type { 494 HTT_HW_TO_SW_RING, 495 HTT_SW_TO_HW_RING, 496 HTT_SW_TO_SW_RING, 497}; 498 499enum htt_srng_ring_id { 500 HTT_RXDMA_HOST_BUF_RING, 501 HTT_RXDMA_MONITOR_STATUS_RING, 502 HTT_RXDMA_MONITOR_BUF_RING, 503 HTT_RXDMA_MONITOR_DESC_RING, 504 HTT_RXDMA_MONITOR_DEST_RING, 505 HTT_HOST1_TO_FW_RXBUF_RING, 506 HTT_HOST2_TO_FW_RXBUF_RING, 507 HTT_RXDMA_NON_MONITOR_DEST_RING, 508 HTT_RXDMA_HOST_BUF_RING2, 509 HTT_TX_MON_HOST2MON_BUF_RING, 510 HTT_TX_MON_MON2HOST_DEST_RING, 511 HTT_RX_MON_HOST2MON_BUF_RING, 512 HTT_RX_MON_MON2HOST_DEST_RING, 513}; 514 515/* host -> target HTT_SRING_SETUP message 516 * 517 * After target is booted up, Host can send SRING setup message for 518 * each host facing LMAC SRING. Target setups up HW registers based 519 * on setup message and confirms back to Host if response_required is set. 520 * Host should wait for confirmation message before sending new SRING 521 * setup message 522 * 523 * The message would appear as follows: 524 * 525 * |31 24|23 20|19|18 16|15|14 8|7 0| 526 * |--------------- +-----------------+----------------+------------------| 527 * | ring_type | ring_id | pdev_id | msg_type | 528 * |----------------------------------------------------------------------| 529 * | ring_base_addr_lo | 530 * |----------------------------------------------------------------------| 531 * | ring_base_addr_hi | 532 * |----------------------------------------------------------------------| 533 * |ring_misc_cfg_flag|ring_entry_size| ring_size | 534 * |----------------------------------------------------------------------| 535 * | ring_head_offset32_remote_addr_lo | 536 * |----------------------------------------------------------------------| 537 * | ring_head_offset32_remote_addr_hi | 538 * |----------------------------------------------------------------------| 539 * | ring_tail_offset32_remote_addr_lo | 540 * |----------------------------------------------------------------------| 541 * | ring_tail_offset32_remote_addr_hi | 542 * |----------------------------------------------------------------------| 543 * | ring_msi_addr_lo | 544 * |----------------------------------------------------------------------| 545 * | ring_msi_addr_hi | 546 * |----------------------------------------------------------------------| 547 * | ring_msi_data | 548 * |----------------------------------------------------------------------| 549 * | intr_timer_th |IM| intr_batch_counter_th | 550 * |----------------------------------------------------------------------| 551 * | reserved |RR|PTCF| intr_low_threshold | 552 * |----------------------------------------------------------------------| 553 * Where 554 * IM = sw_intr_mode 555 * RR = response_required 556 * PTCF = prefetch_timer_cfg 557 * 558 * The message is interpreted as follows: 559 * dword0 - b'0:7 - msg_type: This will be set to 560 * HTT_H2T_MSG_TYPE_SRING_SETUP 561 * b'8:15 - pdev_id: 562 * 0 (for rings at SOC/UMAC level), 563 * 1/2/3 mac id (for rings at LMAC level) 564 * b'16:23 - ring_id: identify which ring is to setup, 565 * more details can be got from enum htt_srng_ring_id 566 * b'24:31 - ring_type: identify type of host rings, 567 * more details can be got from enum htt_srng_ring_type 568 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address 569 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address 570 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words 571 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units 572 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and 573 * SW_TO_HW_RING. 574 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs. 575 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo: 576 * Lower 32 bits of memory address of the remote variable 577 * storing the 4-byte word offset that identifies the head 578 * element within the ring. 579 * (The head offset variable has type u32.) 580 * Valid for HW_TO_SW and SW_TO_SW rings. 581 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi: 582 * Upper 32 bits of memory address of the remote variable 583 * storing the 4-byte word offset that identifies the head 584 * element within the ring. 585 * (The head offset variable has type u32.) 586 * Valid for HW_TO_SW and SW_TO_SW rings. 587 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo: 588 * Lower 32 bits of memory address of the remote variable 589 * storing the 4-byte word offset that identifies the tail 590 * element within the ring. 591 * (The tail offset variable has type u32.) 592 * Valid for HW_TO_SW and SW_TO_SW rings. 593 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi: 594 * Upper 32 bits of memory address of the remote variable 595 * storing the 4-byte word offset that identifies the tail 596 * element within the ring. 597 * (The tail offset variable has type u32.) 598 * Valid for HW_TO_SW and SW_TO_SW rings. 599 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address 600 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 601 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address 602 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 603 * dword10 - b'0:31 - ring_msi_data: MSI data 604 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs 605 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 606 * dword11 - b'0:14 - intr_batch_counter_th: 607 * batch counter threshold is in units of 4-byte words. 608 * HW internally maintains and increments batch count. 609 * (see SRING spec for detail description). 610 * When batch count reaches threshold value, an interrupt 611 * is generated by HW. 612 * b'15 - sw_intr_mode: 613 * This configuration shall be static. 614 * Only programmed at power up. 615 * 0: generate pulse style sw interrupts 616 * 1: generate level style sw interrupts 617 * b'16:31 - intr_timer_th: 618 * The timer init value when timer is idle or is 619 * initialized to start downcounting. 620 * In 8us units (to cover a range of 0 to 524 ms) 621 * dword12 - b'0:15 - intr_low_threshold: 622 * Used only by Consumer ring to generate ring_sw_int_p. 623 * Ring entries low threshold water mark, that is used 624 * in combination with the interrupt timer as well as 625 * the clearing of the level interrupt. 626 * b'16:18 - prefetch_timer_cfg: 627 * Used only by Consumer ring to set timer mode to 628 * support Application prefetch handling. 629 * The external tail offset/pointer will be updated 630 * at following intervals: 631 * 3'b000: (Prefetch feature disabled; used only for debug) 632 * 3'b001: 1 usec 633 * 3'b010: 4 usec 634 * 3'b011: 8 usec (default) 635 * 3'b100: 16 usec 636 * Others: Reserved 637 * b'19 - response_required: 638 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response 639 * b'20:31 - reserved: reserved for future use 640 */ 641 642#define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 643#define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8) 644#define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16) 645#define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24) 646 647#define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0) 648#define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16) 649#define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25) 650#define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27) 651#define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28) 652#define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29) 653 654#define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0) 655#define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15) 656#define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16) 657 658#define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0) 659#define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG GENMASK(18, 16) 660#define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19) 661 662struct htt_srng_setup_cmd { 663 __le32 info0; 664 __le32 ring_base_addr_lo; 665 __le32 ring_base_addr_hi; 666 __le32 info1; 667 __le32 ring_head_off32_remote_addr_lo; 668 __le32 ring_head_off32_remote_addr_hi; 669 __le32 ring_tail_off32_remote_addr_lo; 670 __le32 ring_tail_off32_remote_addr_hi; 671 __le32 ring_msi_addr_lo; 672 __le32 ring_msi_addr_hi; 673 __le32 msi_data; 674 __le32 intr_info; 675 __le32 info2; 676} __packed; 677 678/* host -> target FW PPDU_STATS config message 679 * 680 * @details 681 * The following field definitions describe the format of the HTT host 682 * to target FW for PPDU_STATS_CFG msg. 683 * The message allows the host to configure the PPDU_STATS_IND messages 684 * produced by the target. 685 * 686 * |31 24|23 16|15 8|7 0| 687 * |-----------------------------------------------------------| 688 * | REQ bit mask | pdev_mask | msg type | 689 * |-----------------------------------------------------------| 690 * Header fields: 691 * - MSG_TYPE 692 * Bits 7:0 693 * Purpose: identifies this is a req to configure ppdu_stats_ind from target 694 * Value: 0x11 695 * - PDEV_MASK 696 * Bits 8:15 697 * Purpose: identifies which pdevs this PPDU stats configuration applies to 698 * Value: This is a overloaded field, refer to usage and interpretation of 699 * PDEV in interface document. 700 * Bit 8 : Reserved for SOC stats 701 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 702 * Indicates MACID_MASK in DBS 703 * - REQ_TLV_BIT_MASK 704 * Bits 16:31 705 * Purpose: each set bit indicates the corresponding PPDU stats TLV type 706 * needs to be included in the target's PPDU_STATS_IND messages. 707 * Value: refer htt_ppdu_stats_tlv_tag_t <<<??? 708 * 709 */ 710 711struct htt_ppdu_stats_cfg_cmd { 712 __le32 msg; 713} __packed; 714 715#define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0) 716#define HTT_PPDU_STATS_CFG_SOC_STATS BIT(8) 717#define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 9) 718#define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16) 719 720enum htt_ppdu_stats_tag_type { 721 HTT_PPDU_STATS_TAG_COMMON, 722 HTT_PPDU_STATS_TAG_USR_COMMON, 723 HTT_PPDU_STATS_TAG_USR_RATE, 724 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64, 725 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256, 726 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS, 727 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON, 728 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64, 729 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256, 730 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS, 731 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH, 732 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY, 733 HTT_PPDU_STATS_TAG_INFO, 734 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD, 735 736 /* New TLV's are added above to this line */ 737 HTT_PPDU_STATS_TAG_MAX, 738}; 739 740#define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \ 741 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \ 742 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \ 743 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \ 744 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \ 745 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \ 746 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \ 747 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY)) 748 749#define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \ 750 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \ 751 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \ 752 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \ 753 BIT(HTT_PPDU_STATS_TAG_INFO) | \ 754 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \ 755 HTT_PPDU_STATS_TAG_DEFAULT) 756 757enum htt_stats_internal_ppdu_frametype { 758 HTT_STATS_PPDU_FTYPE_CTRL, 759 HTT_STATS_PPDU_FTYPE_DATA, 760 HTT_STATS_PPDU_FTYPE_BAR, 761 HTT_STATS_PPDU_FTYPE_MAX 762}; 763 764/* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message 765 * 766 * details: 767 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to 768 * configure RXDMA rings. 769 * The configuration is per ring based and includes both packet subtypes 770 * and PPDU/MPDU TLVs. 771 * 772 * The message would appear as follows: 773 * 774 * |31 29|28|27|26|25|24|23 16|15 8|7 0| 775 * |-------+--+--+--+--+--+-----------+----------------+---------------| 776 * | rsvd1 |ED|DT|OV|PS|SS| ring_id | pdev_id | msg_type | 777 * |-------------------------------------------------------------------| 778 * | rsvd2 | ring_buffer_size | 779 * |-------------------------------------------------------------------| 780 * | packet_type_enable_flags_0 | 781 * |-------------------------------------------------------------------| 782 * | packet_type_enable_flags_1 | 783 * |-------------------------------------------------------------------| 784 * | packet_type_enable_flags_2 | 785 * |-------------------------------------------------------------------| 786 * | packet_type_enable_flags_3 | 787 * |-------------------------------------------------------------------| 788 * | tlv_filter_in_flags | 789 * |-------------------------------------------------------------------| 790 * Where: 791 * PS = pkt_swap 792 * SS = status_swap 793 * The message is interpreted as follows: 794 * dword0 - b'0:7 - msg_type: This will be set to 795 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG 796 * b'8:15 - pdev_id: 797 * 0 (for rings at SOC/UMAC level), 798 * 1/2/3 mac id (for rings at LMAC level) 799 * b'16:23 - ring_id : Identify the ring to configure. 800 * More details can be got from enum htt_srng_ring_id 801 * b'24 - status_swap: 1 is to swap status TLV 802 * b'25 - pkt_swap: 1 is to swap packet TLV 803 * b'26 - rx_offset_valid (OV): flag to indicate rx offsets 804 * configuration fields are valid 805 * b'27 - drop_thresh_valid (DT): flag to indicate if the 806 * rx_drop_threshold field is valid 807 * b'28 - rx_mon_global_en: Enable/Disable global register 808 * configuration in Rx monitor module. 809 * b'29:31 - rsvd1: reserved for future use 810 * dword1 - b'0:16 - ring_buffer_size: size of buffers referenced by rx ring, 811 * in byte units. 812 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 813 * - b'16:31 - rsvd2: Reserved for future use 814 * dword2 - b'0:31 - packet_type_enable_flags_0: 815 * Enable MGMT packet from 0b0000 to 0b1001 816 * bits from low to high: FP, MD, MO - 3 bits 817 * FP: Filter_Pass 818 * MD: Monitor_Direct 819 * MO: Monitor_Other 820 * 10 mgmt subtypes * 3 bits -> 30 bits 821 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs 822 * dword3 - b'0:31 - packet_type_enable_flags_1: 823 * Enable MGMT packet from 0b1010 to 0b1111 824 * bits from low to high: FP, MD, MO - 3 bits 825 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs 826 * dword4 - b'0:31 - packet_type_enable_flags_2: 827 * Enable CTRL packet from 0b0000 to 0b1001 828 * bits from low to high: FP, MD, MO - 3 bits 829 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs 830 * dword5 - b'0:31 - packet_type_enable_flags_3: 831 * Enable CTRL packet from 0b1010 to 0b1111, 832 * MCAST_DATA, UCAST_DATA, NULL_DATA 833 * bits from low to high: FP, MD, MO - 3 bits 834 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs 835 * dword6 - b'0:31 - tlv_filter_in_flags: 836 * Filter in Attention/MPDU/PPDU/Header/User tlvs 837 * Refer to CFG_TLV_FILTER_IN_FLAG defs 838 */ 839 840#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 841#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 842#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 843#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 844#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 845#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_OFFSET_VALID BIT(26) 846#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_DROP_THRES_VAL BIT(27) 847#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_EN_RXMON BIT(28) 848 849#define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0) 850#define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT GENMASK(18, 16) 851#define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL GENMASK(21, 19) 852#define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA GENMASK(24, 22) 853 854#define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_DROP_THRESHOLD GENMASK(9, 0) 855#define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_LOG_MGMT_TYPE BIT(17) 856#define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_CTRL_TYPE BIT(18) 857#define HTT_RX_RING_SELECTION_CFG_CMD_INFO2_EN_LOG_DATA_TYPE BIT(19) 858 859#define HTT_RX_RING_SELECTION_CFG_CMD_INFO3_EN_TLV_PKT_OFFSET BIT(0) 860#define HTT_RX_RING_SELECTION_CFG_CMD_INFO3_PKT_TLV_OFFSET GENMASK(14, 1) 861 862#define HTT_RX_RING_SELECTION_CFG_RX_PACKET_OFFSET GENMASK(15, 0) 863#define HTT_RX_RING_SELECTION_CFG_RX_HEADER_OFFSET GENMASK(31, 16) 864#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_OFFSET GENMASK(15, 0) 865#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_OFFSET GENMASK(31, 16) 866#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_OFFSET GENMASK(15, 0) 867#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_START_OFFSET GENMASK(31, 16) 868#define HTT_RX_RING_SELECTION_CFG_RX_ATTENTION_OFFSET GENMASK(15, 0) 869 870#define HTT_RX_RING_SELECTION_CFG_WORD_MASK_COMPACT_SET BIT(23) 871#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_START_MASK GENMASK(15, 0) 872#define HTT_RX_RING_SELECTION_CFG_RX_MPDU_END_MASK GENMASK(18, 16) 873#define HTT_RX_RING_SELECTION_CFG_RX_MSDU_END_MASK GENMASK(16, 0) 874 875enum htt_rx_filter_tlv_flags { 876 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0), 877 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1), 878 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2), 879 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3), 880 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4), 881 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5), 882 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6), 883 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7), 884 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8), 885 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9), 886 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10), 887 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11), 888 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12), 889 HTT_RX_FILTER_TLV_FLAGS_PPDU_START_USER_INFO = BIT(13), 890}; 891 892enum htt_rx_mgmt_pkt_filter_tlv_flags0 { 893 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0), 894 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1), 895 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2), 896 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3), 897 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4), 898 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5), 899 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6), 900 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7), 901 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8), 902 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9), 903 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10), 904 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11), 905 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12), 906 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13), 907 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14), 908 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15), 909 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16), 910 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17), 911 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18), 912 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19), 913 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20), 914 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21), 915 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22), 916 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23), 917 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24), 918 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25), 919 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26), 920 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27), 921 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28), 922 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29), 923}; 924 925enum htt_rx_mgmt_pkt_filter_tlv_flags1 { 926 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0), 927 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1), 928 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2), 929 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3), 930 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4), 931 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5), 932 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6), 933 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7), 934 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8), 935 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9), 936 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10), 937 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11), 938 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12), 939 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13), 940 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14), 941 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15), 942 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16), 943 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17), 944}; 945 946enum htt_rx_ctrl_pkt_filter_tlv_flags2 { 947 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0), 948 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1), 949 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2), 950 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3), 951 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4), 952 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5), 953 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6), 954 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7), 955 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8), 956 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9), 957 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10), 958 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11), 959 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12), 960 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13), 961 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14), 962 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15), 963 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16), 964 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17), 965 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18), 966 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19), 967 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20), 968 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21), 969 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22), 970 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23), 971 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24), 972 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25), 973 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26), 974 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27), 975 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28), 976 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29), 977}; 978 979enum htt_rx_ctrl_pkt_filter_tlv_flags3 { 980 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0), 981 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1), 982 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2), 983 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3), 984 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4), 985 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5), 986 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6), 987 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7), 988 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8), 989 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9), 990 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10), 991 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11), 992 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12), 993 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13), 994 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14), 995 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15), 996 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16), 997 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17), 998}; 999 1000enum htt_rx_data_pkt_filter_tlv_flasg3 { 1001 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18), 1002 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19), 1003 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20), 1004 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21), 1005 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22), 1006 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23), 1007 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24), 1008 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25), 1009 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26), 1010}; 1011 1012#define HTT_RX_FP_MGMT_FILTER_FLAGS0 \ 1013 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 1014 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 1015 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 1016 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 1017 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 1018 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 1019 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 1020 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 1021 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 1022 1023#define HTT_RX_MD_MGMT_FILTER_FLAGS0 \ 1024 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 1025 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 1026 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 1027 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 1028 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 1029 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 1030 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 1031 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 1032 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 1033 1034#define HTT_RX_MO_MGMT_FILTER_FLAGS0 \ 1035 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 1036 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 1037 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 1038 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 1039 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 1040 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 1041 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 1042 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 1043 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 1044 1045#define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 1046 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 1047 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 1048 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 1049 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 1050 1051#define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 1052 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 1053 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 1054 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 1055 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 1056 1057#define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 1058 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 1059 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 1060 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 1061 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 1062 1063#define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 1064 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 1065 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 1066 1067#define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 1068 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 1069 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 1070 1071#define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 1072 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 1073 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 1074 1075#define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 1076 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 1077 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 1078 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 1079 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 1080 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 1081 1082#define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 1083 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 1084 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 1085 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 1086 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 1087 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 1088 1089#define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 1090 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 1091 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 1092 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 1093 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 1094 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 1095 1096#define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 1097 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 1098 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 1099 1100#define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 1101 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 1102 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 1103 1104#define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 1105 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 1106 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 1107 1108#define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \ 1109 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \ 1110 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 1111 1112#define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \ 1113 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \ 1114 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 1115 1116#define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \ 1117 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \ 1118 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 1119 1120#define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \ 1121 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \ 1122 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 1123 1124#define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \ 1125 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \ 1126 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 1127 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 1128 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 1129 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 1130 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 1131 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 1132 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 1133 1134#define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \ 1135 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \ 1136 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 1137 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 1138 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 1139 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 1140 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 1141 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 1142 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 1143 1144#define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3 1145 1146#define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3 1147 1148#define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3 1149 1150#define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3 1151 1152#define HTT_RX_MON_FILTER_TLV_FLAGS \ 1153 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1154 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 1155 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 1156 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 1157 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 1158 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 1159 1160#define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \ 1161 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1162 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 1163 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 1164 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 1165 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 1166 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 1167 1168#define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \ 1169 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1170 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \ 1171 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 1172 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \ 1173 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \ 1174 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \ 1175 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \ 1176 HTT_RX_FILTER_TLV_FLAGS_ATTENTION) 1177 1178#define HTT_RX_MON_FILTER_TLV_FLAGS_MON_DEST_RING \ 1179 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1180 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \ 1181 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 1182 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \ 1183 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \ 1184 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \ 1185 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \ 1186 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 1187 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 1188 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 1189 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 1190 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE | \ 1191 HTT_RX_FILTER_TLV_FLAGS_PPDU_START_USER_INFO) 1192 1193/* msdu start. mpdu end, attention, rx hdr tlv's are not subscribed */ 1194#define HTT_RX_TLV_FLAGS_RXDMA_RING \ 1195 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 1196 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 1197 HTT_RX_FILTER_TLV_FLAGS_MSDU_END) 1198 1199#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 1200#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 1201 1202struct htt_rx_ring_selection_cfg_cmd { 1203 __le32 info0; 1204 __le32 info1; 1205 __le32 pkt_type_en_flags0; 1206 __le32 pkt_type_en_flags1; 1207 __le32 pkt_type_en_flags2; 1208 __le32 pkt_type_en_flags3; 1209 __le32 rx_filter_tlv; 1210 __le32 rx_packet_offset; 1211 __le32 rx_mpdu_offset; 1212 __le32 rx_msdu_offset; 1213 __le32 rx_attn_offset; 1214 __le32 info2; 1215 __le32 reserved[2]; 1216 __le32 rx_mpdu_start_end_mask; 1217 __le32 rx_msdu_end_word_mask; 1218 __le32 info3; 1219} __packed; 1220 1221#define HTT_RX_RING_TLV_DROP_THRESHOLD_VALUE 32 1222#define HTT_RX_RING_DEFAULT_DMA_LENGTH 0x7 1223#define HTT_RX_RING_PKT_TLV_OFFSET 0x1 1224 1225struct htt_rx_ring_tlv_filter { 1226 u32 rx_filter; /* see htt_rx_filter_tlv_flags */ 1227 u32 pkt_filter_flags0; /* MGMT */ 1228 u32 pkt_filter_flags1; /* MGMT */ 1229 u32 pkt_filter_flags2; /* CTRL */ 1230 u32 pkt_filter_flags3; /* DATA */ 1231 bool offset_valid; 1232 u16 rx_packet_offset; 1233 u16 rx_header_offset; 1234 u16 rx_mpdu_end_offset; 1235 u16 rx_mpdu_start_offset; 1236 u16 rx_msdu_end_offset; 1237 u16 rx_msdu_start_offset; 1238 u16 rx_attn_offset; 1239 u16 rx_mpdu_start_wmask; 1240 u16 rx_mpdu_end_wmask; 1241 u32 rx_msdu_end_wmask; 1242 u32 conf_len_ctrl; 1243 u32 conf_len_mgmt; 1244 u32 conf_len_data; 1245 u16 rx_drop_threshold; 1246 bool enable_log_mgmt_type; 1247 bool enable_log_ctrl_type; 1248 bool enable_log_data_type; 1249 bool enable_rx_tlv_offset; 1250 u16 rx_tlv_offset; 1251 bool drop_threshold_valid; 1252 bool rxmon_disable; 1253}; 1254 1255#define HTT_STATS_FRAME_CTRL_TYPE_MGMT 0x0 1256#define HTT_STATS_FRAME_CTRL_TYPE_CTRL 0x1 1257#define HTT_STATS_FRAME_CTRL_TYPE_DATA 0x2 1258#define HTT_STATS_FRAME_CTRL_TYPE_RESV 0x3 1259 1260#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 1261#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 1262#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 1263#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 1264#define HTT_TX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 1265 1266#define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_RING_BUFF_SIZE GENMASK(15, 0) 1267#define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_PKT_TYPE GENMASK(18, 16) 1268#define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_MGMT GENMASK(21, 19) 1269#define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_CTRL GENMASK(24, 22) 1270#define HTT_TX_RING_SELECTION_CFG_CMD_INFO1_CONF_LEN_DATA GENMASK(27, 25) 1271 1272#define HTT_TX_RING_SELECTION_CFG_CMD_INFO2_PKT_TYPE_EN_FLAG GENMASK(2, 0) 1273 1274struct htt_tx_ring_selection_cfg_cmd { 1275 __le32 info0; 1276 __le32 info1; 1277 __le32 info2; 1278 __le32 tlv_filter_mask_in0; 1279 __le32 tlv_filter_mask_in1; 1280 __le32 tlv_filter_mask_in2; 1281 __le32 tlv_filter_mask_in3; 1282 __le32 reserved[3]; 1283} __packed; 1284 1285#define HTT_TX_RING_TLV_FILTER_MGMT_DMA_LEN GENMASK(3, 0) 1286#define HTT_TX_RING_TLV_FILTER_CTRL_DMA_LEN GENMASK(7, 4) 1287#define HTT_TX_RING_TLV_FILTER_DATA_DMA_LEN GENMASK(11, 8) 1288 1289#define HTT_TX_MON_FILTER_HYBRID_MODE \ 1290 (HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS | \ 1291 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS | \ 1292 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START | \ 1293 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END | \ 1294 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU | \ 1295 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU | \ 1296 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA | \ 1297 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA | \ 1298 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT | \ 1299 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT | \ 1300 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE | \ 1301 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO | \ 1302 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2) 1303 1304struct htt_tx_ring_tlv_filter { 1305 u32 tx_mon_downstream_tlv_flags; 1306 u32 tx_mon_upstream_tlv_flags0; 1307 u32 tx_mon_upstream_tlv_flags1; 1308 u32 tx_mon_upstream_tlv_flags2; 1309 bool tx_mon_mgmt_filter; 1310 bool tx_mon_data_filter; 1311 bool tx_mon_ctrl_filter; 1312 u16 tx_mon_pkt_dma_len; 1313} __packed; 1314 1315enum htt_tx_mon_upstream_tlv_flags0 { 1316 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_START_STATUS = BIT(1), 1317 HTT_TX_FILTER_TLV_FLAGS0_RESPONSE_END_STATUS = BIT(2), 1318 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START = BIT(3), 1319 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_END = BIT(4), 1320 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PPDU = BIT(5), 1321 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_PPDU = BIT(6), 1322 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_ACK_OR_BA = BIT(7), 1323 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_1K_BA = BIT(8), 1324 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_START_PROT = BIT(9), 1325 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_PROT = BIT(10), 1326 HTT_TX_FILTER_TLV_FLAGS0_TX_FES_STATUS_USER_RESPONSE = BIT(11), 1327 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_BITMAP_ACK = BIT(12), 1328 HTT_TX_FILTER_TLV_FLAGS0_RX_FRAME_1K_BITMAP_ACK = BIT(13), 1329 HTT_TX_FILTER_TLV_FLAGS0_COEX_TX_STATUS = BIT(14), 1330 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO = BIT(15), 1331 HTT_TX_FILTER_TLV_FLAGS0_RECEIVED_RESPONSE_INFO_PART2 = BIT(16), 1332}; 1333 1334#define HTT_TX_FILTER_TLV_FLAGS2_TXPCU_PHYTX_OTHER_TRANSMIT_INFO32 BIT(11) 1335 1336/* HTT message target->host */ 1337 1338enum htt_t2h_msg_type { 1339 HTT_T2H_MSG_TYPE_VERSION_CONF, 1340 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, 1341 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 1342 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 1343 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 1344 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 1345 HTT_T2H_MSG_TYPE_PEER_MAP2 = 0x1e, 1346 HTT_T2H_MSG_TYPE_PEER_UNMAP2 = 0x1f, 1347 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d, 1348 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c, 1349 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24, 1350 HTT_T2H_MSG_TYPE_MLO_TIMESTAMP_OFFSET_IND = 0x28, 1351 HTT_T2H_MSG_TYPE_PEER_MAP3 = 0x2b, 1352 HTT_T2H_MSG_TYPE_VDEV_TXRX_STATS_PERIODIC_IND = 0x2c, 1353}; 1354 1355#define HTT_TARGET_VERSION_MAJOR 3 1356 1357#define HTT_T2H_MSG_TYPE GENMASK(7, 0) 1358#define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8) 1359#define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16) 1360 1361struct htt_t2h_version_conf_msg { 1362 __le32 version; 1363} __packed; 1364 1365#define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8) 1366#define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16) 1367#define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0) 1368#define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16) 1369#define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0) 1370#define HTT_T2H_PEER_MAP3_INFO2_HW_PEER_ID GENMASK(15, 0) 1371#define HTT_T2H_PEER_MAP3_INFO2_AST_HASH_VAL GENMASK(31, 16) 1372#define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16) 1373#define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16 1374 1375struct htt_t2h_peer_map_event { 1376 __le32 info; 1377 __le32 mac_addr_l32; 1378 __le32 info1; 1379 __le32 info2; 1380} __packed; 1381 1382#define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID 1383#define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID 1384#define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \ 1385 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 1386#define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M 1387#define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 1388 1389struct htt_t2h_peer_unmap_event { 1390 __le32 info; 1391 __le32 mac_addr_l32; 1392 __le32 info1; 1393} __packed; 1394 1395struct htt_resp_msg { 1396 union { 1397 struct htt_t2h_version_conf_msg version_msg; 1398 struct htt_t2h_peer_map_event peer_map_ev; 1399 struct htt_t2h_peer_unmap_event peer_unmap_ev; 1400 }; 1401} __packed; 1402 1403#define HTT_VDEV_GET_STATS_U64(msg_l32, msg_u32)\ 1404 (((u64)__le32_to_cpu(msg_u32) << 32) | (__le32_to_cpu(msg_l32))) 1405#define HTT_T2H_VDEV_STATS_PERIODIC_MSG_TYPE GENMASK(7, 0) 1406#define HTT_T2H_VDEV_STATS_PERIODIC_PDEV_ID GENMASK(15, 8) 1407#define HTT_T2H_VDEV_STATS_PERIODIC_NUM_VDEV GENMASK(23, 16) 1408#define HTT_T2H_VDEV_STATS_PERIODIC_PAYLOAD_BYTES GENMASK(15, 0) 1409#define HTT_VDEV_TXRX_STATS_COMMON_TLV 0 1410#define HTT_VDEV_TXRX_STATS_HW_STATS_TLV 1 1411 1412struct htt_t2h_vdev_txrx_stats_ind { 1413 __le32 vdev_id; 1414 __le32 rx_msdu_byte_cnt_lo; 1415 __le32 rx_msdu_byte_cnt_hi; 1416 __le32 rx_msdu_cnt_lo; 1417 __le32 rx_msdu_cnt_hi; 1418 __le32 tx_msdu_byte_cnt_lo; 1419 __le32 tx_msdu_byte_cnt_hi; 1420 __le32 tx_msdu_cnt_lo; 1421 __le32 tx_msdu_cnt_hi; 1422 __le32 tx_retry_cnt_lo; 1423 __le32 tx_retry_cnt_hi; 1424 __le32 tx_retry_byte_cnt_lo; 1425 __le32 tx_retry_byte_cnt_hi; 1426 __le32 tx_drop_cnt_lo; 1427 __le32 tx_drop_cnt_hi; 1428 __le32 tx_drop_byte_cnt_lo; 1429 __le32 tx_drop_byte_cnt_hi; 1430 __le32 msdu_ttl_cnt_lo; 1431 __le32 msdu_ttl_cnt_hi; 1432 __le32 msdu_ttl_byte_cnt_lo; 1433 __le32 msdu_ttl_byte_cnt_hi; 1434} __packed; 1435 1436struct htt_t2h_vdev_common_stats_tlv { 1437 __le32 soc_drop_count_lo; 1438 __le32 soc_drop_count_hi; 1439} __packed; 1440 1441/* ppdu stats 1442 * 1443 * @details 1444 * The following field definitions describe the format of the HTT target 1445 * to host ppdu stats indication message. 1446 * 1447 * 1448 * |31 16|15 12|11 10|9 8|7 0 | 1449 * |----------------------------------------------------------------------| 1450 * | payload_size | rsvd |pdev_id|mac_id | msg type | 1451 * |----------------------------------------------------------------------| 1452 * | ppdu_id | 1453 * |----------------------------------------------------------------------| 1454 * | Timestamp in us | 1455 * |----------------------------------------------------------------------| 1456 * | reserved | 1457 * |----------------------------------------------------------------------| 1458 * | type-specific stats info | 1459 * | (see htt_ppdu_stats.h) | 1460 * |----------------------------------------------------------------------| 1461 * Header fields: 1462 * - MSG_TYPE 1463 * Bits 7:0 1464 * Purpose: Identifies this is a PPDU STATS indication 1465 * message. 1466 * Value: 0x1d 1467 * - mac_id 1468 * Bits 9:8 1469 * Purpose: mac_id of this ppdu_id 1470 * Value: 0-3 1471 * - pdev_id 1472 * Bits 11:10 1473 * Purpose: pdev_id of this ppdu_id 1474 * Value: 0-3 1475 * 0 (for rings at SOC level), 1476 * 1/2/3 PDEV -> 0/1/2 1477 * - payload_size 1478 * Bits 31:16 1479 * Purpose: total tlv size 1480 * Value: payload_size in bytes 1481 */ 1482 1483#define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10) 1484#define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16) 1485 1486struct ath12k_htt_ppdu_stats_msg { 1487 __le32 info; 1488 __le32 ppdu_id; 1489 __le32 timestamp; 1490 __le32 rsvd; 1491 u8 data[]; 1492} __packed; 1493 1494struct htt_tlv { 1495 __le32 header; 1496 u8 value[]; 1497} __packed; 1498 1499#define HTT_TLV_TAG GENMASK(11, 0) 1500#define HTT_TLV_LEN GENMASK(23, 12) 1501 1502enum HTT_PPDU_STATS_BW { 1503 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0, 1504 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1, 1505 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2, 1506 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3, 1507 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4, 1508 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */ 1509 HTT_PPDU_STATS_BANDWIDTH_DYN = 6, 1510}; 1511 1512#define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0) 1513#define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8) 1514/* bw - HTT_PPDU_STATS_BW */ 1515#define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16) 1516 1517struct htt_ppdu_stats_common { 1518 __le32 ppdu_id; 1519 __le16 sched_cmdid; 1520 u8 ring_id; 1521 u8 num_users; 1522 __le32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/ 1523 __le32 chain_mask; 1524 __le32 fes_duration_us; /* frame exchange sequence */ 1525 __le32 ppdu_sch_eval_start_tstmp_us; 1526 __le32 ppdu_sch_end_tstmp_us; 1527 __le32 ppdu_start_tstmp_us; 1528 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted 1529 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted 1530 */ 1531 __le16 phy_mode; 1532 __le16 bw_mhz; 1533} __packed; 1534 1535enum htt_ppdu_stats_gi { 1536 HTT_PPDU_STATS_SGI_0_8_US, 1537 HTT_PPDU_STATS_SGI_0_4_US, 1538 HTT_PPDU_STATS_SGI_1_6_US, 1539 HTT_PPDU_STATS_SGI_3_2_US, 1540}; 1541 1542#define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0) 1543#define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4) 1544 1545enum HTT_PPDU_STATS_PPDU_TYPE { 1546 HTT_PPDU_STATS_PPDU_TYPE_SU, 1547 HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO, 1548 HTT_PPDU_STATS_PPDU_TYPE_MU_OFDMA, 1549 HTT_PPDU_STATS_PPDU_TYPE_MU_MIMO_OFDMA, 1550 HTT_PPDU_STATS_PPDU_TYPE_UL_TRIG, 1551 HTT_PPDU_STATS_PPDU_TYPE_BURST_BCN, 1552 HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_RESP, 1553 HTT_PPDU_STATS_PPDU_TYPE_UL_BSR_TRIG, 1554 HTT_PPDU_STATS_PPDU_TYPE_UL_RESP, 1555 HTT_PPDU_STATS_PPDU_TYPE_MAX 1556}; 1557 1558#define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0) 1559#define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1) 1560 1561#define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1562#define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2) 1563#define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3) 1564#define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4) 1565#define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8) 1566#define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12) 1567#define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16) 1568#define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20) 1569#define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24) 1570#define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28) 1571#define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29) 1572 1573#define HTT_USR_RATE_PPDU_TYPE(_val) \ 1574 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M) 1575#define HTT_USR_RATE_PREAMBLE(_val) \ 1576 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M) 1577#define HTT_USR_RATE_BW(_val) \ 1578 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M) 1579#define HTT_USR_RATE_NSS(_val) \ 1580 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M) 1581#define HTT_USR_RATE_MCS(_val) \ 1582 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M) 1583#define HTT_USR_RATE_GI(_val) \ 1584 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M) 1585#define HTT_USR_RATE_DCM(_val) \ 1586 le32_get_bits(_val, HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M) 1587 1588#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1589#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2) 1590#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3) 1591#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4) 1592#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8) 1593#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12) 1594#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16) 1595#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20) 1596#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24) 1597#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28) 1598#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29) 1599 1600struct htt_ppdu_stats_user_rate { 1601 u8 tid_num; 1602 u8 reserved0; 1603 __le16 sw_peer_id; 1604 __le32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/ 1605 __le16 ru_end; 1606 __le16 ru_start; 1607 __le16 resp_ru_end; 1608 __le16 resp_ru_start; 1609 __le32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */ 1610 __le32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */ 1611 /* Note: resp_rate_info is only valid for if resp_type is UL */ 1612 __le32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */ 1613} __packed; 1614 1615#define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0) 1616#define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8) 1617#define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9) 1618#define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11) 1619#define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14) 1620#define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16) 1621 1622#define HTT_TX_INFO_IS_AMSDU(_flags) \ 1623 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M) 1624#define HTT_TX_INFO_BA_ACK_FAILED(_flags) \ 1625 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M) 1626#define HTT_TX_INFO_RATECODE(_flags) \ 1627 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M) 1628#define HTT_TX_INFO_PEERID(_flags) \ 1629 u32_get_bits(_flags, HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M) 1630 1631enum htt_ppdu_stats_usr_compln_status { 1632 HTT_PPDU_STATS_USER_STATUS_OK, 1633 HTT_PPDU_STATS_USER_STATUS_FILTERED, 1634 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT, 1635 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH, 1636 HTT_PPDU_STATS_USER_STATUS_ABORT, 1637}; 1638 1639#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0) 1640#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4) 1641#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8) 1642#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9) 1643 1644#define HTT_USR_CMPLTN_IS_AMPDU(_val) \ 1645 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M) 1646#define HTT_USR_CMPLTN_LONG_RETRY(_val) \ 1647 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M) 1648#define HTT_USR_CMPLTN_SHORT_RETRY(_val) \ 1649 le32_get_bits(_val, HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M) 1650 1651struct htt_ppdu_stats_usr_cmpltn_cmn { 1652 u8 status; 1653 u8 tid_num; 1654 __le16 sw_peer_id; 1655 /* RSSI value of last ack packet (units = dB above noise floor) */ 1656 __le32 ack_rssi; 1657 __le16 mpdu_tried; 1658 __le16 mpdu_success; 1659 __le32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/ 1660} __packed; 1661 1662#define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0) 1663#define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9) 1664#define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25) 1665 1666#define HTT_PPDU_STATS_NON_QOS_TID 16 1667 1668struct htt_ppdu_stats_usr_cmpltn_ack_ba_status { 1669 __le32 ppdu_id; 1670 __le16 sw_peer_id; 1671 __le16 reserved0; 1672 __le32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */ 1673 __le16 current_seq; 1674 __le16 start_seq; 1675 __le32 success_bytes; 1676} __packed; 1677 1678struct htt_ppdu_user_stats { 1679 u16 peer_id; 1680 u16 delay_ba; 1681 u32 tlv_flags; 1682 bool is_valid_peer_id; 1683 struct htt_ppdu_stats_user_rate rate; 1684 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn; 1685 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba; 1686}; 1687 1688#define HTT_PPDU_STATS_MAX_USERS 8 1689#define HTT_PPDU_DESC_MAX_DEPTH 16 1690 1691struct htt_ppdu_stats { 1692 struct htt_ppdu_stats_common common; 1693 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS]; 1694}; 1695 1696struct htt_ppdu_stats_info { 1697 u32 tlv_bitmap; 1698 u32 ppdu_id; 1699 u32 frame_type; 1700 u32 frame_ctrl; 1701 u32 delay_ba; 1702 u32 bar_num_users; 1703 struct htt_ppdu_stats ppdu_stats; 1704 struct list_head list; 1705}; 1706 1707/* @brief target -> host MLO offset indiciation message 1708 * 1709 * @details 1710 * The following field definitions describe the format of the HTT target 1711 * to host mlo offset indication message. 1712 * 1713 * 1714 * |31 29|28 |26|25 22|21 16|15 13|12 10 |9 8|7 0| 1715 * |---------------------------------------------------------------------| 1716 * | rsvd1 | mac_freq |chip_id |pdev_id|msgtype| 1717 * |---------------------------------------------------------------------| 1718 * | sync_timestamp_lo_us | 1719 * |---------------------------------------------------------------------| 1720 * | sync_timestamp_hi_us | 1721 * |---------------------------------------------------------------------| 1722 * | mlo_offset_lo | 1723 * |---------------------------------------------------------------------| 1724 * | mlo_offset_hi | 1725 * |---------------------------------------------------------------------| 1726 * | mlo_offset_clcks | 1727 * |---------------------------------------------------------------------| 1728 * | rsvd2 | mlo_comp_clks |mlo_comp_us | 1729 * |---------------------------------------------------------------------| 1730 * | rsvd3 |mlo_comp_timer | 1731 * |---------------------------------------------------------------------| 1732 * Header fields 1733 * - MSG_TYPE 1734 * Bits 7:0 1735 * Purpose: Identifies this is a MLO offset indication msg 1736 * - PDEV_ID 1737 * Bits 9:8 1738 * Purpose: Pdev of this MLO offset 1739 * - CHIP_ID 1740 * Bits 12:10 1741 * Purpose: chip_id of this MLO offset 1742 * - MAC_FREQ 1743 * Bits 28:13 1744 * - SYNC_TIMESTAMP_LO_US 1745 * Purpose: clock frequency of the mac HW block in MHz 1746 * Bits: 31:0 1747 * Purpose: lower 32 bits of the WLAN global time stamp at which 1748 * last sync interrupt was received 1749 * - SYNC_TIMESTAMP_HI_US 1750 * Bits: 31:0 1751 * Purpose: upper 32 bits of WLAN global time stamp at which 1752 * last sync interrupt was received 1753 * - MLO_OFFSET_LO 1754 * Bits: 31:0 1755 * Purpose: lower 32 bits of the MLO offset in us 1756 * - MLO_OFFSET_HI 1757 * Bits: 31:0 1758 * Purpose: upper 32 bits of the MLO offset in us 1759 * - MLO_COMP_US 1760 * Bits: 15:0 1761 * Purpose: MLO time stamp compensation applied in us 1762 * - MLO_COMP_CLCKS 1763 * Bits: 25:16 1764 * Purpose: MLO time stamp compensation applied in clock ticks 1765 * - MLO_COMP_TIMER 1766 * Bits: 21:0 1767 * Purpose: Periodic timer at which compensation is applied 1768 */ 1769 1770#define HTT_T2H_MLO_OFFSET_INFO_MSG_TYPE GENMASK(7, 0) 1771#define HTT_T2H_MLO_OFFSET_INFO_PDEV_ID GENMASK(9, 8) 1772 1773struct ath12k_htt_mlo_offset_msg { 1774 __le32 info; 1775 __le32 sync_timestamp_lo_us; 1776 __le32 sync_timestamp_hi_us; 1777 __le32 mlo_offset_hi; 1778 __le32 mlo_offset_lo; 1779 __le32 mlo_offset_clks; 1780 __le32 mlo_comp_clks; 1781 __le32 mlo_comp_timer; 1782} __packed; 1783 1784/* @brief host -> target FW extended statistics retrieve 1785 * 1786 * @details 1787 * The following field definitions describe the format of the HTT host 1788 * to target FW extended stats retrieve message. 1789 * The message specifies the type of stats the host wants to retrieve. 1790 * 1791 * |31 24|23 16|15 8|7 0| 1792 * |-----------------------------------------------------------| 1793 * | reserved | stats type | pdev_mask | msg type | 1794 * |-----------------------------------------------------------| 1795 * | config param [0] | 1796 * |-----------------------------------------------------------| 1797 * | config param [1] | 1798 * |-----------------------------------------------------------| 1799 * | config param [2] | 1800 * |-----------------------------------------------------------| 1801 * | config param [3] | 1802 * |-----------------------------------------------------------| 1803 * | reserved | 1804 * |-----------------------------------------------------------| 1805 * | cookie LSBs | 1806 * |-----------------------------------------------------------| 1807 * | cookie MSBs | 1808 * |-----------------------------------------------------------| 1809 * Header fields: 1810 * - MSG_TYPE 1811 * Bits 7:0 1812 * Purpose: identifies this is a extended stats upload request message 1813 * Value: 0x10 1814 * - PDEV_MASK 1815 * Bits 8:15 1816 * Purpose: identifies the mask of PDEVs to retrieve stats from 1817 * Value: This is a overloaded field, refer to usage and interpretation of 1818 * PDEV in interface document. 1819 * Bit 8 : Reserved for SOC stats 1820 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 1821 * Indicates MACID_MASK in DBS 1822 * - STATS_TYPE 1823 * Bits 23:16 1824 * Purpose: identifies which FW statistics to upload 1825 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h) 1826 * - Reserved 1827 * Bits 31:24 1828 * - CONFIG_PARAM [0] 1829 * Bits 31:0 1830 * Purpose: give an opaque configuration value to the specified stats type 1831 * Value: stats-type specific configuration value 1832 * Refer to htt_stats.h for interpretation for each stats sub_type 1833 * - CONFIG_PARAM [1] 1834 * Bits 31:0 1835 * Purpose: give an opaque configuration value to the specified stats type 1836 * Value: stats-type specific configuration value 1837 * Refer to htt_stats.h for interpretation for each stats sub_type 1838 * - CONFIG_PARAM [2] 1839 * Bits 31:0 1840 * Purpose: give an opaque configuration value to the specified stats type 1841 * Value: stats-type specific configuration value 1842 * Refer to htt_stats.h for interpretation for each stats sub_type 1843 * - CONFIG_PARAM [3] 1844 * Bits 31:0 1845 * Purpose: give an opaque configuration value to the specified stats type 1846 * Value: stats-type specific configuration value 1847 * Refer to htt_stats.h for interpretation for each stats sub_type 1848 * - Reserved [31:0] for future use. 1849 * - COOKIE_LSBS 1850 * Bits 31:0 1851 * Purpose: Provide a mechanism to match a target->host stats confirmation 1852 * message with its preceding host->target stats request message. 1853 * Value: LSBs of the opaque cookie specified by the host-side requestor 1854 * - COOKIE_MSBS 1855 * Bits 31:0 1856 * Purpose: Provide a mechanism to match a target->host stats confirmation 1857 * message with its preceding host->target stats request message. 1858 * Value: MSBs of the opaque cookie specified by the host-side requestor 1859 */ 1860 1861struct htt_ext_stats_cfg_hdr { 1862 u8 msg_type; 1863 u8 pdev_mask; 1864 u8 stats_type; 1865 u8 reserved; 1866} __packed; 1867 1868struct htt_ext_stats_cfg_cmd { 1869 struct htt_ext_stats_cfg_hdr hdr; 1870 __le32 cfg_param0; 1871 __le32 cfg_param1; 1872 __le32 cfg_param2; 1873 __le32 cfg_param3; 1874 __le32 reserved; 1875 __le32 cookie_lsb; 1876 __le32 cookie_msb; 1877} __packed; 1878 1879/* htt stats config default params */ 1880#define HTT_STAT_DEFAULT_RESET_START_OFFSET 0 1881#define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff 1882#define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff 1883#define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff 1884#define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff 1885#define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff 1886#define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00 1887#define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00 1888 1889/* HTT_DBG_EXT_STATS_PEER_INFO 1890 * PARAMS: 1891 * @config_param0: 1892 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request 1893 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t 1894 * [Bit31 : Bit16] sw_peer_id 1895 * @config_param1: 1896 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum) 1897 * 0 bit htt_peer_stats_cmn_tlv 1898 * 1 bit htt_peer_details_tlv 1899 * 2 bit htt_tx_peer_rate_stats_tlv 1900 * 3 bit htt_rx_peer_rate_stats_tlv 1901 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv 1902 * 5 bit htt_rx_tid_stats_tlv 1903 * 6 bit htt_msdu_flow_stats_tlv 1904 * @config_param2: [Bit31 : Bit0] mac_addr31to0 1905 * @config_param3: [Bit15 : Bit0] mac_addr47to32 1906 * [Bit31 : Bit16] reserved 1907 */ 1908#define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0) 1909#define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f 1910 1911/* Used to set different configs to the specified stats type.*/ 1912struct htt_ext_stats_cfg_params { 1913 u32 cfg0; 1914 u32 cfg1; 1915 u32 cfg2; 1916 u32 cfg3; 1917}; 1918 1919enum vdev_stats_offload_timer_duration { 1920 ATH12K_STATS_TIMER_DUR_500MS = 1, 1921 ATH12K_STATS_TIMER_DUR_1SEC = 2, 1922 ATH12K_STATS_TIMER_DUR_2SEC = 3, 1923}; 1924 1925#define ATH12K_HTT_MAC_ADDR_L32_0 GENMASK(7, 0) 1926#define ATH12K_HTT_MAC_ADDR_L32_1 GENMASK(15, 8) 1927#define ATH12K_HTT_MAC_ADDR_L32_2 GENMASK(23, 16) 1928#define ATH12K_HTT_MAC_ADDR_L32_3 GENMASK(31, 24) 1929#define ATH12K_HTT_MAC_ADDR_H16_0 GENMASK(7, 0) 1930#define ATH12K_HTT_MAC_ADDR_H16_1 GENMASK(15, 8) 1931 1932struct htt_mac_addr { 1933 __le32 mac_addr_l32; 1934 __le32 mac_addr_h16; 1935} __packed; 1936 1937static inline void ath12k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr) 1938{ 1939 memcpy(addr, &addr_l32, 4); 1940 memcpy(addr + 4, &addr_h16, ETH_ALEN - 4); 1941} 1942 1943int ath12k_dp_service_srng(struct ath12k_base *ab, 1944 struct ath12k_ext_irq_grp *irq_grp, 1945 int budget); 1946int ath12k_dp_htt_connect(struct ath12k_dp *dp); 1947void ath12k_dp_vdev_tx_attach(struct ath12k *ar, struct ath12k_link_vif *arvif); 1948void ath12k_dp_free(struct ath12k_base *ab); 1949int ath12k_dp_alloc(struct ath12k_base *ab); 1950void ath12k_dp_cc_config(struct ath12k_base *ab); 1951void ath12k_dp_partner_cc_init(struct ath12k_base *ab); 1952int ath12k_dp_pdev_alloc(struct ath12k_base *ab); 1953void ath12k_dp_pdev_pre_alloc(struct ath12k *ar); 1954void ath12k_dp_pdev_free(struct ath12k_base *ab); 1955int ath12k_dp_tx_htt_srng_setup(struct ath12k_base *ab, u32 ring_id, 1956 int mac_id, enum hal_ring_type ring_type); 1957int ath12k_dp_peer_setup(struct ath12k *ar, int vdev_id, const u8 *addr); 1958void ath12k_dp_peer_cleanup(struct ath12k *ar, int vdev_id, const u8 *addr); 1959void ath12k_dp_srng_cleanup(struct ath12k_base *ab, struct dp_srng *ring); 1960int ath12k_dp_srng_setup(struct ath12k_base *ab, struct dp_srng *ring, 1961 enum hal_ring_type type, int ring_num, 1962 int mac_id, int num_entries); 1963void ath12k_dp_link_desc_cleanup(struct ath12k_base *ab, 1964 struct dp_link_desc_bank *desc_bank, 1965 u32 ring_type, struct dp_srng *ring); 1966int ath12k_dp_link_desc_setup(struct ath12k_base *ab, 1967 struct dp_link_desc_bank *link_desc_banks, 1968 u32 ring_type, struct hal_srng *srng, 1969 u32 n_link_desc); 1970struct ath12k_rx_desc_info *ath12k_dp_get_rx_desc(struct ath12k_base *ab, 1971 u32 cookie); 1972struct ath12k_tx_desc_info *ath12k_dp_get_tx_desc(struct ath12k_base *ab, 1973 u32 desc_id); 1974bool ath12k_dp_wmask_compaction_rx_tlv_supported(struct ath12k_base *ab); 1975void ath12k_dp_hal_rx_desc_init(struct ath12k_base *ab); 1976#endif
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