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debugfs_htt_stats.h
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linux-6.19.14/drivers/net/wireless/ath/ath12k/debugfs_htt_stats.h
1/* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2/* 3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7#ifndef DEBUG_HTT_STATS_H 8#define DEBUG_HTT_STATS_H 9 10#define ATH12K_HTT_STATS_BUF_SIZE (1024 * 512) 11#define ATH12K_HTT_STATS_COOKIE_LSB GENMASK_ULL(31, 0) 12#define ATH12K_HTT_STATS_COOKIE_MSB GENMASK_ULL(63, 32) 13#define ATH12K_HTT_STATS_MAGIC_VALUE 0xF0F0F0F0 14#define ATH12K_HTT_STATS_SUBTYPE_MAX 16 15#define ATH12K_HTT_MAX_STRING_LEN 256 16 17#define ATH12K_HTT_STATS_RESET_BITMAP32_OFFSET(_idx) ((_idx) & 0x1f) 18#define ATH12K_HTT_STATS_RESET_BITMAP64_OFFSET(_idx) ((_idx) & 0x3f) 19#define ATH12K_HTT_STATS_RESET_BITMAP32_BIT(_idx) (1 << \ 20 ATH12K_HTT_STATS_RESET_BITMAP32_OFFSET(_idx)) 21#define ATH12K_HTT_STATS_RESET_BITMAP64_BIT(_idx) (1 << \ 22 ATH12K_HTT_STATS_RESET_BITMAP64_OFFSET(_idx)) 23 24void ath12k_debugfs_htt_stats_register(struct ath12k *ar); 25 26#ifdef CONFIG_ATH12K_DEBUGFS 27void ath12k_debugfs_htt_ext_stats_handler(struct ath12k_base *ab, 28 struct sk_buff *skb); 29#else /* CONFIG_ATH12K_DEBUGFS */ 30static inline void ath12k_debugfs_htt_ext_stats_handler(struct ath12k_base *ab, 31 struct sk_buff *skb) 32{ 33} 34#endif 35 36/** 37 * DOC: target -> host extended statistics upload 38 * 39 * The following field definitions describe the format of the HTT 40 * target to host stats upload confirmation message. 41 * The message contains a cookie echoed from the HTT host->target stats 42 * upload request, which identifies which request the confirmation is 43 * for, and a single stats can span over multiple HTT stats indication 44 * due to the HTT message size limitation so every HTT ext stats 45 * indication will have tag-length-value stats information elements. 46 * The tag-length header for each HTT stats IND message also includes a 47 * status field, to indicate whether the request for the stat type in 48 * question was fully met, partially met, unable to be met, or invalid 49 * (if the stat type in question is disabled in the target). 50 * A Done bit 1's indicate the end of the of stats info elements. 51 * 52 * 53 * |31 16|15 12|11|10 8|7 5|4 0| 54 * |--------------------------------------------------------------| 55 * | reserved | msg type | 56 * |--------------------------------------------------------------| 57 * | cookie LSBs | 58 * |--------------------------------------------------------------| 59 * | cookie MSBs | 60 * |--------------------------------------------------------------| 61 * | stats entry length | rsvd | D| S | stat type | 62 * |--------------------------------------------------------------| 63 * | type-specific stats info | 64 * | (see debugfs_htt_stats.h) | 65 * |--------------------------------------------------------------| 66 * Header fields: 67 * - MSG_TYPE 68 * Bits 7:0 69 * Purpose: Identifies this is a extended statistics upload confirmation 70 * message. 71 * Value: 0x1c 72 * - COOKIE_LSBS 73 * Bits 31:0 74 * Purpose: Provide a mechanism to match a target->host stats confirmation 75 * message with its preceding host->target stats request message. 76 * Value: MSBs of the opaque cookie specified by the host-side requestor 77 * - COOKIE_MSBS 78 * Bits 31:0 79 * Purpose: Provide a mechanism to match a target->host stats confirmation 80 * message with its preceding host->target stats request message. 81 * Value: MSBs of the opaque cookie specified by the host-side requestor 82 * 83 * Stats Information Element tag-length header fields: 84 * - STAT_TYPE 85 * Bits 7:0 86 * Purpose: identifies the type of statistics info held in the 87 * following information element 88 * Value: ath12k_dbg_htt_ext_stats_type 89 * - STATUS 90 * Bits 10:8 91 * Purpose: indicate whether the requested stats are present 92 * Value: 93 * 0 -> The requested stats have been delivered in full 94 * 1 -> The requested stats have been delivered in part 95 * 2 -> The requested stats could not be delivered (error case) 96 * 3 -> The requested stat type is either not recognized (invalid) 97 * - DONE 98 * Bits 11 99 * Purpose: 100 * Indicates the completion of the stats entry, this will be the last 101 * stats conf HTT segment for the requested stats type. 102 * Value: 103 * 0 -> the stats retrieval is ongoing 104 * 1 -> the stats retrieval is complete 105 * - LENGTH 106 * Bits 31:16 107 * Purpose: indicate the stats information size 108 * Value: This field specifies the number of bytes of stats information 109 * that follows the element tag-length header. 110 * It is expected but not required that this length is a multiple of 111 * 4 bytes. 112 */ 113 114#define ATH12K_HTT_T2H_EXT_STATS_INFO1_DONE BIT(11) 115#define ATH12K_HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16) 116 117struct ath12k_htt_extd_stats_msg { 118 __le32 info0; 119 __le64 cookie; 120 __le32 info1; 121 u8 data[]; 122} __packed; 123 124/* htt_dbg_ext_stats_type */ 125enum ath12k_dbg_htt_ext_stats_type { 126 ATH12K_DBG_HTT_EXT_STATS_RESET = 0, 127 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX = 1, 128 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_SCHED = 4, 129 ATH12K_DBG_HTT_EXT_STATS_PDEV_ERROR = 5, 130 ATH12K_DBG_HTT_EXT_STATS_PDEV_TQM = 6, 131 ATH12K_DBG_HTT_EXT_STATS_TX_DE_INFO = 8, 132 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_RATE = 9, 133 ATH12K_DBG_HTT_EXT_STATS_PDEV_RX_RATE = 10, 134 ATH12K_DBG_HTT_EXT_STATS_TX_SELFGEN_INFO = 12, 135 ATH12K_DBG_HTT_EXT_STATS_SRNG_INFO = 15, 136 ATH12K_DBG_HTT_EXT_STATS_SFM_INFO = 16, 137 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_MU = 17, 138 ATH12K_DBG_HTT_EXT_STATS_PDEV_CCA_STATS = 19, 139 ATH12K_DBG_HTT_EXT_STATS_TX_SOUNDING_INFO = 22, 140 ATH12K_DBG_HTT_EXT_STATS_PDEV_OBSS_PD_STATS = 23, 141 ATH12K_DBG_HTT_EXT_STATS_LATENCY_PROF_STATS = 25, 142 ATH12K_DBG_HTT_EXT_STATS_PDEV_UL_TRIG_STATS = 26, 143 ATH12K_DBG_HTT_EXT_STATS_PDEV_UL_MUMIMO_TRIG_STATS = 27, 144 ATH12K_DBG_HTT_EXT_STATS_FSE_RX = 28, 145 ATH12K_DBG_HTT_EXT_STATS_PDEV_RX_RATE_EXT = 30, 146 ATH12K_DBG_HTT_EXT_STATS_PDEV_TX_RATE_TXBF = 31, 147 ATH12K_DBG_HTT_EXT_STATS_TXBF_OFDMA = 32, 148 ATH12K_DBG_HTT_EXT_STATS_DLPAGER_STATS = 36, 149 ATH12K_DBG_HTT_EXT_PHY_COUNTERS_AND_PHY_STATS = 37, 150 ATH12K_DBG_HTT_EXT_VDEVS_TXRX_STATS = 38, 151 ATH12K_DBG_HTT_EXT_PDEV_PER_STATS = 40, 152 ATH12K_DBG_HTT_EXT_AST_ENTRIES = 41, 153 ATH12K_DBG_HTT_EXT_STATS_SOC_ERROR = 45, 154 ATH12K_DBG_HTT_DBG_PDEV_PUNCTURE_STATS = 46, 155 ATH12K_DBG_HTT_EXT_STATS_PDEV_SCHED_ALGO = 49, 156 ATH12K_DBG_HTT_EXT_STATS_MANDATORY_MUOFDMA = 51, 157 ATH12K_DGB_HTT_EXT_STATS_PDEV_MBSSID_CTRL_FRAME = 54, 158 ATH12K_DBG_HTT_PDEV_TDMA_STATS = 57, 159 ATH12K_DBG_HTT_MLO_SCHED_STATS = 63, 160 ATH12K_DBG_HTT_PDEV_MLO_IPC_STATS = 64, 161 ATH12K_DBG_HTT_EXT_PDEV_RTT_RESP_STATS = 65, 162 ATH12K_DBG_HTT_EXT_PDEV_RTT_INITIATOR_STATS = 66, 163 164 /* keep this last */ 165 ATH12K_DBG_HTT_NUM_EXT_STATS, 166}; 167 168enum ath12k_dbg_htt_tlv_tag { 169 HTT_STATS_TX_PDEV_CMN_TAG = 0, 170 HTT_STATS_TX_PDEV_UNDERRUN_TAG = 1, 171 HTT_STATS_TX_PDEV_SIFS_TAG = 2, 172 HTT_STATS_TX_PDEV_FLUSH_TAG = 3, 173 HTT_STATS_STRING_TAG = 5, 174 HTT_STATS_TX_TQM_GEN_MPDU_TAG = 11, 175 HTT_STATS_TX_TQM_LIST_MPDU_TAG = 12, 176 HTT_STATS_TX_TQM_LIST_MPDU_CNT_TAG = 13, 177 HTT_STATS_TX_TQM_CMN_TAG = 14, 178 HTT_STATS_TX_TQM_PDEV_TAG = 15, 179 HTT_STATS_TX_DE_EAPOL_PACKETS_TAG = 17, 180 HTT_STATS_TX_DE_CLASSIFY_FAILED_TAG = 18, 181 HTT_STATS_TX_DE_CLASSIFY_STATS_TAG = 19, 182 HTT_STATS_TX_DE_CLASSIFY_STATUS_TAG = 20, 183 HTT_STATS_TX_DE_ENQUEUE_PACKETS_TAG = 21, 184 HTT_STATS_TX_DE_ENQUEUE_DISCARD_TAG = 22, 185 HTT_STATS_TX_DE_CMN_TAG = 23, 186 HTT_STATS_TX_PDEV_MU_MIMO_STATS_TAG = 25, 187 HTT_STATS_SFM_CMN_TAG = 26, 188 HTT_STATS_SRING_STATS_TAG = 27, 189 HTT_STATS_TX_PDEV_RATE_STATS_TAG = 34, 190 HTT_STATS_RX_PDEV_RATE_STATS_TAG = 35, 191 HTT_STATS_TX_PDEV_SCHEDULER_TXQ_STATS_TAG = 36, 192 HTT_STATS_TX_SCHED_CMN_TAG = 37, 193 HTT_STATS_SCHED_TXQ_CMD_POSTED_TAG = 39, 194 HTT_STATS_SFM_CLIENT_USER_TAG = 41, 195 HTT_STATS_SFM_CLIENT_TAG = 42, 196 HTT_STATS_TX_TQM_ERROR_STATS_TAG = 43, 197 HTT_STATS_SCHED_TXQ_CMD_REAPED_TAG = 44, 198 HTT_STATS_TX_SELFGEN_AC_ERR_STATS_TAG = 46, 199 HTT_STATS_TX_SELFGEN_CMN_STATS_TAG = 47, 200 HTT_STATS_TX_SELFGEN_AC_STATS_TAG = 48, 201 HTT_STATS_TX_SELFGEN_AX_STATS_TAG = 49, 202 HTT_STATS_TX_SELFGEN_AX_ERR_STATS_TAG = 50, 203 HTT_STATS_HW_INTR_MISC_TAG = 54, 204 HTT_STATS_HW_PDEV_ERRS_TAG = 56, 205 HTT_STATS_TX_DE_COMPL_STATS_TAG = 65, 206 HTT_STATS_WHAL_TX_TAG = 66, 207 HTT_STATS_TX_PDEV_SIFS_HIST_TAG = 67, 208 HTT_STATS_PDEV_CCA_1SEC_HIST_TAG = 70, 209 HTT_STATS_PDEV_CCA_100MSEC_HIST_TAG = 71, 210 HTT_STATS_PDEV_CCA_STAT_CUMULATIVE_TAG = 72, 211 HTT_STATS_PDEV_CCA_COUNTERS_TAG = 73, 212 HTT_STATS_TX_PDEV_MPDU_STATS_TAG = 74, 213 HTT_STATS_TX_SOUNDING_STATS_TAG = 80, 214 HTT_STATS_SCHED_TXQ_SCHED_ORDER_SU_TAG = 86, 215 HTT_STATS_SCHED_TXQ_SCHED_INELIGIBILITY_TAG = 87, 216 HTT_STATS_PDEV_OBSS_PD_TAG = 88, 217 HTT_STATS_HW_WAR_TAG = 89, 218 HTT_STATS_LATENCY_PROF_STATS_TAG = 91, 219 HTT_STATS_LATENCY_CTX_TAG = 92, 220 HTT_STATS_LATENCY_CNT_TAG = 93, 221 HTT_STATS_RX_PDEV_UL_TRIG_STATS_TAG = 94, 222 HTT_STATS_RX_PDEV_UL_OFDMA_USER_STATS_TAG = 95, 223 HTT_STATS_RX_PDEV_UL_MUMIMO_TRIG_STATS_TAG = 97, 224 HTT_STATS_RX_FSE_STATS_TAG = 98, 225 HTT_STATS_SCHED_TXQ_SUPERCYCLE_TRIGGER_TAG = 100, 226 HTT_STATS_PDEV_CTRL_PATH_TX_STATS_TAG = 102, 227 HTT_STATS_RX_PDEV_RATE_EXT_STATS_TAG = 103, 228 HTT_STATS_PDEV_TX_RATE_TXBF_STATS_TAG = 108, 229 HTT_STATS_TX_SELFGEN_AC_SCHED_STATUS_STATS_TAG = 111, 230 HTT_STATS_TX_SELFGEN_AX_SCHED_STATUS_STATS_TAG = 112, 231 HTT_STATS_DLPAGER_STATS_TAG = 120, 232 HTT_STATS_PHY_COUNTERS_TAG = 121, 233 HTT_STATS_PHY_STATS_TAG = 122, 234 HTT_STATS_PHY_RESET_COUNTERS_TAG = 123, 235 HTT_STATS_PHY_RESET_STATS_TAG = 124, 236 HTT_STATS_SOC_TXRX_STATS_COMMON_TAG = 125, 237 HTT_STATS_PER_RATE_STATS_TAG = 128, 238 HTT_STATS_MU_PPDU_DIST_TAG = 129, 239 HTT_STATS_TX_PDEV_MUMIMO_GRP_STATS_TAG = 130, 240 HTT_STATS_AST_ENTRY_TAG = 132, 241 HTT_STATS_TX_PDEV_RATE_STATS_BE_OFDMA_TAG = 135, 242 HTT_STATS_TX_SELFGEN_BE_ERR_STATS_TAG = 137, 243 HTT_STATS_TX_SELFGEN_BE_STATS_TAG = 138, 244 HTT_STATS_TX_SELFGEN_BE_SCHED_STATUS_STATS_TAG = 139, 245 HTT_STATS_TX_PDEV_HISTOGRAM_STATS_TAG = 144, 246 HTT_STATS_TXBF_OFDMA_AX_NDPA_STATS_TAG = 147, 247 HTT_STATS_TXBF_OFDMA_AX_NDP_STATS_TAG = 148, 248 HTT_STATS_TXBF_OFDMA_AX_BRP_STATS_TAG = 149, 249 HTT_STATS_TXBF_OFDMA_AX_STEER_STATS_TAG = 150, 250 HTT_STATS_DMAC_RESET_STATS_TAG = 155, 251 HTT_STATS_PHY_TPC_STATS_TAG = 157, 252 HTT_STATS_PDEV_PUNCTURE_STATS_TAG = 158, 253 HTT_STATS_PDEV_SCHED_ALGO_OFDMA_STATS_TAG = 165, 254 HTT_STATS_TXBF_OFDMA_AX_STEER_MPDU_STATS_TAG = 172, 255 HTT_STATS_PDEV_MBSSID_CTRL_FRAME_STATS_TAG = 176, 256 HTT_STATS_PDEV_TDMA_TAG = 187, 257 HTT_STATS_MLO_SCHED_STATS_TAG = 190, 258 HTT_STATS_PDEV_MLO_IPC_STATS_TAG = 191, 259 HTT_STATS_PDEV_RTT_RESP_STATS_TAG = 194, 260 HTT_STATS_PDEV_RTT_INIT_STATS_TAG = 195, 261 HTT_STATS_PDEV_RTT_HW_STATS_TAG = 196, 262 HTT_STATS_PDEV_RTT_TBR_SELFGEN_QUEUED_STATS_TAG = 197, 263 HTT_STATS_PDEV_RTT_TBR_CMD_RESULT_STATS_TAG = 198, 264 265 HTT_STATS_MAX_TAG, 266}; 267 268#define ATH12K_HTT_STATS_MAC_ID GENMASK(7, 0) 269 270#define ATH12K_HTT_TX_PDEV_MAX_SIFS_BURST_STATS 9 271#define ATH12K_HTT_TX_PDEV_MAX_FLUSH_REASON_STATS 150 272 273/* MU MIMO distribution stats is a 2-dimensional array 274 * with dimension one denoting stats for nr4[0] or nr8[1] 275 */ 276#define ATH12K_HTT_STATS_NUM_NR_BINS 2 277#define ATH12K_HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST 10 278#define ATH12K_HTT_TX_PDEV_MAX_SIFS_BURST_HIST_STATS 10 279#define ATH12K_HTT_STATS_MAX_NUM_SCHED_STATUS 9 280#define ATH12K_HTT_STATS_NUM_SCHED_STATUS_WORDS \ 281 (ATH12K_HTT_STATS_NUM_NR_BINS * ATH12K_HTT_STATS_MAX_NUM_SCHED_STATUS) 282#define ATH12K_HTT_STATS_MU_PPDU_PER_BURST_WORDS \ 283 (ATH12K_HTT_STATS_NUM_NR_BINS * ATH12K_HTT_STATS_MAX_NUM_MU_PPDU_PER_BURST) 284 285enum ath12k_htt_tx_pdev_underrun_enum { 286 HTT_STATS_TX_PDEV_NO_DATA_UNDERRUN = 0, 287 HTT_STATS_TX_PDEV_DATA_UNDERRUN_BETWEEN_MPDU = 1, 288 HTT_STATS_TX_PDEV_DATA_UNDERRUN_WITHIN_MPDU = 2, 289 HTT_TX_PDEV_MAX_URRN_STATS = 3, 290}; 291 292enum ath12k_htt_stats_reset_cfg_param_alloc_pos { 293 ATH12K_HTT_STATS_RESET_PARAM_CFG_32_BYTES = 1, 294 ATH12K_HTT_STATS_RESET_PARAM_CFG_64_BYTES, 295 ATH12K_HTT_STATS_RESET_PARAM_CFG_128_BYTES, 296}; 297 298struct debug_htt_stats_req { 299 bool done; 300 bool override_cfg_param; 301 u8 pdev_id; 302 enum ath12k_dbg_htt_ext_stats_type type; 303 u32 cfg_param[4]; 304 u8 peer_addr[ETH_ALEN]; 305 struct completion htt_stats_rcvd; 306 u32 buf_len; 307 u8 buf[]; 308}; 309 310struct ath12k_htt_tx_pdev_stats_cmn_tlv { 311 __le32 mac_id__word; 312 __le32 hw_queued; 313 __le32 hw_reaped; 314 __le32 underrun; 315 __le32 hw_paused; 316 __le32 hw_flush; 317 __le32 hw_filt; 318 __le32 tx_abort; 319 __le32 mpdu_requed; 320 __le32 tx_xretry; 321 __le32 data_rc; 322 __le32 mpdu_dropped_xretry; 323 __le32 illgl_rate_phy_err; 324 __le32 cont_xretry; 325 __le32 tx_timeout; 326 __le32 pdev_resets; 327 __le32 phy_underrun; 328 __le32 txop_ovf; 329 __le32 seq_posted; 330 __le32 seq_failed_queueing; 331 __le32 seq_completed; 332 __le32 seq_restarted; 333 __le32 mu_seq_posted; 334 __le32 seq_switch_hw_paused; 335 __le32 next_seq_posted_dsr; 336 __le32 seq_posted_isr; 337 __le32 seq_ctrl_cached; 338 __le32 mpdu_count_tqm; 339 __le32 msdu_count_tqm; 340 __le32 mpdu_removed_tqm; 341 __le32 msdu_removed_tqm; 342 __le32 mpdus_sw_flush; 343 __le32 mpdus_hw_filter; 344 __le32 mpdus_truncated; 345 __le32 mpdus_ack_failed; 346 __le32 mpdus_expired; 347 __le32 mpdus_seq_hw_retry; 348 __le32 ack_tlv_proc; 349 __le32 coex_abort_mpdu_cnt_valid; 350 __le32 coex_abort_mpdu_cnt; 351 __le32 num_total_ppdus_tried_ota; 352 __le32 num_data_ppdus_tried_ota; 353 __le32 local_ctrl_mgmt_enqued; 354 __le32 local_ctrl_mgmt_freed; 355 __le32 local_data_enqued; 356 __le32 local_data_freed; 357 __le32 mpdu_tried; 358 __le32 isr_wait_seq_posted; 359 360 __le32 tx_active_dur_us_low; 361 __le32 tx_active_dur_us_high; 362 __le32 remove_mpdus_max_retries; 363 __le32 comp_delivered; 364 __le32 ppdu_ok; 365 __le32 self_triggers; 366 __le32 tx_time_dur_data; 367 __le32 seq_qdepth_repost_stop; 368 __le32 mu_seq_min_msdu_repost_stop; 369 __le32 seq_min_msdu_repost_stop; 370 __le32 seq_txop_repost_stop; 371 __le32 next_seq_cancel; 372 __le32 fes_offsets_err_cnt; 373 __le32 num_mu_peer_blacklisted; 374 __le32 mu_ofdma_seq_posted; 375 __le32 ul_mumimo_seq_posted; 376 __le32 ul_ofdma_seq_posted; 377 378 __le32 thermal_suspend_cnt; 379 __le32 dfs_suspend_cnt; 380 __le32 tx_abort_suspend_cnt; 381 __le32 tgt_specific_opaque_txq_suspend_info; 382 __le32 last_suspend_reason; 383} __packed; 384 385struct ath12k_htt_tx_pdev_stats_urrn_tlv { 386 DECLARE_FLEX_ARRAY(__le32, urrn_stats); 387} __packed; 388 389struct ath12k_htt_tx_pdev_stats_flush_tlv { 390 DECLARE_FLEX_ARRAY(__le32, flush_errs); 391} __packed; 392 393struct ath12k_htt_tx_pdev_stats_phy_err_tlv { 394 DECLARE_FLEX_ARRAY(__le32, phy_errs); 395} __packed; 396 397struct ath12k_htt_tx_pdev_stats_sifs_tlv { 398 DECLARE_FLEX_ARRAY(__le32, sifs_status); 399} __packed; 400 401struct ath12k_htt_pdev_ctrl_path_tx_stats_tlv { 402 __le32 fw_tx_mgmt_subtype[ATH12K_HTT_STATS_SUBTYPE_MAX]; 403} __packed; 404 405struct ath12k_htt_tx_pdev_stats_sifs_hist_tlv { 406 DECLARE_FLEX_ARRAY(__le32, sifs_hist_status); 407} __packed; 408 409enum ath12k_htt_stats_hw_mode { 410 ATH12K_HTT_STATS_HWMODE_AC = 0, 411 ATH12K_HTT_STATS_HWMODE_AX = 1, 412 ATH12K_HTT_STATS_HWMODE_BE = 2, 413}; 414 415struct ath12k_htt_tx_pdev_mu_ppdu_dist_stats_tlv { 416 __le32 hw_mode; 417 __le32 num_seq_term_status[ATH12K_HTT_STATS_NUM_SCHED_STATUS_WORDS]; 418 __le32 num_ppdu_cmpl_per_burst[ATH12K_HTT_STATS_MU_PPDU_PER_BURST_WORDS]; 419 __le32 num_seq_posted[ATH12K_HTT_STATS_NUM_NR_BINS]; 420 __le32 num_ppdu_posted_per_burst[ATH12K_HTT_STATS_MU_PPDU_PER_BURST_WORDS]; 421} __packed; 422 423#define ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS 12 424#define ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS 4 425#define ATH12K_HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS 5 426#define ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS 4 427#define ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS 8 428#define ATH12K_HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES 7 429#define ATH12K_HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4 430#define ATH12K_HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8 431#define ATH12K_HTT_TX_PDEV_STATS_NUM_LTF 4 432#define ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS 2 433#define ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS 2 434#define ATH12K_HTT_TX_PDEV_STATS_NUM_11AX_TRIGGER_TYPES 6 435#define ATH12K_HTT_TX_PDEV_STATS_NUM_PER_COUNTERS 101 436 437#define ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_DROP_COUNTERS \ 438 (ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS + \ 439 ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS + \ 440 ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS) 441 442struct ath12k_htt_tx_pdev_rate_stats_tlv { 443 __le32 mac_id_word; 444 __le32 tx_ldpc; 445 __le32 rts_cnt; 446 __le32 ack_rssi; 447 __le32 tx_mcs[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 448 __le32 tx_su_mcs[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 449 __le32 tx_mu_mcs[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 450 __le32 tx_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 451 __le32 tx_bw[ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 452 __le32 tx_stbc[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 453 __le32 tx_pream[ATH12K_HTT_TX_PDEV_STATS_NUM_PREAMBLE_TYPES]; 454 __le32 tx_gi[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 455 [ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 456 __le32 tx_dcm[ATH12K_HTT_TX_PDEV_STATS_NUM_DCM_COUNTERS]; 457 __le32 rts_success; 458 __le32 tx_legacy_cck_rate[ATH12K_HTT_TX_PDEV_STATS_NUM_LEGACY_CCK_STATS]; 459 __le32 tx_legacy_ofdm_rate[ATH12K_HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; 460 __le32 ac_mu_mimo_tx_ldpc; 461 __le32 ax_mu_mimo_tx_ldpc; 462 __le32 ofdma_tx_ldpc; 463 __le32 tx_he_ltf[ATH12K_HTT_TX_PDEV_STATS_NUM_LTF]; 464 __le32 ac_mu_mimo_tx_mcs[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 465 __le32 ax_mu_mimo_tx_mcs[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 466 __le32 ofdma_tx_mcs[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 467 __le32 ac_mu_mimo_tx_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 468 __le32 ax_mu_mimo_tx_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 469 __le32 ofdma_tx_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 470 __le32 ac_mu_mimo_tx_bw[ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 471 __le32 ax_mu_mimo_tx_bw[ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 472 __le32 ofdma_tx_bw[ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 473 __le32 ac_mu_mimo_tx_gi[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 474 [ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 475 __le32 ax_mimo_tx_gi[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 476 [ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 477 __le32 ofdma_tx_gi[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 478 [ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_COUNTERS]; 479 __le32 trigger_type_11ax[ATH12K_HTT_TX_PDEV_STATS_NUM_11AX_TRIGGER_TYPES]; 480 __le32 tx_11ax_su_ext; 481 __le32 tx_mcs_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 482 __le32 tx_stbc_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 483 __le32 tx_gi_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 484 [ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 485 __le32 ax_mu_mimo_tx_mcs_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 486 __le32 ofdma_tx_mcs_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 487 __le32 ax_tx_gi_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 488 [ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 489 __le32 ofd_tx_gi_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 490 [ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 491 __le32 tx_mcs_ext_2[ATH12K_HTT_TX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; 492 __le32 tx_bw_320mhz; 493} __packed; 494 495struct ath12k_htt_tx_histogram_stats_tlv { 496 __le32 rate_retry_mcs_drop_cnt; 497 __le32 mcs_drop_rate[ATH12K_HTT_TX_PDEV_STATS_NUM_MCS_DROP_COUNTERS]; 498 __le32 per_histogram_cnt[ATH12K_HTT_TX_PDEV_STATS_NUM_PER_COUNTERS]; 499 __le32 low_latency_rate_cnt; 500 __le32 su_burst_rate_drop_cnt; 501 __le32 su_burst_rate_drop_fail_cnt; 502} __packed; 503 504#define ATH12K_HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS 4 505#define ATH12K_HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8 506#define ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS 12 507#define ATH12K_HTT_RX_PDEV_STATS_NUM_GI_COUNTERS 4 508#define ATH12K_HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS 5 509#define ATH12K_HTT_RX_PDEV_STATS_NUM_BW_COUNTERS 4 510#define ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS 8 511#define ATH12K_HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES 7 512#define ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER 8 513#define ATH12K_HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_NSS 16 514#define ATH12K_HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS 6 515#define ATH12K_HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER 8 516#define ATH12K_HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS 2 517 518struct ath12k_htt_rx_pdev_rate_stats_tlv { 519 __le32 mac_id_word; 520 __le32 nsts; 521 __le32 rx_ldpc; 522 __le32 rts_cnt; 523 __le32 rssi_mgmt; 524 __le32 rssi_data; 525 __le32 rssi_comb; 526 __le32 rx_mcs[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 527 __le32 rx_nss[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 528 __le32 rx_dcm[ATH12K_HTT_RX_PDEV_STATS_NUM_DCM_COUNTERS]; 529 __le32 rx_stbc[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 530 __le32 rx_bw[ATH12K_HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 531 __le32 rx_pream[ATH12K_HTT_RX_PDEV_STATS_NUM_PREAMBLE_TYPES]; 532 u8 rssi_chain_in_db[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 533 [ATH12K_HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 534 __le32 rx_gi[ATH12K_HTT_RX_PDEV_STATS_NUM_GI_COUNTERS] 535 [ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 536 __le32 rssi_in_dbm; 537 __le32 rx_11ax_su_ext; 538 __le32 rx_11ac_mumimo; 539 __le32 rx_11ax_mumimo; 540 __le32 rx_11ax_ofdma; 541 __le32 txbf; 542 __le32 rx_legacy_cck_rate[ATH12K_HTT_RX_PDEV_STATS_NUM_LEGACY_CCK_STATS]; 543 __le32 rx_legacy_ofdm_rate[ATH12K_HTT_RX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; 544 __le32 rx_active_dur_us_low; 545 __le32 rx_active_dur_us_high; 546 __le32 rx_11ax_ul_ofdma; 547 __le32 ul_ofdma_rx_mcs[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 548 __le32 ul_ofdma_rx_gi[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 549 [ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 550 __le32 ul_ofdma_rx_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 551 __le32 ul_ofdma_rx_bw[ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS]; 552 __le32 ul_ofdma_rx_stbc; 553 __le32 ul_ofdma_rx_ldpc; 554 __le32 rx_ulofdma_non_data_ppdu[ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 555 __le32 rx_ulofdma_data_ppdu[ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 556 __le32 rx_ulofdma_mpdu_ok[ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 557 __le32 rx_ulofdma_mpdu_fail[ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 558 __le32 nss_count; 559 __le32 pilot_count; 560 __le32 rx_pil_evm_db[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 561 [ATH12K_HTT_RX_PDEV_STATS_RXEVM_MAX_PILOTS_NSS]; 562 __le32 rx_pilot_evm_db_mean[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 563 s8 rx_ul_fd_rssi[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 564 [ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 565 __le32 per_chain_rssi_pkt_type; 566 s8 rx_per_chain_rssi_in_dbm[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 567 [ATH12K_HTT_RX_PDEV_STATS_NUM_BW_COUNTERS]; 568 __le32 rx_su_ndpa; 569 __le32 rx_11ax_su_txbf_mcs[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 570 __le32 rx_mu_ndpa; 571 __le32 rx_11ax_mu_txbf_mcs[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 572 __le32 rx_br_poll; 573 __le32 rx_11ax_dl_ofdma_mcs[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS]; 574 __le32 rx_11ax_dl_ofdma_ru[ATH12K_HTT_RX_PDEV_STATS_NUM_RU_SIZE_COUNTERS]; 575 __le32 rx_ulmumimo_non_data_ppdu[ATH12K_HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 576 __le32 rx_ulmumimo_data_ppdu[ATH12K_HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 577 __le32 rx_ulmumimo_mpdu_ok[ATH12K_HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 578 __le32 rx_ulmumimo_mpdu_fail[ATH12K_HTT_RX_PDEV_MAX_ULMUMIMO_NUM_USER]; 579 __le32 rx_ulofdma_non_data_nusers[ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 580 __le32 rx_ulofdma_data_nusers[ATH12K_HTT_RX_PDEV_MAX_OFDMA_NUM_USER]; 581 __le32 rx_mcs_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_EXTRA_MCS_COUNTERS]; 582} __packed; 583 584#define ATH12K_HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS 4 585#define ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT 14 586#define ATH12K_HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS 2 587#define ATH12K_HTT_RX_PDEV_STATS_NUM_BW_EXT2_COUNTERS 5 588#define ATH12K_HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS 5 589 590struct ath12k_htt_rx_pdev_rate_ext_stats_tlv { 591 u8 rssi_chain_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 592 [ATH12K_HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS]; 593 s8 rx_per_chain_rssi_ext_in_dbm[ATH12K_HTT_RX_PDEV_STATS_NUM_SPATIAL_STREAMS] 594 [ATH12K_HTT_RX_PDEV_STATS_NUM_BW_EXT_COUNTERS]; 595 __le32 rssi_mcast_in_dbm; 596 __le32 rssi_mgmt_in_dbm; 597 __le32 rx_mcs_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 598 __le32 rx_stbc_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 599 __le32 rx_gi_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_GI_COUNTERS] 600 [ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 601 __le32 ul_ofdma_rx_mcs_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 602 __le32 ul_ofdma_rx_gi_ext[ATH12K_HTT_TX_PDEV_STATS_NUM_GI_COUNTERS] 603 [ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 604 __le32 rx_11ax_su_txbf_mcs_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 605 __le32 rx_11ax_mu_txbf_mcs_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 606 __le32 rx_11ax_dl_ofdma_mcs_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_MCS_COUNTERS_EXT]; 607 __le32 rx_mcs_ext_2[ATH12K_HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; 608 __le32 rx_bw_ext[ATH12K_HTT_RX_PDEV_STATS_NUM_BW_EXT2_COUNTERS]; 609 __le32 rx_gi_ext_2[ATH12K_HTT_RX_PDEV_STATS_NUM_GI_COUNTERS] 610 [ATH12K_HTT_RX_PDEV_STATS_NUM_EXTRA2_MCS_COUNTERS]; 611 __le32 rx_su_punctured_mode[ATH12K_HTT_RX_PDEV_STATS_NUM_PUNCTURED_MODE_COUNTERS]; 612} __packed; 613 614#define ATH12K_HTT_TX_PDEV_STATS_SCHED_PER_TXQ_MAC_ID GENMASK(7, 0) 615#define ATH12K_HTT_TX_PDEV_STATS_SCHED_PER_TXQ_ID GENMASK(15, 8) 616 617#define ATH12K_HTT_TX_PDEV_NUM_SCHED_ORDER_LOG 20 618 619struct ath12k_htt_stats_tx_sched_cmn_tlv { 620 __le32 mac_id__word; 621 __le32 current_timestamp; 622} __packed; 623 624struct ath12k_htt_tx_pdev_stats_sched_per_txq_tlv { 625 __le32 mac_id__word; 626 __le32 sched_policy; 627 __le32 last_sched_cmd_posted_timestamp; 628 __le32 last_sched_cmd_compl_timestamp; 629 __le32 sched_2_tac_lwm_count; 630 __le32 sched_2_tac_ring_full; 631 __le32 sched_cmd_post_failure; 632 __le32 num_active_tids; 633 __le32 num_ps_schedules; 634 __le32 sched_cmds_pending; 635 __le32 num_tid_register; 636 __le32 num_tid_unregister; 637 __le32 num_qstats_queried; 638 __le32 qstats_update_pending; 639 __le32 last_qstats_query_timestamp; 640 __le32 num_tqm_cmdq_full; 641 __le32 num_de_sched_algo_trigger; 642 __le32 num_rt_sched_algo_trigger; 643 __le32 num_tqm_sched_algo_trigger; 644 __le32 notify_sched; 645 __le32 dur_based_sendn_term; 646 __le32 su_notify2_sched; 647 __le32 su_optimal_queued_msdus_sched; 648 __le32 su_delay_timeout_sched; 649 __le32 su_min_txtime_sched_delay; 650 __le32 su_no_delay; 651 __le32 num_supercycles; 652 __le32 num_subcycles_with_sort; 653 __le32 num_subcycles_no_sort; 654} __packed; 655 656struct ath12k_htt_sched_txq_cmd_posted_tlv { 657 DECLARE_FLEX_ARRAY(__le32, sched_cmd_posted); 658} __packed; 659 660struct ath12k_htt_sched_txq_cmd_reaped_tlv { 661 DECLARE_FLEX_ARRAY(__le32, sched_cmd_reaped); 662} __packed; 663 664struct ath12k_htt_sched_txq_sched_order_su_tlv { 665 DECLARE_FLEX_ARRAY(__le32, sched_order_su); 666} __packed; 667 668struct ath12k_htt_sched_txq_sched_ineligibility_tlv { 669 DECLARE_FLEX_ARRAY(__le32, sched_ineligibility); 670} __packed; 671 672enum ath12k_htt_sched_txq_supercycle_triggers_tlv_enum { 673 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_NONE = 0, 674 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_FORCED, 675 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_TIDQ_ENTRIES, 676 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_LESS_NUM_ACTIVE_TIDS, 677 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_MAX_ITR_REACHED, 678 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_DUR_THRESHOLD_REACHED, 679 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_TWT_TRIGGER, 680 ATH12K_HTT_SCHED_SUPERCYCLE_TRIGGER_MAX, 681}; 682 683struct ath12k_htt_sched_txq_supercycle_triggers_tlv { 684 DECLARE_FLEX_ARRAY(__le32, supercycle_triggers); 685} __packed; 686 687struct ath12k_htt_hw_stats_pdev_errs_tlv { 688 __le32 mac_id__word; 689 __le32 tx_abort; 690 __le32 tx_abort_fail_count; 691 __le32 rx_abort; 692 __le32 rx_abort_fail_count; 693 __le32 warm_reset; 694 __le32 cold_reset; 695 __le32 tx_flush; 696 __le32 tx_glb_reset; 697 __le32 tx_txq_reset; 698 __le32 rx_timeout_reset; 699 __le32 mac_cold_reset_restore_cal; 700 __le32 mac_cold_reset; 701 __le32 mac_warm_reset; 702 __le32 mac_only_reset; 703 __le32 phy_warm_reset; 704 __le32 phy_warm_reset_ucode_trig; 705 __le32 mac_warm_reset_restore_cal; 706 __le32 mac_sfm_reset; 707 __le32 phy_warm_reset_m3_ssr; 708 __le32 phy_warm_reset_reason_phy_m3; 709 __le32 phy_warm_reset_reason_tx_hw_stuck; 710 __le32 phy_warm_reset_reason_num_rx_frame_stuck; 711 __le32 phy_warm_reset_reason_wal_rx_rec_rx_busy; 712 __le32 phy_warm_reset_reason_wal_rx_rec_mac_hng; 713 __le32 phy_warm_reset_reason_mac_conv_phy_reset; 714 __le32 wal_rx_recovery_rst_mac_hang_cnt; 715 __le32 wal_rx_recovery_rst_known_sig_cnt; 716 __le32 wal_rx_recovery_rst_no_rx_cnt; 717 __le32 wal_rx_recovery_rst_no_rx_consec_cnt; 718 __le32 wal_rx_recovery_rst_rx_busy_cnt; 719 __le32 wal_rx_recovery_rst_phy_mac_hang_cnt; 720 __le32 rx_flush_cnt; 721 __le32 phy_warm_reset_reason_tx_exp_cca_stuck; 722 __le32 phy_warm_reset_reason_tx_consec_flsh_war; 723 __le32 phy_warm_reset_reason_tx_hwsch_reset_war; 724 __le32 phy_warm_reset_reason_hwsch_cca_wdog_war; 725 __le32 fw_rx_rings_reset; 726 __le32 rx_dest_drain_rx_descs_leak_prevented; 727 __le32 rx_dest_drain_rx_descs_saved_cnt; 728 __le32 rx_dest_drain_rxdma2reo_leak_detected; 729 __le32 rx_dest_drain_rxdma2fw_leak_detected; 730 __le32 rx_dest_drain_rxdma2wbm_leak_detected; 731 __le32 rx_dest_drain_rxdma1_2sw_leak_detected; 732 __le32 rx_dest_drain_rx_drain_ok_mac_idle; 733 __le32 rx_dest_drain_ok_mac_not_idle; 734 __le32 rx_dest_drain_prerequisite_invld; 735 __le32 rx_dest_drain_skip_non_lmac_reset; 736 __le32 rx_dest_drain_hw_fifo_notempty_post_wait; 737} __packed; 738 739#define ATH12K_HTT_STATS_MAX_HW_INTR_NAME_LEN 8 740struct ath12k_htt_hw_stats_intr_misc_tlv { 741 u8 hw_intr_name[ATH12K_HTT_STATS_MAX_HW_INTR_NAME_LEN]; 742 __le32 mask; 743 __le32 count; 744} __packed; 745 746struct ath12k_htt_hw_stats_whal_tx_tlv { 747 __le32 mac_id__word; 748 __le32 last_unpause_ppdu_id; 749 __le32 hwsch_unpause_wait_tqm_write; 750 __le32 hwsch_dummy_tlv_skipped; 751 __le32 hwsch_misaligned_offset_received; 752 __le32 hwsch_reset_count; 753 __le32 hwsch_dev_reset_war; 754 __le32 hwsch_delayed_pause; 755 __le32 hwsch_long_delayed_pause; 756 __le32 sch_rx_ppdu_no_response; 757 __le32 sch_selfgen_response; 758 __le32 sch_rx_sifs_resp_trigger; 759} __packed; 760 761struct ath12k_htt_hw_war_stats_tlv { 762 __le32 mac_id__word; 763 DECLARE_FLEX_ARRAY(__le32, hw_wars); 764} __packed; 765 766struct ath12k_htt_tx_tqm_cmn_stats_tlv { 767 __le32 mac_id__word; 768 __le32 max_cmdq_id; 769 __le32 list_mpdu_cnt_hist_intvl; 770 __le32 add_msdu; 771 __le32 q_empty; 772 __le32 q_not_empty; 773 __le32 drop_notification; 774 __le32 desc_threshold; 775 __le32 hwsch_tqm_invalid_status; 776 __le32 missed_tqm_gen_mpdus; 777 __le32 tqm_active_tids; 778 __le32 tqm_inactive_tids; 779 __le32 tqm_active_msduq_flows; 780 __le32 msduq_timestamp_updates; 781 __le32 msduq_updates_mpdu_head_info_cmd; 782 __le32 msduq_updates_emp_to_nonemp_status; 783 __le32 get_mpdu_head_info_cmds_by_query; 784 __le32 get_mpdu_head_info_cmds_by_tac; 785 __le32 gen_mpdu_cmds_by_query; 786 __le32 high_prio_q_not_empty; 787} __packed; 788 789struct ath12k_htt_tx_tqm_error_stats_tlv { 790 __le32 q_empty_failure; 791 __le32 q_not_empty_failure; 792 __le32 add_msdu_failure; 793 __le32 tqm_cache_ctl_err; 794 __le32 tqm_soft_reset; 795 __le32 tqm_reset_num_in_use_link_descs; 796 __le32 tqm_reset_num_lost_link_descs; 797 __le32 tqm_reset_num_lost_host_tx_buf_cnt; 798 __le32 tqm_reset_num_in_use_internal_tqm; 799 __le32 tqm_reset_num_in_use_idle_link_rng; 800 __le32 tqm_reset_time_to_tqm_hang_delta_ms; 801 __le32 tqm_reset_recovery_time_ms; 802 __le32 tqm_reset_num_peers_hdl; 803 __le32 tqm_reset_cumm_dirty_hw_mpduq_cnt; 804 __le32 tqm_reset_cumm_dirty_hw_msduq_proc; 805 __le32 tqm_reset_flush_cache_cmd_su_cnt; 806 __le32 tqm_reset_flush_cache_cmd_other_cnt; 807 __le32 tqm_reset_flush_cache_cmd_trig_type; 808 __le32 tqm_reset_flush_cache_cmd_trig_cfg; 809 __le32 tqm_reset_flush_cmd_skp_status_null; 810} __packed; 811 812struct ath12k_htt_tx_tqm_gen_mpdu_stats_tlv { 813 DECLARE_FLEX_ARRAY(__le32, gen_mpdu_end_reason); 814} __packed; 815 816#define ATH12K_HTT_TX_TQM_MAX_LIST_MPDU_END_REASON 16 817#define ATH12K_HTT_TX_TQM_MAX_LIST_MPDU_CNT_HISTOGRAM_BINS 16 818 819struct ath12k_htt_tx_tqm_list_mpdu_stats_tlv { 820 DECLARE_FLEX_ARRAY(__le32, list_mpdu_end_reason); 821} __packed; 822 823struct ath12k_htt_tx_tqm_list_mpdu_cnt_tlv { 824 DECLARE_FLEX_ARRAY(__le32, list_mpdu_cnt_hist); 825} __packed; 826 827struct ath12k_htt_tx_tqm_pdev_stats_tlv { 828 __le32 msdu_count; 829 __le32 mpdu_count; 830 __le32 remove_msdu; 831 __le32 remove_mpdu; 832 __le32 remove_msdu_ttl; 833 __le32 send_bar; 834 __le32 bar_sync; 835 __le32 notify_mpdu; 836 __le32 sync_cmd; 837 __le32 write_cmd; 838 __le32 hwsch_trigger; 839 __le32 ack_tlv_proc; 840 __le32 gen_mpdu_cmd; 841 __le32 gen_list_cmd; 842 __le32 remove_mpdu_cmd; 843 __le32 remove_mpdu_tried_cmd; 844 __le32 mpdu_queue_stats_cmd; 845 __le32 mpdu_head_info_cmd; 846 __le32 msdu_flow_stats_cmd; 847 __le32 remove_msdu_cmd; 848 __le32 remove_msdu_ttl_cmd; 849 __le32 flush_cache_cmd; 850 __le32 update_mpduq_cmd; 851 __le32 enqueue; 852 __le32 enqueue_notify; 853 __le32 notify_mpdu_at_head; 854 __le32 notify_mpdu_state_valid; 855 __le32 sched_udp_notify1; 856 __le32 sched_udp_notify2; 857 __le32 sched_nonudp_notify1; 858 __le32 sched_nonudp_notify2; 859} __packed; 860 861struct ath12k_htt_tx_de_cmn_stats_tlv { 862 __le32 mac_id__word; 863 __le32 tcl2fw_entry_count; 864 __le32 not_to_fw; 865 __le32 invalid_pdev_vdev_peer; 866 __le32 tcl_res_invalid_addrx; 867 __le32 wbm2fw_entry_count; 868 __le32 invalid_pdev; 869 __le32 tcl_res_addrx_timeout; 870 __le32 invalid_vdev; 871 __le32 invalid_tcl_exp_frame_desc; 872 __le32 vdev_id_mismatch_cnt; 873} __packed; 874 875struct ath12k_htt_tx_de_eapol_packets_stats_tlv { 876 __le32 m1_packets; 877 __le32 m2_packets; 878 __le32 m3_packets; 879 __le32 m4_packets; 880 __le32 g1_packets; 881 __le32 g2_packets; 882 __le32 rc4_packets; 883 __le32 eap_packets; 884 __le32 eapol_start_packets; 885 __le32 eapol_logoff_packets; 886 __le32 eapol_encap_asf_packets; 887} __packed; 888 889struct ath12k_htt_tx_de_classify_stats_tlv { 890 __le32 arp_packets; 891 __le32 igmp_packets; 892 __le32 dhcp_packets; 893 __le32 host_inspected; 894 __le32 htt_included; 895 __le32 htt_valid_mcs; 896 __le32 htt_valid_nss; 897 __le32 htt_valid_preamble_type; 898 __le32 htt_valid_chainmask; 899 __le32 htt_valid_guard_interval; 900 __le32 htt_valid_retries; 901 __le32 htt_valid_bw_info; 902 __le32 htt_valid_power; 903 __le32 htt_valid_key_flags; 904 __le32 htt_valid_no_encryption; 905 __le32 fse_entry_count; 906 __le32 fse_priority_be; 907 __le32 fse_priority_high; 908 __le32 fse_priority_low; 909 __le32 fse_traffic_ptrn_be; 910 __le32 fse_traffic_ptrn_over_sub; 911 __le32 fse_traffic_ptrn_bursty; 912 __le32 fse_traffic_ptrn_interactive; 913 __le32 fse_traffic_ptrn_periodic; 914 __le32 fse_hwqueue_alloc; 915 __le32 fse_hwqueue_created; 916 __le32 fse_hwqueue_send_to_host; 917 __le32 mcast_entry; 918 __le32 bcast_entry; 919 __le32 htt_update_peer_cache; 920 __le32 htt_learning_frame; 921 __le32 fse_invalid_peer; 922 __le32 mec_notify; 923} __packed; 924 925struct ath12k_htt_tx_de_classify_failed_stats_tlv { 926 __le32 ap_bss_peer_not_found; 927 __le32 ap_bcast_mcast_no_peer; 928 __le32 sta_delete_in_progress; 929 __le32 ibss_no_bss_peer; 930 __le32 invalid_vdev_type; 931 __le32 invalid_ast_peer_entry; 932 __le32 peer_entry_invalid; 933 __le32 ethertype_not_ip; 934 __le32 eapol_lookup_failed; 935 __le32 qpeer_not_allow_data; 936 __le32 fse_tid_override; 937 __le32 ipv6_jumbogram_zero_length; 938 __le32 qos_to_non_qos_in_prog; 939 __le32 ap_bcast_mcast_eapol; 940 __le32 unicast_on_ap_bss_peer; 941 __le32 ap_vdev_invalid; 942 __le32 incomplete_llc; 943 __le32 eapol_duplicate_m3; 944 __le32 eapol_duplicate_m4; 945} __packed; 946 947struct ath12k_htt_tx_de_classify_status_stats_tlv { 948 __le32 eok; 949 __le32 classify_done; 950 __le32 lookup_failed; 951 __le32 send_host_dhcp; 952 __le32 send_host_mcast; 953 __le32 send_host_unknown_dest; 954 __le32 send_host; 955 __le32 status_invalid; 956} __packed; 957 958struct ath12k_htt_tx_de_enqueue_packets_stats_tlv { 959 __le32 enqueued_pkts; 960 __le32 to_tqm; 961 __le32 to_tqm_bypass; 962} __packed; 963 964struct ath12k_htt_tx_de_enqueue_discard_stats_tlv { 965 __le32 discarded_pkts; 966 __le32 local_frames; 967 __le32 is_ext_msdu; 968} __packed; 969 970struct ath12k_htt_tx_de_compl_stats_tlv { 971 __le32 tcl_dummy_frame; 972 __le32 tqm_dummy_frame; 973 __le32 tqm_notify_frame; 974 __le32 fw2wbm_enq; 975 __le32 tqm_bypass_frame; 976} __packed; 977 978enum ath12k_htt_tx_mumimo_grp_invalid_reason_code_stats { 979 ATH12K_HTT_TX_MUMIMO_GRP_VALID, 980 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_NUM_MU_USERS_EXCEEDED_MU_MAX_USERS, 981 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_SCHED_ALGO_NOT_MU_COMPATIBLE_GID, 982 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_NON_PRIMARY_GRP, 983 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_ZERO_CANDIDATES, 984 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_MORE_CANDIDATES, 985 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_GROUP_SIZE_EXCEED_NSS, 986 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_GROUP_INELIGIBLE, 987 ATH12K_HTT_TX_MUMIMO_GRP_INVALID, 988 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_GROUP_EFF_MU_TPUT_OMBPS, 989 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_MAX_REASON_CODE, 990}; 991 992#define ATH12K_HTT_NUM_AC_WMM 0x4 993#define ATH12K_HTT_MAX_NUM_SBT_INTR 4 994#define ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS 4 995#define ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS 8 996#define ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS 8 997#define ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS 7 998#define ATH12K_HTT_TX_NUM_OFDMA_USER_STATS 74 999#define ATH12K_HTT_TX_NUM_UL_MUMIMO_USER_STATS 8 1000#define ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ 8 1001#define ATH12K_HTT_STATS_MUMIMO_TPUT_NUM_BINS 10 1002 1003#define ATH12K_HTT_STATS_MAX_INVALID_REASON_CODE \ 1004 ATH12K_HTT_TX_MUMIMO_GRP_INVALID_MAX_REASON_CODE 1005#define ATH12K_HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS \ 1006 (ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ * ATH12K_HTT_STATS_MAX_INVALID_REASON_CODE) 1007 1008struct ath12k_htt_tx_selfgen_cmn_stats_tlv { 1009 __le32 mac_id__word; 1010 __le32 su_bar; 1011 __le32 rts; 1012 __le32 cts2self; 1013 __le32 qos_null; 1014 __le32 delayed_bar_1; 1015 __le32 delayed_bar_2; 1016 __le32 delayed_bar_3; 1017 __le32 delayed_bar_4; 1018 __le32 delayed_bar_5; 1019 __le32 delayed_bar_6; 1020 __le32 delayed_bar_7; 1021} __packed; 1022 1023struct ath12k_htt_tx_selfgen_ac_stats_tlv { 1024 __le32 ac_su_ndpa; 1025 __le32 ac_su_ndp; 1026 __le32 ac_mu_mimo_ndpa; 1027 __le32 ac_mu_mimo_ndp; 1028 __le32 ac_mu_mimo_brpoll[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS - 1]; 1029} __packed; 1030 1031struct ath12k_htt_tx_selfgen_ax_stats_tlv { 1032 __le32 ax_su_ndpa; 1033 __le32 ax_su_ndp; 1034 __le32 ax_mu_mimo_ndpa; 1035 __le32 ax_mu_mimo_ndp; 1036 __le32 ax_mu_mimo_brpoll[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS - 1]; 1037 __le32 ax_basic_trigger; 1038 __le32 ax_bsr_trigger; 1039 __le32 ax_mu_bar_trigger; 1040 __le32 ax_mu_rts_trigger; 1041 __le32 ax_ulmumimo_trigger; 1042} __packed; 1043 1044struct ath12k_htt_tx_selfgen_be_stats_tlv { 1045 __le32 be_su_ndpa; 1046 __le32 be_su_ndp; 1047 __le32 be_mu_mimo_ndpa; 1048 __le32 be_mu_mimo_ndp; 1049 __le32 be_mu_mimo_brpoll[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1]; 1050 __le32 be_basic_trigger; 1051 __le32 be_bsr_trigger; 1052 __le32 be_mu_bar_trigger; 1053 __le32 be_mu_rts_trigger; 1054 __le32 be_ulmumimo_trigger; 1055 __le32 be_su_ndpa_queued; 1056 __le32 be_su_ndp_queued; 1057 __le32 be_mu_mimo_ndpa_queued; 1058 __le32 be_mu_mimo_ndp_queued; 1059 __le32 be_mu_mimo_brpoll_queued[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1]; 1060 __le32 be_ul_mumimo_trigger[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 1061} __packed; 1062 1063struct ath12k_htt_tx_selfgen_ac_err_stats_tlv { 1064 __le32 ac_su_ndp_err; 1065 __le32 ac_su_ndpa_err; 1066 __le32 ac_mu_mimo_ndpa_err; 1067 __le32 ac_mu_mimo_ndp_err; 1068 __le32 ac_mu_mimo_brp1_err; 1069 __le32 ac_mu_mimo_brp2_err; 1070 __le32 ac_mu_mimo_brp3_err; 1071} __packed; 1072 1073struct ath12k_htt_tx_selfgen_ax_err_stats_tlv { 1074 __le32 ax_su_ndp_err; 1075 __le32 ax_su_ndpa_err; 1076 __le32 ax_mu_mimo_ndpa_err; 1077 __le32 ax_mu_mimo_ndp_err; 1078 __le32 ax_mu_mimo_brp_err[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS - 1]; 1079 __le32 ax_basic_trigger_err; 1080 __le32 ax_bsr_trigger_err; 1081 __le32 ax_mu_bar_trigger_err; 1082 __le32 ax_mu_rts_trigger_err; 1083 __le32 ax_ulmumimo_trigger_err; 1084} __packed; 1085 1086struct ath12k_htt_tx_selfgen_be_err_stats_tlv { 1087 __le32 be_su_ndp_err; 1088 __le32 be_su_ndpa_err; 1089 __le32 be_mu_mimo_ndpa_err; 1090 __le32 be_mu_mimo_ndp_err; 1091 __le32 be_mu_mimo_brp_err[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1]; 1092 __le32 be_basic_trigger_err; 1093 __le32 be_bsr_trigger_err; 1094 __le32 be_mu_bar_trigger_err; 1095 __le32 be_mu_rts_trigger_err; 1096 __le32 be_ulmumimo_trigger_err; 1097 __le32 be_mu_mimo_brp_err_num_cbf_rxd[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 1098 __le32 be_su_ndpa_flushed; 1099 __le32 be_su_ndp_flushed; 1100 __le32 be_mu_mimo_ndpa_flushed; 1101 __le32 be_mu_mimo_ndp_flushed; 1102 __le32 be_mu_mimo_brpoll_flushed[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS - 1]; 1103 __le32 be_ul_mumimo_trigger_err[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 1104} __packed; 1105 1106enum ath12k_htt_tx_selfgen_sch_tsflag_error_stats { 1107 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_FLUSH_RCVD_ERR, 1108 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_FILT_SCHED_CMD_ERR, 1109 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_MISMATCH_ERR, 1110 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_CBF_MIMO_CTRL_MISMATCH_ERR, 1111 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_CBF_BW_MISMATCH_ERR, 1112 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RETRY_COUNT_FAIL_ERR, 1113 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_RESP_TOO_LATE_RECEIVED_ERR, 1114 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_SIFS_STALL_NO_NEXT_CMD_ERR, 1115 1116 ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS 1117}; 1118 1119struct ath12k_htt_tx_selfgen_ac_sched_status_stats_tlv { 1120 __le32 ac_su_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1121 __le32 ac_su_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1122 __le32 ac_su_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1123 __le32 ac_mu_mimo_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1124 __le32 ac_mu_mimo_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1125 __le32 ac_mu_mimo_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1126 __le32 ac_mu_mimo_brp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1127 __le32 ac_mu_mimo_brp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1128} __packed; 1129 1130struct ath12k_htt_tx_selfgen_ax_sched_status_stats_tlv { 1131 __le32 ax_su_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1132 __le32 ax_su_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1133 __le32 ax_su_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1134 __le32 ax_mu_mimo_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1135 __le32 ax_mu_mimo_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1136 __le32 ax_mu_mimo_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1137 __le32 ax_mu_brp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1138 __le32 ax_mu_brp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1139 __le32 ax_mu_bar_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1140 __le32 ax_mu_bar_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1141 __le32 ax_basic_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1142 __le32 ax_basic_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1143 __le32 ax_ulmumimo_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1144 __le32 ax_ulmumimo_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1145} __packed; 1146 1147struct ath12k_htt_tx_selfgen_be_sched_status_stats_tlv { 1148 __le32 be_su_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1149 __le32 be_su_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1150 __le32 be_su_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1151 __le32 be_mu_mimo_ndpa_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1152 __le32 be_mu_mimo_ndp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1153 __le32 be_mu_mimo_ndp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1154 __le32 be_mu_brp_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1155 __le32 be_mu_brp_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1156 __le32 be_mu_bar_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1157 __le32 be_mu_bar_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1158 __le32 be_basic_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1159 __le32 be_basic_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1160 __le32 be_ulmumimo_trig_sch_status[ATH12K_HTT_TX_PDEV_STATS_NUM_TX_ERR_STATUS]; 1161 __le32 be_ulmumimo_trig_sch_flag_err[ATH12K_HTT_TX_SELFGEN_SCH_TSFLAG_ERR_STATS]; 1162} __packed; 1163 1164struct ath12k_htt_stats_string_tlv { 1165 DECLARE_FLEX_ARRAY(__le32, data); 1166} __packed; 1167 1168#define ATH12K_HTT_SRING_STATS_MAC_ID GENMASK(7, 0) 1169#define ATH12K_HTT_SRING_STATS_RING_ID GENMASK(15, 8) 1170#define ATH12K_HTT_SRING_STATS_ARENA GENMASK(23, 16) 1171#define ATH12K_HTT_SRING_STATS_EP BIT(24) 1172#define ATH12K_HTT_SRING_STATS_NUM_AVAIL_WORDS GENMASK(15, 0) 1173#define ATH12K_HTT_SRING_STATS_NUM_VALID_WORDS GENMASK(31, 16) 1174#define ATH12K_HTT_SRING_STATS_HEAD_PTR GENMASK(15, 0) 1175#define ATH12K_HTT_SRING_STATS_TAIL_PTR GENMASK(31, 16) 1176#define ATH12K_HTT_SRING_STATS_CONSUMER_EMPTY GENMASK(15, 0) 1177#define ATH12K_HTT_SRING_STATS_PRODUCER_FULL GENMASK(31, 16) 1178#define ATH12K_HTT_SRING_STATS_PREFETCH_COUNT GENMASK(15, 0) 1179#define ATH12K_HTT_SRING_STATS_INTERNAL_TAIL_PTR GENMASK(31, 16) 1180 1181struct ath12k_htt_sring_stats_tlv { 1182 __le32 mac_id__ring_id__arena__ep; 1183 __le32 base_addr_lsb; 1184 __le32 base_addr_msb; 1185 __le32 ring_size; 1186 __le32 elem_size; 1187 __le32 num_avail_words__num_valid_words; 1188 __le32 head_ptr__tail_ptr; 1189 __le32 consumer_empty__producer_full; 1190 __le32 prefetch_count__internal_tail_ptr; 1191} __packed; 1192 1193struct ath12k_htt_sfm_cmn_tlv { 1194 __le32 mac_id__word; 1195 __le32 buf_total; 1196 __le32 mem_empty; 1197 __le32 deallocate_bufs; 1198 __le32 num_records; 1199} __packed; 1200 1201struct ath12k_htt_sfm_client_tlv { 1202 __le32 client_id; 1203 __le32 buf_min; 1204 __le32 buf_max; 1205 __le32 buf_busy; 1206 __le32 buf_alloc; 1207 __le32 buf_avail; 1208 __le32 num_users; 1209} __packed; 1210 1211struct ath12k_htt_sfm_client_user_tlv { 1212 DECLARE_FLEX_ARRAY(__le32, dwords_used_by_user_n); 1213} __packed; 1214 1215struct ath12k_htt_tx_pdev_mu_mimo_sch_stats_tlv { 1216 __le32 mu_mimo_sch_posted; 1217 __le32 mu_mimo_sch_failed; 1218 __le32 mu_mimo_ppdu_posted; 1219 __le32 ac_mu_mimo_sch_nusers[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS]; 1220 __le32 ax_mu_mimo_sch_nusers[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS]; 1221 __le32 ax_ofdma_sch_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS]; 1222 __le32 ax_ul_ofdma_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS]; 1223 __le32 ax_ul_ofdma_bsr_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS]; 1224 __le32 ax_ul_ofdma_bar_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS]; 1225 __le32 ax_ul_ofdma_brp_nusers[ATH12K_HTT_TX_NUM_OFDMA_USER_STATS]; 1226 __le32 ax_ul_mumimo_nusers[ATH12K_HTT_TX_NUM_UL_MUMIMO_USER_STATS]; 1227 __le32 ax_ul_mumimo_brp_nusers[ATH12K_HTT_TX_NUM_UL_MUMIMO_USER_STATS]; 1228 __le32 ac_mu_mimo_per_grp_sz[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS]; 1229 __le32 ax_mu_mimo_per_grp_sz[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS]; 1230 __le32 be_mu_mimo_sch_nusers[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 1231 __le32 be_mu_mimo_per_grp_sz[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 1232 __le32 ac_mu_mimo_grp_sz_ext[ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS]; 1233} __packed; 1234 1235struct ath12k_htt_tx_pdev_mumimo_grp_stats_tlv { 1236 __le32 dl_mumimo_grp_best_grp_size[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ]; 1237 __le32 dl_mumimo_grp_best_num_usrs[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS]; 1238 __le32 dl_mumimo_grp_eligible[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ]; 1239 __le32 dl_mumimo_grp_ineligible[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ]; 1240 __le32 dl_mumimo_grp_invalid[ATH12K_HTT_TX_NUM_MUMIMO_GRP_INVALID_WORDS]; 1241 __le32 dl_mumimo_grp_tputs[ATH12K_HTT_STATS_MUMIMO_TPUT_NUM_BINS]; 1242 __le32 ul_mumimo_grp_best_grp_size[ATH12K_HTT_STATS_NUM_MAX_MUMIMO_SZ]; 1243 __le32 ul_mumimo_grp_best_usrs[ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS]; 1244 __le32 ul_mumimo_grp_tputs[ATH12K_HTT_STATS_MUMIMO_TPUT_NUM_BINS]; 1245} __packed; 1246 1247enum ath12k_htt_stats_tx_sched_modes { 1248 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_MIMO_AC = 0, 1249 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_MIMO_AX, 1250 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_OFDMA_AX, 1251 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_OFDMA_BE, 1252 ATH12K_HTT_STATS_TX_SCHED_MODE_MU_MIMO_BE 1253}; 1254 1255struct ath12k_htt_tx_pdev_mpdu_stats_tlv { 1256 __le32 mpdus_queued_usr; 1257 __le32 mpdus_tried_usr; 1258 __le32 mpdus_failed_usr; 1259 __le32 mpdus_requeued_usr; 1260 __le32 err_no_ba_usr; 1261 __le32 mpdu_underrun_usr; 1262 __le32 ampdu_underrun_usr; 1263 __le32 user_index; 1264 __le32 tx_sched_mode; 1265} __packed; 1266 1267struct ath12k_htt_pdev_stats_cca_counters_tlv { 1268 __le32 tx_frame_usec; 1269 __le32 rx_frame_usec; 1270 __le32 rx_clear_usec; 1271 __le32 my_rx_frame_usec; 1272 __le32 usec_cnt; 1273 __le32 med_rx_idle_usec; 1274 __le32 med_tx_idle_global_usec; 1275 __le32 cca_obss_usec; 1276} __packed; 1277 1278struct ath12k_htt_pdev_cca_stats_hist_v1_tlv { 1279 __le32 chan_num; 1280 __le32 num_records; 1281 __le32 valid_cca_counters_bitmap; 1282 __le32 collection_interval; 1283} __packed; 1284 1285#define ATH12K_HTT_TX_CV_CORR_MAX_NUM_COLUMNS 8 1286#define ATH12K_HTT_TX_NUM_AC_MUMIMO_USER_STATS 4 1287#define ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS 8 1288#define ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS 8 1289#define ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS 4 1290#define ATH12K_HTT_TX_NUM_MCS_CNTRS 12 1291#define ATH12K_HTT_TX_NUM_EXTRA_MCS_CNTRS 2 1292 1293#define ATH12K_HTT_TX_NUM_OF_SOUNDING_STATS_WORDS \ 1294 (ATH12K_HTT_TX_PDEV_STATS_NUM_BW_COUNTERS * \ 1295 ATH12K_HTT_TX_NUM_AX_MUMIMO_USER_STATS) 1296 1297enum ath12k_htt_txbf_sound_steer_modes { 1298 ATH12K_HTT_IMPL_STEER_STATS = 0, 1299 ATH12K_HTT_EXPL_SUSIFS_STEER_STATS = 1, 1300 ATH12K_HTT_EXPL_SURBO_STEER_STATS = 2, 1301 ATH12K_HTT_EXPL_MUSIFS_STEER_STATS = 3, 1302 ATH12K_HTT_EXPL_MURBO_STEER_STATS = 4, 1303 ATH12K_HTT_TXBF_MAX_NUM_OF_MODES = 5 1304}; 1305 1306enum ath12k_htt_stats_sounding_tx_mode { 1307 ATH12K_HTT_TX_AC_SOUNDING_MODE = 0, 1308 ATH12K_HTT_TX_AX_SOUNDING_MODE = 1, 1309 ATH12K_HTT_TX_BE_SOUNDING_MODE = 2, 1310 ATH12K_HTT_TX_CMN_SOUNDING_MODE = 3, 1311}; 1312 1313struct ath12k_htt_tx_sounding_stats_tlv { 1314 __le32 tx_sounding_mode; 1315 __le32 cbf_20[ATH12K_HTT_TXBF_MAX_NUM_OF_MODES]; 1316 __le32 cbf_40[ATH12K_HTT_TXBF_MAX_NUM_OF_MODES]; 1317 __le32 cbf_80[ATH12K_HTT_TXBF_MAX_NUM_OF_MODES]; 1318 __le32 cbf_160[ATH12K_HTT_TXBF_MAX_NUM_OF_MODES]; 1319 __le32 sounding[ATH12K_HTT_TX_NUM_OF_SOUNDING_STATS_WORDS]; 1320 __le32 cv_nc_mismatch_err; 1321 __le32 cv_fcs_err; 1322 __le32 cv_frag_idx_mismatch; 1323 __le32 cv_invalid_peer_id; 1324 __le32 cv_no_txbf_setup; 1325 __le32 cv_expiry_in_update; 1326 __le32 cv_pkt_bw_exceed; 1327 __le32 cv_dma_not_done_err; 1328 __le32 cv_update_failed; 1329 __le32 cv_total_query; 1330 __le32 cv_total_pattern_query; 1331 __le32 cv_total_bw_query; 1332 __le32 cv_invalid_bw_coding; 1333 __le32 cv_forced_sounding; 1334 __le32 cv_standalone_sounding; 1335 __le32 cv_nc_mismatch; 1336 __le32 cv_fb_type_mismatch; 1337 __le32 cv_ofdma_bw_mismatch; 1338 __le32 cv_bw_mismatch; 1339 __le32 cv_pattern_mismatch; 1340 __le32 cv_preamble_mismatch; 1341 __le32 cv_nr_mismatch; 1342 __le32 cv_in_use_cnt_exceeded; 1343 __le32 cv_found; 1344 __le32 cv_not_found; 1345 __le32 sounding_320[ATH12K_HTT_TX_NUM_BE_MUMIMO_USER_STATS]; 1346 __le32 cbf_320[ATH12K_HTT_TXBF_MAX_NUM_OF_MODES]; 1347 __le32 cv_ntbr_sounding; 1348 __le32 cv_found_upload_in_progress; 1349 __le32 cv_expired_during_query; 1350 __le32 cv_dma_timeout_error; 1351 __le32 cv_buf_ibf_uploads; 1352 __le32 cv_buf_ebf_uploads; 1353 __le32 cv_buf_received; 1354 __le32 cv_buf_fed_back; 1355 __le32 cv_total_query_ibf; 1356 __le32 cv_found_ibf; 1357 __le32 cv_not_found_ibf; 1358 __le32 cv_expired_during_query_ibf; 1359} __packed; 1360 1361struct ath12k_htt_pdev_obss_pd_stats_tlv { 1362 __le32 num_obss_tx_ppdu_success; 1363 __le32 num_obss_tx_ppdu_failure; 1364 __le32 num_sr_tx_transmissions; 1365 __le32 num_spatial_reuse_opportunities; 1366 __le32 num_non_srg_opportunities; 1367 __le32 num_non_srg_ppdu_tried; 1368 __le32 num_non_srg_ppdu_success; 1369 __le32 num_srg_opportunities; 1370 __le32 num_srg_ppdu_tried; 1371 __le32 num_srg_ppdu_success; 1372 __le32 num_psr_opportunities; 1373 __le32 num_psr_ppdu_tried; 1374 __le32 num_psr_ppdu_success; 1375 __le32 num_non_srg_tried_per_ac[ATH12K_HTT_NUM_AC_WMM]; 1376 __le32 num_non_srg_success_ac[ATH12K_HTT_NUM_AC_WMM]; 1377 __le32 num_srg_tried_per_ac[ATH12K_HTT_NUM_AC_WMM]; 1378 __le32 num_srg_success_per_ac[ATH12K_HTT_NUM_AC_WMM]; 1379 __le32 num_obss_min_dur_check_flush_cnt; 1380 __le32 num_sr_ppdu_abort_flush_cnt; 1381} __packed; 1382 1383#define ATH12K_HTT_STATS_MAX_PROF_STATS_NAME_LEN 32 1384#define ATH12K_HTT_LATENCY_PROFILE_NUM_MAX_HIST 3 1385#define ATH12K_HTT_INTERRUPTS_LATENCY_PROFILE_MAX_HIST 3 1386 1387struct ath12k_htt_latency_prof_stats_tlv { 1388 __le32 print_header; 1389 s8 latency_prof_name[ATH12K_HTT_STATS_MAX_PROF_STATS_NAME_LEN]; 1390 __le32 cnt; 1391 __le32 min; 1392 __le32 max; 1393 __le32 last; 1394 __le32 tot; 1395 __le32 avg; 1396 __le32 hist_intvl; 1397 __le32 hist[ATH12K_HTT_LATENCY_PROFILE_NUM_MAX_HIST]; 1398} __packed; 1399 1400struct ath12k_htt_latency_prof_ctx_tlv { 1401 __le32 duration; 1402 __le32 tx_msdu_cnt; 1403 __le32 tx_mpdu_cnt; 1404 __le32 tx_ppdu_cnt; 1405 __le32 rx_msdu_cnt; 1406 __le32 rx_mpdu_cnt; 1407} __packed; 1408 1409struct ath12k_htt_latency_prof_cnt_tlv { 1410 __le32 prof_enable_cnt; 1411} __packed; 1412 1413#define ATH12K_HTT_RX_NUM_MCS_CNTRS 12 1414#define ATH12K_HTT_RX_NUM_GI_CNTRS 4 1415#define ATH12K_HTT_RX_NUM_SPATIAL_STREAMS 8 1416#define ATH12K_HTT_RX_NUM_BW_CNTRS 4 1417#define ATH12K_HTT_RX_NUM_RU_SIZE_CNTRS 6 1418#define ATH12K_HTT_RX_NUM_RU_SIZE_160MHZ_CNTRS 7 1419#define ATH12K_HTT_RX_UL_MAX_UPLINK_RSSI_TRACK 5 1420#define ATH12K_HTT_RX_NUM_REDUCED_CHAN_TYPES 2 1421#define ATH12K_HTT_RX_NUM_EXTRA_MCS_CNTRS 2 1422 1423enum ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE { 1424 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_26, 1425 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_52, 1426 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_106, 1427 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_242, 1428 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_484, 1429 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_996, 1430 ATH12K_HTT_TX_RX_PDEV_STATS_AX_RU_SIZE_996x2, 1431 ATH12K_HTT_TX_RX_PDEV_STATS_NUM_AX_RU_SIZE_CNTRS, 1432}; 1433 1434struct ath12k_htt_rx_pdev_ul_ofdma_user_stats_tlv { 1435 __le32 user_index; 1436 __le32 rx_ulofdma_non_data_ppdu; 1437 __le32 rx_ulofdma_data_ppdu; 1438 __le32 rx_ulofdma_mpdu_ok; 1439 __le32 rx_ulofdma_mpdu_fail; 1440 __le32 rx_ulofdma_non_data_nusers; 1441 __le32 rx_ulofdma_data_nusers; 1442} __packed; 1443 1444struct ath12k_htt_rx_pdev_ul_trigger_stats_tlv { 1445 __le32 mac_id__word; 1446 __le32 rx_11ax_ul_ofdma; 1447 __le32 ul_ofdma_rx_mcs[ATH12K_HTT_RX_NUM_MCS_CNTRS]; 1448 __le32 ul_ofdma_rx_gi[ATH12K_HTT_RX_NUM_GI_CNTRS][ATH12K_HTT_RX_NUM_MCS_CNTRS]; 1449 __le32 ul_ofdma_rx_nss[ATH12K_HTT_RX_NUM_SPATIAL_STREAMS]; 1450 __le32 ul_ofdma_rx_bw[ATH12K_HTT_RX_NUM_BW_CNTRS]; 1451 __le32 ul_ofdma_rx_stbc; 1452 __le32 ul_ofdma_rx_ldpc; 1453 __le32 data_ru_size_ppdu[ATH12K_HTT_RX_NUM_RU_SIZE_160MHZ_CNTRS]; 1454 __le32 non_data_ru_size_ppdu[ATH12K_HTT_RX_NUM_RU_SIZE_160MHZ_CNTRS]; 1455 __le32 uplink_sta_aid[ATH12K_HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 1456 __le32 uplink_sta_target_rssi[ATH12K_HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 1457 __le32 uplink_sta_fd_rssi[ATH12K_HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 1458 __le32 uplink_sta_power_headroom[ATH12K_HTT_RX_UL_MAX_UPLINK_RSSI_TRACK]; 1459 __le32 red_bw[ATH12K_HTT_RX_NUM_REDUCED_CHAN_TYPES][ATH12K_HTT_RX_NUM_BW_CNTRS]; 1460 __le32 ul_ofdma_bsc_trig_rx_qos_null_only; 1461} __packed; 1462 1463#define ATH12K_HTT_TX_UL_MUMIMO_USER_STATS 8 1464 1465struct ath12k_htt_rx_ul_mumimo_trig_stats_tlv { 1466 __le32 mac_id__word; 1467 __le32 rx_11ax_ul_mumimo; 1468 __le32 ul_mumimo_rx_mcs[ATH12K_HTT_RX_NUM_MCS_CNTRS]; 1469 __le32 ul_rx_gi[ATH12K_HTT_RX_NUM_GI_CNTRS][ATH12K_HTT_RX_NUM_MCS_CNTRS]; 1470 __le32 ul_mumimo_rx_nss[ATH12K_HTT_RX_NUM_SPATIAL_STREAMS]; 1471 __le32 ul_mumimo_rx_bw[ATH12K_HTT_RX_NUM_BW_CNTRS]; 1472 __le32 ul_mumimo_rx_stbc; 1473 __le32 ul_mumimo_rx_ldpc; 1474 __le32 ul_mumimo_rx_mcs_ext[ATH12K_HTT_RX_NUM_EXTRA_MCS_CNTRS]; 1475 __le32 ul_gi_ext[ATH12K_HTT_RX_NUM_GI_CNTRS][ATH12K_HTT_RX_NUM_EXTRA_MCS_CNTRS]; 1476 s8 ul_rssi[ATH12K_HTT_RX_NUM_SPATIAL_STREAMS][ATH12K_HTT_RX_NUM_BW_CNTRS]; 1477 s8 tgt_rssi[ATH12K_HTT_TX_UL_MUMIMO_USER_STATS][ATH12K_HTT_RX_NUM_BW_CNTRS]; 1478 s8 fd[ATH12K_HTT_TX_UL_MUMIMO_USER_STATS][ATH12K_HTT_RX_NUM_SPATIAL_STREAMS]; 1479 s8 db[ATH12K_HTT_TX_UL_MUMIMO_USER_STATS][ATH12K_HTT_RX_NUM_SPATIAL_STREAMS]; 1480 __le32 red_bw[ATH12K_HTT_RX_NUM_REDUCED_CHAN_TYPES][ATH12K_HTT_RX_NUM_BW_CNTRS]; 1481 __le32 mumimo_bsc_trig_rx_qos_null_only; 1482} __packed; 1483 1484#define ATH12K_HTT_RX_NUM_MAX_PEAK_OCCUPANCY_INDEX 10 1485#define ATH12K_HTT_RX_NUM_MAX_CURR_OCCUPANCY_INDEX 10 1486#define ATH12K_HTT_RX_NUM_SQUARE_INDEX 6 1487#define ATH12K_HTT_RX_NUM_MAX_PEAK_SEARCH_INDEX 4 1488#define ATH12K_HTT_RX_NUM_MAX_PENDING_SEARCH_INDEX 4 1489 1490struct ath12k_htt_rx_fse_stats_tlv { 1491 __le32 fse_enable_cnt; 1492 __le32 fse_disable_cnt; 1493 __le32 fse_cache_invalidate_entry_cnt; 1494 __le32 fse_full_cache_invalidate_cnt; 1495 __le32 fse_num_cache_hits_cnt; 1496 __le32 fse_num_searches_cnt; 1497 __le32 fse_cache_occupancy_peak_cnt[ATH12K_HTT_RX_NUM_MAX_PEAK_OCCUPANCY_INDEX]; 1498 __le32 fse_cache_occupancy_curr_cnt[ATH12K_HTT_RX_NUM_MAX_CURR_OCCUPANCY_INDEX]; 1499 __le32 fse_search_stat_square_cnt[ATH12K_HTT_RX_NUM_SQUARE_INDEX]; 1500 __le32 fse_search_stat_peak_cnt[ATH12K_HTT_RX_NUM_MAX_PEAK_SEARCH_INDEX]; 1501 __le32 fse_search_stat_pending_cnt[ATH12K_HTT_RX_NUM_MAX_PENDING_SEARCH_INDEX]; 1502} __packed; 1503 1504#define ATH12K_HTT_TX_BF_RATE_STATS_NUM_MCS_COUNTERS 14 1505#define ATH12K_HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS 8 1506#define ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS 8 1507#define ATH12K_HTT_TXBF_NUM_BW_CNTRS 5 1508#define ATH12K_HTT_TXBF_NUM_REDUCED_CHAN_TYPES 2 1509 1510struct ath12k_htt_pdev_txrate_txbf_stats_tlv { 1511 __le32 tx_su_txbf_mcs[ATH12K_HTT_TX_BF_RATE_STATS_NUM_MCS_COUNTERS]; 1512 __le32 tx_su_ibf_mcs[ATH12K_HTT_TX_BF_RATE_STATS_NUM_MCS_COUNTERS]; 1513 __le32 tx_su_ol_mcs[ATH12K_HTT_TX_BF_RATE_STATS_NUM_MCS_COUNTERS]; 1514 __le32 tx_su_txbf_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1515 __le32 tx_su_ibf_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1516 __le32 tx_su_ol_nss[ATH12K_HTT_TX_PDEV_STATS_NUM_SPATIAL_STREAMS]; 1517 __le32 tx_su_txbf_bw[ATH12K_HTT_TXBF_NUM_BW_CNTRS]; 1518 __le32 tx_su_ibf_bw[ATH12K_HTT_TXBF_NUM_BW_CNTRS]; 1519 __le32 tx_su_ol_bw[ATH12K_HTT_TXBF_NUM_BW_CNTRS]; 1520 __le32 tx_legacy_ofdm_rate[ATH12K_HTT_TX_PDEV_STATS_NUM_LEGACY_OFDM_STATS]; 1521 __le32 txbf[ATH12K_HTT_TXBF_NUM_REDUCED_CHAN_TYPES][ATH12K_HTT_TXBF_NUM_BW_CNTRS]; 1522 __le32 ibf[ATH12K_HTT_TXBF_NUM_REDUCED_CHAN_TYPES][ATH12K_HTT_TXBF_NUM_BW_CNTRS]; 1523 __le32 ol[ATH12K_HTT_TXBF_NUM_REDUCED_CHAN_TYPES][ATH12K_HTT_TXBF_NUM_BW_CNTRS]; 1524 __le32 txbf_flag_set_mu_mode; 1525 __le32 txbf_flag_set_final_status; 1526 __le32 txbf_flag_not_set_verified_txbf_mode; 1527 __le32 txbf_flag_not_set_disable_p2p_access; 1528 __le32 txbf_flag_not_set_max_nss_in_he160; 1529 __le32 txbf_flag_not_set_disable_uldlofdma; 1530 __le32 txbf_flag_not_set_mcs_threshold_val; 1531 __le32 txbf_flag_not_set_final_status; 1532} __packed; 1533 1534struct ath12k_htt_txbf_ofdma_ax_ndpa_stats_elem_t { 1535 __le32 ax_ofdma_ndpa_queued; 1536 __le32 ax_ofdma_ndpa_tried; 1537 __le32 ax_ofdma_ndpa_flush; 1538 __le32 ax_ofdma_ndpa_err; 1539} __packed; 1540 1541struct ath12k_htt_txbf_ofdma_ax_ndpa_stats_tlv { 1542 __le32 num_elems_ax_ndpa_arr; 1543 __le32 arr_elem_size_ax_ndpa; 1544 DECLARE_FLEX_ARRAY(struct ath12k_htt_txbf_ofdma_ax_ndpa_stats_elem_t, ax_ndpa); 1545} __packed; 1546 1547struct ath12k_htt_txbf_ofdma_ax_ndp_stats_elem_t { 1548 __le32 ax_ofdma_ndp_queued; 1549 __le32 ax_ofdma_ndp_tried; 1550 __le32 ax_ofdma_ndp_flush; 1551 __le32 ax_ofdma_ndp_err; 1552} __packed; 1553 1554struct ath12k_htt_txbf_ofdma_ax_ndp_stats_tlv { 1555 __le32 num_elems_ax_ndp_arr; 1556 __le32 arr_elem_size_ax_ndp; 1557 DECLARE_FLEX_ARRAY(struct ath12k_htt_txbf_ofdma_ax_ndp_stats_elem_t, ax_ndp); 1558} __packed; 1559 1560struct ath12k_htt_txbf_ofdma_ax_brp_stats_elem_t { 1561 __le32 ax_ofdma_brp_queued; 1562 __le32 ax_ofdma_brp_tried; 1563 __le32 ax_ofdma_brp_flushed; 1564 __le32 ax_ofdma_brp_err; 1565 __le32 ax_ofdma_num_cbf_rcvd; 1566} __packed; 1567 1568struct ath12k_htt_txbf_ofdma_ax_brp_stats_tlv { 1569 __le32 num_elems_ax_brp_arr; 1570 __le32 arr_elem_size_ax_brp; 1571 DECLARE_FLEX_ARRAY(struct ath12k_htt_txbf_ofdma_ax_brp_stats_elem_t, ax_brp); 1572} __packed; 1573 1574struct ath12k_htt_txbf_ofdma_ax_steer_stats_elem_t { 1575 __le32 num_ppdu_steer; 1576 __le32 num_ppdu_ol; 1577 __le32 num_usr_prefetch; 1578 __le32 num_usr_sound; 1579 __le32 num_usr_force_sound; 1580} __packed; 1581 1582struct ath12k_htt_txbf_ofdma_ax_steer_stats_tlv { 1583 __le32 num_elems_ax_steer_arr; 1584 __le32 arr_elem_size_ax_steer; 1585 DECLARE_FLEX_ARRAY(struct ath12k_htt_txbf_ofdma_ax_steer_stats_elem_t, ax_steer); 1586} __packed; 1587 1588struct ath12k_htt_txbf_ofdma_ax_steer_mpdu_stats_tlv { 1589 __le32 ax_ofdma_rbo_steer_mpdus_tried; 1590 __le32 ax_ofdma_rbo_steer_mpdus_failed; 1591 __le32 ax_ofdma_sifs_steer_mpdus_tried; 1592 __le32 ax_ofdma_sifs_steer_mpdus_failed; 1593} __packed; 1594 1595enum ath12k_htt_stats_page_lock_state { 1596 ATH12K_HTT_STATS_PAGE_LOCKED = 0, 1597 ATH12K_HTT_STATS_PAGE_UNLOCKED = 1, 1598 ATH12K_NUM_PG_LOCK_STATE 1599}; 1600 1601#define ATH12K_PAGER_MAX 10 1602 1603#define ATH12K_HTT_DLPAGER_ASYNC_LOCK_PG_CNT_INFO0 GENMASK(7, 0) 1604#define ATH12K_HTT_DLPAGER_SYNC_LOCK_PG_CNT_INFO0 GENMASK(15, 8) 1605#define ATH12K_HTT_DLPAGER_TOTAL_LOCK_PAGES_INFO1 GENMASK(15, 0) 1606#define ATH12K_HTT_DLPAGER_TOTAL_FREE_PAGES_INFO1 GENMASK(31, 16) 1607#define ATH12K_HTT_DLPAGER_TOTAL_LOCK_PAGES_INFO2 GENMASK(15, 0) 1608#define ATH12K_HTT_DLPAGER_TOTAL_FREE_PAGES_INFO2 GENMASK(31, 16) 1609 1610struct ath12k_htt_pgs_info { 1611 __le32 page_num; 1612 __le32 num_pgs; 1613 __le32 ts_lsb; 1614 __le32 ts_msb; 1615} __packed; 1616 1617struct ath12k_htt_dl_pager_stats_tlv { 1618 __le32 info0; 1619 __le32 info1; 1620 __le32 info2; 1621 struct ath12k_htt_pgs_info pgs_info[ATH12K_NUM_PG_LOCK_STATE][ATH12K_PAGER_MAX]; 1622} __packed; 1623 1624#define ATH12K_HTT_STATS_MAX_CHAINS 8 1625#define ATH12K_HTT_MAX_RX_PKT_CNT 8 1626#define ATH12K_HTT_MAX_RX_PKT_CRC_PASS_CNT 8 1627#define ATH12K_HTT_MAX_PER_BLK_ERR_CNT 20 1628#define ATH12K_HTT_MAX_RX_OTA_ERR_CNT 14 1629#define ATH12K_HTT_MAX_CH_PWR_INFO_SIZE 16 1630 1631struct ath12k_htt_phy_stats_tlv { 1632 a_sle32 nf_chain[ATH12K_HTT_STATS_MAX_CHAINS]; 1633 __le32 false_radar_cnt; 1634 __le32 radar_cs_cnt; 1635 a_sle32 ani_level; 1636 __le32 fw_run_time; 1637 a_sle32 runtime_nf_chain[ATH12K_HTT_STATS_MAX_CHAINS]; 1638} __packed; 1639 1640struct ath12k_htt_phy_counters_tlv { 1641 __le32 rx_ofdma_timing_err_cnt; 1642 __le32 rx_cck_fail_cnt; 1643 __le32 mactx_abort_cnt; 1644 __le32 macrx_abort_cnt; 1645 __le32 phytx_abort_cnt; 1646 __le32 phyrx_abort_cnt; 1647 __le32 phyrx_defer_abort_cnt; 1648 __le32 rx_gain_adj_lstf_event_cnt; 1649 __le32 rx_gain_adj_non_legacy_cnt; 1650 __le32 rx_pkt_cnt[ATH12K_HTT_MAX_RX_PKT_CNT]; 1651 __le32 rx_pkt_crc_pass_cnt[ATH12K_HTT_MAX_RX_PKT_CRC_PASS_CNT]; 1652 __le32 per_blk_err_cnt[ATH12K_HTT_MAX_PER_BLK_ERR_CNT]; 1653 __le32 rx_ota_err_cnt[ATH12K_HTT_MAX_RX_OTA_ERR_CNT]; 1654} __packed; 1655 1656struct ath12k_htt_phy_reset_stats_tlv { 1657 __le32 pdev_id; 1658 __le32 chan_mhz; 1659 __le32 chan_band_center_freq1; 1660 __le32 chan_band_center_freq2; 1661 __le32 chan_phy_mode; 1662 __le32 chan_flags; 1663 __le32 chan_num; 1664 __le32 reset_cause; 1665 __le32 prev_reset_cause; 1666 __le32 phy_warm_reset_src; 1667 __le32 rx_gain_tbl_mode; 1668 __le32 xbar_val; 1669 __le32 force_calibration; 1670 __le32 phyrf_mode; 1671 __le32 phy_homechan; 1672 __le32 phy_tx_ch_mask; 1673 __le32 phy_rx_ch_mask; 1674 __le32 phybb_ini_mask; 1675 __le32 phyrf_ini_mask; 1676 __le32 phy_dfs_en_mask; 1677 __le32 phy_sscan_en_mask; 1678 __le32 phy_synth_sel_mask; 1679 __le32 phy_adfs_freq; 1680 __le32 cck_fir_settings; 1681 __le32 phy_dyn_pri_chan; 1682 __le32 cca_thresh; 1683 __le32 dyn_cca_status; 1684 __le32 rxdesense_thresh_hw; 1685 __le32 rxdesense_thresh_sw; 1686} __packed; 1687 1688struct ath12k_htt_phy_reset_counters_tlv { 1689 __le32 pdev_id; 1690 __le32 cf_active_low_fail_cnt; 1691 __le32 cf_active_low_pass_cnt; 1692 __le32 phy_off_through_vreg_cnt; 1693 __le32 force_calibration_cnt; 1694 __le32 rf_mode_switch_phy_off_cnt; 1695 __le32 temperature_recal_cnt; 1696} __packed; 1697 1698struct ath12k_htt_phy_tpc_stats_tlv { 1699 __le32 pdev_id; 1700 __le32 tx_power_scale; 1701 __le32 tx_power_scale_db; 1702 __le32 min_negative_tx_power; 1703 __le32 reg_ctl_domain; 1704 __le32 max_reg_allowed_power[ATH12K_HTT_STATS_MAX_CHAINS]; 1705 __le32 max_reg_allowed_power_6ghz[ATH12K_HTT_STATS_MAX_CHAINS]; 1706 __le32 twice_max_rd_power; 1707 __le32 max_tx_power; 1708 __le32 home_max_tx_power; 1709 __le32 psd_power; 1710 __le32 eirp_power; 1711 __le32 power_type_6ghz; 1712 __le32 sub_band_cfreq[ATH12K_HTT_MAX_CH_PWR_INFO_SIZE]; 1713 __le32 sub_band_txpower[ATH12K_HTT_MAX_CH_PWR_INFO_SIZE]; 1714} __packed; 1715 1716struct ath12k_htt_t2h_soc_txrx_stats_common_tlv { 1717 __le32 inv_peers_msdu_drop_count_hi; 1718 __le32 inv_peers_msdu_drop_count_lo; 1719} __packed; 1720 1721#define ATH12K_HTT_AST_PDEV_ID_INFO GENMASK(1, 0) 1722#define ATH12K_HTT_AST_VDEV_ID_INFO GENMASK(9, 2) 1723#define ATH12K_HTT_AST_NEXT_HOP_INFO BIT(10) 1724#define ATH12K_HTT_AST_MCAST_INFO BIT(11) 1725#define ATH12K_HTT_AST_MONITOR_DIRECT_INFO BIT(12) 1726#define ATH12K_HTT_AST_MESH_STA_INFO BIT(13) 1727#define ATH12K_HTT_AST_MEC_INFO BIT(14) 1728#define ATH12K_HTT_AST_INTRA_BSS_INFO BIT(15) 1729 1730struct ath12k_htt_ast_entry_tlv { 1731 __le32 sw_peer_id; 1732 __le32 ast_index; 1733 struct htt_mac_addr mac_addr; 1734 __le32 info; 1735} __packed; 1736 1737enum ath12k_htt_stats_direction { 1738 ATH12K_HTT_STATS_DIRECTION_TX, 1739 ATH12K_HTT_STATS_DIRECTION_RX 1740}; 1741 1742enum ath12k_htt_stats_ppdu_type { 1743 ATH12K_HTT_STATS_PPDU_TYPE_MODE_SU, 1744 ATH12K_HTT_STATS_PPDU_TYPE_DL_MU_MIMO, 1745 ATH12K_HTT_STATS_PPDU_TYPE_UL_MU_MIMO, 1746 ATH12K_HTT_STATS_PPDU_TYPE_DL_MU_OFDMA, 1747 ATH12K_HTT_STATS_PPDU_TYPE_UL_MU_OFDMA 1748}; 1749 1750enum ath12k_htt_stats_param_type { 1751 ATH12K_HTT_STATS_PREAM_OFDM, 1752 ATH12K_HTT_STATS_PREAM_CCK, 1753 ATH12K_HTT_STATS_PREAM_HT, 1754 ATH12K_HTT_STATS_PREAM_VHT, 1755 ATH12K_HTT_STATS_PREAM_HE, 1756 ATH12K_HTT_STATS_PREAM_EHT, 1757 ATH12K_HTT_STATS_PREAM_RSVD1, 1758 ATH12K_HTT_STATS_PREAM_COUNT, 1759}; 1760 1761#define ATH12K_HTT_PUNCT_STATS_MAX_SUBBAND_CNT 32 1762 1763struct ath12k_htt_pdev_puncture_stats_tlv { 1764 __le32 mac_id__word; 1765 __le32 direction; 1766 __le32 preamble; 1767 __le32 ppdu_type; 1768 __le32 subband_cnt; 1769 __le32 last_used_pattern_mask; 1770 __le32 num_subbands_used_cnt[ATH12K_HTT_PUNCT_STATS_MAX_SUBBAND_CNT]; 1771} __packed; 1772 1773struct ath12k_htt_dmac_reset_stats_tlv { 1774 __le32 reset_count; 1775 __le32 reset_time_lo_ms; 1776 __le32 reset_time_hi_ms; 1777 __le32 disengage_time_lo_ms; 1778 __le32 disengage_time_hi_ms; 1779 __le32 engage_time_lo_ms; 1780 __le32 engage_time_hi_ms; 1781 __le32 disengage_count; 1782 __le32 engage_count; 1783 __le32 drain_dest_ring_mask; 1784} __packed; 1785 1786struct ath12k_htt_pdev_sched_algo_ofdma_stats_tlv { 1787 __le32 mac_id__word; 1788 __le32 rate_based_dlofdma_enabled_cnt[ATH12K_HTT_NUM_AC_WMM]; 1789 __le32 rate_based_dlofdma_disabled_cnt[ATH12K_HTT_NUM_AC_WMM]; 1790 __le32 rate_based_dlofdma_probing_cnt[ATH12K_HTT_NUM_AC_WMM]; 1791 __le32 rate_based_dlofdma_monitor_cnt[ATH12K_HTT_NUM_AC_WMM]; 1792 __le32 chan_acc_lat_based_dlofdma_enabled_cnt[ATH12K_HTT_NUM_AC_WMM]; 1793 __le32 chan_acc_lat_based_dlofdma_disabled_cnt[ATH12K_HTT_NUM_AC_WMM]; 1794 __le32 chan_acc_lat_based_dlofdma_monitor_cnt[ATH12K_HTT_NUM_AC_WMM]; 1795 __le32 downgrade_to_dl_su_ru_alloc_fail[ATH12K_HTT_NUM_AC_WMM]; 1796 __le32 candidate_list_single_user_disable_ofdma[ATH12K_HTT_NUM_AC_WMM]; 1797 __le32 dl_cand_list_dropped_high_ul_qos_weight[ATH12K_HTT_NUM_AC_WMM]; 1798 __le32 ax_dlofdma_disabled_due_to_pipelining[ATH12K_HTT_NUM_AC_WMM]; 1799 __le32 dlofdma_disabled_su_only_eligible[ATH12K_HTT_NUM_AC_WMM]; 1800 __le32 dlofdma_disabled_consec_no_mpdus_tried[ATH12K_HTT_NUM_AC_WMM]; 1801 __le32 dlofdma_disabled_consec_no_mpdus_success[ATH12K_HTT_NUM_AC_WMM]; 1802} __packed; 1803 1804#define ATH12K_HTT_TX_PDEV_STATS_NUM_BW_CNTRS 4 1805#define ATH12K_HTT_PDEV_STAT_NUM_SPATIAL_STREAMS 8 1806#define ATH12K_HTT_TXBF_RATE_STAT_NUM_MCS_CNTRS 14 1807 1808enum ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE { 1809 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_26, 1810 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_52, 1811 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_52_26, 1812 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_106, 1813 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_106_26, 1814 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_242, 1815 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_484, 1816 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_484_242, 1817 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996, 1818 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996_484, 1819 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996_484_242, 1820 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x2, 1821 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x2_484, 1822 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x3, 1823 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x3_484, 1824 ATH12K_HTT_TX_RX_PDEV_STATS_BE_RU_SIZE_996x4, 1825 ATH12K_HTT_TX_RX_PDEV_NUM_BE_RU_SIZE_CNTRS, 1826}; 1827 1828enum ATH12K_HTT_RC_MODE { 1829 ATH12K_HTT_RC_MODE_SU_OL, 1830 ATH12K_HTT_RC_MODE_SU_BF, 1831 ATH12K_HTT_RC_MODE_MU1_INTF, 1832 ATH12K_HTT_RC_MODE_MU2_INTF, 1833 ATH12K_HTT_RC_MODE_MU3_INTF, 1834 ATH12K_HTT_RC_MODE_MU4_INTF, 1835 ATH12K_HTT_RC_MODE_MU5_INTF, 1836 ATH12K_HTT_RC_MODE_MU6_INTF, 1837 ATH12K_HTT_RC_MODE_MU7_INTF, 1838 ATH12K_HTT_RC_MODE_2D_COUNT 1839}; 1840 1841enum ath12k_htt_stats_rc_mode { 1842 ATH12K_HTT_STATS_RC_MODE_DLSU = 0, 1843 ATH12K_HTT_STATS_RC_MODE_DLMUMIMO = 1, 1844 ATH12K_HTT_STATS_RC_MODE_DLOFDMA = 2, 1845 ATH12K_HTT_STATS_RC_MODE_ULMUMIMO = 3, 1846 ATH12K_HTT_STATS_RC_MODE_ULOFDMA = 4, 1847}; 1848 1849enum ath12k_htt_stats_ru_type { 1850 ATH12K_HTT_STATS_RU_TYPE_INVALID, 1851 ATH12K_HTT_STATS_RU_TYPE_SINGLE_RU_ONLY, 1852 ATH12K_HTT_STATS_RU_TYPE_SINGLE_AND_MULTI_RU, 1853}; 1854 1855struct ath12k_htt_tx_rate_stats { 1856 __le32 ppdus_tried; 1857 __le32 ppdus_ack_failed; 1858 __le32 mpdus_tried; 1859 __le32 mpdus_failed; 1860} __packed; 1861 1862struct ath12k_htt_tx_per_rate_stats_tlv { 1863 __le32 rc_mode; 1864 __le32 last_probed_mcs; 1865 __le32 last_probed_nss; 1866 __le32 last_probed_bw; 1867 struct ath12k_htt_tx_rate_stats per_bw[ATH12K_HTT_TX_PDEV_STATS_NUM_BW_CNTRS]; 1868 struct ath12k_htt_tx_rate_stats per_nss[ATH12K_HTT_PDEV_STAT_NUM_SPATIAL_STREAMS]; 1869 struct ath12k_htt_tx_rate_stats per_mcs[ATH12K_HTT_TXBF_RATE_STAT_NUM_MCS_CNTRS]; 1870 struct ath12k_htt_tx_rate_stats per_bw320; 1871 __le32 probe_cnt[ATH12K_HTT_RC_MODE_2D_COUNT]; 1872 __le32 ru_type; 1873 struct ath12k_htt_tx_rate_stats ru[ATH12K_HTT_TX_RX_PDEV_NUM_BE_RU_SIZE_CNTRS]; 1874} __packed; 1875 1876#define ATH12K_HTT_TX_PDEV_NUM_BE_MCS_CNTRS 16 1877#define ATH12K_HTT_TX_PDEV_NUM_BE_BW_CNTRS 5 1878#define ATH12K_HTT_TX_PDEV_NUM_EHT_SIG_MCS_CNTRS 4 1879#define ATH12K_HTT_TX_PDEV_NUM_GI_CNTRS 4 1880 1881struct ath12k_htt_tx_pdev_rate_stats_be_ofdma_tlv { 1882 __le32 mac_id__word; 1883 __le32 be_ofdma_tx_ldpc; 1884 __le32 be_ofdma_tx_mcs[ATH12K_HTT_TX_PDEV_NUM_BE_MCS_CNTRS]; 1885 __le32 be_ofdma_tx_nss[ATH12K_HTT_PDEV_STAT_NUM_SPATIAL_STREAMS]; 1886 __le32 be_ofdma_tx_bw[ATH12K_HTT_TX_PDEV_NUM_BE_BW_CNTRS]; 1887 __le32 gi[ATH12K_HTT_TX_PDEV_NUM_GI_CNTRS][ATH12K_HTT_TX_PDEV_NUM_BE_MCS_CNTRS]; 1888 __le32 be_ofdma_tx_ru_size[ATH12K_HTT_TX_RX_PDEV_NUM_BE_RU_SIZE_CNTRS]; 1889 __le32 be_ofdma_eht_sig_mcs[ATH12K_HTT_TX_PDEV_NUM_EHT_SIG_MCS_CNTRS]; 1890} __packed; 1891 1892struct ath12k_htt_pdev_mbssid_ctrl_frame_tlv { 1893 __le32 mac_id__word; 1894 __le32 basic_trigger_across_bss; 1895 __le32 basic_trigger_within_bss; 1896 __le32 bsr_trigger_across_bss; 1897 __le32 bsr_trigger_within_bss; 1898 __le32 mu_rts_across_bss; 1899 __le32 mu_rts_within_bss; 1900 __le32 ul_mumimo_trigger_across_bss; 1901 __le32 ul_mumimo_trigger_within_bss; 1902} __packed; 1903 1904struct ath12k_htt_pdev_tdma_stats_tlv { 1905 __le32 mac_id__word; 1906 __le32 num_tdma_active_schedules; 1907 __le32 num_tdma_reserved_schedules; 1908 __le32 num_tdma_restricted_schedules; 1909 __le32 num_tdma_unconfigured_schedules; 1910 __le32 num_tdma_slot_switches; 1911 __le32 num_tdma_edca_switches; 1912} __packed; 1913 1914struct ath12k_htt_mlo_sched_stats_tlv { 1915 __le32 pref_link_num_sec_link_sched; 1916 __le32 pref_link_num_pref_link_timeout; 1917 __le32 pref_link_num_pref_link_sch_delay_ipc; 1918 __le32 pref_link_num_pref_link_timeout_ipc; 1919} __packed; 1920 1921#define ATH12K_HTT_HWMLO_MAX_LINKS 6 1922#define ATH12K_HTT_MLO_MAX_IPC_RINGS 7 1923 1924struct ath12k_htt_pdev_mlo_ipc_stats_tlv { 1925 __le32 mlo_ipc_ring_cnt[ATH12K_HTT_HWMLO_MAX_LINKS][ATH12K_HTT_MLO_MAX_IPC_RINGS]; 1926} __packed; 1927 1928struct ath12k_htt_stats_pdev_rtt_resp_stats_tlv { 1929 __le32 pdev_id; 1930 __le32 tx_11mc_ftm_suc; 1931 __le32 tx_11mc_ftm_suc_retry; 1932 __le32 tx_11mc_ftm_fail; 1933 __le32 rx_11mc_ftmr_cnt; 1934 __le32 rx_11mc_ftmr_dup_cnt; 1935 __le32 rx_11mc_iftmr_cnt; 1936 __le32 rx_11mc_iftmr_dup_cnt; 1937 __le32 ftmr_drop_11mc_resp_role_not_enabled_cnt; 1938 __le32 initiator_active_responder_rejected_cnt; 1939 __le32 responder_terminate_cnt; 1940 __le32 active_rsta_open; 1941 __le32 active_rsta_mac; 1942 __le32 active_rsta_mac_phy; 1943 __le32 num_assoc_ranging_peers; 1944 __le32 num_unassoc_ranging_peers; 1945 __le32 responder_alloc_cnt; 1946 __le32 responder_alloc_failure; 1947 __le32 pn_check_failure_cnt; 1948 __le32 pasn_m1_auth_recv_cnt; 1949 __le32 pasn_m1_auth_drop_cnt; 1950 __le32 pasn_m2_auth_recv_cnt; 1951 __le32 pasn_m2_auth_tx_fail_cnt; 1952 __le32 pasn_m3_auth_recv_cnt; 1953 __le32 pasn_m3_auth_drop_cnt; 1954 __le32 pasn_peer_create_request_cnt; 1955 __le32 pasn_peer_create_timeout_cnt; 1956 __le32 pasn_peer_created_cnt; 1957 __le32 sec_ranging_not_supported_mfp_not_setup; 1958 __le32 non_sec_ranging_discarded_for_assoc_peer; 1959 __le32 open_ranging_discarded_set_for_pasn_peer; 1960 __le32 unassoc_non_pasn_ranging_not_supported; 1961 __le32 num_req_bw_20_mhz; 1962 __le32 num_req_bw_40_mhz; 1963 __le32 num_req_bw_80_mhz; 1964 __le32 num_req_bw_160_mhz; 1965 __le32 tx_11az_ftm_successful; 1966 __le32 tx_11az_ftm_failed; 1967 __le32 rx_11az_ftmr_cnt; 1968 __le32 rx_11az_ftmr_dup_cnt; 1969 __le32 rx_11az_iftmr_dup_cnt; 1970 __le32 malformed_ftmr; 1971 __le32 ftmr_drop_ntb_resp_role_not_enabled_cnt; 1972 __le32 ftmr_drop_tb_resp_role_not_enabled_cnt; 1973 __le32 invalid_ftm_request_params; 1974 __le32 requested_bw_format_not_supported; 1975 __le32 ntb_unsec_unassoc_ranging_peer_alloc_failed; 1976 __le32 tb_unassoc_unsec_pasn_peer_creation_failed; 1977 __le32 num_ranging_sequences_processed; 1978 __le32 ntb_tx_ndp; 1979 __le32 ndp_rx_cnt; 1980 __le32 num_ntb_ranging_ndpas_recv; 1981 __le32 recv_lmr; 1982 __le32 invalid_ftmr_cnt; 1983 __le32 max_time_bw_meas_exp_cnt; 1984} __packed; 1985 1986#define ATH12K_HTT_MAX_SCH_CMD_RESULT 25 1987#define ATH12K_HTT_SCH_CMD_STATUS_CNT 9 1988 1989struct ath12k_htt_stats_pdev_rtt_init_stats_tlv { 1990 __le32 pdev_id; 1991 __le32 tx_11mc_ftmr_cnt; 1992 __le32 tx_11mc_ftmr_fail; 1993 __le32 tx_11mc_ftmr_suc_retry; 1994 __le32 rx_11mc_ftm_cnt; 1995 __le32 tx_meas_req_count; 1996 __le32 init_role_not_enabled; 1997 __le32 initiator_terminate_cnt; 1998 __le32 tx_11az_ftmr_fail; 1999 __le32 tx_11az_ftmr_start; 2000 __le32 tx_11az_ftmr_stop; 2001 __le32 rx_11az_ftm_cnt; 2002 __le32 active_ista; 2003 __le32 invalid_preamble; 2004 __le32 invalid_chan_bw_format; 2005 __le32 mgmt_buff_alloc_fail_cnt; 2006 __le32 ftm_parse_failure; 2007 __le32 ranging_negotiation_successful_cnt; 2008 __le32 incompatible_ftm_params; 2009 __le32 sec_ranging_req_in_open_mode; 2010 __le32 ftmr_tx_failed_null_11az_peer; 2011 __le32 ftmr_retry_timeout; 2012 __le32 max_time_bw_meas_exp_cnt; 2013 __le32 tb_meas_duration_expiry_cnt; 2014 __le32 num_tb_ranging_requests; 2015 __le32 ntbr_triggered_successfully; 2016 __le32 ntbr_trigger_failed; 2017 __le32 invalid_or_no_vreg_idx; 2018 __le32 set_vreg_params_failed; 2019 __le32 sac_mismatch; 2020 __le32 pasn_m1_auth_recv_cnt; 2021 __le32 pasn_m1_auth_tx_fail_cnt; 2022 __le32 pasn_m2_auth_recv_cnt; 2023 __le32 pasn_m2_auth_drop_cnt; 2024 __le32 pasn_m3_auth_recv_cnt; 2025 __le32 pasn_m3_auth_tx_fail_cnt; 2026 __le32 pasn_peer_create_request_cnt; 2027 __le32 pasn_peer_create_timeout_cnt; 2028 __le32 pasn_peer_created_cnt; 2029 __le32 ntbr_ndpa_failed; 2030 __le32 ntbr_sequence_successful; 2031 __le32 ntbr_ndp_failed; 2032 __le32 sch_cmd_status_cnts[ATH12K_HTT_SCH_CMD_STATUS_CNT]; 2033 __le32 lmr_timeout; 2034 __le32 lmr_recv; 2035 __le32 num_trigger_frames_received; 2036 __le32 num_tb_ranging_ndpas_recv; 2037 __le32 ndp_rx_cnt; 2038} __packed; 2039 2040struct ath12k_htt_stats_pdev_rtt_hw_stats_tlv { 2041 __le32 ista_ranging_ndpa_cnt; 2042 __le32 ista_ranging_ndp_cnt; 2043 __le32 ista_ranging_i2r_lmr_cnt; 2044 __le32 rtsa_ranging_resp_cnt; 2045 __le32 rtsa_ranging_ndp_cnt; 2046 __le32 rsta_ranging_lmr_cnt; 2047 __le32 tb_ranging_cts2s_rcvd_cnt; 2048 __le32 tb_ranging_ndp_rcvd_cnt; 2049 __le32 tb_ranging_lmr_rcvd_cnt; 2050 __le32 tb_ranging_tf_poll_resp_sent_cnt; 2051 __le32 tb_ranging_tf_sound_resp_sent_cnt; 2052 __le32 tb_ranging_tf_report_resp_sent_cnt; 2053} __packed; 2054 2055enum ath12k_htt_stats_txsend_ftype { 2056 ATH12K_HTT_FTYPE_TF_POLL, 2057 ATH12K_HTT_FTYPE_TF_SOUND, 2058 ATH12K_HTT_FTYPE_TBR_NDPA, 2059 ATH12K_HTT_FTYPE_TBR_NDP, 2060 ATH12K_HTT_FTYPE_TBR_LMR, 2061 ATH12K_HTT_FTYPE_TF_RPRT, 2062 ATH12K_HTT_FTYPE_MAX 2063}; 2064 2065struct ath12k_htt_stats_pdev_rtt_tbr_tlv { 2066 __le32 su_ftype[ATH12K_HTT_FTYPE_MAX]; 2067 __le32 mu_ftype[ATH12K_HTT_FTYPE_MAX]; 2068} __packed; 2069 2070struct ath12k_htt_stats_pdev_rtt_tbr_cmd_result_stats_tlv { 2071 __le32 tbr_num_sch_cmd_result_buckets; 2072 __le32 su_res[ATH12K_HTT_FTYPE_MAX][ATH12K_HTT_MAX_SCH_CMD_RESULT]; 2073 __le32 mu_res[ATH12K_HTT_FTYPE_MAX][ATH12K_HTT_MAX_SCH_CMD_RESULT]; 2074} __packed; 2075 2076#endif
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