core.h

   1/* SPDX-License-Identifier: BSD-3-Clause-Clear */
   2/*
   3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
   4 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
   5 */
   6
   7#ifndef ATH12K_CORE_H
   8#define ATH12K_CORE_H
   9
  10#include <linux/types.h>
  11#include <linux/interrupt.h>
  12#include <linux/irq.h>
  13#include <linux/bitfield.h>
  14#include <linux/dmi.h>
  15#include <linux/ctype.h>
  16#include <linux/firmware.h>
  17#include <linux/of_reserved_mem.h>
  18#include <linux/panic_notifier.h>
  19#include <linux/average.h>
  20#include <linux/of.h>
  21#include "qmi.h"
  22#include "htc.h"
  23#include "wmi.h"
  24#include "hal.h"
  25#include "dp.h"
  26#include "ce.h"
  27#include "mac.h"
  28#include "hw.h"
  29#include "hal_rx.h"
  30#include "reg.h"
  31#include "dbring.h"
  32#include "fw.h"
  33#include "acpi.h"
  34#include "wow.h"
  35#include "debugfs_htt_stats.h"
  36#include "coredump.h"
  37
  38#define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
  39
  40#define ATH12K_TX_MGMT_NUM_PENDING_MAX	512
  41
  42#define ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI 64
  43
  44/* Pending management packets threshold for dropping probe responses */
  45#define ATH12K_PRB_RSP_DROP_THRESHOLD ((ATH12K_TX_MGMT_TARGET_MAX_SUPPORT_WMI * 3) / 4)
  46
  47/* SMBIOS type containing Board Data File Name Extension */
  48#define ATH12K_SMBIOS_BDF_EXT_TYPE 0xF8
  49
  50/* SMBIOS type structure length (excluding strings-set) */
  51#define ATH12K_SMBIOS_BDF_EXT_LENGTH 0x9
  52
  53/* The magic used by QCA spec */
  54#define ATH12K_SMBIOS_BDF_EXT_MAGIC "BDF_"
  55
  56#define ATH12K_INVALID_HW_MAC_ID	0xFF
  57#define ATH12K_CONNECTION_LOSS_HZ	(3 * HZ)
  58
  59#define ATH12K_MON_TIMER_INTERVAL  10
  60#define ATH12K_RESET_TIMEOUT_HZ			(20 * HZ)
  61#define ATH12K_RESET_MAX_FAIL_COUNT_FIRST	3
  62#define ATH12K_RESET_MAX_FAIL_COUNT_FINAL	5
  63#define ATH12K_RESET_FAIL_TIMEOUT_HZ		(20 * HZ)
  64#define ATH12K_RECONFIGURE_TIMEOUT_HZ		(10 * HZ)
  65#define ATH12K_RECOVER_START_TIMEOUT_HZ		(20 * HZ)
  66
  67#define ATH12K_MAX_DEVICES 3
  68#define ATH12K_GROUP_MAX_RADIO (ATH12K_MAX_DEVICES * MAX_RADIOS)
  69#define ATH12K_INVALID_GROUP_ID  0xFF
  70#define ATH12K_INVALID_DEVICE_ID 0xFF
  71
  72#define ATH12K_MAX_MLO_PEERS            256
  73#define ATH12K_MLO_PEER_ID_INVALID      0xFFFF
  74
  75#define ATH12K_INVALID_RSSI_FULL -1
  76#define ATH12K_INVALID_RSSI_EMPTY -128
  77
  78enum ath12k_bdf_search {
  79	ATH12K_BDF_SEARCH_DEFAULT,
  80	ATH12K_BDF_SEARCH_BUS_AND_BOARD,
  81};
  82
  83enum wme_ac {
  84	WME_AC_BE,
  85	WME_AC_BK,
  86	WME_AC_VI,
  87	WME_AC_VO,
  88	WME_NUM_AC
  89};
  90
  91#define ATH12K_HT_MCS_MAX	7
  92#define ATH12K_VHT_MCS_MAX	9
  93#define ATH12K_HE_MCS_MAX	11
  94#define ATH12K_EHT_MCS_MAX	15
  95
  96enum ath12k_crypt_mode {
  97	/* Only use hardware crypto engine */
  98	ATH12K_CRYPT_MODE_HW,
  99	/* Only use software crypto */
 100	ATH12K_CRYPT_MODE_SW,
 101};
 102
 103static inline enum wme_ac ath12k_tid_to_ac(u32 tid)
 104{
 105	return (((tid == 0) || (tid == 3)) ? WME_AC_BE :
 106		((tid == 1) || (tid == 2)) ? WME_AC_BK :
 107		((tid == 4) || (tid == 5)) ? WME_AC_VI :
 108		WME_AC_VO);
 109}
 110
 111static inline u64 ath12k_le32hilo_to_u64(__le32 hi, __le32 lo)
 112{
 113	u64 hi64 = le32_to_cpu(hi);
 114	u64 lo64 = le32_to_cpu(lo);
 115
 116	return (hi64 << 32) | lo64;
 117}
 118
 119enum ath12k_skb_flags {
 120	ATH12K_SKB_HW_80211_ENCAP = BIT(0),
 121	ATH12K_SKB_CIPHER_SET = BIT(1),
 122	ATH12K_SKB_MLO_STA = BIT(2),
 123};
 124
 125struct ath12k_skb_cb {
 126	dma_addr_t paddr;
 127	struct ath12k *ar;
 128	struct ieee80211_vif *vif;
 129	dma_addr_t paddr_ext_desc;
 130	u32 cipher;
 131	u8 flags;
 132	u8 link_id;
 133};
 134
 135struct ath12k_skb_rxcb {
 136	dma_addr_t paddr;
 137	bool is_first_msdu;
 138	bool is_last_msdu;
 139	bool is_continuation;
 140	bool is_mcbc;
 141	bool is_eapol;
 142	struct hal_rx_desc *rx_desc;
 143	u8 err_rel_src;
 144	u8 err_code;
 145	u8 hw_link_id;
 146	u8 unmapped;
 147	u8 is_frag;
 148	u8 tid;
 149	u16 peer_id;
 150	bool is_end_of_ppdu;
 151};
 152
 153enum ath12k_hw_rev {
 154	ATH12K_HW_QCN9274_HW10,
 155	ATH12K_HW_QCN9274_HW20,
 156	ATH12K_HW_WCN7850_HW20,
 157	ATH12K_HW_IPQ5332_HW10,
 158};
 159
 160enum ath12k_firmware_mode {
 161	/* the default mode, standard 802.11 functionality */
 162	ATH12K_FIRMWARE_MODE_NORMAL,
 163
 164	/* factory tests etc */
 165	ATH12K_FIRMWARE_MODE_FTM,
 166};
 167
 168#define ATH12K_IRQ_NUM_MAX 57
 169#define ATH12K_EXT_IRQ_NUM_MAX	16
 170#define ATH12K_MAX_TCL_RING_NUM	3
 171
 172struct ath12k_ext_irq_grp {
 173	struct ath12k_base *ab;
 174	u32 irqs[ATH12K_EXT_IRQ_NUM_MAX];
 175	u32 num_irq;
 176	u32 grp_id;
 177	u64 timestamp;
 178	bool napi_enabled;
 179	struct napi_struct napi;
 180	struct net_device *napi_ndev;
 181};
 182
 183enum ath12k_smbios_cc_type {
 184	/* disable country code setting from SMBIOS */
 185	ATH12K_SMBIOS_CC_DISABLE = 0,
 186
 187	/* set country code by ANSI country name, based on ISO3166-1 alpha2 */
 188	ATH12K_SMBIOS_CC_ISO = 1,
 189
 190	/* worldwide regdomain */
 191	ATH12K_SMBIOS_CC_WW = 2,
 192};
 193
 194struct ath12k_smbios_bdf {
 195	struct dmi_header hdr;
 196	u8 features_disabled;
 197
 198	/* enum ath12k_smbios_cc_type */
 199	u8 country_code_flag;
 200
 201	/* To set specific country, you need to set country code
 202	 * flag=ATH12K_SMBIOS_CC_ISO first, then if country is United
 203	 * States, then country code value = 0x5553 ("US",'U' = 0x55, 'S'=
 204	 * 0x53). To set country to INDONESIA, then country code value =
 205	 * 0x4944 ("IN", 'I'=0x49, 'D'=0x44). If country code flag =
 206	 * ATH12K_SMBIOS_CC_WW, then you can use worldwide regulatory
 207	 * setting.
 208	 */
 209	u16 cc_code;
 210
 211	u8 bdf_enabled;
 212	u8 bdf_ext[];
 213} __packed;
 214
 215#define HEHANDLE_CAP_PHYINFO_SIZE       3
 216#define HECAP_PHYINFO_SIZE              9
 217#define HECAP_MACINFO_SIZE              5
 218#define HECAP_TXRX_MCS_NSS_SIZE         2
 219#define HECAP_PPET16_PPET8_MAX_SIZE     25
 220
 221#define HE_PPET16_PPET8_SIZE            8
 222
 223/* 802.11ax PPE (PPDU packet Extension) threshold */
 224struct he_ppe_threshold {
 225	u32 numss_m1;
 226	u32 ru_mask;
 227	u32 ppet16_ppet8_ru3_ru0[HE_PPET16_PPET8_SIZE];
 228};
 229
 230struct ath12k_he {
 231	u8 hecap_macinfo[HECAP_MACINFO_SIZE];
 232	u32 hecap_rxmcsnssmap;
 233	u32 hecap_txmcsnssmap;
 234	u32 hecap_phyinfo[HEHANDLE_CAP_PHYINFO_SIZE];
 235	struct he_ppe_threshold   hecap_ppet;
 236	u32 heop_param;
 237};
 238
 239enum {
 240	WMI_HOST_TP_SCALE_MAX   = 0,
 241	WMI_HOST_TP_SCALE_50    = 1,
 242	WMI_HOST_TP_SCALE_25    = 2,
 243	WMI_HOST_TP_SCALE_12    = 3,
 244	WMI_HOST_TP_SCALE_MIN   = 4,
 245	WMI_HOST_TP_SCALE_SIZE   = 5,
 246};
 247
 248enum ath12k_scan_state {
 249	ATH12K_SCAN_IDLE,
 250	ATH12K_SCAN_STARTING,
 251	ATH12K_SCAN_RUNNING,
 252	ATH12K_SCAN_ABORTING,
 253};
 254
 255enum ath12k_11d_state {
 256	ATH12K_11D_IDLE,
 257	ATH12K_11D_PREPARING,
 258	ATH12K_11D_RUNNING,
 259};
 260
 261enum ath12k_hw_group_flags {
 262	ATH12K_GROUP_FLAG_REGISTERED,
 263	ATH12K_GROUP_FLAG_UNREGISTER,
 264};
 265
 266enum ath12k_dev_flags {
 267	ATH12K_FLAG_CAC_RUNNING,
 268	ATH12K_FLAG_CRASH_FLUSH,
 269	ATH12K_FLAG_RAW_MODE,
 270	ATH12K_FLAG_HW_CRYPTO_DISABLED,
 271	ATH12K_FLAG_RECOVERY,
 272	ATH12K_FLAG_UNREGISTERING,
 273	ATH12K_FLAG_REGISTERED,
 274	ATH12K_FLAG_QMI_FAIL,
 275	ATH12K_FLAG_HTC_SUSPEND_COMPLETE,
 276	ATH12K_FLAG_CE_IRQ_ENABLED,
 277	ATH12K_FLAG_EXT_IRQ_ENABLED,
 278	ATH12K_FLAG_QMI_FW_READY_COMPLETE,
 279	ATH12K_FLAG_FTM_SEGMENTED,
 280	ATH12K_FLAG_FIXED_MEM_REGION,
 281};
 282
 283struct ath12k_tx_conf {
 284	bool changed;
 285	u16 ac;
 286	struct ieee80211_tx_queue_params tx_queue_params;
 287};
 288
 289struct ath12k_key_conf {
 290	enum set_key_cmd cmd;
 291	struct list_head list;
 292	struct ieee80211_sta *sta;
 293	struct ieee80211_key_conf *key;
 294};
 295
 296struct ath12k_vif_cache {
 297	struct ath12k_tx_conf tx_conf;
 298	struct ath12k_key_conf key_conf;
 299	u32 bss_conf_changed;
 300};
 301
 302struct ath12k_rekey_data {
 303	u8 kck[NL80211_KCK_LEN];
 304	u8 kek[NL80211_KCK_LEN];
 305	u64 replay_ctr;
 306	bool enable_offload;
 307};
 308
 309struct ath12k_link_vif {
 310	u32 vdev_id;
 311	u32 beacon_interval;
 312	u32 dtim_period;
 313	u16 ast_hash;
 314	u16 ast_idx;
 315	u16 tcl_metadata;
 316	u8 hal_addr_search_flags;
 317	u8 search_type;
 318
 319	struct ath12k *ar;
 320
 321	int bank_id;
 322	u8 vdev_id_check_en;
 323	bool beacon_prot;
 324
 325	struct wmi_wmm_params_all_arg wmm_params;
 326	struct list_head list;
 327
 328	bool is_created;
 329	bool is_started;
 330	bool is_up;
 331	u8 bssid[ETH_ALEN];
 332	struct cfg80211_bitrate_mask bitrate_mask;
 333	struct delayed_work connection_loss_work;
 334	int num_legacy_stations;
 335	int rtscts_prot_mode;
 336	int txpower;
 337	bool rsnie_present;
 338	bool wpaie_present;
 339	u8 vdev_stats_id;
 340	u32 punct_bitmap;
 341	u8 link_id;
 342	struct ath12k_vif *ahvif;
 343	struct ath12k_rekey_data rekey_data;
 344	struct ath12k_link_stats link_stats;
 345	spinlock_t link_stats_lock; /* Protects updates to link_stats */
 346
 347	u8 current_cntdown_counter;
 348
 349	/* only used in station mode */
 350	bool is_sta_assoc_link;
 351
 352	struct ath12k_reg_tpc_power_info reg_tpc_info;
 353
 354	bool group_key_valid;
 355	struct wmi_vdev_install_key_arg group_key;
 356	bool pairwise_key_done;
 357	u16 num_stations;
 358	bool is_csa_in_progress;
 359	struct wiphy_work bcn_tx_work;
 360};
 361
 362struct ath12k_vif {
 363	enum wmi_vdev_type vdev_type;
 364	enum wmi_vdev_subtype vdev_subtype;
 365	struct ieee80211_vif *vif;
 366	struct ath12k_hw *ah;
 367
 368	union {
 369		struct {
 370			u32 uapsd;
 371		} sta;
 372		struct {
 373			/* 127 stations; wmi limit */
 374			u8 tim_bitmap[16];
 375			u8 tim_len;
 376			u32 ssid_len;
 377			u8 ssid[IEEE80211_MAX_SSID_LEN];
 378			bool hidden_ssid;
 379			/* P2P_IE with NoA attribute for P2P_GO case */
 380			u32 noa_len;
 381			u8 *noa_data;
 382		} ap;
 383	} u;
 384
 385	u32 aid;
 386	u32 key_cipher;
 387	u8 tx_encap_type;
 388	bool ps;
 389	atomic_t mcbc_gsn;
 390
 391	struct ath12k_link_vif deflink;
 392	struct ath12k_link_vif __rcu *link[ATH12K_NUM_MAX_LINKS];
 393	struct ath12k_vif_cache *cache[IEEE80211_MLD_MAX_NUM_LINKS];
 394	/* indicates bitmap of link vif created in FW */
 395	u32 links_map;
 396	/* Must be last - ends in a flexible-array member.
 397	 *
 398	 * FIXME: Driver should not copy struct ieee80211_chanctx_conf,
 399	 * especially because it has a flexible array. Find a better way.
 400	 */
 401	struct ieee80211_chanctx_conf chanctx;
 402};
 403
 404struct ath12k_vif_iter {
 405	u32 vdev_id;
 406	struct ath12k *ar;
 407	struct ath12k_link_vif *arvif;
 408};
 409
 410#define HAL_AST_IDX_INVALID	0xFFFF
 411#define HAL_RX_MAX_MCS		12
 412#define HAL_RX_MAX_MCS_HT	31
 413#define HAL_RX_MAX_MCS_VHT	9
 414#define HAL_RX_MAX_MCS_HE	11
 415#define HAL_RX_MAX_MCS_BE	15
 416#define HAL_RX_MAX_NSS		8
 417#define HAL_RX_MAX_NUM_LEGACY_RATES 12
 418
 419#define ATH12K_SCAN_TIMEOUT_HZ (20 * HZ)
 420
 421struct ath12k_rx_peer_rate_stats {
 422	u64 ht_mcs_count[HAL_RX_MAX_MCS_HT + 1];
 423	u64 vht_mcs_count[HAL_RX_MAX_MCS_VHT + 1];
 424	u64 he_mcs_count[HAL_RX_MAX_MCS_HE + 1];
 425	u64 be_mcs_count[HAL_RX_MAX_MCS_BE + 1];
 426	u64 nss_count[HAL_RX_MAX_NSS];
 427	u64 bw_count[HAL_RX_BW_MAX];
 428	u64 gi_count[HAL_RX_GI_MAX];
 429	u64 legacy_count[HAL_RX_MAX_NUM_LEGACY_RATES];
 430	u64 rx_rate[HAL_RX_BW_MAX][HAL_RX_GI_MAX][HAL_RX_MAX_NSS][HAL_RX_MAX_MCS_HT + 1];
 431};
 432
 433struct ath12k_rx_peer_stats {
 434	u64 num_msdu;
 435	u64 num_mpdu_fcs_ok;
 436	u64 num_mpdu_fcs_err;
 437	u64 tcp_msdu_count;
 438	u64 udp_msdu_count;
 439	u64 other_msdu_count;
 440	u64 ampdu_msdu_count;
 441	u64 non_ampdu_msdu_count;
 442	u64 stbc_count;
 443	u64 beamformed_count;
 444	u64 coding_count[HAL_RX_SU_MU_CODING_MAX];
 445	u64 tid_count[IEEE80211_NUM_TIDS + 1];
 446	u64 pream_cnt[HAL_RX_PREAMBLE_MAX];
 447	u64 reception_type[HAL_RX_RECEPTION_TYPE_MAX];
 448	u64 rx_duration;
 449	u64 dcm_count;
 450	u64 ru_alloc_cnt[HAL_RX_RU_ALLOC_TYPE_MAX];
 451	struct ath12k_rx_peer_rate_stats pkt_stats;
 452	struct ath12k_rx_peer_rate_stats byte_stats;
 453};
 454
 455#define ATH12K_HE_MCS_NUM       12
 456#define ATH12K_VHT_MCS_NUM      10
 457#define ATH12K_BW_NUM           5
 458#define ATH12K_NSS_NUM          4
 459#define ATH12K_LEGACY_NUM       12
 460#define ATH12K_GI_NUM           4
 461#define ATH12K_HT_MCS_NUM       32
 462
 463enum ath12k_pkt_rx_err {
 464	ATH12K_PKT_RX_ERR_FCS,
 465	ATH12K_PKT_RX_ERR_TKIP,
 466	ATH12K_PKT_RX_ERR_CRYPT,
 467	ATH12K_PKT_RX_ERR_PEER_IDX_INVAL,
 468	ATH12K_PKT_RX_ERR_MAX,
 469};
 470
 471enum ath12k_ampdu_subfrm_num {
 472	ATH12K_AMPDU_SUBFRM_NUM_10,
 473	ATH12K_AMPDU_SUBFRM_NUM_20,
 474	ATH12K_AMPDU_SUBFRM_NUM_30,
 475	ATH12K_AMPDU_SUBFRM_NUM_40,
 476	ATH12K_AMPDU_SUBFRM_NUM_50,
 477	ATH12K_AMPDU_SUBFRM_NUM_60,
 478	ATH12K_AMPDU_SUBFRM_NUM_MORE,
 479	ATH12K_AMPDU_SUBFRM_NUM_MAX,
 480};
 481
 482enum ath12k_amsdu_subfrm_num {
 483	ATH12K_AMSDU_SUBFRM_NUM_1,
 484	ATH12K_AMSDU_SUBFRM_NUM_2,
 485	ATH12K_AMSDU_SUBFRM_NUM_3,
 486	ATH12K_AMSDU_SUBFRM_NUM_4,
 487	ATH12K_AMSDU_SUBFRM_NUM_MORE,
 488	ATH12K_AMSDU_SUBFRM_NUM_MAX,
 489};
 490
 491enum ath12k_counter_type {
 492	ATH12K_COUNTER_TYPE_BYTES,
 493	ATH12K_COUNTER_TYPE_PKTS,
 494	ATH12K_COUNTER_TYPE_MAX,
 495};
 496
 497enum ath12k_stats_type {
 498	ATH12K_STATS_TYPE_SUCC,
 499	ATH12K_STATS_TYPE_FAIL,
 500	ATH12K_STATS_TYPE_RETRY,
 501	ATH12K_STATS_TYPE_AMPDU,
 502	ATH12K_STATS_TYPE_MAX,
 503};
 504
 505struct ath12k_htt_data_stats {
 506	u64 legacy[ATH12K_COUNTER_TYPE_MAX][ATH12K_LEGACY_NUM];
 507	u64 ht[ATH12K_COUNTER_TYPE_MAX][ATH12K_HT_MCS_NUM];
 508	u64 vht[ATH12K_COUNTER_TYPE_MAX][ATH12K_VHT_MCS_NUM];
 509	u64 he[ATH12K_COUNTER_TYPE_MAX][ATH12K_HE_MCS_NUM];
 510	u64 bw[ATH12K_COUNTER_TYPE_MAX][ATH12K_BW_NUM];
 511	u64 nss[ATH12K_COUNTER_TYPE_MAX][ATH12K_NSS_NUM];
 512	u64 gi[ATH12K_COUNTER_TYPE_MAX][ATH12K_GI_NUM];
 513	u64 transmit_type[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RECEPTION_TYPE_MAX];
 514	u64 ru_loc[ATH12K_COUNTER_TYPE_MAX][HAL_RX_RU_ALLOC_TYPE_MAX];
 515};
 516
 517struct ath12k_htt_tx_stats {
 518	struct ath12k_htt_data_stats stats[ATH12K_STATS_TYPE_MAX];
 519	u64 tx_duration;
 520	u64 ba_fails;
 521	u64 ack_fails;
 522	u16 ru_start;
 523	u16 ru_tones;
 524	u32 mu_group[MAX_MU_GROUP_ID];
 525};
 526
 527struct ath12k_per_ppdu_tx_stats {
 528	u16 succ_pkts;
 529	u16 failed_pkts;
 530	u16 retry_pkts;
 531	u32 succ_bytes;
 532	u32 failed_bytes;
 533	u32 retry_bytes;
 534};
 535
 536struct ath12k_wbm_tx_stats {
 537	u64 wbm_tx_comp_stats[HAL_WBM_REL_HTT_TX_COMP_STATUS_MAX];
 538};
 539
 540DECLARE_EWMA(avg_rssi, 10, 8)
 541
 542struct ath12k_link_sta {
 543	struct ath12k_link_vif *arvif;
 544	struct ath12k_sta *ahsta;
 545
 546	/* link address similar to ieee80211_link_sta */
 547	u8 addr[ETH_ALEN];
 548
 549	/* the following are protected by ar->data_lock */
 550	u32 changed; /* IEEE80211_RC_* */
 551	u32 bw;
 552	u32 nss;
 553	u32 smps;
 554
 555	struct wiphy_work update_wk;
 556	struct rate_info txrate;
 557	struct rate_info last_txrate;
 558	u64 rx_duration;
 559	u64 tx_duration;
 560	u8 rssi_comb;
 561	struct ewma_avg_rssi avg_rssi;
 562	u8 link_id;
 563	struct ath12k_rx_peer_stats *rx_stats;
 564	struct ath12k_wbm_tx_stats *wbm_tx_stats;
 565	u32 bw_prev;
 566	u32 peer_nss;
 567	s8 rssi_beacon;
 568	s8 chain_signal[IEEE80211_MAX_CHAINS];
 569
 570	/* For now the assoc link will be considered primary */
 571	bool is_assoc_link;
 572
 573	 /* for firmware use only */
 574	u8 link_idx;
 575	u32 tx_retry_failed;
 576	u32 tx_retry_count;
 577};
 578
 579struct ath12k_reoq_buf {
 580	void *vaddr;
 581	dma_addr_t paddr_aligned;
 582	u32 size;
 583};
 584
 585struct ath12k_sta {
 586	struct ath12k_vif *ahvif;
 587	enum hal_pn_type pn_type;
 588	struct ath12k_link_sta deflink;
 589	struct ath12k_link_sta __rcu *link[IEEE80211_MLD_MAX_NUM_LINKS];
 590	/* indicates bitmap of link sta created in FW */
 591	u16 links_map;
 592	u8 assoc_link_id;
 593	u16 ml_peer_id;
 594	u8 num_peer;
 595
 596	enum ieee80211_sta_state state;
 597
 598	struct ath12k_reoq_buf reoq_bufs[IEEE80211_NUM_TIDS + 1];
 599};
 600
 601#define ATH12K_HALF_20MHZ_BW	10
 602#define ATH12K_2GHZ_MIN_CENTER	2412
 603#define ATH12K_2GHZ_MAX_CENTER	2484
 604#define ATH12K_5GHZ_MIN_CENTER	4900
 605#define ATH12K_5GHZ_MAX_CENTER	5920
 606#define ATH12K_6GHZ_MIN_CENTER	5935
 607#define ATH12K_6GHZ_MAX_CENTER	7115
 608#define ATH12K_MIN_2GHZ_FREQ	(ATH12K_2GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW - 1)
 609#define ATH12K_MAX_2GHZ_FREQ	(ATH12K_2GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW + 1)
 610#define ATH12K_MIN_5GHZ_FREQ	(ATH12K_5GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW)
 611#define ATH12K_MAX_5GHZ_FREQ	(ATH12K_5GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW)
 612#define ATH12K_MIN_6GHZ_FREQ	(ATH12K_6GHZ_MIN_CENTER - ATH12K_HALF_20MHZ_BW)
 613#define ATH12K_MAX_6GHZ_FREQ	(ATH12K_6GHZ_MAX_CENTER + ATH12K_HALF_20MHZ_BW)
 614#define ATH12K_NUM_CHANS 101
 615#define ATH12K_MAX_5GHZ_CHAN 173
 616
 617static inline bool ath12k_is_2ghz_channel_freq(u32 freq)
 618{
 619	return freq >= ATH12K_MIN_2GHZ_FREQ &&
 620	       freq <= ATH12K_MAX_2GHZ_FREQ;
 621}
 622
 623enum ath12k_hw_state {
 624	ATH12K_HW_STATE_OFF,
 625	ATH12K_HW_STATE_ON,
 626	ATH12K_HW_STATE_RESTARTING,
 627	ATH12K_HW_STATE_RESTARTED,
 628	ATH12K_HW_STATE_WEDGED,
 629	ATH12K_HW_STATE_TM,
 630	/* Add other states as required */
 631};
 632
 633/* Antenna noise floor */
 634#define ATH12K_DEFAULT_NOISE_FLOOR -95
 635
 636struct ath12k_ftm_event_obj {
 637	u32 data_pos;
 638	u32 expected_seq;
 639	u8 *eventdata;
 640};
 641
 642struct ath12k_fw_stats {
 643	u32 pdev_id;
 644	u32 stats_id;
 645	struct list_head pdevs;
 646	struct list_head vdevs;
 647	struct list_head bcn;
 648	u32 num_vdev_recvd;
 649};
 650
 651struct ath12k_dbg_htt_stats {
 652	enum ath12k_dbg_htt_ext_stats_type type;
 653	u32 cfg_param[4];
 654	u8 reset;
 655	struct debug_htt_stats_req *stats_req;
 656};
 657
 658struct ath12k_debug {
 659	struct dentry *debugfs_pdev;
 660	struct dentry *debugfs_pdev_symlink;
 661	struct ath12k_dbg_htt_stats htt_stats;
 662	enum wmi_halphy_ctrl_path_stats_id tpc_stats_type;
 663	bool tpc_request;
 664	struct completion tpc_complete;
 665	struct wmi_tpc_stats_arg *tpc_stats;
 666	u32 rx_filter;
 667	bool extd_rx_stats;
 668};
 669
 670struct ath12k_per_peer_tx_stats {
 671	u32 succ_bytes;
 672	u32 retry_bytes;
 673	u32 failed_bytes;
 674	u32 duration;
 675	u16 succ_pkts;
 676	u16 retry_pkts;
 677	u16 failed_pkts;
 678	u16 ru_start;
 679	u16 ru_tones;
 680	u8 ba_fails;
 681	u8 ppdu_type;
 682	u32 mu_grpid;
 683	u32 mu_pos;
 684	bool is_ampdu;
 685};
 686
 687struct ath12k_pdev_rssi_offsets {
 688	s32 temp_offset;
 689	s8 min_nf_dbm;
 690	/* Cache the sum here to avoid calculating it every time in hot path
 691	 * noise_floor = min_nf_dbm + temp_offset
 692	 */
 693	s32 noise_floor;
 694};
 695
 696#define ATH12K_FLUSH_TIMEOUT (5 * HZ)
 697#define ATH12K_VDEV_DELETE_TIMEOUT_HZ (5 * HZ)
 698
 699struct ath12k {
 700	struct ath12k_base *ab;
 701	struct ath12k_pdev *pdev;
 702	struct ath12k_hw *ah;
 703	struct ath12k_wmi_pdev *wmi;
 704	struct ath12k_pdev_dp dp;
 705	u8 mac_addr[ETH_ALEN];
 706	u32 ht_cap_info;
 707	u32 vht_cap_info;
 708	struct ath12k_he ar_he;
 709	bool supports_6ghz;
 710	struct {
 711		struct completion started;
 712		struct completion completed;
 713		struct completion on_channel;
 714		struct delayed_work timeout;
 715		enum ath12k_scan_state state;
 716		bool is_roc;
 717		int roc_freq;
 718		bool roc_notify;
 719		struct wiphy_work vdev_clean_wk;
 720		struct ath12k_link_vif *arvif;
 721	} scan;
 722
 723	struct {
 724		struct ieee80211_supported_band sbands[NUM_NL80211_BANDS];
 725		struct ieee80211_sband_iftype_data
 726			iftype[NUM_NL80211_BANDS][NUM_NL80211_IFTYPES];
 727	} mac;
 728
 729	unsigned long dev_flags;
 730	unsigned int filter_flags;
 731	u32 min_tx_power;
 732	u32 max_tx_power;
 733	u32 txpower_limit_2g;
 734	u32 txpower_limit_5g;
 735	u32 txpower_scale;
 736	u32 power_scale;
 737	u32 chan_tx_pwr;
 738	u32 rts_threshold;
 739	u32 num_stations;
 740	u32 max_num_stations;
 741
 742	/* protects the radio specific data like debug stats, ppdu_stats_info stats,
 743	 * vdev_stop_status info, scan data, ath12k_sta info, ath12k_link_vif info,
 744	 * channel context data, survey info, test mode data, regd_channel_update_queue.
 745	 */
 746	spinlock_t data_lock;
 747
 748	struct list_head arvifs;
 749	/* should never be NULL; needed for regular htt rx */
 750	struct ieee80211_channel *rx_channel;
 751
 752	/* valid during scan; needed for mgmt rx during scan */
 753	struct ieee80211_channel *scan_channel;
 754
 755	u8 cfg_tx_chainmask;
 756	u8 cfg_rx_chainmask;
 757	u8 num_rx_chains;
 758	u8 num_tx_chains;
 759	/* pdev_idx starts from 0 whereas pdev->pdev_id starts with 1 */
 760	u8 pdev_idx;
 761	u8 lmac_id;
 762	u8 hw_link_id;
 763
 764	struct completion peer_assoc_done;
 765	struct completion peer_delete_done;
 766
 767	int install_key_status;
 768	struct completion install_key_done;
 769
 770	int last_wmi_vdev_start_status;
 771	struct completion vdev_setup_done;
 772	struct completion vdev_delete_done;
 773
 774	int num_peers;
 775	int max_num_peers;
 776	u32 num_started_vdevs;
 777	u32 num_created_vdevs;
 778	unsigned long long allocated_vdev_map;
 779
 780	struct idr txmgmt_idr;
 781	/* protects txmgmt_idr data */
 782	spinlock_t txmgmt_idr_lock;
 783	atomic_t num_pending_mgmt_tx;
 784	wait_queue_head_t txmgmt_empty_waitq;
 785
 786	/* cycle count is reported twice for each visited channel during scan.
 787	 * access protected by data_lock
 788	 */
 789	u32 survey_last_rx_clear_count;
 790	u32 survey_last_cycle_count;
 791
 792	/* Channel info events are expected to come in pairs without and with
 793	 * COMPLETE flag set respectively for each channel visit during scan.
 794	 *
 795	 * However there are deviations from this rule. This flag is used to
 796	 * avoid reporting garbage data.
 797	 */
 798	bool ch_info_can_report_survey;
 799	struct survey_info survey[ATH12K_NUM_CHANS];
 800	struct completion bss_survey_done;
 801
 802	struct work_struct regd_update_work;
 803	struct work_struct regd_channel_update_work;
 804	struct list_head regd_channel_update_queue;
 805
 806	struct wiphy_work wmi_mgmt_tx_work;
 807	struct sk_buff_head wmi_mgmt_tx_queue;
 808
 809	struct ath12k_wow wow;
 810	struct completion target_suspend;
 811	bool target_suspend_ack;
 812	struct ath12k_per_peer_tx_stats peer_tx_stats;
 813	struct list_head ppdu_stats_info;
 814	u32 ppdu_stat_list_depth;
 815
 816	struct ath12k_per_peer_tx_stats cached_stats;
 817	u32 last_ppdu_id;
 818	u32 cached_ppdu_id;
 819#ifdef CONFIG_ATH12K_DEBUGFS
 820	struct ath12k_debug debug;
 821#endif
 822
 823	bool dfs_block_radar_events;
 824	bool monitor_vdev_created;
 825	bool monitor_started;
 826	int monitor_vdev_id;
 827
 828	struct wiphy_radio_freq_range freq_range;
 829
 830	bool nlo_enabled;
 831
 832	/* Protected by wiphy::mtx lock. */
 833	u32 vdev_id_11d_scan;
 834	struct completion completed_11d_scan;
 835	enum ath12k_11d_state state_11d;
 836	u8 alpha2[REG_ALPHA2_LEN];
 837	bool regdom_set_by_user;
 838	struct completion regd_update_completed;
 839
 840	struct completion fw_stats_complete;
 841	struct completion fw_stats_done;
 842
 843	struct completion mlo_setup_done;
 844	u32 mlo_setup_status;
 845	u8 ftm_msgref;
 846	struct ath12k_fw_stats fw_stats;
 847	unsigned long last_tx_power_update;
 848
 849	s8 max_allowed_tx_power;
 850	struct ath12k_pdev_rssi_offsets rssi_info;
 851};
 852
 853struct ath12k_hw {
 854	struct ieee80211_hw *hw;
 855	struct device *dev;
 856
 857	/* Protect the write operation of the hardware state ath12k_hw::state
 858	 * between hardware start<=>reconfigure<=>stop transitions.
 859	 */
 860	struct mutex hw_mutex;
 861	enum ath12k_hw_state state;
 862	bool regd_updated;
 863	bool use_6ghz_regd;
 864
 865	u8 num_radio;
 866
 867	DECLARE_BITMAP(free_ml_peer_id_map, ATH12K_MAX_MLO_PEERS);
 868
 869	/* protected by wiphy_lock() */
 870	struct list_head ml_peers;
 871
 872	/* Keep last */
 873	struct ath12k radio[] __aligned(sizeof(void *));
 874};
 875
 876struct ath12k_band_cap {
 877	u32 phy_id;
 878	u32 max_bw_supported;
 879	u32 ht_cap_info;
 880	u32 he_cap_info[2];
 881	u32 he_mcs;
 882	u32 he_cap_phy_info[PSOC_HOST_MAX_PHY_SIZE];
 883	struct ath12k_wmi_ppe_threshold_arg he_ppet;
 884	u16 he_6ghz_capa;
 885	u32 eht_cap_mac_info[WMI_MAX_EHTCAP_MAC_SIZE];
 886	u32 eht_cap_phy_info[WMI_MAX_EHTCAP_PHY_SIZE];
 887	u32 eht_mcs_20_only;
 888	u32 eht_mcs_80;
 889	u32 eht_mcs_160;
 890	u32 eht_mcs_320;
 891	struct ath12k_wmi_ppe_threshold_arg eht_ppet;
 892	u32 eht_cap_info_internal;
 893};
 894
 895struct ath12k_pdev_cap {
 896	u32 supported_bands;
 897	u32 ampdu_density;
 898	u32 vht_cap;
 899	u32 vht_mcs;
 900	u32 he_mcs;
 901	u32 tx_chain_mask;
 902	u32 rx_chain_mask;
 903	u32 tx_chain_mask_shift;
 904	u32 rx_chain_mask_shift;
 905	struct ath12k_band_cap band[NUM_NL80211_BANDS];
 906	u32 eml_cap;
 907	u32 mld_cap;
 908	bool nss_ratio_enabled;
 909	u8 nss_ratio_info;
 910};
 911
 912struct mlo_timestamp {
 913	u32 info;
 914	u32 sync_timestamp_lo_us;
 915	u32 sync_timestamp_hi_us;
 916	u32 mlo_offset_lo;
 917	u32 mlo_offset_hi;
 918	u32 mlo_offset_clks;
 919	u32 mlo_comp_clks;
 920	u32 mlo_comp_timer;
 921};
 922
 923struct ath12k_pdev {
 924	struct ath12k *ar;
 925	u32 pdev_id;
 926	u32 hw_link_id;
 927	struct ath12k_pdev_cap cap;
 928	u8 mac_addr[ETH_ALEN];
 929	struct mlo_timestamp timestamp;
 930};
 931
 932struct ath12k_fw_pdev {
 933	u32 pdev_id;
 934	u32 phy_id;
 935	u32 supported_bands;
 936};
 937
 938struct ath12k_board_data {
 939	const struct firmware *fw;
 940	const void *data;
 941	size_t len;
 942};
 943
 944struct ath12k_device_dp_tx_err_stats {
 945	/* TCL Ring Descriptor unavailable */
 946	u32 desc_na[DP_TCL_NUM_RING_MAX];
 947	/* Other failures during dp_tx due to mem allocation failure
 948	 * idr unavailable etc.
 949	 */
 950	atomic_t misc_fail;
 951};
 952
 953struct ath12k_device_dp_stats {
 954	u32 err_ring_pkts;
 955	u32 invalid_rbm;
 956	u32 rxdma_error[HAL_REO_ENTR_RING_RXDMA_ECODE_MAX];
 957	u32 reo_error[HAL_REO_DEST_RING_ERROR_CODE_MAX];
 958	u32 hal_reo_error[DP_REO_DST_RING_MAX];
 959	struct ath12k_device_dp_tx_err_stats tx_err;
 960	u32 reo_rx[DP_REO_DST_RING_MAX][ATH12K_MAX_DEVICES];
 961	u32 rx_wbm_rel_source[HAL_WBM_REL_SRC_MODULE_MAX][ATH12K_MAX_DEVICES];
 962	u32 tqm_rel_reason[MAX_TQM_RELEASE_REASON];
 963	u32 fw_tx_status[MAX_FW_TX_STATUS];
 964	u32 tx_wbm_rel_source[HAL_WBM_REL_SRC_MODULE_MAX];
 965	u32 tx_enqueued[DP_TCL_NUM_RING_MAX];
 966	u32 tx_completed[DP_TCL_NUM_RING_MAX];
 967	u32 reo_excep_msdu_buf_type;
 968};
 969
 970struct ath12k_reg_freq {
 971	u32 start_freq;
 972	u32 end_freq;
 973};
 974
 975struct ath12k_mlo_memory {
 976	struct target_mem_chunk chunk[ATH12K_QMI_WLANFW_MAX_NUM_MEM_SEG_V01];
 977	int mlo_mem_size;
 978	bool init_done;
 979};
 980
 981struct ath12k_hw_link {
 982	u8 device_id;
 983	u8 pdev_idx;
 984};
 985
 986/* Holds info on the group of devices that are registered as a single
 987 * wiphy, protected with struct ath12k_hw_group::mutex.
 988 */
 989struct ath12k_hw_group {
 990	struct list_head list;
 991	u8 id;
 992	u8 num_devices;
 993	u8 num_probed;
 994	u8 num_started;
 995	unsigned long flags;
 996	struct ath12k_base *ab[ATH12K_MAX_DEVICES];
 997
 998	/* protects access to this struct */
 999	struct mutex mutex;
1000
1001	/* Holds information of wiphy (hw) registration.
1002	 *
1003	 * In Multi/Single Link Operation case, all pdevs are registered as
1004	 * a single wiphy. In other (legacy/Non-MLO) cases, each pdev is
1005	 * registered as separate wiphys.
1006	 */
1007	struct ath12k_hw *ah[ATH12K_GROUP_MAX_RADIO];
1008	u8 num_hw;
1009	bool mlo_capable;
1010	struct device_node *wsi_node[ATH12K_MAX_DEVICES];
1011	struct ath12k_mlo_memory mlo_mem;
1012	struct ath12k_hw_link hw_links[ATH12K_GROUP_MAX_RADIO];
1013	bool hw_link_id_init_done;
1014};
1015
1016/* Holds WSI info specific to each device, excluding WSI group info */
1017struct ath12k_wsi_info {
1018	u32 index;
1019	u32 hw_link_id_base;
1020};
1021
1022struct ath12k_dp_profile_params {
1023	u32 tx_comp_ring_size;
1024	u32 rxdma_monitor_buf_ring_size;
1025	u32 rxdma_monitor_dst_ring_size;
1026	u32 num_pool_tx_desc;
1027	u32 rx_desc_count;
1028};
1029
1030struct ath12k_mem_profile_based_param {
1031	u32 num_vdevs;
1032	u32 max_client_single;
1033	u32 max_client_dbs;
1034	u32 max_client_dbs_sbs;
1035	struct ath12k_dp_profile_params dp_params;
1036};
1037
1038/* Master structure to hold the hw data which may be used in core module */
1039struct ath12k_base {
1040	enum ath12k_hw_rev hw_rev;
1041	struct platform_device *pdev;
1042	struct device *dev;
1043	struct ath12k_qmi qmi;
1044	struct ath12k_wmi_base wmi_ab;
1045	struct completion fw_ready;
1046	u8 device_id;
1047	int num_radios;
1048	/* HW channel counters frequency value in hertz common to all MACs */
1049	u32 cc_freq_hz;
1050
1051	struct ath12k_dump_file_data *dump_data;
1052	size_t ath12k_coredump_len;
1053	struct work_struct dump_work;
1054
1055	struct ath12k_htc htc;
1056
1057	struct ath12k_dp dp;
1058
1059	void __iomem *mem;
1060	unsigned long mem_len;
1061
1062	void __iomem *mem_ce;
1063	u32 ce_remap_base_addr;
1064	bool ce_remap;
1065
1066	struct {
1067		enum ath12k_bus bus;
1068		const struct ath12k_hif_ops *ops;
1069	} hif;
1070
1071	struct {
1072		struct completion wakeup_completed;
1073		u32 wmi_conf_rx_decap_mode;
1074	} wow;
1075
1076	struct ath12k_ce ce;
1077	struct timer_list rx_replenish_retry;
1078	struct ath12k_hal hal;
1079	/* To synchronize core_start/core_stop */
1080	struct mutex core_lock;
1081	/* Protects data like peers */
1082	spinlock_t base_lock;
1083
1084	/* Single pdev device (struct ath12k_hw_params::single_pdev_only):
1085	 *
1086	 * Firmware maintains data for all bands but advertises a single
1087	 * phy to the host which is stored as a single element in this
1088	 * array.
1089	 *
1090	 * Other devices:
1091	 *
1092	 * This array will contain as many elements as the number of
1093	 * radios.
1094	 */
1095	struct ath12k_pdev pdevs[MAX_RADIOS];
1096
1097	/* struct ath12k_hw_params::single_pdev_only devices use this to
1098	 * store phy specific data
1099	 */
1100	struct ath12k_fw_pdev fw_pdev[MAX_RADIOS];
1101	u8 fw_pdev_count;
1102
1103	struct ath12k_pdev __rcu *pdevs_active[MAX_RADIOS];
1104
1105	struct ath12k_wmi_hal_reg_capabilities_ext_arg hal_reg_cap[MAX_RADIOS];
1106	unsigned long long free_vdev_map;
1107	unsigned long long free_vdev_stats_id_map;
1108	struct list_head peers;
1109	wait_queue_head_t peer_mapping_wq;
1110	u8 mac_addr[ETH_ALEN];
1111	bool wmi_ready;
1112	u32 wlan_init_status;
1113	int irq_num[ATH12K_IRQ_NUM_MAX];
1114	struct ath12k_ext_irq_grp ext_irq_grp[ATH12K_EXT_IRQ_GRP_NUM_MAX];
1115	struct napi_struct *napi;
1116	struct ath12k_wmi_target_cap_arg target_caps;
1117	u32 ext_service_bitmap[WMI_SERVICE_EXT_BM_SIZE];
1118	bool pdevs_macaddr_valid;
1119
1120	const struct ath12k_hw_params *hw_params;
1121
1122	const struct firmware *cal_file;
1123
1124	/* Below regd's are protected by ab->data_lock */
1125	/* This is the regd set for every radio
1126	 * by the firmware during initialization
1127	 */
1128	struct ieee80211_regdomain *default_regd[MAX_RADIOS];
1129	/* This regd is set during dynamic country setting
1130	 * This may or may not be used during the runtime
1131	 */
1132	struct ieee80211_regdomain *new_regd[MAX_RADIOS];
1133
1134	struct ath12k_reg_info *reg_info[MAX_RADIOS];
1135
1136	/* Current DFS Regulatory */
1137	enum ath12k_dfs_region dfs_region;
1138	struct ath12k_device_dp_stats device_stats;
1139#ifdef CONFIG_ATH12K_DEBUGFS
1140	struct dentry *debugfs_soc;
1141#endif
1142
1143	unsigned long dev_flags;
1144	struct completion driver_recovery;
1145	struct workqueue_struct *workqueue;
1146	struct work_struct restart_work;
1147	struct workqueue_struct *workqueue_aux;
1148	struct work_struct reset_work;
1149	atomic_t reset_count;
1150	atomic_t recovery_count;
1151	bool is_reset;
1152	struct completion reset_complete;
1153	/* continuous recovery fail count */
1154	atomic_t fail_cont_count;
1155	unsigned long reset_fail_timeout;
1156	struct work_struct update_11d_work;
1157	u8 new_alpha2[2];
1158	struct {
1159		/* protected by data_lock */
1160		u32 fw_crash_counter;
1161	} stats;
1162	u32 pktlog_defs_checksum;
1163
1164	struct ath12k_dbring_cap *db_caps;
1165	u32 num_db_cap;
1166
1167	struct completion htc_suspend;
1168
1169	u64 fw_soc_drop_count;
1170	bool static_window_map;
1171
1172	struct work_struct rfkill_work;
1173	/* true means radio is on */
1174	bool rfkill_radio_on;
1175
1176	struct {
1177		enum ath12k_bdf_search bdf_search;
1178		u32 vendor;
1179		u32 device;
1180		u32 subsystem_vendor;
1181		u32 subsystem_device;
1182	} id;
1183
1184	struct {
1185		u32 api_version;
1186
1187		const struct firmware *fw;
1188		const u8 *amss_data;
1189		size_t amss_len;
1190		const u8 *amss_dualmac_data;
1191		size_t amss_dualmac_len;
1192		const u8 *m3_data;
1193		size_t m3_len;
1194
1195		DECLARE_BITMAP(fw_features, ATH12K_FW_FEATURE_COUNT);
1196		bool fw_features_valid;
1197	} fw;
1198
1199	const struct hal_rx_ops *hal_rx_ops;
1200
1201	struct completion restart_completed;
1202
1203#ifdef CONFIG_ACPI
1204
1205	struct {
1206		bool started;
1207		u32 func_bit;
1208		bool acpi_tas_enable;
1209		bool acpi_bios_sar_enable;
1210		bool acpi_disable_11be;
1211		bool acpi_disable_rfkill;
1212		bool acpi_cca_enable;
1213		bool acpi_band_edge_enable;
1214		bool acpi_enable_bdf;
1215		u32 bit_flag;
1216		char bdf_string[ATH12K_ACPI_BDF_MAX_LEN];
1217		u8 tas_cfg[ATH12K_ACPI_DSM_TAS_CFG_SIZE];
1218		u8 tas_sar_power_table[ATH12K_ACPI_DSM_TAS_DATA_SIZE];
1219		u8 bios_sar_data[ATH12K_ACPI_DSM_BIOS_SAR_DATA_SIZE];
1220		u8 geo_offset_data[ATH12K_ACPI_DSM_GEO_OFFSET_DATA_SIZE];
1221		u8 cca_data[ATH12K_ACPI_DSM_CCA_DATA_SIZE];
1222		u8 band_edge_power[ATH12K_ACPI_DSM_BAND_EDGE_DATA_SIZE];
1223	} acpi;
1224
1225#endif /* CONFIG_ACPI */
1226
1227	struct notifier_block panic_nb;
1228
1229	struct ath12k_hw_group *ag;
1230	struct ath12k_wsi_info wsi_info;
1231	enum ath12k_firmware_mode fw_mode;
1232	struct ath12k_ftm_event_obj ftm_event_obj;
1233	bool hw_group_ref;
1234
1235	/* Denote whether MLO is possible within the device */
1236	bool single_chip_mlo_support;
1237
1238	struct ath12k_reg_freq reg_freq_2ghz;
1239	struct ath12k_reg_freq reg_freq_5ghz;
1240	struct ath12k_reg_freq reg_freq_6ghz;
1241	const struct ath12k_mem_profile_based_param *profile_param;
1242	enum ath12k_qmi_mem_mode target_mem_mode;
1243
1244	/* must be last */
1245	u8 drv_priv[] __aligned(sizeof(void *));
1246};
1247
1248struct ath12k_pdev_map {
1249	struct ath12k_base *ab;
1250	u8 pdev_idx;
1251};
1252
1253struct ath12k_fw_stats_vdev {
1254	struct list_head list;
1255
1256	u32 vdev_id;
1257	u32 beacon_snr;
1258	u32 data_snr;
1259	u32 num_tx_frames[WLAN_MAX_AC];
1260	u32 num_rx_frames;
1261	u32 num_tx_frames_retries[WLAN_MAX_AC];
1262	u32 num_tx_frames_failures[WLAN_MAX_AC];
1263	u32 num_rts_fail;
1264	u32 num_rts_success;
1265	u32 num_rx_err;
1266	u32 num_rx_discard;
1267	u32 num_tx_not_acked;
1268	u32 tx_rate_history[MAX_TX_RATE_VALUES];
1269	u32 beacon_rssi_history[MAX_TX_RATE_VALUES];
1270};
1271
1272struct ath12k_fw_stats_bcn {
1273	struct list_head list;
1274
1275	u32 vdev_id;
1276	u32 tx_bcn_succ_cnt;
1277	u32 tx_bcn_outage_cnt;
1278};
1279
1280struct ath12k_fw_stats_pdev {
1281	struct list_head list;
1282
1283	/* PDEV stats */
1284	s32 ch_noise_floor;
1285	u32 tx_frame_count;
1286	u32 rx_frame_count;
1287	u32 rx_clear_count;
1288	u32 cycle_count;
1289	u32 phy_err_count;
1290	u32 chan_tx_power;
1291	u32 ack_rx_bad;
1292	u32 rts_bad;
1293	u32 rts_good;
1294	u32 fcs_bad;
1295	u32 no_beacons;
1296	u32 mib_int_count;
1297
1298	/* PDEV TX stats */
1299	s32 comp_queued;
1300	s32 comp_delivered;
1301	s32 msdu_enqued;
1302	s32 mpdu_enqued;
1303	s32 wmm_drop;
1304	s32 local_enqued;
1305	s32 local_freed;
1306	s32 hw_queued;
1307	s32 hw_reaped;
1308	s32 underrun;
1309	s32 tx_abort;
1310	s32 mpdus_requed;
1311	u32 tx_ko;
1312	u32 data_rc;
1313	u32 self_triggers;
1314	u32 sw_retry_failure;
1315	u32 illgl_rate_phy_err;
1316	u32 pdev_cont_xretry;
1317	u32 pdev_tx_timeout;
1318	u32 pdev_resets;
1319	u32 stateless_tid_alloc_failure;
1320	u32 phy_underrun;
1321	u32 txop_ovf;
1322
1323	/* PDEV RX stats */
1324	s32 mid_ppdu_route_change;
1325	s32 status_rcvd;
1326	s32 r0_frags;
1327	s32 r1_frags;
1328	s32 r2_frags;
1329	s32 r3_frags;
1330	s32 htt_msdus;
1331	s32 htt_mpdus;
1332	s32 loc_msdus;
1333	s32 loc_mpdus;
1334	s32 oversize_amsdu;
1335	s32 phy_errs;
1336	s32 phy_err_drop;
1337	s32 mpdu_errs;
1338};
1339
1340int ath12k_core_qmi_firmware_ready(struct ath12k_base *ab);
1341void ath12k_core_hw_group_cleanup(struct ath12k_hw_group *ag);
1342int ath12k_core_pre_init(struct ath12k_base *ab);
1343int ath12k_core_init(struct ath12k_base *ath12k);
1344void ath12k_core_deinit(struct ath12k_base *ath12k);
1345struct ath12k_base *ath12k_core_alloc(struct device *dev, size_t priv_size,
1346				      enum ath12k_bus bus);
1347void ath12k_core_free(struct ath12k_base *ath12k);
1348int ath12k_core_fetch_board_data_api_1(struct ath12k_base *ab,
1349				       struct ath12k_board_data *bd,
1350				       char *filename);
1351int ath12k_core_fetch_bdf(struct ath12k_base *ath12k,
1352			  struct ath12k_board_data *bd);
1353void ath12k_core_free_bdf(struct ath12k_base *ab, struct ath12k_board_data *bd);
1354int ath12k_core_fetch_regdb(struct ath12k_base *ab, struct ath12k_board_data *bd);
1355int ath12k_core_check_dt(struct ath12k_base *ath12k);
1356int ath12k_core_check_smbios(struct ath12k_base *ab);
1357void ath12k_core_halt(struct ath12k *ar);
1358int ath12k_core_resume_early(struct ath12k_base *ab);
1359int ath12k_core_resume(struct ath12k_base *ab);
1360int ath12k_core_suspend(struct ath12k_base *ab);
1361int ath12k_core_suspend_late(struct ath12k_base *ab);
1362void ath12k_core_hw_group_unassign(struct ath12k_base *ab);
1363u8 ath12k_get_num_partner_link(struct ath12k *ar);
1364
1365const struct firmware *ath12k_core_firmware_request(struct ath12k_base *ab,
1366						    const char *filename);
1367u32 ath12k_core_get_max_station_per_radio(struct ath12k_base *ab);
1368u32 ath12k_core_get_max_peers_per_radio(struct ath12k_base *ab);
1369
1370void ath12k_core_hw_group_set_mlo_capable(struct ath12k_hw_group *ag);
1371void ath12k_fw_stats_init(struct ath12k *ar);
1372void ath12k_fw_stats_bcn_free(struct list_head *head);
1373void ath12k_fw_stats_free(struct ath12k_fw_stats *stats);
1374void ath12k_fw_stats_reset(struct ath12k *ar);
1375struct reserved_mem *ath12k_core_get_reserved_mem(struct ath12k_base *ab,
1376						  int index);
1377enum ath12k_qmi_mem_mode ath12k_core_get_memory_mode(struct ath12k_base *ab);
1378
1379static inline const char *ath12k_scan_state_str(enum ath12k_scan_state state)
1380{
1381	switch (state) {
1382	case ATH12K_SCAN_IDLE:
1383		return "idle";
1384	case ATH12K_SCAN_STARTING:
1385		return "starting";
1386	case ATH12K_SCAN_RUNNING:
1387		return "running";
1388	case ATH12K_SCAN_ABORTING:
1389		return "aborting";
1390	}
1391
1392	return "unknown";
1393}
1394
1395static inline struct ath12k_skb_cb *ATH12K_SKB_CB(struct sk_buff *skb)
1396{
1397	BUILD_BUG_ON(sizeof(struct ath12k_skb_cb) >
1398		     IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
1399	return (struct ath12k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
1400}
1401
1402static inline struct ath12k_skb_rxcb *ATH12K_SKB_RXCB(struct sk_buff *skb)
1403{
1404	BUILD_BUG_ON(sizeof(struct ath12k_skb_rxcb) > sizeof(skb->cb));
1405	return (struct ath12k_skb_rxcb *)skb->cb;
1406}
1407
1408static inline struct ath12k_vif *ath12k_vif_to_ahvif(struct ieee80211_vif *vif)
1409{
1410	return (struct ath12k_vif *)vif->drv_priv;
1411}
1412
1413static inline struct ath12k_sta *ath12k_sta_to_ahsta(struct ieee80211_sta *sta)
1414{
1415	return (struct ath12k_sta *)sta->drv_priv;
1416}
1417
1418static inline struct ieee80211_sta *ath12k_ahsta_to_sta(struct ath12k_sta *ahsta)
1419{
1420	return container_of((void *)ahsta, struct ieee80211_sta, drv_priv);
1421}
1422
1423static inline struct ieee80211_vif *ath12k_ahvif_to_vif(struct ath12k_vif *ahvif)
1424{
1425	return container_of((void *)ahvif, struct ieee80211_vif, drv_priv);
1426}
1427
1428static inline struct ath12k *ath12k_ab_to_ar(struct ath12k_base *ab,
1429					     int mac_id)
1430{
1431	return ab->pdevs[ath12k_hw_mac_id_to_pdev_id(ab->hw_params, mac_id)].ar;
1432}
1433
1434static inline void ath12k_core_create_firmware_path(struct ath12k_base *ab,
1435						    const char *filename,
1436						    void *buf, size_t buf_len)
1437{
1438	const char *fw_name = NULL;
1439
1440	of_property_read_string(ab->dev->of_node, "firmware-name", &fw_name);
1441
1442	if (fw_name && strncmp(filename, "board", 5))
1443		snprintf(buf, buf_len, "%s/%s/%s/%s", ATH12K_FW_DIR,
1444			 ab->hw_params->fw.dir, fw_name, filename);
1445	else
1446		snprintf(buf, buf_len, "%s/%s/%s", ATH12K_FW_DIR,
1447			 ab->hw_params->fw.dir, filename);
1448}
1449
1450static inline const char *ath12k_bus_str(enum ath12k_bus bus)
1451{
1452	switch (bus) {
1453	case ATH12K_BUS_PCI:
1454		return "pci";
1455	case ATH12K_BUS_AHB:
1456		return "ahb";
1457	}
1458
1459	return "unknown";
1460}
1461
1462static inline struct ath12k_hw *ath12k_hw_to_ah(struct ieee80211_hw  *hw)
1463{
1464	return hw->priv;
1465}
1466
1467static inline struct ath12k *ath12k_ah_to_ar(struct ath12k_hw *ah, u8 hw_link_id)
1468{
1469	if (WARN(hw_link_id >= ah->num_radio,
1470		 "bad hw link id %d, so switch to default link\n", hw_link_id))
1471		hw_link_id = 0;
1472
1473	return &ah->radio[hw_link_id];
1474}
1475
1476static inline struct ath12k_hw *ath12k_ar_to_ah(struct ath12k *ar)
1477{
1478	return ar->ah;
1479}
1480
1481static inline struct ieee80211_hw *ath12k_ar_to_hw(struct ath12k *ar)
1482{
1483	return ar->ah->hw;
1484}
1485
1486#define for_each_ar(ah, ar, index) \
1487	for ((index) = 0; ((index) < (ah)->num_radio && \
1488	     ((ar) = &(ah)->radio[(index)])); (index)++)
1489
1490static inline struct ath12k_hw *ath12k_ag_to_ah(struct ath12k_hw_group *ag, int idx)
1491{
1492	return ag->ah[idx];
1493}
1494
1495static inline void ath12k_ag_set_ah(struct ath12k_hw_group *ag, int idx,
1496				    struct ath12k_hw *ah)
1497{
1498	ag->ah[idx] = ah;
1499}
1500
1501static inline struct ath12k_hw_group *ath12k_ab_to_ag(struct ath12k_base *ab)
1502{
1503	return ab->ag;
1504}
1505
1506static inline struct ath12k_base *ath12k_ag_to_ab(struct ath12k_hw_group *ag,
1507						  u8 device_id)
1508{
1509	return ag->ab[device_id];
1510}
1511
1512static inline s32 ath12k_pdev_get_noise_floor(struct ath12k *ar)
1513{
1514	lockdep_assert_held(&ar->data_lock);
1515
1516	return ar->rssi_info.noise_floor;
1517}
1518
1519#endif /* _CORE_H_ */