rx_desc.h

   1/* SPDX-License-Identifier: BSD-3-Clause-Clear */
   2/*
   3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved.
   4 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
   5 */
   6#ifndef ATH11K_RX_DESC_H
   7#define ATH11K_RX_DESC_H
   8
   9enum rx_desc_rxpcu_filter {
  10	RX_DESC_RXPCU_FILTER_PASS,
  11	RX_DESC_RXPCU_FILTER_MONITOR_CLIENT,
  12	RX_DESC_RXPCU_FILTER_MONITOR_OTHER,
  13};
  14
  15/* rxpcu_filter_pass
  16 *		This MPDU passed the normal frame filter programming of rxpcu.
  17 *
  18 * rxpcu_filter_monitor_client
  19 *		 This MPDU did not pass the regular frame filter and would
  20 *		 have been dropped, were it not for the frame fitting into the
  21 *		 'monitor_client' category.
  22 *
  23 * rxpcu_filter_monitor_other
  24 *		This MPDU did not pass the regular frame filter and also did
  25 *		not pass the rxpcu_monitor_client filter. It would have been
  26 *		dropped accept that it did pass the 'monitor_other' category.
  27 */
  28
  29#define RX_DESC_INFO0_RXPCU_MPDU_FITLER	GENMASK(1, 0)
  30#define RX_DESC_INFO0_SW_FRAME_GRP_ID	GENMASK(8, 2)
  31
  32enum rx_desc_sw_frame_grp_id {
  33	RX_DESC_SW_FRAME_GRP_ID_NDP_FRAME,
  34	RX_DESC_SW_FRAME_GRP_ID_MCAST_DATA,
  35	RX_DESC_SW_FRAME_GRP_ID_UCAST_DATA,
  36	RX_DESC_SW_FRAME_GRP_ID_NULL_DATA,
  37	RX_DESC_SW_FRAME_GRP_ID_MGMT_0000,
  38	RX_DESC_SW_FRAME_GRP_ID_MGMT_0001,
  39	RX_DESC_SW_FRAME_GRP_ID_MGMT_0010,
  40	RX_DESC_SW_FRAME_GRP_ID_MGMT_0011,
  41	RX_DESC_SW_FRAME_GRP_ID_MGMT_0100,
  42	RX_DESC_SW_FRAME_GRP_ID_MGMT_0101,
  43	RX_DESC_SW_FRAME_GRP_ID_MGMT_0110,
  44	RX_DESC_SW_FRAME_GRP_ID_MGMT_0111,
  45	RX_DESC_SW_FRAME_GRP_ID_MGMT_1000,
  46	RX_DESC_SW_FRAME_GRP_ID_MGMT_1001,
  47	RX_DESC_SW_FRAME_GRP_ID_MGMT_1010,
  48	RX_DESC_SW_FRAME_GRP_ID_MGMT_1011,
  49	RX_DESC_SW_FRAME_GRP_ID_MGMT_1100,
  50	RX_DESC_SW_FRAME_GRP_ID_MGMT_1101,
  51	RX_DESC_SW_FRAME_GRP_ID_MGMT_1110,
  52	RX_DESC_SW_FRAME_GRP_ID_MGMT_1111,
  53	RX_DESC_SW_FRAME_GRP_ID_CTRL_0000,
  54	RX_DESC_SW_FRAME_GRP_ID_CTRL_0001,
  55	RX_DESC_SW_FRAME_GRP_ID_CTRL_0010,
  56	RX_DESC_SW_FRAME_GRP_ID_CTRL_0011,
  57	RX_DESC_SW_FRAME_GRP_ID_CTRL_0100,
  58	RX_DESC_SW_FRAME_GRP_ID_CTRL_0101,
  59	RX_DESC_SW_FRAME_GRP_ID_CTRL_0110,
  60	RX_DESC_SW_FRAME_GRP_ID_CTRL_0111,
  61	RX_DESC_SW_FRAME_GRP_ID_CTRL_1000,
  62	RX_DESC_SW_FRAME_GRP_ID_CTRL_1001,
  63	RX_DESC_SW_FRAME_GRP_ID_CTRL_1010,
  64	RX_DESC_SW_FRAME_GRP_ID_CTRL_1011,
  65	RX_DESC_SW_FRAME_GRP_ID_CTRL_1100,
  66	RX_DESC_SW_FRAME_GRP_ID_CTRL_1101,
  67	RX_DESC_SW_FRAME_GRP_ID_CTRL_1110,
  68	RX_DESC_SW_FRAME_GRP_ID_CTRL_1111,
  69	RX_DESC_SW_FRAME_GRP_ID_UNSUPPORTED,
  70	RX_DESC_SW_FRAME_GRP_ID_PHY_ERR,
  71};
  72
  73enum rx_desc_decap_type {
  74	RX_DESC_DECAP_TYPE_RAW,
  75	RX_DESC_DECAP_TYPE_NATIVE_WIFI,
  76	RX_DESC_DECAP_TYPE_ETHERNET2_DIX,
  77	RX_DESC_DECAP_TYPE_8023,
  78};
  79
  80enum rx_desc_decrypt_status_code {
  81	RX_DESC_DECRYPT_STATUS_CODE_OK,
  82	RX_DESC_DECRYPT_STATUS_CODE_UNPROTECTED_FRAME,
  83	RX_DESC_DECRYPT_STATUS_CODE_DATA_ERR,
  84	RX_DESC_DECRYPT_STATUS_CODE_KEY_INVALID,
  85	RX_DESC_DECRYPT_STATUS_CODE_PEER_ENTRY_INVALID,
  86	RX_DESC_DECRYPT_STATUS_CODE_OTHER,
  87};
  88
  89#define RX_ATTENTION_INFO1_FIRST_MPDU		BIT(0)
  90#define RX_ATTENTION_INFO1_RSVD_1A		BIT(1)
  91#define RX_ATTENTION_INFO1_MCAST_BCAST		BIT(2)
  92#define RX_ATTENTION_INFO1_AST_IDX_NOT_FOUND	BIT(3)
  93#define RX_ATTENTION_INFO1_AST_IDX_TIMEDOUT	BIT(4)
  94#define RX_ATTENTION_INFO1_POWER_MGMT		BIT(5)
  95#define RX_ATTENTION_INFO1_NON_QOS		BIT(6)
  96#define RX_ATTENTION_INFO1_NULL_DATA		BIT(7)
  97#define RX_ATTENTION_INFO1_MGMT_TYPE		BIT(8)
  98#define RX_ATTENTION_INFO1_CTRL_TYPE		BIT(9)
  99#define RX_ATTENTION_INFO1_MORE_DATA		BIT(10)
 100#define RX_ATTENTION_INFO1_EOSP			BIT(11)
 101#define RX_ATTENTION_INFO1_A_MSDU_ERROR		BIT(12)
 102#define RX_ATTENTION_INFO1_FRAGMENT		BIT(13)
 103#define RX_ATTENTION_INFO1_ORDER		BIT(14)
 104#define RX_ATTENTION_INFO1_CCE_MATCH		BIT(15)
 105#define RX_ATTENTION_INFO1_OVERFLOW_ERR		BIT(16)
 106#define RX_ATTENTION_INFO1_MSDU_LEN_ERR		BIT(17)
 107#define RX_ATTENTION_INFO1_TCP_UDP_CKSUM_FAIL	BIT(18)
 108#define RX_ATTENTION_INFO1_IP_CKSUM_FAIL	BIT(19)
 109#define RX_ATTENTION_INFO1_SA_IDX_INVALID	BIT(20)
 110#define RX_ATTENTION_INFO1_DA_IDX_INVALID	BIT(21)
 111#define RX_ATTENTION_INFO1_RSVD_1B		BIT(22)
 112#define RX_ATTENTION_INFO1_RX_IN_TX_DECRYPT_BYP	BIT(23)
 113#define RX_ATTENTION_INFO1_ENCRYPT_REQUIRED	BIT(24)
 114#define RX_ATTENTION_INFO1_DIRECTED		BIT(25)
 115#define RX_ATTENTION_INFO1_BUFFER_FRAGMENT	BIT(26)
 116#define RX_ATTENTION_INFO1_MPDU_LEN_ERR		BIT(27)
 117#define RX_ATTENTION_INFO1_TKIP_MIC_ERR		BIT(28)
 118#define RX_ATTENTION_INFO1_DECRYPT_ERR		BIT(29)
 119#define RX_ATTENTION_INFO1_UNDECRYPT_FRAME_ERR	BIT(30)
 120#define RX_ATTENTION_INFO1_FCS_ERR		BIT(31)
 121
 122#define RX_ATTENTION_INFO2_FLOW_IDX_TIMEOUT	BIT(0)
 123#define RX_ATTENTION_INFO2_FLOW_IDX_INVALID	BIT(1)
 124#define RX_ATTENTION_INFO2_WIFI_PARSER_ERR	BIT(2)
 125#define RX_ATTENTION_INFO2_AMSDU_PARSER_ERR	BIT(3)
 126#define RX_ATTENTION_INFO2_SA_IDX_TIMEOUT	BIT(4)
 127#define RX_ATTENTION_INFO2_DA_IDX_TIMEOUT	BIT(5)
 128#define RX_ATTENTION_INFO2_MSDU_LIMIT_ERR	BIT(6)
 129#define RX_ATTENTION_INFO2_DA_IS_VALID		BIT(7)
 130#define RX_ATTENTION_INFO2_DA_IS_MCBC		BIT(8)
 131#define RX_ATTENTION_INFO2_SA_IS_VALID		BIT(9)
 132#define RX_ATTENTION_INFO2_DCRYPT_STATUS_CODE	GENMASK(12, 10)
 133#define RX_ATTENTION_INFO2_RX_BITMAP_NOT_UPDED	BIT(13)
 134#define RX_ATTENTION_INFO2_MSDU_DONE		BIT(31)
 135
 136struct rx_attention {
 137	__le16 info0;
 138	__le16 phy_ppdu_id;
 139	__le32 info1;
 140	__le32 info2;
 141} __packed;
 142
 143/* rx_attention
 144 *
 145 * rxpcu_mpdu_filter_in_category
 146 *		Field indicates what the reason was that this mpdu frame
 147 *		was allowed to come into the receive path by rxpcu. Values
 148 *		are defined in enum %RX_DESC_RXPCU_FILTER_*.
 149 *
 150 * sw_frame_group_id
 151 *		SW processes frames based on certain classifications. Values
 152 *		are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*.
 153 *
 154 * phy_ppdu_id
 155 *		A ppdu counter value that PHY increments for every PPDU
 156 *		received. The counter value wraps around.
 157 *
 158 * first_mpdu
 159 *		Indicates the first MSDU of the PPDU.  If both first_mpdu
 160 *		and last_mpdu are set in the MSDU then this is a not an
 161 *		A-MPDU frame but a stand alone MPDU.  Interior MPDU in an
 162 *		A-MPDU shall have both first_mpdu and last_mpdu bits set to
 163 *		0.  The PPDU start status will only be valid when this bit
 164 *		is set.
 165 *
 166 * mcast_bcast
 167 *		Multicast / broadcast indicator.  Only set when the MAC
 168 *		address 1 bit 0 is set indicating mcast/bcast and the BSSID
 169 *		matches one of the 4 BSSID registers. Only set when
 170 *		first_msdu is set.
 171 *
 172 * ast_index_not_found
 173 *		Only valid when first_msdu is set. Indicates no AST matching
 174 *		entries within the max search count.
 175 *
 176 * ast_index_timeout
 177 *		Only valid when first_msdu is set. Indicates an unsuccessful
 178 *		search in the address search table due to timeout.
 179 *
 180 * power_mgmt
 181 *		Power management bit set in the 802.11 header.  Only set
 182 *		when first_msdu is set.
 183 *
 184 * non_qos
 185 *		Set if packet is not a non-QoS data frame.  Only set when
 186 *		first_msdu is set.
 187 *
 188 * null_data
 189 *		Set if frame type indicates either null data or QoS null
 190 *		data format.  Only set when first_msdu is set.
 191 *
 192 * mgmt_type
 193 *		Set if packet is a management packet.  Only set when
 194 *		first_msdu is set.
 195 *
 196 * ctrl_type
 197 *		Set if packet is a control packet.  Only set when first_msdu
 198 *		is set.
 199 *
 200 * more_data
 201 *		Set if more bit in frame control is set.  Only set when
 202 *		first_msdu is set.
 203 *
 204 * eosp
 205 *		Set if the EOSP (end of service period) bit in the QoS
 206 *		control field is set.  Only set when first_msdu is set.
 207 *
 208 * a_msdu_error
 209 *		Set if number of MSDUs in A-MSDU is above a threshold or if the
 210 *		size of the MSDU is invalid. This receive buffer will contain
 211 *		all of the remainder of MSDUs in this MPDU w/o decapsulation.
 212 *
 213 * fragment
 214 *		Indicates that this is an 802.11 fragment frame.  This is
 215 *		set when either the more_frag bit is set in the frame
 216 *		control or the fragment number is not zero.  Only set when
 217 *		first_msdu is set.
 218 *
 219 * order
 220 *		Set if the order bit in the frame control is set.  Only set
 221 *		when first_msdu is set.
 222 *
 223 * cce_match
 224 *		Indicates that this status has a corresponding MSDU that
 225 *		requires FW processing. The OLE will have classification
 226 *		ring mask registers which will indicate the ring(s) for
 227 *		packets and descriptors which need FW attention.
 228 *
 229 * overflow_err
 230 *		PCU Receive FIFO does not have enough space to store the
 231 *		full receive packet.  Enough space is reserved in the
 232 *		receive FIFO for the status is written.  This MPDU remaining
 233 *		packets in the PPDU will be filtered and no Ack response
 234 *		will be transmitted.
 235 *
 236 * msdu_length_err
 237 *		Indicates that the MSDU length from the 802.3 encapsulated
 238 *		length field extends beyond the MPDU boundary.
 239 *
 240 * tcp_udp_chksum_fail
 241 *		Indicates that the computed checksum (tcp_udp_chksum) did
 242 *		not match the checksum in the TCP/UDP header.
 243 *
 244 * ip_chksum_fail
 245 *		Indicates that the computed checksum did not match the
 246 *		checksum in the IP header.
 247 *
 248 * sa_idx_invalid
 249 *		Indicates no matching entry was found in the address search
 250 *		table for the source MAC address.
 251 *
 252 * da_idx_invalid
 253 *		Indicates no matching entry was found in the address search
 254 *		table for the destination MAC address.
 255 *
 256 * rx_in_tx_decrypt_byp
 257 *		Indicates that RX packet is not decrypted as Crypto is busy
 258 *		with TX packet processing.
 259 *
 260 * encrypt_required
 261 *		Indicates that this data type frame is not encrypted even if
 262 *		the policy for this MPDU requires encryption as indicated in
 263 *		the peer table key type.
 264 *
 265 * directed
 266 *		MPDU is a directed packet which means that the RA matched
 267 *		our STA addresses.  In proxySTA it means that the TA matched
 268 *		an entry in our address search table with the corresponding
 269 *		'no_ack' bit is the address search entry cleared.
 270 *
 271 * buffer_fragment
 272 *		Indicates that at least one of the rx buffers has been
 273 *		fragmented.  If set the FW should look at the rx_frag_info
 274 *		descriptor described below.
 275 *
 276 * mpdu_length_err
 277 *		Indicates that the MPDU was pre-maturely terminated
 278 *		resulting in a truncated MPDU.  Don't trust the MPDU length
 279 *		field.
 280 *
 281 * tkip_mic_err
 282 *		Indicates that the MPDU Michael integrity check failed
 283 *
 284 * decrypt_err
 285 *		Indicates that the MPDU decrypt integrity check failed
 286 *
 287 * fcs_err
 288 *		Indicates that the MPDU FCS check failed
 289 *
 290 * flow_idx_timeout
 291 *		Indicates an unsuccessful flow search due to the expiring of
 292 *		the search timer.
 293 *
 294 * flow_idx_invalid
 295 *		flow id is not valid.
 296 *
 297 * amsdu_parser_error
 298 *		A-MSDU could not be properly de-agregated.
 299 *
 300 * sa_idx_timeout
 301 *		Indicates an unsuccessful search for the source MAC address
 302 *		due to the expiring of the search timer.
 303 *
 304 * da_idx_timeout
 305 *		Indicates an unsuccessful search for the destination MAC
 306 *		address due to the expiring of the search timer.
 307 *
 308 * msdu_limit_error
 309 *		Indicates that the MSDU threshold was exceeded and thus
 310 *		all the rest of the MSDUs will not be scattered and will not
 311 *		be decasulated but will be DMA'ed in RAW format as a single
 312 *		MSDU buffer.
 313 *
 314 * da_is_valid
 315 *		Indicates that OLE found a valid DA entry.
 316 *
 317 * da_is_mcbc
 318 *		Field Only valid if da_is_valid is set. Indicates the DA address
 319 *		was a Multicast or Broadcast address.
 320 *
 321 * sa_is_valid
 322 *		Indicates that OLE found a valid SA entry.
 323 *
 324 * decrypt_status_code
 325 *		Field provides insight into the decryption performed. Values are
 326 *		defined in enum %RX_DESC_DECRYPT_STATUS_CODE*.
 327 *
 328 * rx_bitmap_not_updated
 329 *		Frame is received, but RXPCU could not update the receive bitmap
 330 *		due to (temporary) fifo constraints.
 331 *
 332 * msdu_done
 333 *		If set indicates that the RX packet data, RX header data, RX
 334 *		PPDU start descriptor, RX MPDU start/end descriptor, RX MSDU
 335 *		start/end descriptors and RX Attention descriptor are all
 336 *		valid.  This bit must be in the last octet of the
 337 *		descriptor.
 338 */
 339
 340#define RX_MPDU_START_INFO0_NDP_FRAME		BIT(9)
 341#define RX_MPDU_START_INFO0_PHY_ERR		BIT(10)
 342#define RX_MPDU_START_INFO0_PHY_ERR_MPDU_HDR	BIT(11)
 343#define RX_MPDU_START_INFO0_PROTO_VER_ERR	BIT(12)
 344#define RX_MPDU_START_INFO0_AST_LOOKUP_VALID	BIT(13)
 345
 346#define RX_MPDU_START_INFO1_MPDU_FCTRL_VALID	BIT(0)
 347#define RX_MPDU_START_INFO1_MPDU_DUR_VALID	BIT(1)
 348#define RX_MPDU_START_INFO1_MAC_ADDR1_VALID	BIT(2)
 349#define RX_MPDU_START_INFO1_MAC_ADDR2_VALID	BIT(3)
 350#define RX_MPDU_START_INFO1_MAC_ADDR3_VALID	BIT(4)
 351#define RX_MPDU_START_INFO1_MAC_ADDR4_VALID	BIT(5)
 352#define RX_MPDU_START_INFO1_MPDU_SEQ_CTRL_VALID	BIT(6)
 353#define RX_MPDU_START_INFO1_MPDU_QOS_CTRL_VALID	BIT(7)
 354#define RX_MPDU_START_INFO1_MPDU_HT_CTRL_VALID	BIT(8)
 355#define RX_MPDU_START_INFO1_ENCRYPT_INFO_VALID	BIT(9)
 356#define RX_MPDU_START_INFO1_MPDU_FRAG_NUMBER	GENMASK(13, 10)
 357#define RX_MPDU_START_INFO1_MORE_FRAG_FLAG	BIT(14)
 358#define RX_MPDU_START_INFO1_FROM_DS		BIT(16)
 359#define RX_MPDU_START_INFO1_TO_DS		BIT(17)
 360#define RX_MPDU_START_INFO1_ENCRYPTED		BIT(18)
 361#define RX_MPDU_START_INFO1_MPDU_RETRY		BIT(19)
 362#define RX_MPDU_START_INFO1_MPDU_SEQ_NUM	GENMASK(31, 20)
 363
 364#define RX_MPDU_START_INFO2_EPD_EN		BIT(0)
 365#define RX_MPDU_START_INFO2_ALL_FRAME_ENCPD	BIT(1)
 366#define RX_MPDU_START_INFO2_ENC_TYPE		GENMASK(5, 2)
 367#define RX_MPDU_START_INFO2_VAR_WEP_KEY_WIDTH	GENMASK(7, 6)
 368#define RX_MPDU_START_INFO2_MESH_STA		BIT(8)
 369#define RX_MPDU_START_INFO2_BSSID_HIT		BIT(9)
 370#define RX_MPDU_START_INFO2_BSSID_NUM		GENMASK(13, 10)
 371#define RX_MPDU_START_INFO2_TID			GENMASK(17, 14)
 372#define RX_MPDU_START_INFO2_TID_WCN6855		GENMASK(18, 15)
 373
 374#define RX_MPDU_START_INFO3_REO_DEST_IND		GENMASK(4, 0)
 375#define RX_MPDU_START_INFO3_FLOW_ID_TOEPLITZ		BIT(7)
 376#define RX_MPDU_START_INFO3_PKT_SEL_FP_UCAST_DATA	BIT(8)
 377#define RX_MPDU_START_INFO3_PKT_SEL_FP_MCAST_DATA	BIT(9)
 378#define RX_MPDU_START_INFO3_PKT_SEL_FP_CTRL_BAR		BIT(10)
 379#define RX_MPDU_START_INFO3_RXDMA0_SRC_RING_SEL		GENMASK(12, 11)
 380#define RX_MPDU_START_INFO3_RXDMA0_DST_RING_SEL		GENMASK(14, 13)
 381
 382#define RX_MPDU_START_INFO4_REO_QUEUE_DESC_HI	GENMASK(7, 0)
 383#define RX_MPDU_START_INFO4_RECV_QUEUE_NUM	GENMASK(23, 8)
 384#define RX_MPDU_START_INFO4_PRE_DELIM_ERR_WARN	BIT(24)
 385#define RX_MPDU_START_INFO4_FIRST_DELIM_ERR	BIT(25)
 386
 387#define RX_MPDU_START_INFO5_KEY_ID		GENMASK(7, 0)
 388#define RX_MPDU_START_INFO5_NEW_PEER_ENTRY	BIT(8)
 389#define RX_MPDU_START_INFO5_DECRYPT_NEEDED	BIT(9)
 390#define RX_MPDU_START_INFO5_DECAP_TYPE		GENMASK(11, 10)
 391#define RX_MPDU_START_INFO5_VLAN_TAG_C_PADDING	BIT(12)
 392#define RX_MPDU_START_INFO5_VLAN_TAG_S_PADDING	BIT(13)
 393#define RX_MPDU_START_INFO5_STRIP_VLAN_TAG_C	BIT(14)
 394#define RX_MPDU_START_INFO5_STRIP_VLAN_TAG_S	BIT(15)
 395#define RX_MPDU_START_INFO5_PRE_DELIM_COUNT	GENMASK(27, 16)
 396#define RX_MPDU_START_INFO5_AMPDU_FLAG		BIT(28)
 397#define RX_MPDU_START_INFO5_BAR_FRAME		BIT(29)
 398
 399#define RX_MPDU_START_INFO6_MPDU_LEN		GENMASK(13, 0)
 400#define RX_MPDU_START_INFO6_FIRST_MPDU		BIT(14)
 401#define RX_MPDU_START_INFO6_MCAST_BCAST		BIT(15)
 402#define RX_MPDU_START_INFO6_AST_IDX_NOT_FOUND	BIT(16)
 403#define RX_MPDU_START_INFO6_AST_IDX_TIMEOUT	BIT(17)
 404#define RX_MPDU_START_INFO6_POWER_MGMT		BIT(18)
 405#define RX_MPDU_START_INFO6_NON_QOS		BIT(19)
 406#define RX_MPDU_START_INFO6_NULL_DATA		BIT(20)
 407#define RX_MPDU_START_INFO6_MGMT_TYPE		BIT(21)
 408#define RX_MPDU_START_INFO6_CTRL_TYPE		BIT(22)
 409#define RX_MPDU_START_INFO6_MORE_DATA		BIT(23)
 410#define RX_MPDU_START_INFO6_EOSP		BIT(24)
 411#define RX_MPDU_START_INFO6_FRAGMENT		BIT(25)
 412#define RX_MPDU_START_INFO6_ORDER		BIT(26)
 413#define RX_MPDU_START_INFO6_UAPSD_TRIGGER	BIT(27)
 414#define RX_MPDU_START_INFO6_ENCRYPT_REQUIRED	BIT(28)
 415#define RX_MPDU_START_INFO6_DIRECTED		BIT(29)
 416
 417#define RX_MPDU_START_RAW_MPDU			BIT(0)
 418
 419struct rx_mpdu_start_ipq8074 {
 420	__le16 info0;
 421	__le16 phy_ppdu_id;
 422	__le16 ast_index;
 423	__le16 sw_peer_id;
 424	__le32 info1;
 425	__le32 info2;
 426	__le32 pn[4];
 427	__le32 peer_meta_data;
 428	__le32 info3;
 429	__le32 reo_queue_desc_lo;
 430	__le32 info4;
 431	__le32 info5;
 432	__le32 info6;
 433	__le16 frame_ctrl;
 434	__le16 duration;
 435	u8 addr1[ETH_ALEN];
 436	u8 addr2[ETH_ALEN];
 437	u8 addr3[ETH_ALEN];
 438	__le16 seq_ctrl;
 439	u8 addr4[ETH_ALEN];
 440	__le16 qos_ctrl;
 441	__le32 ht_ctrl;
 442	__le32 raw;
 443} __packed;
 444
 445#define RX_MPDU_START_INFO7_REO_DEST_IND		GENMASK(4, 0)
 446#define RX_MPDU_START_INFO7_LMAC_PEER_ID_MSB		GENMASK(6, 5)
 447#define RX_MPDU_START_INFO7_FLOW_ID_TOEPLITZ		BIT(7)
 448#define RX_MPDU_START_INFO7_PKT_SEL_FP_UCAST_DATA	BIT(8)
 449#define RX_MPDU_START_INFO7_PKT_SEL_FP_MCAST_DATA	BIT(9)
 450#define RX_MPDU_START_INFO7_PKT_SEL_FP_CTRL_BAR		BIT(10)
 451#define RX_MPDU_START_INFO7_RXDMA0_SRC_RING_SEL		GENMASK(12, 11)
 452#define RX_MPDU_START_INFO7_RXDMA0_DST_RING_SEL		GENMASK(14, 13)
 453
 454#define RX_MPDU_START_INFO8_REO_QUEUE_DESC_HI		GENMASK(7, 0)
 455#define RX_MPDU_START_INFO8_RECV_QUEUE_NUM		GENMASK(23, 8)
 456#define RX_MPDU_START_INFO8_PRE_DELIM_ERR_WARN		BIT(24)
 457#define RX_MPDU_START_INFO8_FIRST_DELIM_ERR		BIT(25)
 458
 459#define RX_MPDU_START_INFO9_EPD_EN			BIT(0)
 460#define RX_MPDU_START_INFO9_ALL_FRAME_ENCPD		BIT(1)
 461#define RX_MPDU_START_INFO9_ENC_TYPE			GENMASK(5, 2)
 462#define RX_MPDU_START_INFO9_VAR_WEP_KEY_WIDTH		GENMASK(7, 6)
 463#define RX_MPDU_START_INFO9_MESH_STA			GENMASK(9, 8)
 464#define RX_MPDU_START_INFO9_BSSID_HIT			BIT(10)
 465#define RX_MPDU_START_INFO9_BSSID_NUM			GENMASK(14, 11)
 466#define RX_MPDU_START_INFO9_TID				GENMASK(18, 15)
 467
 468#define RX_MPDU_START_INFO10_RXPCU_MPDU_FLTR		GENMASK(1, 0)
 469#define RX_MPDU_START_INFO10_SW_FRAME_GRP_ID		GENMASK(8, 2)
 470#define RX_MPDU_START_INFO10_NDP_FRAME			BIT(9)
 471#define RX_MPDU_START_INFO10_PHY_ERR			BIT(10)
 472#define RX_MPDU_START_INFO10_PHY_ERR_MPDU_HDR		BIT(11)
 473#define RX_MPDU_START_INFO10_PROTO_VER_ERR		BIT(12)
 474#define RX_MPDU_START_INFO10_AST_LOOKUP_VALID		BIT(13)
 475
 476#define RX_MPDU_START_INFO11_MPDU_FCTRL_VALID		BIT(0)
 477#define RX_MPDU_START_INFO11_MPDU_DUR_VALID		BIT(1)
 478#define RX_MPDU_START_INFO11_MAC_ADDR1_VALID		BIT(2)
 479#define RX_MPDU_START_INFO11_MAC_ADDR2_VALID		BIT(3)
 480#define RX_MPDU_START_INFO11_MAC_ADDR3_VALID		BIT(4)
 481#define RX_MPDU_START_INFO11_MAC_ADDR4_VALID		BIT(5)
 482#define RX_MPDU_START_INFO11_MPDU_SEQ_CTRL_VALID	BIT(6)
 483#define RX_MPDU_START_INFO11_MPDU_QOS_CTRL_VALID	BIT(7)
 484#define RX_MPDU_START_INFO11_MPDU_HT_CTRL_VALID		BIT(8)
 485#define RX_MPDU_START_INFO11_ENCRYPT_INFO_VALID		BIT(9)
 486#define RX_MPDU_START_INFO11_MPDU_FRAG_NUMBER		GENMASK(13, 10)
 487#define RX_MPDU_START_INFO11_MORE_FRAG_FLAG		BIT(14)
 488#define RX_MPDU_START_INFO11_FROM_DS			BIT(16)
 489#define RX_MPDU_START_INFO11_TO_DS			BIT(17)
 490#define RX_MPDU_START_INFO11_ENCRYPTED			BIT(18)
 491#define RX_MPDU_START_INFO11_MPDU_RETRY			BIT(19)
 492#define RX_MPDU_START_INFO11_MPDU_SEQ_NUM		GENMASK(31, 20)
 493
 494#define RX_MPDU_START_INFO12_KEY_ID			GENMASK(7, 0)
 495#define RX_MPDU_START_INFO12_NEW_PEER_ENTRY		BIT(8)
 496#define RX_MPDU_START_INFO12_DECRYPT_NEEDED		BIT(9)
 497#define RX_MPDU_START_INFO12_DECAP_TYPE			GENMASK(11, 10)
 498#define RX_MPDU_START_INFO12_VLAN_TAG_C_PADDING		BIT(12)
 499#define RX_MPDU_START_INFO12_VLAN_TAG_S_PADDING		BIT(13)
 500#define RX_MPDU_START_INFO12_STRIP_VLAN_TAG_C		BIT(14)
 501#define RX_MPDU_START_INFO12_STRIP_VLAN_TAG_S		BIT(15)
 502#define RX_MPDU_START_INFO12_PRE_DELIM_COUNT		GENMASK(27, 16)
 503#define RX_MPDU_START_INFO12_AMPDU_FLAG			BIT(28)
 504#define RX_MPDU_START_INFO12_BAR_FRAME			BIT(29)
 505#define RX_MPDU_START_INFO12_RAW_MPDU			BIT(30)
 506
 507#define RX_MPDU_START_INFO13_MPDU_LEN			GENMASK(13, 0)
 508#define RX_MPDU_START_INFO13_FIRST_MPDU			BIT(14)
 509#define RX_MPDU_START_INFO13_MCAST_BCAST		BIT(15)
 510#define RX_MPDU_START_INFO13_AST_IDX_NOT_FOUND		BIT(16)
 511#define RX_MPDU_START_INFO13_AST_IDX_TIMEOUT		BIT(17)
 512#define RX_MPDU_START_INFO13_POWER_MGMT			BIT(18)
 513#define RX_MPDU_START_INFO13_NON_QOS			BIT(19)
 514#define RX_MPDU_START_INFO13_NULL_DATA			BIT(20)
 515#define RX_MPDU_START_INFO13_MGMT_TYPE			BIT(21)
 516#define RX_MPDU_START_INFO13_CTRL_TYPE			BIT(22)
 517#define RX_MPDU_START_INFO13_MORE_DATA			BIT(23)
 518#define RX_MPDU_START_INFO13_EOSP			BIT(24)
 519#define RX_MPDU_START_INFO13_FRAGMENT			BIT(25)
 520#define RX_MPDU_START_INFO13_ORDER			BIT(26)
 521#define RX_MPDU_START_INFO13_UAPSD_TRIGGER		BIT(27)
 522#define RX_MPDU_START_INFO13_ENCRYPT_REQUIRED		BIT(28)
 523#define RX_MPDU_START_INFO13_DIRECTED			BIT(29)
 524#define RX_MPDU_START_INFO13_AMSDU_PRESENT		BIT(30)
 525
 526struct rx_mpdu_start_qcn9074 {
 527	__le32 info7;
 528	__le32 reo_queue_desc_lo;
 529	__le32 info8;
 530	__le32 pn[4];
 531	__le32 info9;
 532	__le32 peer_meta_data;
 533	__le16 info10;
 534	__le16 phy_ppdu_id;
 535	__le16 ast_index;
 536	__le16 sw_peer_id;
 537	__le32 info11;
 538	__le32 info12;
 539	__le32 info13;
 540	__le16 frame_ctrl;
 541	__le16 duration;
 542	u8 addr1[ETH_ALEN];
 543	u8 addr2[ETH_ALEN];
 544	u8 addr3[ETH_ALEN];
 545	__le16 seq_ctrl;
 546	u8 addr4[ETH_ALEN];
 547	__le16 qos_ctrl;
 548	__le32 ht_ctrl;
 549} __packed;
 550
 551struct rx_mpdu_start_wcn6855 {
 552	__le32 info3;
 553	__le32 reo_queue_desc_lo;
 554	__le32 info4;
 555	__le32 pn[4];
 556	__le32 info2;
 557	__le32 peer_meta_data;
 558	__le16 info0;
 559	__le16 phy_ppdu_id;
 560	__le16 ast_index;
 561	__le16 sw_peer_id;
 562	__le32 info1;
 563	__le32 info5;
 564	__le32 info6;
 565	__le16 frame_ctrl;
 566	__le16 duration;
 567	u8 addr1[ETH_ALEN];
 568	u8 addr2[ETH_ALEN];
 569	u8 addr3[ETH_ALEN];
 570	__le16 seq_ctrl;
 571	u8 addr4[ETH_ALEN];
 572	__le16 qos_ctrl;
 573	__le32 ht_ctrl;
 574} __packed;
 575
 576/* rx_mpdu_start
 577 *
 578 * rxpcu_mpdu_filter_in_category
 579 *		Field indicates what the reason was that this mpdu frame
 580 *		was allowed to come into the receive path by rxpcu. Values
 581 *		are defined in enum %RX_DESC_RXPCU_FILTER_*.
 582 *		Note: for ndp frame, if it was expected because the preceding
 583 *		NDPA was filter_pass, the setting rxpcu_filter_pass will be
 584 *		used. This setting will also be used for every ndp frame in
 585 *		case Promiscuous mode is enabled.
 586 *
 587 * sw_frame_group_id
 588 *		SW processes frames based on certain classifications. Values
 589 *		are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*.
 590 *
 591 * ndp_frame
 592 *		Indicates that the received frame was an NDP frame.
 593 *
 594 * phy_err
 595 *		Indicates that PHY error was received before MAC received data.
 596 *
 597 * phy_err_during_mpdu_header
 598 *		PHY error was received before MAC received the complete MPDU
 599 *		header which was needed for proper decoding.
 600 *
 601 * protocol_version_err
 602 *		RXPCU detected a version error in the frame control field.
 603 *
 604 * ast_based_lookup_valid
 605 *		AST based lookup for this frame has found a valid result.
 606 *
 607 * phy_ppdu_id
 608 *		A ppdu counter value that PHY increments for every PPDU
 609 *		received. The counter value wraps around.
 610 *
 611 * ast_index
 612 *		This field indicates the index of the AST entry corresponding
 613 *		to this MPDU. It is provided by the GSE module instantiated in
 614 *		RXPCU. A value of 0xFFFF indicates an invalid AST index.
 615 *
 616 * sw_peer_id
 617 *		This field indicates a unique peer identifier. It is set equal
 618 *		to field 'sw_peer_id' from the AST entry.
 619 *
 620 * mpdu_frame_control_valid, mpdu_duration_valid, mpdu_qos_control_valid,
 621 * mpdu_ht_control_valid, frame_encryption_info_valid
 622 *		Indicates that each fields have valid entries.
 623 *
 624 * mac_addr_adx_valid
 625 *		Corresponding mac_addr_adx_{lo/hi} has valid entries.
 626 *
 627 * from_ds, to_ds
 628 *		Valid only when mpdu_frame_control_valid is set. Indicates that
 629 *		frame is received from DS and sent to DS.
 630 *
 631 * encrypted
 632 *		Protected bit from the frame control.
 633 *
 634 * mpdu_retry
 635 *		Retry bit from frame control. Only valid when first_msdu is set.
 636 *
 637 * mpdu_sequence_number
 638 *		The sequence number from the 802.11 header.
 639 *
 640 * epd_en
 641 *		If set, use EPD instead of LPD.
 642 *
 643 * all_frames_shall_be_encrypted
 644 *		If set, all frames (data only?) shall be encrypted. If not,
 645 *		RX CRYPTO shall set an error flag.
 646 *
 647 * encrypt_type
 648 *		Values are defined in enum %HAL_ENCRYPT_TYPE_.
 649 *
 650 * mesh_sta
 651 *		Indicates a Mesh (11s) STA.
 652 *
 653 * bssid_hit
 654 *		 BSSID of the incoming frame matched one of the 8 BSSID
 655 *		 register values.
 656 *
 657 * bssid_number
 658 *		This number indicates which one out of the 8 BSSID register
 659 *		values matched the incoming frame.
 660 *
 661 * tid
 662 *		TID field in the QoS control field
 663 *
 664 * pn
 665 *		The PN number.
 666 *
 667 * peer_meta_data
 668 *		Meta data that SW has programmed in the Peer table entry
 669 *		of the transmitting STA.
 670 *
 671 * rx_reo_queue_desc_addr_lo
 672 *		Address (lower 32 bits) of the REO queue descriptor.
 673 *
 674 * rx_reo_queue_desc_addr_hi
 675 *		Address (upper 8 bits) of the REO queue descriptor.
 676 *
 677 * receive_queue_number
 678 *		Indicates the MPDU queue ID to which this MPDU link
 679 *		descriptor belongs.
 680 *
 681 * pre_delim_err_warning
 682 *		Indicates that a delimiter FCS error was found in between the
 683 *		previous MPDU and this MPDU. Note that this is just a warning,
 684 *		and does not mean that this MPDU is corrupted in any way. If
 685 *		it is, there will be other errors indicated such as FCS or
 686 *		decrypt errors.
 687 *
 688 * first_delim_err
 689 *		Indicates that the first delimiter had a FCS failure.
 690 *
 691 * key_id
 692 *		The key ID octet from the IV.
 693 *
 694 * new_peer_entry
 695 *		Set if new RX_PEER_ENTRY TLV follows. If clear, RX_PEER_ENTRY
 696 *		doesn't follow so RX DECRYPTION module either uses old peer
 697 *		entry or not decrypt.
 698 *
 699 * decrypt_needed
 700 *		When RXPCU sets bit 'ast_index_not_found or ast_index_timeout',
 701 *		RXPCU will also ensure that this bit is NOT set. CRYPTO for that
 702 *		reason only needs to evaluate this bit and non of the other ones
 703 *
 704 * decap_type
 705 *		Used by the OLE during decapsulation. Values are defined in
 706 *		enum %MPDU_START_DECAP_TYPE_*.
 707 *
 708 * rx_insert_vlan_c_tag_padding
 709 * rx_insert_vlan_s_tag_padding
 710 *		Insert 4 byte of all zeros as VLAN tag or double VLAN tag if
 711 *		the rx payload does not have VLAN.
 712 *
 713 * strip_vlan_c_tag_decap
 714 * strip_vlan_s_tag_decap
 715 *		Strip VLAN or double VLAN during decapsulation.
 716 *
 717 * pre_delim_count
 718 *		The number of delimiters before this MPDU. Note that this
 719 *		number is cleared at PPDU start. If this MPDU is the first
 720 *		received MPDU in the PPDU and this MPDU gets filtered-in,
 721 *		this field will indicate the number of delimiters located
 722 *		after the last MPDU in the previous PPDU.
 723 *
 724 *		If this MPDU is located after the first received MPDU in
 725 *		an PPDU, this field will indicate the number of delimiters
 726 *		located between the previous MPDU and this MPDU.
 727 *
 728 * ampdu_flag
 729 *		Received frame was part of an A-MPDU.
 730 *
 731 * bar_frame
 732 *		Received frame is a BAR frame
 733 *
 734 * mpdu_length
 735 *		MPDU length before decapsulation.
 736 *
 737 * first_mpdu..directed
 738 *		See definition in RX attention descriptor
 739 *
 740 */
 741
 742enum rx_msdu_start_pkt_type {
 743	RX_MSDU_START_PKT_TYPE_11A,
 744	RX_MSDU_START_PKT_TYPE_11B,
 745	RX_MSDU_START_PKT_TYPE_11N,
 746	RX_MSDU_START_PKT_TYPE_11AC,
 747	RX_MSDU_START_PKT_TYPE_11AX,
 748};
 749
 750enum rx_msdu_start_sgi {
 751	RX_MSDU_START_SGI_0_8_US,
 752	RX_MSDU_START_SGI_0_4_US,
 753	RX_MSDU_START_SGI_1_6_US,
 754	RX_MSDU_START_SGI_3_2_US,
 755};
 756
 757enum rx_msdu_start_recv_bw {
 758	RX_MSDU_START_RECV_BW_20MHZ,
 759	RX_MSDU_START_RECV_BW_40MHZ,
 760	RX_MSDU_START_RECV_BW_80MHZ,
 761	RX_MSDU_START_RECV_BW_160MHZ,
 762};
 763
 764enum rx_msdu_start_reception_type {
 765	RX_MSDU_START_RECEPTION_TYPE_SU,
 766	RX_MSDU_START_RECEPTION_TYPE_DL_MU_MIMO,
 767	RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA,
 768	RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA_MIMO,
 769	RX_MSDU_START_RECEPTION_TYPE_UL_MU_MIMO,
 770	RX_MSDU_START_RECEPTION_TYPE_UL_MU_OFDMA,
 771	RX_MSDU_START_RECEPTION_TYPE_UL_MU_OFDMA_MIMO,
 772};
 773
 774#define RX_MSDU_START_INFO1_MSDU_LENGTH		GENMASK(13, 0)
 775#define RX_MSDU_START_INFO1_RSVD_1A		BIT(14)
 776#define RX_MSDU_START_INFO1_IPSEC_ESP		BIT(15)
 777#define RX_MSDU_START_INFO1_L3_OFFSET		GENMASK(22, 16)
 778#define RX_MSDU_START_INFO1_IPSEC_AH		BIT(23)
 779#define RX_MSDU_START_INFO1_L4_OFFSET		GENMASK(31, 24)
 780
 781#define RX_MSDU_START_INFO2_MSDU_NUMBER		GENMASK(7, 0)
 782#define RX_MSDU_START_INFO2_DECAP_TYPE		GENMASK(9, 8)
 783#define RX_MSDU_START_INFO2_IPV4		BIT(10)
 784#define RX_MSDU_START_INFO2_IPV6		BIT(11)
 785#define RX_MSDU_START_INFO2_TCP			BIT(12)
 786#define RX_MSDU_START_INFO2_UDP			BIT(13)
 787#define RX_MSDU_START_INFO2_IP_FRAG		BIT(14)
 788#define RX_MSDU_START_INFO2_TCP_ONLY_ACK	BIT(15)
 789#define RX_MSDU_START_INFO2_DA_IS_BCAST_MCAST	BIT(16)
 790#define RX_MSDU_START_INFO2_SELECTED_TOEPLITZ_HASH	GENMASK(18, 17)
 791#define RX_MSDU_START_INFO2_IP_FIXED_HDR_VALID		BIT(19)
 792#define RX_MSDU_START_INFO2_IP_EXTN_HDR_VALID		BIT(20)
 793#define RX_MSDU_START_INFO2_IP_TCP_UDP_HDR_VALID	BIT(21)
 794#define RX_MSDU_START_INFO2_MESH_CTRL_PRESENT		BIT(22)
 795#define RX_MSDU_START_INFO2_LDPC			BIT(23)
 796#define RX_MSDU_START_INFO2_IP4_IP6_NXT_HDR		GENMASK(31, 24)
 797#define RX_MSDU_START_INFO2_DECAP_FORMAT		GENMASK(9, 8)
 798
 799#define RX_MSDU_START_INFO3_USER_RSSI		GENMASK(7, 0)
 800#define RX_MSDU_START_INFO3_PKT_TYPE		GENMASK(11, 8)
 801#define RX_MSDU_START_INFO3_STBC		BIT(12)
 802#define RX_MSDU_START_INFO3_SGI			GENMASK(14, 13)
 803#define RX_MSDU_START_INFO3_RATE_MCS		GENMASK(18, 15)
 804#define RX_MSDU_START_INFO3_RECV_BW		GENMASK(20, 19)
 805#define RX_MSDU_START_INFO3_RECEPTION_TYPE	GENMASK(23, 21)
 806#define RX_MSDU_START_INFO3_MIMO_SS_BITMAP	GENMASK(31, 24)
 807
 808struct rx_msdu_start_ipq8074 {
 809	__le16 info0;
 810	__le16 phy_ppdu_id;
 811	__le32 info1;
 812	__le32 info2;
 813	__le32 toeplitz_hash;
 814	__le32 flow_id_toeplitz;
 815	__le32 info3;
 816	__le32 ppdu_start_timestamp;
 817	__le32 phy_meta_data;
 818} __packed;
 819
 820struct rx_msdu_start_qcn9074 {
 821	__le16 info0;
 822	__le16 phy_ppdu_id;
 823	__le32 info1;
 824	__le32 info2;
 825	__le32 toeplitz_hash;
 826	__le32 flow_id_toeplitz;
 827	__le32 info3;
 828	__le32 ppdu_start_timestamp;
 829	__le32 phy_meta_data;
 830	__le16 vlan_ctag_c1;
 831	__le16 vlan_stag_c1;
 832} __packed;
 833
 834struct rx_msdu_start_wcn6855 {
 835	__le16 info0;
 836	__le16 phy_ppdu_id;
 837	__le32 info1;
 838	__le32 info2;
 839	__le32 toeplitz_hash;
 840	__le32 flow_id_toeplitz;
 841	__le32 info3;
 842	__le32 ppdu_start_timestamp;
 843	__le32 phy_meta_data;
 844	__le16 vlan_ctag_ci;
 845	__le16 vlan_stag_ci;
 846} __packed;
 847
 848/* rx_msdu_start
 849 *
 850 * rxpcu_mpdu_filter_in_category
 851 *		Field indicates what the reason was that this mpdu frame
 852 *		was allowed to come into the receive path by rxpcu. Values
 853 *		are defined in enum %RX_DESC_RXPCU_FILTER_*.
 854 *
 855 * sw_frame_group_id
 856 *		SW processes frames based on certain classifications. Values
 857 *		are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*.
 858 *
 859 * phy_ppdu_id
 860 *		A ppdu counter value that PHY increments for every PPDU
 861 *		received. The counter value wraps around.
 862 *
 863 * msdu_length
 864 *		MSDU length in bytes after decapsulation.
 865 *
 866 * ipsec_esp
 867 *		Set if IPv4/v6 packet is using IPsec ESP.
 868 *
 869 * l3_offset
 870 *		Depending upon mode bit, this field either indicates the
 871 *		L3 offset in bytes from the start of the RX_HEADER or the IP
 872 *		offset in bytes from the start of the packet after
 873 *		decapsulation. The latter is only valid if ipv4_proto or
 874 *		ipv6_proto is set.
 875 *
 876 * ipsec_ah
 877 *		Set if IPv4/v6 packet is using IPsec AH
 878 *
 879 * l4_offset
 880 *		Depending upon mode bit, this field either indicates the
 881 *		L4 offset in bytes from the start of RX_HEADER (only valid
 882 *		if either ipv4_proto or ipv6_proto is set to 1) or indicates
 883 *		the offset in bytes to the start of TCP or UDP header from
 884 *		the start of the IP header after decapsulation (Only valid if
 885 *		tcp_proto or udp_proto is set). The value 0 indicates that
 886 *		the offset is longer than 127 bytes.
 887 *
 888 * msdu_number
 889 *		Indicates the MSDU number within a MPDU.  This value is
 890 *		reset to zero at the start of each MPDU.  If the number of
 891 *		MSDU exceeds 255 this number will wrap using modulo 256.
 892 *
 893 * decap_type
 894 *		Indicates the format after decapsulation. Values are defined in
 895 *		enum %MPDU_START_DECAP_TYPE_*.
 896 *
 897 * ipv4_proto
 898 *		Set if L2 layer indicates IPv4 protocol.
 899 *
 900 * ipv6_proto
 901 *		Set if L2 layer indicates IPv6 protocol.
 902 *
 903 * tcp_proto
 904 *		Set if the ipv4_proto or ipv6_proto are set and the IP protocol
 905 *		indicates TCP.
 906 *
 907 * udp_proto
 908 *		Set if the ipv4_proto or ipv6_proto are set and the IP protocol
 909 *		indicates UDP.
 910 *
 911 * ip_frag
 912 *		Indicates that either the IP More frag bit is set or IP frag
 913 *		number is non-zero.  If set indicates that this is a fragmented
 914 *		IP packet.
 915 *
 916 * tcp_only_ack
 917 *		Set if only the TCP Ack bit is set in the TCP flags and if
 918 *		the TCP payload is 0.
 919 *
 920 * da_is_bcast_mcast
 921 *		The destination address is broadcast or multicast.
 922 *
 923 * toeplitz_hash
 924 *		Actual chosen Hash.
 925 *		0 - Toeplitz hash of 2-tuple (IP source address, IP
 926 *		    destination address)
 927 *		1 - Toeplitz hash of 4-tuple (IP source	address,
 928 *		    IP destination address, L4 (TCP/UDP) source port,
 929 *		    L4 (TCP/UDP) destination port)
 930 *		2 - Toeplitz of flow_id
 931 *		3 - Zero is used
 932 *
 933 * ip_fixed_header_valid
 934 *		Fixed 20-byte IPv4 header or 40-byte IPv6 header parsed
 935 *		fully within first 256 bytes of the packet
 936 *
 937 * ip_extn_header_valid
 938 *		IPv6/IPv6 header, including IPv4 options and
 939 *		recognizable extension headers parsed fully within first 256
 940 *		bytes of the packet
 941 *
 942 * tcp_udp_header_valid
 943 *		Fixed 20-byte TCP (excluding TCP options) or 8-byte UDP
 944 *		header parsed fully within first 256 bytes of the packet
 945 *
 946 * mesh_control_present
 947 *		When set, this MSDU includes the 'Mesh Control' field
 948 *
 949 * ldpc
 950 *
 951 * ip4_protocol_ip6_next_header
 952 *		For IPv4, this is the 8 bit protocol field set). For IPv6 this
 953 *		is the 8 bit next_header field.
 954 *
 955 * toeplitz_hash_2_or_4
 956 *		Controlled by RxOLE register - If register bit set to 0,
 957 *		Toeplitz hash is computed over 2-tuple IPv4 or IPv6 src/dest
 958 *		addresses; otherwise, toeplitz hash is computed over 4-tuple
 959 *		IPv4 or IPv6 src/dest addresses and src/dest ports.
 960 *
 961 * flow_id_toeplitz
 962 *		Toeplitz hash of 5-tuple
 963 *		{IP source address, IP destination address, IP source port, IP
 964 *		destination port, L4 protocol}  in case of non-IPSec.
 965 *
 966 *		In case of IPSec - Toeplitz hash of 4-tuple
 967 *		{IP source address, IP destination address, SPI, L4 protocol}
 968 *
 969 *		The relevant Toeplitz key registers are provided in RxOLE's
 970 *		instance of common parser module. These registers are separate
 971 *		from the Toeplitz keys used by ASE/FSE modules inside RxOLE.
 972 *		The actual value will be passed on from common parser module
 973 *		to RxOLE in one of the WHO_* TLVs.
 974 *
 975 * user_rssi
 976 *		RSSI for this user
 977 *
 978 * pkt_type
 979 *		Values are defined in enum %RX_MSDU_START_PKT_TYPE_*.
 980 *
 981 * stbc
 982 *		When set, use STBC transmission rates.
 983 *
 984 * sgi
 985 *		Field only valid when pkt type is HT, VHT or HE. Values are
 986 *		defined in enum %RX_MSDU_START_SGI_*.
 987 *
 988 * rate_mcs
 989 *		MCS Rate used.
 990 *
 991 * receive_bandwidth
 992 *		Full receive Bandwidth. Values are defined in enum
 993 *		%RX_MSDU_START_RECV_*.
 994 *
 995 * reception_type
 996 *		Indicates what type of reception this is and defined in enum
 997 *		%RX_MSDU_START_RECEPTION_TYPE_*.
 998 *
 999 * mimo_ss_bitmap
1000 *		Field only valid when
1001 *		Reception_type is RX_MSDU_START_RECEPTION_TYPE_DL_MU_MIMO or
1002 *		RX_MSDU_START_RECEPTION_TYPE_DL_MU_OFDMA_MIMO.
1003 *
1004 *		Bitmap, with each bit indicating if the related spatial
1005 *		stream is used for this STA
1006 *
1007 *		LSB related to SS 0
1008 *
1009 *		0 - spatial stream not used for this reception
1010 *		1 - spatial stream used for this reception
1011 *
1012 * ppdu_start_timestamp
1013 *		Timestamp that indicates when the PPDU that contained this MPDU
1014 *		started on the medium.
1015 *
1016 * phy_meta_data
1017 *		SW programmed Meta data provided by the PHY. Can be used for SW
1018 *		to indicate the channel the device is on.
1019 */
1020
1021#define RX_MSDU_END_INFO0_RXPCU_MPDU_FITLER	GENMASK(1, 0)
1022#define RX_MSDU_END_INFO0_SW_FRAME_GRP_ID	GENMASK(8, 2)
1023
1024#define RX_MSDU_END_INFO1_KEY_ID		GENMASK(7, 0)
1025#define RX_MSDU_END_INFO1_CCE_SUPER_RULE	GENMASK(13, 8)
1026#define RX_MSDU_END_INFO1_CCND_TRUNCATE		BIT(14)
1027#define RX_MSDU_END_INFO1_CCND_CCE_DIS		BIT(15)
1028#define RX_MSDU_END_INFO1_EXT_WAPI_PN		GENMASK(31, 16)
1029
1030#define RX_MSDU_END_INFO2_REPORTED_MPDU_LEN	GENMASK(13, 0)
1031#define RX_MSDU_END_INFO2_FIRST_MSDU		BIT(14)
1032#define RX_MSDU_END_INFO2_FIRST_MSDU_WCN6855	BIT(28)
1033#define RX_MSDU_END_INFO2_LAST_MSDU		BIT(15)
1034#define RX_MSDU_END_INFO2_LAST_MSDU_WCN6855	BIT(29)
1035#define RX_MSDU_END_INFO2_SA_IDX_TIMEOUT	BIT(16)
1036#define RX_MSDU_END_INFO2_DA_IDX_TIMEOUT	BIT(17)
1037#define RX_MSDU_END_INFO2_MSDU_LIMIT_ERR	BIT(18)
1038#define RX_MSDU_END_INFO2_FLOW_IDX_TIMEOUT	BIT(19)
1039#define RX_MSDU_END_INFO2_FLOW_IDX_INVALID	BIT(20)
1040#define RX_MSDU_END_INFO2_WIFI_PARSER_ERR	BIT(21)
1041#define RX_MSDU_END_INFO2_AMSDU_PARSET_ERR	BIT(22)
1042#define RX_MSDU_END_INFO2_SA_IS_VALID		BIT(23)
1043#define RX_MSDU_END_INFO2_DA_IS_VALID		BIT(24)
1044#define RX_MSDU_END_INFO2_DA_IS_MCBC		BIT(25)
1045#define RX_MSDU_END_INFO2_L3_HDR_PADDING	GENMASK(27, 26)
1046
1047#define RX_MSDU_END_INFO3_TCP_FLAG		GENMASK(8, 0)
1048#define RX_MSDU_END_INFO3_LRO_ELIGIBLE		BIT(9)
1049
1050#define RX_MSDU_END_INFO4_DA_OFFSET		GENMASK(5, 0)
1051#define RX_MSDU_END_INFO4_SA_OFFSET		GENMASK(11, 6)
1052#define RX_MSDU_END_INFO4_DA_OFFSET_VALID	BIT(12)
1053#define RX_MSDU_END_INFO4_SA_OFFSET_VALID	BIT(13)
1054#define RX_MSDU_END_INFO4_L3_TYPE		GENMASK(31, 16)
1055
1056#define RX_MSDU_END_INFO5_MSDU_DROP		BIT(0)
1057#define RX_MSDU_END_INFO5_REO_DEST_IND		GENMASK(5, 1)
1058#define RX_MSDU_END_INFO5_FLOW_IDX		GENMASK(25, 6)
1059
1060struct rx_msdu_end_ipq8074 {
1061	__le16 info0;
1062	__le16 phy_ppdu_id;
1063	__le16 ip_hdr_cksum;
1064	__le16 tcp_udp_cksum;
1065	__le32 info1;
1066	__le32 ext_wapi_pn[2];
1067	__le32 info2;
1068	__le32 ipv6_options_crc;
1069	__le32 tcp_seq_num;
1070	__le32 tcp_ack_num;
1071	__le16 info3;
1072	__le16 window_size;
1073	__le32 info4;
1074	__le32 rule_indication[2];
1075	__le16 sa_idx;
1076	__le16 da_idx;
1077	__le32 info5;
1078	__le32 fse_metadata;
1079	__le16 cce_metadata;
1080	__le16 sa_sw_peer_id;
1081} __packed;
1082
1083struct rx_msdu_end_wcn6855 {
1084	__le16 info0;
1085	__le16 phy_ppdu_id;
1086	__le16 ip_hdr_cksum;
1087	__le16 reported_mpdu_len;
1088	__le32 info1;
1089	__le32 ext_wapi_pn[2];
1090	__le32 info4;
1091	__le32 ipv6_options_crc;
1092	__le32 tcp_seq_num;
1093	__le32 tcp_ack_num;
1094	__le16 info3;
1095	__le16 window_size;
1096	__le32 info2;
1097	__le16 sa_idx;
1098	__le16 da_idx;
1099	__le32 info5;
1100	__le32 fse_metadata;
1101	__le16 cce_metadata;
1102	__le16 sa_sw_peer_id;
1103	__le32 rule_indication[2];
1104	__le32 info6;
1105	__le32 info7;
1106} __packed;
1107
1108#define RX_MSDU_END_MPDU_LENGTH_INFO		GENMASK(13, 0)
1109
1110#define RX_MSDU_END_INFO2_DA_OFFSET		GENMASK(5, 0)
1111#define RX_MSDU_END_INFO2_SA_OFFSET		GENMASK(11, 6)
1112#define RX_MSDU_END_INFO2_DA_OFFSET_VALID	BIT(12)
1113#define RX_MSDU_END_INFO2_SA_OFFSET_VALID	BIT(13)
1114#define RX_MSDU_END_INFO2_L3_TYPE		GENMASK(31, 16)
1115
1116#define RX_MSDU_END_INFO4_SA_IDX_TIMEOUT	BIT(0)
1117#define RX_MSDU_END_INFO4_DA_IDX_TIMEOUT	BIT(1)
1118#define RX_MSDU_END_INFO4_MSDU_LIMIT_ERR	BIT(2)
1119#define RX_MSDU_END_INFO4_FLOW_IDX_TIMEOUT	BIT(3)
1120#define RX_MSDU_END_INFO4_FLOW_IDX_INVALID	BIT(4)
1121#define RX_MSDU_END_INFO4_WIFI_PARSER_ERR	BIT(5)
1122#define RX_MSDU_END_INFO4_AMSDU_PARSER_ERR	BIT(6)
1123#define RX_MSDU_END_INFO4_SA_IS_VALID		BIT(7)
1124#define RX_MSDU_END_INFO4_DA_IS_VALID		BIT(8)
1125#define RX_MSDU_END_INFO4_DA_IS_MCBC		BIT(9)
1126#define RX_MSDU_END_INFO4_L3_HDR_PADDING	GENMASK(11, 10)
1127#define RX_MSDU_END_INFO4_FIRST_MSDU		BIT(12)
1128#define RX_MSDU_END_INFO4_LAST_MSDU		BIT(13)
1129
1130#define RX_MSDU_END_INFO6_AGGR_COUNT		GENMASK(7, 0)
1131#define RX_MSDU_END_INFO6_FLOW_AGGR_CONTN	BIT(8)
1132#define RX_MSDU_END_INFO6_FISA_TIMEOUT		BIT(9)
1133
1134struct rx_msdu_end_qcn9074 {
1135	__le16 info0;
1136	__le16 phy_ppdu_id;
1137	__le16 ip_hdr_cksum;
1138	__le16 mpdu_length_info;
1139	__le32 info1;
1140	__le32 rule_indication[2];
1141	__le32 info2;
1142	__le32 ipv6_options_crc;
1143	__le32 tcp_seq_num;
1144	__le32 tcp_ack_num;
1145	__le16 info3;
1146	__le16 window_size;
1147	__le16 tcp_udp_cksum;
1148	__le16 info4;
1149	__le16 sa_idx;
1150	__le16 da_idx;
1151	__le32 info5;
1152	__le32 fse_metadata;
1153	__le16 cce_metadata;
1154	__le16 sa_sw_peer_id;
1155	__le32 info6;
1156	__le16 cum_l4_cksum;
1157	__le16 cum_ip_length;
1158} __packed;
1159
1160/* rx_msdu_end
1161 *
1162 * rxpcu_mpdu_filter_in_category
1163 *		Field indicates what the reason was that this mpdu frame
1164 *		was allowed to come into the receive path by rxpcu. Values
1165 *		are defined in enum %RX_DESC_RXPCU_FILTER_*.
1166 *
1167 * sw_frame_group_id
1168 *		SW processes frames based on certain classifications. Values
1169 *		are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*.
1170 *
1171 * phy_ppdu_id
1172 *		A ppdu counter value that PHY increments for every PPDU
1173 *		received. The counter value wraps around.
1174 *
1175 * ip_hdr_cksum
1176 *		This can include the IP header checksum or the pseudo
1177 *		header checksum used by TCP/UDP checksum.
1178 *
1179 * tcp_udp_chksum
1180 *		The value of the computed TCP/UDP checksum.  A mode bit
1181 *		selects whether this checksum is the full checksum or the
1182 *		partial checksum which does not include the pseudo header.
1183 *
1184 * key_id
1185 *		The key ID octet from the IV. Only valid when first_msdu is set.
1186 *
1187 * cce_super_rule
1188 *		Indicates the super filter rule.
1189 *
1190 * cce_classify_not_done_truncate
1191 *		Classification failed due to truncated frame.
1192 *
1193 * cce_classify_not_done_cce_dis
1194 *		Classification failed due to CCE global disable
1195 *
1196 * ext_wapi_pn*
1197 *		Extension PN (packet number) which is only used by WAPI.
1198 *
1199 * reported_mpdu_length
1200 *		MPDU length before decapsulation. Only valid when first_msdu is
1201 *		set. This field is taken directly from the length field of the
1202 *		A-MPDU delimiter or the preamble length field for non-A-MPDU
1203 *		frames.
1204 *
1205 * first_msdu
1206 *		Indicates the first MSDU of A-MSDU. If both first_msdu and
1207 *		last_msdu are set in the MSDU then this is a non-aggregated MSDU
1208 *		frame: normal MPDU. Interior MSDU in an A-MSDU shall have both
1209 *		first_mpdu and last_mpdu bits set to 0.
1210 *
1211 * last_msdu
1212 *		Indicates the last MSDU of the A-MSDU. MPDU end status is only
1213 *		valid when last_msdu is set.
1214 *
1215 * sa_idx_timeout
1216 *		Indicates an unsuccessful MAC source address search due to the
1217 *		expiring of the search timer.
1218 *
1219 * da_idx_timeout
1220 *		Indicates an unsuccessful MAC destination address search due to
1221 *		the expiring of the search timer.
1222 *
1223 * msdu_limit_error
1224 *		Indicates that the MSDU threshold was exceeded and thus all the
1225 *		rest of the MSDUs will not be scattered and will not be
1226 *		decapsulated but will be DMA'ed in RAW format as a single MSDU.
1227 *
1228 * flow_idx_timeout
1229 *		Indicates an unsuccessful flow search due to the expiring of
1230 *		the search timer.
1231 *
1232 * flow_idx_invalid
1233 *		flow id is not valid.
1234 *
1235 * amsdu_parser_error
1236 *		A-MSDU could not be properly de-agregated.
1237 *
1238 * sa_is_valid
1239 *		Indicates that OLE found a valid SA entry.
1240 *
1241 * da_is_valid
1242 *		Indicates that OLE found a valid DA entry.
1243 *
1244 * da_is_mcbc
1245 *		Field Only valid if da_is_valid is set. Indicates the DA address
1246 *		was a Multicast of Broadcast address.
1247 *
1248 * l3_header_padding
1249 *		Number of bytes padded  to make sure that the L3 header will
1250 *		always start of a Dword boundary.
1251 *
1252 * ipv6_options_crc
1253 *		32 bit CRC computed out of  IP v6 extension headers.
1254 *
1255 * tcp_seq_number
1256 *		TCP sequence number.
1257 *
1258 * tcp_ack_number
1259 *		TCP acknowledge number.
1260 *
1261 * tcp_flag
1262 *		TCP flags {NS, CWR, ECE, URG, ACK, PSH, RST, SYN, FIN}.
1263 *
1264 * lro_eligible
1265 *		Computed out of TCP and IP fields to indicate that this
1266 *		MSDU is eligible for LRO.
1267 *
1268 * window_size
1269 *		TCP receive window size.
1270 *
1271 * da_offset
1272 *		Offset into MSDU buffer for DA.
1273 *
1274 * sa_offset
1275 *		Offset into MSDU buffer for SA.
1276 *
1277 * da_offset_valid
1278 *		da_offset field is valid. This will be set to 0 in case
1279 *		of a dynamic A-MSDU when DA is compressed.
1280 *
1281 * sa_offset_valid
1282 *		sa_offset field is valid. This will be set to 0 in case
1283 *		of a dynamic A-MSDU when SA is compressed.
1284 *
1285 * l3_type
1286 *		The 16-bit type value indicating the type of L3 later
1287 *		extracted from LLC/SNAP, set to zero if SNAP is not
1288 *		available.
1289 *
1290 * rule_indication
1291 *		Bitmap indicating which of rules have matched.
1292 *
1293 * sa_idx
1294 *		The offset in the address table which matches MAC source address
1295 *
1296 * da_idx
1297 *		The offset in the address table which matches MAC destination
1298 *		address.
1299 *
1300 * msdu_drop
1301 *		REO shall drop this MSDU and not forward it to any other ring.
1302 *
1303 * reo_destination_indication
1304 *		The id of the reo exit ring where the msdu frame shall push
1305 *		after (MPDU level) reordering has finished. Values are defined
1306 *		in enum %HAL_RX_MSDU_DESC_REO_DEST_IND_.
1307 *
1308 * flow_idx
1309 *		Flow table index.
1310 *
1311 * fse_metadata
1312 *		FSE related meta data.
1313 *
1314 * cce_metadata
1315 *		CCE related meta data.
1316 *
1317 * sa_sw_peer_id
1318 *		sw_peer_id from the address search entry corresponding to the
1319 *		source address of the MSDU.
1320 */
1321
1322enum rx_mpdu_end_rxdma_dest_ring {
1323	RX_MPDU_END_RXDMA_DEST_RING_RELEASE,
1324	RX_MPDU_END_RXDMA_DEST_RING_FW,
1325	RX_MPDU_END_RXDMA_DEST_RING_SW,
1326	RX_MPDU_END_RXDMA_DEST_RING_REO,
1327};
1328
1329#define RX_MPDU_END_INFO1_UNSUP_KTYPE_SHORT_FRAME	BIT(11)
1330#define RX_MPDU_END_INFO1_RX_IN_TX_DECRYPT_BYT		BIT(12)
1331#define RX_MPDU_END_INFO1_OVERFLOW_ERR			BIT(13)
1332#define RX_MPDU_END_INFO1_MPDU_LEN_ERR			BIT(14)
1333#define RX_MPDU_END_INFO1_TKIP_MIC_ERR			BIT(15)
1334#define RX_MPDU_END_INFO1_DECRYPT_ERR			BIT(16)
1335#define RX_MPDU_END_INFO1_UNENCRYPTED_FRAME_ERR		BIT(17)
1336#define RX_MPDU_END_INFO1_PN_FIELDS_VALID		BIT(18)
1337#define RX_MPDU_END_INFO1_FCS_ERR			BIT(19)
1338#define RX_MPDU_END_INFO1_MSDU_LEN_ERR			BIT(20)
1339#define RX_MPDU_END_INFO1_RXDMA0_DEST_RING		GENMASK(22, 21)
1340#define RX_MPDU_END_INFO1_RXDMA1_DEST_RING		GENMASK(24, 23)
1341#define RX_MPDU_END_INFO1_DECRYPT_STATUS_CODE		GENMASK(27, 25)
1342#define RX_MPDU_END_INFO1_RX_BITMAP_NOT_UPD		BIT(28)
1343
1344struct rx_mpdu_end {
1345	__le16 info0;
1346	__le16 phy_ppdu_id;
1347	__le32 info1;
1348} __packed;
1349
1350/* rx_mpdu_end
1351 *
1352 * rxpcu_mpdu_filter_in_category
1353 *		Field indicates what the reason was that this mpdu frame
1354 *		was allowed to come into the receive path by rxpcu. Values
1355 *		are defined in enum %RX_DESC_RXPCU_FILTER_*.
1356 *
1357 * sw_frame_group_id
1358 *		SW processes frames based on certain classifications. Values
1359 *		are defined in enum %RX_DESC_SW_FRAME_GRP_ID_*.
1360 *
1361 * phy_ppdu_id
1362 *		A ppdu counter value that PHY increments for every PPDU
1363 *		received. The counter value wraps around.
1364 *
1365 * unsup_ktype_short_frame
1366 *		This bit will be '1' when WEP or TKIP or WAPI key type is
1367 *		received for 11ah short frame. Crypto will bypass the received
1368 *		packet without decryption to RxOLE after setting this bit.
1369 *
1370 * rx_in_tx_decrypt_byp
1371 *		Indicates that RX packet is not decrypted as Crypto is
1372 *		busy with TX packet processing.
1373 *
1374 * overflow_err
1375 *		RXPCU Receive FIFO ran out of space to receive the full MPDU.
1376 *		Therefore this MPDU is terminated early and is thus corrupted.
1377 *
1378 *		This MPDU will not be ACKed.
1379 *
1380 *		RXPCU might still be able to correctly receive the following
1381 *		MPDUs in the PPDU if enough fifo space became available in time.
1382 *
1383 * mpdu_length_err
1384 *		Set by RXPCU if the expected MPDU length does not correspond
1385 *		with the actually received number of bytes in the MPDU.
1386 *
1387 * tkip_mic_err
1388 *		Set by Rx crypto when crypto detected a TKIP MIC error for
1389 *		this MPDU.
1390 *
1391 * decrypt_err
1392 *		Set by RX CRYPTO when CRYPTO detected a decrypt error for this
1393 *		MPDU or CRYPTO received an encrypted frame, but did not get a
1394 *		valid corresponding key id in the peer entry.
1395 *
1396 * unencrypted_frame_err
1397 *		Set by RX CRYPTO when CRYPTO detected an unencrypted frame while
1398 *		in the peer entry field 'All_frames_shall_be_encrypted' is set.
1399 *
1400 * pn_fields_contain_valid_info
1401 *		Set by RX CRYPTO to indicate that there is a valid PN field
1402 *		present in this MPDU.
1403 *
1404 * fcs_err
1405 *		Set by RXPCU when there is an FCS error detected for this MPDU.
1406 *
1407 * msdu_length_err
1408 *		Set by RXOLE when there is an msdu length error detected
1409 *		in at least 1 of the MSDUs embedded within the MPDU.
1410 *
1411 * rxdma0_destination_ring
1412 * rxdma1_destination_ring
1413 *		The ring to which RXDMA0/1 shall push the frame, assuming
1414 *		no MPDU level errors are detected. In case of MPDU level
1415 *		errors, RXDMA0/1 might change the RXDMA0/1 destination. Values
1416 *		are defined in %enum RX_MPDU_END_RXDMA_DEST_RING_*.
1417 *
1418 * decrypt_status_code
1419 *		Field provides insight into the decryption performed. Values
1420 *		are defined in enum %RX_DESC_DECRYPT_STATUS_CODE_*.
1421 *
1422 * rx_bitmap_not_updated
1423 *		Frame is received, but RXPCU could not update the receive bitmap
1424 *		due to (temporary) fifo constraints.
1425 */
1426
1427/* Padding bytes to avoid TLV's spanning across 128 byte boundary */
1428#define HAL_RX_DESC_PADDING0_BYTES	4
1429#define HAL_RX_DESC_PADDING1_BYTES	16
1430
1431#define HAL_RX_DESC_HDR_STATUS_LEN	120
1432
1433struct hal_rx_desc_ipq8074 {
1434	__le32 msdu_end_tag;
1435	struct rx_msdu_end_ipq8074 msdu_end;
1436	__le32 rx_attn_tag;
1437	struct rx_attention attention;
1438	__le32 msdu_start_tag;
1439	struct rx_msdu_start_ipq8074 msdu_start;
1440	u8 rx_padding0[HAL_RX_DESC_PADDING0_BYTES];
1441	__le32 mpdu_start_tag;
1442	struct rx_mpdu_start_ipq8074 mpdu_start;
1443	__le32 mpdu_end_tag;
1444	struct rx_mpdu_end mpdu_end;
1445	u8 rx_padding1[HAL_RX_DESC_PADDING1_BYTES];
1446	__le32 hdr_status_tag;
1447	__le32 phy_ppdu_id;
1448	u8 hdr_status[HAL_RX_DESC_HDR_STATUS_LEN];
1449	u8 msdu_payload[];
1450} __packed;
1451
1452struct hal_rx_desc_qcn9074 {
1453	__le32 msdu_end_tag;
1454	struct rx_msdu_end_qcn9074 msdu_end;
1455	__le32 rx_attn_tag;
1456	struct rx_attention attention;
1457	__le32 msdu_start_tag;
1458	struct rx_msdu_start_qcn9074 msdu_start;
1459	u8 rx_padding0[HAL_RX_DESC_PADDING0_BYTES];
1460	__le32 mpdu_start_tag;
1461	struct rx_mpdu_start_qcn9074 mpdu_start;
1462	__le32 mpdu_end_tag;
1463	struct rx_mpdu_end mpdu_end;
1464	u8 rx_padding1[HAL_RX_DESC_PADDING1_BYTES];
1465	__le32 hdr_status_tag;
1466	__le32 phy_ppdu_id;
1467	u8 hdr_status[HAL_RX_DESC_HDR_STATUS_LEN];
1468	u8 msdu_payload[];
1469} __packed;
1470
1471struct hal_rx_desc_wcn6855 {
1472	__le32 msdu_end_tag;
1473	struct rx_msdu_end_wcn6855 msdu_end;
1474	__le32 rx_attn_tag;
1475	struct rx_attention attention;
1476	__le32 msdu_start_tag;
1477	struct rx_msdu_start_wcn6855 msdu_start;
1478	u8 rx_padding0[HAL_RX_DESC_PADDING0_BYTES];
1479	__le32 mpdu_start_tag;
1480	struct rx_mpdu_start_wcn6855 mpdu_start;
1481	__le32 mpdu_end_tag;
1482	struct rx_mpdu_end mpdu_end;
1483	u8 rx_padding1[HAL_RX_DESC_PADDING1_BYTES];
1484	__le32 hdr_status_tag;
1485	__le32 phy_ppdu_id;
1486	u8 hdr_status[HAL_RX_DESC_HDR_STATUS_LEN];
1487	u8 msdu_payload[];
1488} __packed;
1489
1490struct hal_rx_desc {
1491	union {
1492		struct hal_rx_desc_ipq8074 ipq8074;
1493		struct hal_rx_desc_qcn9074 qcn9074;
1494		struct hal_rx_desc_wcn6855 wcn6855;
1495	} u;
1496} __packed;
1497
1498#define HAL_RX_RU_ALLOC_TYPE_MAX 6
1499#define RU_26  1
1500#define RU_52  2
1501#define RU_106 4
1502#define RU_242 9
1503#define RU_484 18
1504#define RU_996 37
1505
1506#endif /* ATH11K_RX_DESC_H */