mhi.c

  1// SPDX-License-Identifier: BSD-3-Clause-Clear
  2/*
  3 * Copyright (c) 2020 The Linux Foundation. All rights reserved.
  4 * Copyright (c) 2021-2025 Qualcomm Innovation Center, Inc. All rights reserved.
  5 */
  6
  7#include <linux/msi.h>
  8#include <linux/pci.h>
  9#include <linux/firmware.h>
 10#include <linux/of.h>
 11#include <linux/of_address.h>
 12#include <linux/ioport.h>
 13
 14#include "core.h"
 15#include "debug.h"
 16#include "mhi.h"
 17#include "pci.h"
 18#include "pcic.h"
 19
 20#define MHI_TIMEOUT_DEFAULT_MS	20000
 21#define RDDM_DUMP_SIZE	0x420000
 22#define MHI_CB_INVALID	0xff
 23
 24static const struct mhi_channel_config ath11k_mhi_channels_qca6390[] = {
 25	{
 26		.num = 20,
 27		.name = "IPCR",
 28		.num_elements = 64,
 29		.event_ring = 1,
 30		.dir = DMA_TO_DEVICE,
 31		.ee_mask = 0x4,
 32		.pollcfg = 0,
 33		.doorbell = MHI_DB_BRST_DISABLE,
 34		.lpm_notify = false,
 35		.offload_channel = false,
 36		.doorbell_mode_switch = false,
 37	},
 38	{
 39		.num = 21,
 40		.name = "IPCR",
 41		.num_elements = 64,
 42		.event_ring = 1,
 43		.dir = DMA_FROM_DEVICE,
 44		.ee_mask = 0x4,
 45		.pollcfg = 0,
 46		.doorbell = MHI_DB_BRST_DISABLE,
 47		.lpm_notify = false,
 48		.offload_channel = false,
 49		.doorbell_mode_switch = false,
 50	},
 51};
 52
 53static struct mhi_event_config ath11k_mhi_events_qca6390[] = {
 54	{
 55		.num_elements = 32,
 56		.irq_moderation_ms = 0,
 57		.irq = 1,
 58		.mode = MHI_DB_BRST_DISABLE,
 59		.data_type = MHI_ER_CTRL,
 60		.hardware_event = false,
 61		.client_managed = false,
 62		.offload_channel = false,
 63	},
 64	{
 65		.num_elements = 256,
 66		.irq_moderation_ms = 1,
 67		.irq = 2,
 68		.mode = MHI_DB_BRST_DISABLE,
 69		.priority = 1,
 70		.hardware_event = false,
 71		.client_managed = false,
 72		.offload_channel = false,
 73	},
 74};
 75
 76static const struct mhi_controller_config ath11k_mhi_config_qca6390 = {
 77	.max_channels = 128,
 78	.timeout_ms = 2000,
 79	.use_bounce_buf = false,
 80	.buf_len = 8192,
 81	.num_channels = ARRAY_SIZE(ath11k_mhi_channels_qca6390),
 82	.ch_cfg = ath11k_mhi_channels_qca6390,
 83	.num_events = ARRAY_SIZE(ath11k_mhi_events_qca6390),
 84	.event_cfg = ath11k_mhi_events_qca6390,
 85};
 86
 87static const struct mhi_channel_config ath11k_mhi_channels_qcn9074[] = {
 88	{
 89		.num = 20,
 90		.name = "IPCR",
 91		.num_elements = 32,
 92		.event_ring = 1,
 93		.dir = DMA_TO_DEVICE,
 94		.ee_mask = 0x14,
 95		.pollcfg = 0,
 96		.doorbell = MHI_DB_BRST_DISABLE,
 97		.lpm_notify = false,
 98		.offload_channel = false,
 99		.doorbell_mode_switch = false,
100	},
101	{
102		.num = 21,
103		.name = "IPCR",
104		.num_elements = 32,
105		.event_ring = 1,
106		.dir = DMA_FROM_DEVICE,
107		.ee_mask = 0x14,
108		.pollcfg = 0,
109		.doorbell = MHI_DB_BRST_DISABLE,
110		.lpm_notify = false,
111		.offload_channel = false,
112		.doorbell_mode_switch = false,
113	},
114};
115
116static struct mhi_event_config ath11k_mhi_events_qcn9074[] = {
117	{
118		.num_elements = 32,
119		.irq_moderation_ms = 0,
120		.irq = 1,
121		.data_type = MHI_ER_CTRL,
122		.mode = MHI_DB_BRST_DISABLE,
123		.hardware_event = false,
124		.client_managed = false,
125		.offload_channel = false,
126	},
127	{
128		.num_elements = 256,
129		.irq_moderation_ms = 1,
130		.irq = 2,
131		.mode = MHI_DB_BRST_DISABLE,
132		.priority = 1,
133		.hardware_event = false,
134		.client_managed = false,
135		.offload_channel = false,
136	},
137};
138
139static const struct mhi_controller_config ath11k_mhi_config_qcn9074 = {
140	.max_channels = 30,
141	.timeout_ms = 10000,
142	.use_bounce_buf = false,
143	.buf_len = 0,
144	.num_channels = ARRAY_SIZE(ath11k_mhi_channels_qcn9074),
145	.ch_cfg = ath11k_mhi_channels_qcn9074,
146	.num_events = ARRAY_SIZE(ath11k_mhi_events_qcn9074),
147	.event_cfg = ath11k_mhi_events_qcn9074,
148};
149
150void ath11k_mhi_set_mhictrl_reset(struct ath11k_base *ab)
151{
152	u32 val;
153
154	val = ath11k_pcic_read32(ab, MHISTATUS);
155
156	ath11k_dbg(ab, ATH11K_DBG_PCI, "mhistatus 0x%x\n", val);
157
158	/* After SOC_GLOBAL_RESET, MHISTATUS may still have SYSERR bit set
159	 * and thus need to set MHICTRL_RESET to clear SYSERR.
160	 */
161	ath11k_pcic_write32(ab, MHICTRL, MHICTRL_RESET_MASK);
162
163	mdelay(10);
164}
165
166static void ath11k_mhi_reset_txvecdb(struct ath11k_base *ab)
167{
168	ath11k_pcic_write32(ab, PCIE_TXVECDB, 0);
169}
170
171static void ath11k_mhi_reset_txvecstatus(struct ath11k_base *ab)
172{
173	ath11k_pcic_write32(ab, PCIE_TXVECSTATUS, 0);
174}
175
176static void ath11k_mhi_reset_rxvecdb(struct ath11k_base *ab)
177{
178	ath11k_pcic_write32(ab, PCIE_RXVECDB, 0);
179}
180
181static void ath11k_mhi_reset_rxvecstatus(struct ath11k_base *ab)
182{
183	ath11k_pcic_write32(ab, PCIE_RXVECSTATUS, 0);
184}
185
186void ath11k_mhi_clear_vector(struct ath11k_base *ab)
187{
188	ath11k_mhi_reset_txvecdb(ab);
189	ath11k_mhi_reset_txvecstatus(ab);
190	ath11k_mhi_reset_rxvecdb(ab);
191	ath11k_mhi_reset_rxvecstatus(ab);
192}
193
194static int ath11k_mhi_get_msi(struct ath11k_pci *ab_pci)
195{
196	struct ath11k_base *ab = ab_pci->ab;
197	u32 user_base_data, base_vector;
198	int ret, num_vectors, i;
199	int *irq;
200	unsigned int msi_data;
201
202	ret = ath11k_pcic_get_user_msi_assignment(ab, "MHI", &num_vectors,
203						  &user_base_data, &base_vector);
204	if (ret)
205		return ret;
206
207	ath11k_dbg(ab, ATH11K_DBG_PCI, "num_vectors %d base_vector %d\n",
208		   num_vectors, base_vector);
209
210	irq = kcalloc(num_vectors, sizeof(int), GFP_KERNEL);
211	if (!irq)
212		return -ENOMEM;
213
214	for (i = 0; i < num_vectors; i++) {
215		msi_data = base_vector;
216
217		if (test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
218			msi_data += i;
219
220		irq[i] = ath11k_pci_get_msi_irq(ab, msi_data);
221	}
222
223	ab_pci->mhi_ctrl->irq = irq;
224	ab_pci->mhi_ctrl->nr_irqs = num_vectors;
225
226	return 0;
227}
228
229static int ath11k_mhi_op_runtime_get(struct mhi_controller *mhi_cntrl)
230{
231	return 0;
232}
233
234static void ath11k_mhi_op_runtime_put(struct mhi_controller *mhi_cntrl)
235{
236}
237
238static char *ath11k_mhi_op_callback_to_str(enum mhi_callback reason)
239{
240	switch (reason) {
241	case MHI_CB_IDLE:
242		return "MHI_CB_IDLE";
243	case MHI_CB_PENDING_DATA:
244		return "MHI_CB_PENDING_DATA";
245	case MHI_CB_LPM_ENTER:
246		return "MHI_CB_LPM_ENTER";
247	case MHI_CB_LPM_EXIT:
248		return "MHI_CB_LPM_EXIT";
249	case MHI_CB_EE_RDDM:
250		return "MHI_CB_EE_RDDM";
251	case MHI_CB_EE_MISSION_MODE:
252		return "MHI_CB_EE_MISSION_MODE";
253	case MHI_CB_SYS_ERROR:
254		return "MHI_CB_SYS_ERROR";
255	case MHI_CB_FATAL_ERROR:
256		return "MHI_CB_FATAL_ERROR";
257	case MHI_CB_BW_REQ:
258		return "MHI_CB_BW_REQ";
259	default:
260		return "UNKNOWN";
261	}
262};
263
264static void ath11k_mhi_op_status_cb(struct mhi_controller *mhi_cntrl,
265				    enum mhi_callback cb)
266{
267	struct ath11k_base *ab = dev_get_drvdata(mhi_cntrl->cntrl_dev);
268	struct ath11k_pci *ab_pci = ath11k_pci_priv(ab);
269
270	ath11k_dbg(ab, ATH11K_DBG_BOOT, "notify status reason %s\n",
271		   ath11k_mhi_op_callback_to_str(cb));
272
273	switch (cb) {
274	case MHI_CB_SYS_ERROR:
275		ath11k_warn(ab, "firmware crashed: MHI_CB_SYS_ERROR\n");
276		break;
277	case MHI_CB_EE_RDDM:
278		ath11k_warn(ab, "firmware crashed: MHI_CB_EE_RDDM\n");
279		if (ab_pci->mhi_pre_cb == MHI_CB_EE_RDDM) {
280			ath11k_dbg(ab, ATH11K_DBG_BOOT,
281				   "do not queue again for consecutive RDDM event\n");
282			break;
283		}
284
285		if (!(test_bit(ATH11K_FLAG_UNREGISTERING, &ab->dev_flags)))
286			queue_work(ab->workqueue_aux, &ab->reset_work);
287
288		break;
289	default:
290		break;
291	}
292
293	ab_pci->mhi_pre_cb = cb;
294}
295
296static int ath11k_mhi_op_read_reg(struct mhi_controller *mhi_cntrl,
297				  void __iomem *addr,
298				  u32 *out)
299{
300	*out = readl(addr);
301
302	return 0;
303}
304
305static void ath11k_mhi_op_write_reg(struct mhi_controller *mhi_cntrl,
306				    void __iomem *addr,
307				    u32 val)
308{
309	writel(val, addr);
310}
311
312static int ath11k_mhi_read_addr_from_dt(struct mhi_controller *mhi_ctrl)
313{
314	struct device_node *np;
315	struct resource res;
316	int ret;
317
318	np = of_find_node_by_type(NULL, "memory");
319	if (!np)
320		return -ENOENT;
321
322	ret = of_address_to_resource(np, 0, &res);
323	of_node_put(np);
324	if (ret)
325		return ret;
326
327	mhi_ctrl->iova_start = res.start + 0x1000000;
328	mhi_ctrl->iova_stop = res.end;
329
330	return 0;
331}
332
333int ath11k_mhi_register(struct ath11k_pci *ab_pci)
334{
335	struct ath11k_base *ab = ab_pci->ab;
336	struct mhi_controller *mhi_ctrl;
337	const struct mhi_controller_config *ath11k_mhi_config;
338	int ret;
339
340	mhi_ctrl = mhi_alloc_controller();
341	if (!mhi_ctrl)
342		return -ENOMEM;
343
344	ab_pci->mhi_ctrl = mhi_ctrl;
345	mhi_ctrl->cntrl_dev = ab->dev;
346	mhi_ctrl->regs = ab->mem;
347	mhi_ctrl->reg_len = ab->mem_len;
348
349	if (ab->fw.amss_data && ab->fw.amss_len > 0) {
350		/* use MHI firmware file from firmware-N.bin */
351		mhi_ctrl->fw_data = ab->fw.amss_data;
352		mhi_ctrl->fw_sz = ab->fw.amss_len;
353	} else {
354		/* use the old separate mhi.bin MHI firmware file */
355		ath11k_core_create_firmware_path(ab, ATH11K_AMSS_FILE,
356						 ab_pci->amss_path,
357						 sizeof(ab_pci->amss_path));
358		mhi_ctrl->fw_image = ab_pci->amss_path;
359	}
360
361	ret = ath11k_mhi_get_msi(ab_pci);
362	if (ret) {
363		ath11k_err(ab, "failed to get msi for mhi\n");
364		goto free_controller;
365	}
366
367	if (!test_bit(ATH11K_FLAG_MULTI_MSI_VECTORS, &ab->dev_flags))
368		mhi_ctrl->irq_flags = IRQF_SHARED | IRQF_NOBALANCING;
369
370	if (test_bit(ATH11K_FLAG_FIXED_MEM_RGN, &ab->dev_flags)) {
371		ret = ath11k_mhi_read_addr_from_dt(mhi_ctrl);
372		if (ret < 0)
373			goto free_controller;
374	} else {
375		mhi_ctrl->iova_start = 0;
376		mhi_ctrl->iova_stop = ab_pci->dma_mask;
377	}
378
379	mhi_ctrl->rddm_size = RDDM_DUMP_SIZE;
380	mhi_ctrl->sbl_size = SZ_512K;
381	mhi_ctrl->seg_len = SZ_512K;
382	mhi_ctrl->fbc_download = true;
383	mhi_ctrl->runtime_get = ath11k_mhi_op_runtime_get;
384	mhi_ctrl->runtime_put = ath11k_mhi_op_runtime_put;
385	mhi_ctrl->status_cb = ath11k_mhi_op_status_cb;
386	mhi_ctrl->read_reg = ath11k_mhi_op_read_reg;
387	mhi_ctrl->write_reg = ath11k_mhi_op_write_reg;
388
389	switch (ab->hw_rev) {
390	case ATH11K_HW_QCN9074_HW10:
391		ath11k_mhi_config = &ath11k_mhi_config_qcn9074;
392		break;
393	case ATH11K_HW_QCA6390_HW20:
394	case ATH11K_HW_WCN6855_HW20:
395	case ATH11K_HW_WCN6855_HW21:
396	case ATH11K_HW_QCA2066_HW21:
397	case ATH11K_HW_QCA6698AQ_HW21:
398		ath11k_mhi_config = &ath11k_mhi_config_qca6390;
399		break;
400	default:
401		ath11k_err(ab, "failed assign mhi_config for unknown hw rev %d\n",
402			   ab->hw_rev);
403		ret = -EINVAL;
404		goto free_controller;
405	}
406
407	ab_pci->mhi_pre_cb = MHI_CB_INVALID;
408	ret = mhi_register_controller(mhi_ctrl, ath11k_mhi_config);
409	if (ret) {
410		ath11k_err(ab, "failed to register to mhi bus, err = %d\n", ret);
411		goto free_controller;
412	}
413
414	return 0;
415
416free_controller:
417	mhi_free_controller(mhi_ctrl);
418	ab_pci->mhi_ctrl = NULL;
419	return ret;
420}
421
422void ath11k_mhi_unregister(struct ath11k_pci *ab_pci)
423{
424	struct mhi_controller *mhi_ctrl = ab_pci->mhi_ctrl;
425
426	mhi_unregister_controller(mhi_ctrl);
427	kfree(mhi_ctrl->irq);
428	mhi_free_controller(mhi_ctrl);
429}
430
431int ath11k_mhi_start(struct ath11k_pci *ab_pci)
432{
433	struct ath11k_base *ab = ab_pci->ab;
434	int ret;
435
436	ab_pci->mhi_ctrl->timeout_ms = MHI_TIMEOUT_DEFAULT_MS;
437
438	ret = mhi_prepare_for_power_up(ab_pci->mhi_ctrl);
439	if (ret) {
440		ath11k_warn(ab, "failed to prepare mhi: %d", ret);
441		return ret;
442	}
443
444	ret = mhi_sync_power_up(ab_pci->mhi_ctrl);
445	if (ret) {
446		ath11k_warn(ab, "failed to power up mhi: %d", ret);
447		return ret;
448	}
449
450	return 0;
451}
452
453void ath11k_mhi_stop(struct ath11k_pci *ab_pci, bool is_suspend)
454{
455	/* During suspend we need to use mhi_power_down_keep_dev()
456	 * workaround, otherwise ath11k_core_resume() will timeout
457	 * during resume.
458	 */
459	if (is_suspend)
460		mhi_power_down_keep_dev(ab_pci->mhi_ctrl, true);
461	else
462		mhi_power_down(ab_pci->mhi_ctrl, true);
463
464	mhi_unprepare_after_power_down(ab_pci->mhi_ctrl);
465}
466
467int ath11k_mhi_suspend(struct ath11k_pci *ab_pci)
468{
469	struct ath11k_base *ab = ab_pci->ab;
470	int ret;
471
472	ret = mhi_pm_suspend(ab_pci->mhi_ctrl);
473	if (ret) {
474		ath11k_warn(ab, "failed to suspend mhi: %d", ret);
475		return ret;
476	}
477
478	return 0;
479}
480
481int ath11k_mhi_resume(struct ath11k_pci *ab_pci)
482{
483	struct ath11k_base *ab = ab_pci->ab;
484	int ret;
485
486	/* Do force MHI resume as some devices like QCA6390, WCN6855
487	 * are not in M3 state but they are functional. So just ignore
488	 * the MHI state while resuming.
489	 */
490	ret = mhi_pm_resume_force(ab_pci->mhi_ctrl);
491	if (ret) {
492		ath11k_warn(ab, "failed to resume mhi: %d", ret);
493		return ret;
494	}
495
496	return 0;
497}
498
499void ath11k_mhi_coredump(struct mhi_controller *mhi_ctrl, bool in_panic)
500{
501	mhi_download_rddm_image(mhi_ctrl, in_panic);
502}