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dp.h
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linux-6.19.14/drivers/net/wireless/ath/ath11k/dp.h
1/* SPDX-License-Identifier: BSD-3-Clause-Clear */ 2/* 3 * Copyright (c) 2018-2019 The Linux Foundation. All rights reserved. 4 * Copyright (c) 2021-2023, 2025 Qualcomm Innovation Center, Inc. All rights reserved. 5 */ 6 7#ifndef ATH11K_DP_H 8#define ATH11K_DP_H 9 10#include "hal_rx.h" 11 12#define MAX_RXDMA_PER_PDEV 2 13 14struct ath11k_base; 15struct ath11k_peer; 16struct ath11k_dp; 17struct ath11k_vif; 18struct hal_tcl_status_ring; 19struct ath11k_ext_irq_grp; 20 21struct dp_rx_tid { 22 u8 tid; 23 dma_addr_t paddr; 24 u32 size; 25 u32 ba_win_sz; 26 bool active; 27 28 /* Info related to rx fragments */ 29 u32 cur_sn; 30 u16 last_frag_no; 31 u16 rx_frag_bitmap; 32 33 struct sk_buff_head rx_frags; 34 struct hal_reo_dest_ring *dst_ring_desc; 35 36 /* Timer info related to fragments */ 37 struct timer_list frag_timer; 38 struct ath11k_base *ab; 39 u32 *vaddr_unaligned; 40 dma_addr_t paddr_unaligned; 41 u32 unaligned_size; 42}; 43 44#define DP_REO_DESC_FREE_THRESHOLD 64 45#define DP_REO_DESC_FREE_TIMEOUT_MS 1000 46#define DP_MON_PURGE_TIMEOUT_MS 100 47#define DP_MON_SERVICE_BUDGET 128 48 49struct dp_reo_cache_flush_elem { 50 struct list_head list; 51 struct dp_rx_tid data; 52 unsigned long ts; 53}; 54 55struct dp_reo_cmd { 56 struct list_head list; 57 struct dp_rx_tid data; 58 int cmd_num; 59 void (*handler)(struct ath11k_dp *, void *, 60 enum hal_reo_cmd_status status); 61}; 62 63struct dp_srng { 64 u32 *vaddr_unaligned; 65 u32 *vaddr; 66 dma_addr_t paddr_unaligned; 67 dma_addr_t paddr; 68 int size; 69 u32 ring_id; 70 u8 cached; 71}; 72 73struct dp_rxdma_ring { 74 struct dp_srng refill_buf_ring; 75 struct idr bufs_idr; 76 /* Protects bufs_idr */ 77 spinlock_t idr_lock; 78 int bufs_max; 79}; 80 81#define ATH11K_TX_COMPL_NEXT(x) (((x) + 1) % DP_TX_COMP_RING_SIZE) 82 83struct dp_tx_ring { 84 u8 tcl_data_ring_id; 85 struct dp_srng tcl_data_ring; 86 struct dp_srng tcl_comp_ring; 87 struct idr txbuf_idr; 88 /* Protects txbuf_idr and num_pending */ 89 spinlock_t tx_idr_lock; 90 struct hal_wbm_release_ring *tx_status; 91 int tx_status_head; 92 int tx_status_tail; 93}; 94 95enum dp_mon_status_buf_state { 96 /* PPDU id matches in dst ring and status ring */ 97 DP_MON_STATUS_MATCH, 98 /* status ring dma is not done */ 99 DP_MON_STATUS_NO_DMA, 100 /* status ring is lagging, reap status ring */ 101 DP_MON_STATUS_LAG, 102 /* status ring is leading, reap dst ring and drop */ 103 DP_MON_STATUS_LEAD, 104 /* replinish monitor status ring */ 105 DP_MON_STATUS_REPLINISH, 106}; 107 108struct ath11k_pdev_mon_stats { 109 u32 status_ppdu_state; 110 u32 status_ppdu_start; 111 u32 status_ppdu_end; 112 u32 status_ppdu_compl; 113 u32 status_ppdu_start_mis; 114 u32 status_ppdu_end_mis; 115 u32 status_ppdu_done; 116 u32 dest_ppdu_done; 117 u32 dest_mpdu_done; 118 u32 dest_mpdu_drop; 119 u32 dup_mon_linkdesc_cnt; 120 u32 dup_mon_buf_cnt; 121 u32 dest_mon_stuck; 122 u32 dest_mon_not_reaped; 123}; 124 125struct dp_full_mon_mpdu { 126 struct list_head list; 127 struct sk_buff *head; 128 struct sk_buff *tail; 129}; 130 131struct dp_link_desc_bank { 132 void *vaddr_unaligned; 133 void *vaddr; 134 dma_addr_t paddr_unaligned; 135 dma_addr_t paddr; 136 u32 size; 137}; 138 139/* Size to enforce scatter idle list mode */ 140#define DP_LINK_DESC_ALLOC_SIZE_THRESH 0x200000 141#define DP_LINK_DESC_BANKS_MAX 8 142 143#define DP_RX_DESC_COOKIE_INDEX_MAX 0x3ffff 144#define DP_RX_DESC_COOKIE_POOL_ID_MAX 0x1c0000 145#define DP_RX_DESC_COOKIE_MAX \ 146 (DP_RX_DESC_COOKIE_INDEX_MAX | DP_RX_DESC_COOKIE_POOL_ID_MAX) 147#define DP_NOT_PPDU_ID_WRAP_AROUND 20000 148 149enum ath11k_dp_ppdu_state { 150 DP_PPDU_STATUS_START, 151 DP_PPDU_STATUS_DONE, 152}; 153 154struct ath11k_mon_data { 155 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 156 struct hal_rx_mon_ppdu_info mon_ppdu_info; 157 158 u32 mon_ppdu_status; 159 u32 mon_last_buf_cookie; 160 u64 mon_last_linkdesc_paddr; 161 u16 chan_noise_floor; 162 bool hold_mon_dst_ring; 163 enum dp_mon_status_buf_state buf_state; 164 dma_addr_t mon_status_paddr; 165 struct dp_full_mon_mpdu *mon_mpdu; 166 struct hal_sw_mon_ring_entries sw_mon_entries; 167 struct ath11k_pdev_mon_stats rx_mon_stats; 168 /* lock for monitor data */ 169 spinlock_t mon_lock; 170}; 171 172struct ath11k_pdev_dp { 173 u32 mac_id; 174 u32 mon_dest_ring_stuck_cnt; 175 atomic_t num_tx_pending; 176 wait_queue_head_t tx_empty_waitq; 177 struct dp_rxdma_ring rx_refill_buf_ring; 178 struct dp_srng rx_mac_buf_ring[MAX_RXDMA_PER_PDEV]; 179 struct dp_srng rxdma_err_dst_ring[MAX_RXDMA_PER_PDEV]; 180 struct dp_srng rxdma_mon_dst_ring; 181 struct dp_srng rxdma_mon_desc_ring; 182 183 struct dp_rxdma_ring rxdma_mon_buf_ring; 184 struct dp_rxdma_ring rx_mon_status_refill_ring[MAX_RXDMA_PER_PDEV]; 185 struct ieee80211_rx_status rx_status; 186 struct ath11k_mon_data mon_data; 187}; 188 189#define DP_NUM_CLIENTS_MAX 64 190#define DP_AVG_TIDS_PER_CLIENT 2 191#define DP_NUM_TIDS_MAX (DP_NUM_CLIENTS_MAX * DP_AVG_TIDS_PER_CLIENT) 192#define DP_AVG_MSDUS_PER_FLOW 128 193#define DP_AVG_FLOWS_PER_TID 2 194#define DP_AVG_MPDUS_PER_TID_MAX 128 195#define DP_AVG_MSDUS_PER_MPDU 4 196 197#define DP_RX_HASH_ENABLE 1 /* Enable hash based Rx steering */ 198 199#define DP_BA_WIN_SZ_MAX 256 200 201#define DP_TCL_NUM_RING_MAX 3 202#define DP_TCL_NUM_RING_MAX_QCA6390 1 203 204#define DP_IDLE_SCATTER_BUFS_MAX 16 205 206#define DP_WBM_RELEASE_RING_SIZE 64 207#define DP_TCL_DATA_RING_SIZE 512 208#define DP_TCL_DATA_RING_SIZE_WCN6750 2048 209#define DP_TX_COMP_RING_SIZE 32768 210#define DP_TX_IDR_SIZE DP_TX_COMP_RING_SIZE 211#define DP_TCL_CMD_RING_SIZE 32 212#define DP_TCL_STATUS_RING_SIZE 32 213#define DP_REO_DST_RING_MAX 4 214#define DP_REO_DST_RING_SIZE 2048 215#define DP_REO_REINJECT_RING_SIZE 32 216#define DP_RX_RELEASE_RING_SIZE 1024 217#define DP_REO_EXCEPTION_RING_SIZE 128 218#define DP_REO_CMD_RING_SIZE 256 219#define DP_REO_STATUS_RING_SIZE 2048 220#define DP_RXDMA_BUF_RING_SIZE 4096 221#define DP_RXDMA_REFILL_RING_SIZE 2048 222#define DP_RXDMA_ERR_DST_RING_SIZE 1024 223#define DP_RXDMA_MON_STATUS_RING_SIZE 1024 224#define DP_RXDMA_MONITOR_BUF_RING_SIZE 4096 225#define DP_RXDMA_MONITOR_DST_RING_SIZE 2048 226#define DP_RXDMA_MONITOR_DESC_RING_SIZE 4096 227 228#define DP_RX_RELEASE_RING_NUM 3 229 230#define DP_RX_BUFFER_SIZE 2048 231#define DP_RX_BUFFER_SIZE_LITE 1024 232#define DP_RX_BUFFER_ALIGN_SIZE 128 233 234#define DP_RXDMA_BUF_COOKIE_BUF_ID GENMASK(17, 0) 235#define DP_RXDMA_BUF_COOKIE_PDEV_ID GENMASK(20, 18) 236 237#define DP_HW2SW_MACID(mac_id) ((mac_id) ? ((mac_id) - 1) : 0) 238#define DP_SW2HW_MACID(mac_id) ((mac_id) + 1) 239 240#define DP_TX_DESC_ID_MAC_ID GENMASK(1, 0) 241#define DP_TX_DESC_ID_MSDU_ID GENMASK(18, 2) 242#define DP_TX_DESC_ID_POOL_ID GENMASK(20, 19) 243 244#define ATH11K_SHADOW_DP_TIMER_INTERVAL 20 245#define ATH11K_SHADOW_CTRL_TIMER_INTERVAL 10 246 247struct ath11k_hp_update_timer { 248 struct timer_list timer; 249 bool started; 250 bool init; 251 u32 tx_num; 252 u32 timer_tx_num; 253 u32 ring_id; 254 u32 interval; 255 struct ath11k_base *ab; 256}; 257 258struct ath11k_dp { 259 struct ath11k_base *ab; 260 enum ath11k_htc_ep_id eid; 261 struct completion htt_tgt_version_received; 262 u8 htt_tgt_ver_major; 263 u8 htt_tgt_ver_minor; 264 struct dp_link_desc_bank link_desc_banks[DP_LINK_DESC_BANKS_MAX]; 265 struct dp_srng wbm_idle_ring; 266 struct dp_srng wbm_desc_rel_ring; 267 struct dp_srng tcl_cmd_ring; 268 struct dp_srng tcl_status_ring; 269 struct dp_srng reo_reinject_ring; 270 struct dp_srng rx_rel_ring; 271 struct dp_srng reo_except_ring; 272 struct dp_srng reo_cmd_ring; 273 struct dp_srng reo_status_ring; 274 struct dp_srng reo_dst_ring[DP_REO_DST_RING_MAX]; 275 struct dp_tx_ring tx_ring[DP_TCL_NUM_RING_MAX]; 276 struct hal_wbm_idle_scatter_list scatter_list[DP_IDLE_SCATTER_BUFS_MAX]; 277 struct list_head reo_cmd_list; 278 struct list_head reo_cmd_cache_flush_list; 279 struct list_head dp_full_mon_mpdu_list; 280 u32 reo_cmd_cache_flush_count; 281 /** 282 * protects access to below fields, 283 * - reo_cmd_list 284 * - reo_cmd_cache_flush_list 285 * - reo_cmd_cache_flush_count 286 */ 287 spinlock_t reo_cmd_lock; 288 struct ath11k_hp_update_timer reo_cmd_timer; 289 struct ath11k_hp_update_timer tx_ring_timer[DP_TCL_NUM_RING_MAX]; 290}; 291 292/* HTT definitions */ 293 294#define HTT_TCL_META_DATA_TYPE BIT(0) 295#define HTT_TCL_META_DATA_VALID_HTT BIT(1) 296 297/* vdev meta data */ 298#define HTT_TCL_META_DATA_VDEV_ID GENMASK(9, 2) 299#define HTT_TCL_META_DATA_PDEV_ID GENMASK(11, 10) 300#define HTT_TCL_META_DATA_HOST_INSPECTED BIT(12) 301 302/* peer meta data */ 303#define HTT_TCL_META_DATA_PEER_ID GENMASK(15, 2) 304 305#define HTT_TX_WBM_COMP_STATUS_OFFSET 8 306 307#define HTT_INVALID_PEER_ID 0xffff 308 309/* HTT tx completion is overlaid in wbm_release_ring */ 310#define HTT_TX_WBM_COMP_INFO0_STATUS GENMASK(12, 9) 311#define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13) 312#define HTT_TX_WBM_COMP_INFO0_REINJECT_REASON GENMASK(16, 13) 313 314#define HTT_TX_WBM_COMP_INFO1_ACK_RSSI GENMASK(31, 24) 315#define HTT_TX_WBM_COMP_INFO2_SW_PEER_ID GENMASK(15, 0) 316#define HTT_TX_WBM_COMP_INFO2_VALID BIT(21) 317 318struct htt_tx_wbm_completion { 319 u32 info0; 320 u32 info1; 321 u32 info2; 322 u32 info3; 323} __packed; 324 325enum htt_h2t_msg_type { 326 HTT_H2T_MSG_TYPE_VERSION_REQ = 0, 327 HTT_H2T_MSG_TYPE_SRING_SETUP = 0xb, 328 HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG = 0xc, 329 HTT_H2T_MSG_TYPE_EXT_STATS_CFG = 0x10, 330 HTT_H2T_MSG_TYPE_PPDU_STATS_CFG = 0x11, 331 HTT_H2T_MSG_TYPE_RX_FULL_MONITOR_MODE = 0x17, 332}; 333 334#define HTT_VER_REQ_INFO_MSG_ID GENMASK(7, 0) 335 336struct htt_ver_req_cmd { 337 u32 ver_reg_info; 338} __packed; 339 340enum htt_srng_ring_type { 341 HTT_HW_TO_SW_RING, 342 HTT_SW_TO_HW_RING, 343 HTT_SW_TO_SW_RING, 344}; 345 346enum htt_srng_ring_id { 347 HTT_RXDMA_HOST_BUF_RING, 348 HTT_RXDMA_MONITOR_STATUS_RING, 349 HTT_RXDMA_MONITOR_BUF_RING, 350 HTT_RXDMA_MONITOR_DESC_RING, 351 HTT_RXDMA_MONITOR_DEST_RING, 352 HTT_HOST1_TO_FW_RXBUF_RING, 353 HTT_HOST2_TO_FW_RXBUF_RING, 354 HTT_RXDMA_NON_MONITOR_DEST_RING, 355}; 356 357/* host -> target HTT_SRING_SETUP message 358 * 359 * After target is booted up, Host can send SRING setup message for 360 * each host facing LMAC SRING. Target setups up HW registers based 361 * on setup message and confirms back to Host if response_required is set. 362 * Host should wait for confirmation message before sending new SRING 363 * setup message 364 * 365 * The message would appear as follows: 366 * 367 * |31 24|23 20|19|18 16|15|14 8|7 0| 368 * |--------------- +-----------------+----------------+------------------| 369 * | ring_type | ring_id | pdev_id | msg_type | 370 * |----------------------------------------------------------------------| 371 * | ring_base_addr_lo | 372 * |----------------------------------------------------------------------| 373 * | ring_base_addr_hi | 374 * |----------------------------------------------------------------------| 375 * |ring_misc_cfg_flag|ring_entry_size| ring_size | 376 * |----------------------------------------------------------------------| 377 * | ring_head_offset32_remote_addr_lo | 378 * |----------------------------------------------------------------------| 379 * | ring_head_offset32_remote_addr_hi | 380 * |----------------------------------------------------------------------| 381 * | ring_tail_offset32_remote_addr_lo | 382 * |----------------------------------------------------------------------| 383 * | ring_tail_offset32_remote_addr_hi | 384 * |----------------------------------------------------------------------| 385 * | ring_msi_addr_lo | 386 * |----------------------------------------------------------------------| 387 * | ring_msi_addr_hi | 388 * |----------------------------------------------------------------------| 389 * | ring_msi_data | 390 * |----------------------------------------------------------------------| 391 * | intr_timer_th |IM| intr_batch_counter_th | 392 * |----------------------------------------------------------------------| 393 * | reserved |RR|PTCF| intr_low_threshold | 394 * |----------------------------------------------------------------------| 395 * Where 396 * IM = sw_intr_mode 397 * RR = response_required 398 * PTCF = prefetch_timer_cfg 399 * 400 * The message is interpreted as follows: 401 * dword0 - b'0:7 - msg_type: This will be set to 402 * HTT_H2T_MSG_TYPE_SRING_SETUP 403 * b'8:15 - pdev_id: 404 * 0 (for rings at SOC/UMAC level), 405 * 1/2/3 mac id (for rings at LMAC level) 406 * b'16:23 - ring_id: identify which ring is to setup, 407 * more details can be got from enum htt_srng_ring_id 408 * b'24:31 - ring_type: identify type of host rings, 409 * more details can be got from enum htt_srng_ring_type 410 * dword1 - b'0:31 - ring_base_addr_lo: Lower 32bits of ring base address 411 * dword2 - b'0:31 - ring_base_addr_hi: Upper 32bits of ring base address 412 * dword3 - b'0:15 - ring_size: size of the ring in unit of 4-bytes words 413 * b'16:23 - ring_entry_size: Size of each entry in 4-byte word units 414 * b'24:31 - ring_misc_cfg_flag: Valid only for HW_TO_SW_RING and 415 * SW_TO_HW_RING. 416 * Refer to HTT_SRING_SETUP_RING_MISC_CFG_RING defs. 417 * dword4 - b'0:31 - ring_head_off32_remote_addr_lo: 418 * Lower 32 bits of memory address of the remote variable 419 * storing the 4-byte word offset that identifies the head 420 * element within the ring. 421 * (The head offset variable has type u32.) 422 * Valid for HW_TO_SW and SW_TO_SW rings. 423 * dword5 - b'0:31 - ring_head_off32_remote_addr_hi: 424 * Upper 32 bits of memory address of the remote variable 425 * storing the 4-byte word offset that identifies the head 426 * element within the ring. 427 * (The head offset variable has type u32.) 428 * Valid for HW_TO_SW and SW_TO_SW rings. 429 * dword6 - b'0:31 - ring_tail_off32_remote_addr_lo: 430 * Lower 32 bits of memory address of the remote variable 431 * storing the 4-byte word offset that identifies the tail 432 * element within the ring. 433 * (The tail offset variable has type u32.) 434 * Valid for HW_TO_SW and SW_TO_SW rings. 435 * dword7 - b'0:31 - ring_tail_off32_remote_addr_hi: 436 * Upper 32 bits of memory address of the remote variable 437 * storing the 4-byte word offset that identifies the tail 438 * element within the ring. 439 * (The tail offset variable has type u32.) 440 * Valid for HW_TO_SW and SW_TO_SW rings. 441 * dword8 - b'0:31 - ring_msi_addr_lo: Lower 32bits of MSI cfg address 442 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 443 * dword9 - b'0:31 - ring_msi_addr_hi: Upper 32bits of MSI cfg address 444 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 445 * dword10 - b'0:31 - ring_msi_data: MSI data 446 * Refer to HTT_SRING_SETUP_RING_MSC_CFG_xxx defs 447 * valid only for HW_TO_SW_RING and SW_TO_HW_RING 448 * dword11 - b'0:14 - intr_batch_counter_th: 449 * batch counter threshold is in units of 4-byte words. 450 * HW internally maintains and increments batch count. 451 * (see SRING spec for detail description). 452 * When batch count reaches threshold value, an interrupt 453 * is generated by HW. 454 * b'15 - sw_intr_mode: 455 * This configuration shall be static. 456 * Only programmed at power up. 457 * 0: generate pulse style sw interrupts 458 * 1: generate level style sw interrupts 459 * b'16:31 - intr_timer_th: 460 * The timer init value when timer is idle or is 461 * initialized to start downcounting. 462 * In 8us units (to cover a range of 0 to 524 ms) 463 * dword12 - b'0:15 - intr_low_threshold: 464 * Used only by Consumer ring to generate ring_sw_int_p. 465 * Ring entries low threshold water mark, that is used 466 * in combination with the interrupt timer as well as 467 * the clearing of the level interrupt. 468 * b'16:18 - prefetch_timer_cfg: 469 * Used only by Consumer ring to set timer mode to 470 * support Application prefetch handling. 471 * The external tail offset/pointer will be updated 472 * at following intervals: 473 * 3'b000: (Prefetch feature disabled; used only for debug) 474 * 3'b001: 1 usec 475 * 3'b010: 4 usec 476 * 3'b011: 8 usec (default) 477 * 3'b100: 16 usec 478 * Others: Reserved 479 * b'19 - response_required: 480 * Host needs HTT_T2H_MSG_TYPE_SRING_SETUP_DONE as response 481 * b'20:31 - reserved: reserved for future use 482 */ 483 484#define HTT_SRNG_SETUP_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 485#define HTT_SRNG_SETUP_CMD_INFO0_PDEV_ID GENMASK(15, 8) 486#define HTT_SRNG_SETUP_CMD_INFO0_RING_ID GENMASK(23, 16) 487#define HTT_SRNG_SETUP_CMD_INFO0_RING_TYPE GENMASK(31, 24) 488 489#define HTT_SRNG_SETUP_CMD_INFO1_RING_SIZE GENMASK(15, 0) 490#define HTT_SRNG_SETUP_CMD_INFO1_RING_ENTRY_SIZE GENMASK(23, 16) 491#define HTT_SRNG_SETUP_CMD_INFO1_RING_LOOP_CNT_DIS BIT(25) 492#define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_MSI_SWAP BIT(27) 493#define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_HOST_FW_SWAP BIT(28) 494#define HTT_SRNG_SETUP_CMD_INFO1_RING_FLAGS_TLV_SWAP BIT(29) 495 496#define HTT_SRNG_SETUP_CMD_INTR_INFO_BATCH_COUNTER_THRESH GENMASK(14, 0) 497#define HTT_SRNG_SETUP_CMD_INTR_INFO_SW_INTR_MODE BIT(15) 498#define HTT_SRNG_SETUP_CMD_INTR_INFO_INTR_TIMER_THRESH GENMASK(31, 16) 499 500#define HTT_SRNG_SETUP_CMD_INFO2_INTR_LOW_THRESH GENMASK(15, 0) 501#define HTT_SRNG_SETUP_CMD_INFO2_PRE_FETCH_TIMER_CFG BIT(16) 502#define HTT_SRNG_SETUP_CMD_INFO2_RESPONSE_REQUIRED BIT(19) 503 504struct htt_srng_setup_cmd { 505 u32 info0; 506 u32 ring_base_addr_lo; 507 u32 ring_base_addr_hi; 508 u32 info1; 509 u32 ring_head_off32_remote_addr_lo; 510 u32 ring_head_off32_remote_addr_hi; 511 u32 ring_tail_off32_remote_addr_lo; 512 u32 ring_tail_off32_remote_addr_hi; 513 u32 ring_msi_addr_lo; 514 u32 ring_msi_addr_hi; 515 u32 msi_data; 516 u32 intr_info; 517 u32 info2; 518} __packed; 519 520/* host -> target FW PPDU_STATS config message 521 * 522 * @details 523 * The following field definitions describe the format of the HTT host 524 * to target FW for PPDU_STATS_CFG msg. 525 * The message allows the host to configure the PPDU_STATS_IND messages 526 * produced by the target. 527 * 528 * |31 24|23 16|15 8|7 0| 529 * |-----------------------------------------------------------| 530 * | REQ bit mask | pdev_mask | msg type | 531 * |-----------------------------------------------------------| 532 * Header fields: 533 * - MSG_TYPE 534 * Bits 7:0 535 * Purpose: identifies this is a req to configure ppdu_stats_ind from target 536 * Value: 0x11 537 * - PDEV_MASK 538 * Bits 8:15 539 * Purpose: identifies which pdevs this PPDU stats configuration applies to 540 * Value: This is a overloaded field, refer to usage and interpretation of 541 * PDEV in interface document. 542 * Bit 8 : Reserved for SOC stats 543 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 544 * Indicates MACID_MASK in DBS 545 * - REQ_TLV_BIT_MASK 546 * Bits 16:31 547 * Purpose: each set bit indicates the corresponding PPDU stats TLV type 548 * needs to be included in the target's PPDU_STATS_IND messages. 549 * Value: refer htt_ppdu_stats_tlv_tag_t <<<??? 550 * 551 */ 552 553struct htt_ppdu_stats_cfg_cmd { 554 u32 msg; 555} __packed; 556 557#define HTT_PPDU_STATS_CFG_MSG_TYPE GENMASK(7, 0) 558#define HTT_PPDU_STATS_CFG_SOC_STATS BIT(8) 559#define HTT_PPDU_STATS_CFG_PDEV_ID GENMASK(15, 9) 560#define HTT_PPDU_STATS_CFG_TLV_TYPE_BITMASK GENMASK(31, 16) 561 562enum htt_ppdu_stats_tag_type { 563 HTT_PPDU_STATS_TAG_COMMON, 564 HTT_PPDU_STATS_TAG_USR_COMMON, 565 HTT_PPDU_STATS_TAG_USR_RATE, 566 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64, 567 HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256, 568 HTT_PPDU_STATS_TAG_SCH_CMD_STATUS, 569 HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON, 570 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64, 571 HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256, 572 HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS, 573 HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH, 574 HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY, 575 HTT_PPDU_STATS_TAG_INFO, 576 HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD, 577 578 /* New TLV's are added above to this line */ 579 HTT_PPDU_STATS_TAG_MAX, 580}; 581 582#define HTT_PPDU_STATS_TAG_DEFAULT (BIT(HTT_PPDU_STATS_TAG_COMMON) \ 583 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON) \ 584 | BIT(HTT_PPDU_STATS_TAG_USR_RATE) \ 585 | BIT(HTT_PPDU_STATS_TAG_SCH_CMD_STATUS) \ 586 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_COMMON) \ 587 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_ACK_BA_STATUS) \ 588 | BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_FLUSH) \ 589 | BIT(HTT_PPDU_STATS_TAG_USR_COMMON_ARRAY)) 590 591#define HTT_PPDU_STATS_TAG_PKTLOG (BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_64) | \ 592 BIT(HTT_PPDU_STATS_TAG_USR_MPDU_ENQ_BITMAP_256) | \ 593 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_64) | \ 594 BIT(HTT_PPDU_STATS_TAG_USR_COMPLTN_BA_BITMAP_256) | \ 595 BIT(HTT_PPDU_STATS_TAG_INFO) | \ 596 BIT(HTT_PPDU_STATS_TAG_TX_MGMTCTRL_PAYLOAD) | \ 597 HTT_PPDU_STATS_TAG_DEFAULT) 598 599/* HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG Message 600 * 601 * details: 602 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG message is sent by host to 603 * configure RXDMA rings. 604 * The configuration is per ring based and includes both packet subtypes 605 * and PPDU/MPDU TLVs. 606 * 607 * The message would appear as follows: 608 * 609 * |31 26|25|24|23 16|15 8|7 0| 610 * |-----------------+----------------+----------------+---------------| 611 * | rsvd1 |PS|SS| ring_id | pdev_id | msg_type | 612 * |-------------------------------------------------------------------| 613 * | rsvd2 | ring_buffer_size | 614 * |-------------------------------------------------------------------| 615 * | packet_type_enable_flags_0 | 616 * |-------------------------------------------------------------------| 617 * | packet_type_enable_flags_1 | 618 * |-------------------------------------------------------------------| 619 * | packet_type_enable_flags_2 | 620 * |-------------------------------------------------------------------| 621 * | packet_type_enable_flags_3 | 622 * |-------------------------------------------------------------------| 623 * | tlv_filter_in_flags | 624 * |-------------------------------------------------------------------| 625 * Where: 626 * PS = pkt_swap 627 * SS = status_swap 628 * The message is interpreted as follows: 629 * dword0 - b'0:7 - msg_type: This will be set to 630 * HTT_H2T_MSG_TYPE_RX_RING_SELECTION_CFG 631 * b'8:15 - pdev_id: 632 * 0 (for rings at SOC/UMAC level), 633 * 1/2/3 mac id (for rings at LMAC level) 634 * b'16:23 - ring_id : Identify the ring to configure. 635 * More details can be got from enum htt_srng_ring_id 636 * b'24 - status_swap: 1 is to swap status TLV 637 * b'25 - pkt_swap: 1 is to swap packet TLV 638 * b'26:31 - rsvd1: reserved for future use 639 * dword1 - b'0:16 - ring_buffer_size: size of buffers referenced by rx ring, 640 * in byte units. 641 * Valid only for HW_TO_SW_RING and SW_TO_HW_RING 642 * - b'16:31 - rsvd2: Reserved for future use 643 * dword2 - b'0:31 - packet_type_enable_flags_0: 644 * Enable MGMT packet from 0b0000 to 0b1001 645 * bits from low to high: FP, MD, MO - 3 bits 646 * FP: Filter_Pass 647 * MD: Monitor_Direct 648 * MO: Monitor_Other 649 * 10 mgmt subtypes * 3 bits -> 30 bits 650 * Refer to PKT_TYPE_ENABLE_FLAG0_xxx_MGMT_xxx defs 651 * dword3 - b'0:31 - packet_type_enable_flags_1: 652 * Enable MGMT packet from 0b1010 to 0b1111 653 * bits from low to high: FP, MD, MO - 3 bits 654 * Refer to PKT_TYPE_ENABLE_FLAG1_xxx_MGMT_xxx defs 655 * dword4 - b'0:31 - packet_type_enable_flags_2: 656 * Enable CTRL packet from 0b0000 to 0b1001 657 * bits from low to high: FP, MD, MO - 3 bits 658 * Refer to PKT_TYPE_ENABLE_FLAG2_xxx_CTRL_xxx defs 659 * dword5 - b'0:31 - packet_type_enable_flags_3: 660 * Enable CTRL packet from 0b1010 to 0b1111, 661 * MCAST_DATA, UCAST_DATA, NULL_DATA 662 * bits from low to high: FP, MD, MO - 3 bits 663 * Refer to PKT_TYPE_ENABLE_FLAG3_xxx_CTRL_xxx defs 664 * dword6 - b'0:31 - tlv_filter_in_flags: 665 * Filter in Attention/MPDU/PPDU/Header/User tlvs 666 * Refer to CFG_TLV_FILTER_IN_FLAG defs 667 */ 668 669#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 670#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 671#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_RING_ID GENMASK(23, 16) 672#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_SS BIT(24) 673#define HTT_RX_RING_SELECTION_CFG_CMD_INFO0_PS BIT(25) 674 675#define HTT_RX_RING_SELECTION_CFG_CMD_INFO1_BUF_SIZE GENMASK(15, 0) 676 677enum htt_rx_filter_tlv_flags { 678 HTT_RX_FILTER_TLV_FLAGS_MPDU_START = BIT(0), 679 HTT_RX_FILTER_TLV_FLAGS_MSDU_START = BIT(1), 680 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET = BIT(2), 681 HTT_RX_FILTER_TLV_FLAGS_MSDU_END = BIT(3), 682 HTT_RX_FILTER_TLV_FLAGS_MPDU_END = BIT(4), 683 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER = BIT(5), 684 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER = BIT(6), 685 HTT_RX_FILTER_TLV_FLAGS_ATTENTION = BIT(7), 686 HTT_RX_FILTER_TLV_FLAGS_PPDU_START = BIT(8), 687 HTT_RX_FILTER_TLV_FLAGS_PPDU_END = BIT(9), 688 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS = BIT(10), 689 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT = BIT(11), 690 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE = BIT(12), 691}; 692 693enum htt_rx_mgmt_pkt_filter_tlv_flags0 { 694 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(0), 695 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(1), 696 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ = BIT(2), 697 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(3), 698 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(4), 699 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP = BIT(5), 700 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(6), 701 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(7), 702 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ = BIT(8), 703 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(9), 704 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(10), 705 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP = BIT(11), 706 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(12), 707 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(13), 708 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ = BIT(14), 709 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(15), 710 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(16), 711 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP = BIT(17), 712 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(18), 713 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(19), 714 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV = BIT(20), 715 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(21), 716 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(22), 717 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7 = BIT(23), 718 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(24), 719 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(25), 720 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON = BIT(26), 721 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(27), 722 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(28), 723 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM = BIT(29), 724}; 725 726enum htt_rx_mgmt_pkt_filter_tlv_flags1 { 727 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(0), 728 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(1), 729 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC = BIT(2), 730 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(3), 731 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(4), 732 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH = BIT(5), 733 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(6), 734 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(7), 735 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH = BIT(8), 736 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(9), 737 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(10), 738 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION = BIT(11), 739 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(12), 740 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(13), 741 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK = BIT(14), 742 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(15), 743 HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(16), 744 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15 = BIT(17), 745}; 746 747enum htt_rx_ctrl_pkt_filter_tlv_flags2 { 748 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(0), 749 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(1), 750 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 = BIT(2), 751 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(3), 752 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(4), 753 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 = BIT(5), 754 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(6), 755 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(7), 756 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER = BIT(8), 757 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(9), 758 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(10), 759 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 = BIT(11), 760 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(12), 761 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(13), 762 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL = BIT(14), 763 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(15), 764 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(16), 765 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP = BIT(17), 766 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(18), 767 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(19), 768 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT = BIT(20), 769 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(21), 770 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(22), 771 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER = BIT(23), 772 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(24), 773 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(25), 774 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR = BIT(26), 775 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(27), 776 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(28), 777 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA = BIT(29), 778}; 779 780enum htt_rx_ctrl_pkt_filter_tlv_flags3 { 781 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(0), 782 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(1), 783 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL = BIT(2), 784 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(3), 785 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(4), 786 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS = BIT(5), 787 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(6), 788 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(7), 789 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS = BIT(8), 790 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(9), 791 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(10), 792 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK = BIT(11), 793 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(12), 794 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(13), 795 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND = BIT(14), 796 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(15), 797 HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(16), 798 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK = BIT(17), 799}; 800 801enum htt_rx_data_pkt_filter_tlv_flasg3 { 802 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(18), 803 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(19), 804 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST = BIT(20), 805 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(21), 806 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(22), 807 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST = BIT(23), 808 HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(24), 809 HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(25), 810 HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA = BIT(26), 811}; 812 813#define HTT_RX_FP_MGMT_FILTER_FLAGS0 \ 814 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 815 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 816 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 817 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 818 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 819 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 820 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 821 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 822 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 823 824#define HTT_RX_MD_MGMT_FILTER_FLAGS0 \ 825 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 826 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 827 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 828 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 829 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 830 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 831 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 832 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 833 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 834 835#define HTT_RX_MO_MGMT_FILTER_FLAGS0 \ 836 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_REQ \ 837 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ASSOC_RESP \ 838 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_REQ \ 839 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_REASSOC_RESP \ 840 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_REQ \ 841 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_RESP \ 842 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_PROBE_TIMING_ADV \ 843 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_BEACON \ 844 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_ATIM) 845 846#define HTT_RX_FP_MGMT_FILTER_FLAGS1 (HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 847 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 848 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 849 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 850 | HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 851 852#define HTT_RX_MD_MGMT_FILTER_FLAGS1 (HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 853 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 854 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 855 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 856 | HTT_RX_MD_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 857 858#define HTT_RX_MO_MGMT_FILTER_FLAGS1 (HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DISASSOC \ 859 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_AUTH \ 860 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_DEAUTH \ 861 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION \ 862 | HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_ACTION_NOACK) 863 864#define HTT_RX_FP_CTRL_FILTER_FLASG2 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 865 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 866 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 867 868#define HTT_RX_MD_CTRL_FILTER_FLASG2 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 869 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 870 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 871 872#define HTT_RX_MO_CTRL_FILTER_FLASG2 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_WRAPPER \ 873 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BAR \ 874 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_BA) 875 876#define HTT_RX_FP_CTRL_FILTER_FLASG3 (HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 877 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 878 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 879 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 880 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 881 | HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 882 883#define HTT_RX_MD_CTRL_FILTER_FLASG3 (HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 884 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 885 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 886 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 887 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 888 | HTT_RX_MD_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 889 890#define HTT_RX_MO_CTRL_FILTER_FLASG3 (HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_PSPOLL \ 891 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_RTS \ 892 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CTS \ 893 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_ACK \ 894 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND \ 895 | HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS3_CFEND_ACK) 896 897#define HTT_RX_FP_DATA_FILTER_FLASG3 (HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 898 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 899 | HTT_RX_FP_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 900 901#define HTT_RX_MD_DATA_FILTER_FLASG3 (HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 902 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 903 | HTT_RX_MD_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 904 905#define HTT_RX_MO_DATA_FILTER_FLASG3 (HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_MCAST \ 906 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_UCAST \ 907 | HTT_RX_MO_DATA_PKT_FILTER_TLV_FLASG3_NULL_DATA) 908 909#define HTT_RX_MON_FP_MGMT_FILTER_FLAGS0 \ 910 (HTT_RX_FP_MGMT_FILTER_FLAGS0 | \ 911 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 912 913#define HTT_RX_MON_MO_MGMT_FILTER_FLAGS0 \ 914 (HTT_RX_MO_MGMT_FILTER_FLAGS0 | \ 915 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS0_RESERVED_7) 916 917#define HTT_RX_MON_FP_MGMT_FILTER_FLAGS1 \ 918 (HTT_RX_FP_MGMT_FILTER_FLAGS1 | \ 919 HTT_RX_FP_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 920 921#define HTT_RX_MON_MO_MGMT_FILTER_FLAGS1 \ 922 (HTT_RX_MO_MGMT_FILTER_FLAGS1 | \ 923 HTT_RX_MO_MGMT_PKT_FILTER_TLV_FLAGS1_RESERVED_15) 924 925#define HTT_RX_MON_FP_CTRL_FILTER_FLASG2 \ 926 (HTT_RX_FP_CTRL_FILTER_FLASG2 | \ 927 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 928 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 929 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 930 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 931 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 932 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 933 HTT_RX_FP_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 934 935#define HTT_RX_MON_MO_CTRL_FILTER_FLASG2 \ 936 (HTT_RX_MO_CTRL_FILTER_FLASG2 | \ 937 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_1 | \ 938 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_2 | \ 939 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_TRIGGER | \ 940 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_RESERVED_4 | \ 941 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_BF_REP_POLL | \ 942 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_VHT_NDP | \ 943 HTT_RX_MO_CTRL_PKT_FILTER_TLV_FLAGS2_CTRL_FRAME_EXT) 944 945#define HTT_RX_MON_FP_CTRL_FILTER_FLASG3 HTT_RX_FP_CTRL_FILTER_FLASG3 946 947#define HTT_RX_MON_MO_CTRL_FILTER_FLASG3 HTT_RX_MO_CTRL_FILTER_FLASG3 948 949#define HTT_RX_MON_FP_DATA_FILTER_FLASG3 HTT_RX_FP_DATA_FILTER_FLASG3 950 951#define HTT_RX_MON_MO_DATA_FILTER_FLASG3 HTT_RX_MO_DATA_FILTER_FLASG3 952 953#define HTT_RX_MON_FILTER_TLV_FLAGS \ 954 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 955 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 956 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 957 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 958 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 959 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 960 961#define HTT_RX_MON_FILTER_TLV_FLAGS_MON_STATUS_RING \ 962 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 963 HTT_RX_FILTER_TLV_FLAGS_PPDU_START | \ 964 HTT_RX_FILTER_TLV_FLAGS_PPDU_END | \ 965 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS | \ 966 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_USER_STATS_EXT | \ 967 HTT_RX_FILTER_TLV_FLAGS_PPDU_END_STATUS_DONE) 968 969#define HTT_RX_MON_FILTER_TLV_FLAGS_MON_BUF_RING \ 970 (HTT_RX_FILTER_TLV_FLAGS_MPDU_START | \ 971 HTT_RX_FILTER_TLV_FLAGS_MSDU_START | \ 972 HTT_RX_FILTER_TLV_FLAGS_RX_PACKET | \ 973 HTT_RX_FILTER_TLV_FLAGS_MSDU_END | \ 974 HTT_RX_FILTER_TLV_FLAGS_MPDU_END | \ 975 HTT_RX_FILTER_TLV_FLAGS_PACKET_HEADER | \ 976 HTT_RX_FILTER_TLV_FLAGS_PER_MSDU_HEADER | \ 977 HTT_RX_FILTER_TLV_FLAGS_ATTENTION) 978 979struct htt_rx_ring_selection_cfg_cmd { 980 u32 info0; 981 u32 info1; 982 u32 pkt_type_en_flags0; 983 u32 pkt_type_en_flags1; 984 u32 pkt_type_en_flags2; 985 u32 pkt_type_en_flags3; 986 u32 rx_filter_tlv; 987} __packed; 988 989struct htt_rx_ring_tlv_filter { 990 u32 rx_filter; /* see htt_rx_filter_tlv_flags */ 991 u32 pkt_filter_flags0; /* MGMT */ 992 u32 pkt_filter_flags1; /* MGMT */ 993 u32 pkt_filter_flags2; /* CTRL */ 994 u32 pkt_filter_flags3; /* DATA */ 995}; 996 997#define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_MSG_TYPE GENMASK(7, 0) 998#define HTT_RX_FULL_MON_MODE_CFG_CMD_INFO0_PDEV_ID GENMASK(15, 8) 999 1000#define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ENABLE BIT(0) 1001#define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_ZERO_MPDUS_END BIT(1) 1002#define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_NON_ZERO_MPDUS_END BIT(2) 1003#define HTT_RX_FULL_MON_MODE_CFG_CMD_CFG_RELEASE_RING GENMASK(10, 3) 1004 1005/* Enumeration for full monitor mode destination ring select 1006 * 0 - REO destination ring select 1007 * 1 - FW destination ring select 1008 * 2 - SW destination ring select 1009 * 3 - Release destination ring select 1010 */ 1011enum htt_rx_full_mon_release_ring { 1012 HTT_RX_MON_RING_REO, 1013 HTT_RX_MON_RING_FW, 1014 HTT_RX_MON_RING_SW, 1015 HTT_RX_MON_RING_RELEASE, 1016}; 1017 1018struct htt_rx_full_monitor_mode_cfg_cmd { 1019 u32 info0; 1020 u32 cfg; 1021} __packed; 1022 1023/* HTT message target->host */ 1024 1025enum htt_t2h_msg_type { 1026 HTT_T2H_MSG_TYPE_VERSION_CONF, 1027 HTT_T2H_MSG_TYPE_PEER_MAP = 0x3, 1028 HTT_T2H_MSG_TYPE_PEER_UNMAP = 0x4, 1029 HTT_T2H_MSG_TYPE_RX_ADDBA = 0x5, 1030 HTT_T2H_MSG_TYPE_PKTLOG = 0x8, 1031 HTT_T2H_MSG_TYPE_SEC_IND = 0xb, 1032 HTT_T2H_MSG_TYPE_PEER_MAP2 = 0x1e, 1033 HTT_T2H_MSG_TYPE_PEER_UNMAP2 = 0x1f, 1034 HTT_T2H_MSG_TYPE_PPDU_STATS_IND = 0x1d, 1035 HTT_T2H_MSG_TYPE_EXT_STATS_CONF = 0x1c, 1036 HTT_T2H_MSG_TYPE_BKPRESSURE_EVENT_IND = 0x24, 1037}; 1038 1039#define HTT_TARGET_VERSION_MAJOR 3 1040 1041#define HTT_T2H_MSG_TYPE GENMASK(7, 0) 1042#define HTT_T2H_VERSION_CONF_MINOR GENMASK(15, 8) 1043#define HTT_T2H_VERSION_CONF_MAJOR GENMASK(23, 16) 1044 1045struct htt_t2h_version_conf_msg { 1046 u32 version; 1047} __packed; 1048 1049#define HTT_T2H_PEER_MAP_INFO_VDEV_ID GENMASK(15, 8) 1050#define HTT_T2H_PEER_MAP_INFO_PEER_ID GENMASK(31, 16) 1051#define HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 GENMASK(15, 0) 1052#define HTT_T2H_PEER_MAP_INFO1_HW_PEER_ID GENMASK(31, 16) 1053#define HTT_T2H_PEER_MAP_INFO2_AST_HASH_VAL GENMASK(15, 0) 1054#define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M BIT(16) 1055#define HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 16 1056 1057struct htt_t2h_peer_map_event { 1058 u32 info; 1059 u32 mac_addr_l32; 1060 u32 info1; 1061 u32 info2; 1062} __packed; 1063 1064#define HTT_T2H_PEER_UNMAP_INFO_VDEV_ID HTT_T2H_PEER_MAP_INFO_VDEV_ID 1065#define HTT_T2H_PEER_UNMAP_INFO_PEER_ID HTT_T2H_PEER_MAP_INFO_PEER_ID 1066#define HTT_T2H_PEER_UNMAP_INFO1_MAC_ADDR_H16 \ 1067 HTT_T2H_PEER_MAP_INFO1_MAC_ADDR_H16 1068#define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_M HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_M 1069#define HTT_T2H_PEER_MAP_INFO1_NEXT_HOP_S HTT_T2H_PEER_MAP_INFO2_NEXT_HOP_S 1070 1071struct htt_t2h_peer_unmap_event { 1072 u32 info; 1073 u32 mac_addr_l32; 1074 u32 info1; 1075} __packed; 1076 1077struct htt_resp_msg { 1078 union { 1079 struct htt_t2h_version_conf_msg version_msg; 1080 struct htt_t2h_peer_map_event peer_map_ev; 1081 struct htt_t2h_peer_unmap_event peer_unmap_ev; 1082 }; 1083} __packed; 1084 1085#define HTT_BACKPRESSURE_EVENT_PDEV_ID_M GENMASK(15, 8) 1086#define HTT_BACKPRESSURE_EVENT_RING_TYPE_M GENMASK(23, 16) 1087#define HTT_BACKPRESSURE_EVENT_RING_ID_M GENMASK(31, 24) 1088 1089#define HTT_BACKPRESSURE_EVENT_HP_M GENMASK(15, 0) 1090#define HTT_BACKPRESSURE_EVENT_TP_M GENMASK(31, 16) 1091 1092#define HTT_BACKPRESSURE_UMAC_RING_TYPE 0 1093#define HTT_BACKPRESSURE_LMAC_RING_TYPE 1 1094 1095enum htt_backpressure_umac_ringid { 1096 HTT_SW_RING_IDX_REO_REO2SW1_RING, 1097 HTT_SW_RING_IDX_REO_REO2SW2_RING, 1098 HTT_SW_RING_IDX_REO_REO2SW3_RING, 1099 HTT_SW_RING_IDX_REO_REO2SW4_RING, 1100 HTT_SW_RING_IDX_REO_WBM2REO_LINK_RING, 1101 HTT_SW_RING_IDX_REO_REO2TCL_RING, 1102 HTT_SW_RING_IDX_REO_REO2FW_RING, 1103 HTT_SW_RING_IDX_REO_REO_RELEASE_RING, 1104 HTT_SW_RING_IDX_WBM_PPE_RELEASE_RING, 1105 HTT_SW_RING_IDX_TCL_TCL2TQM_RING, 1106 HTT_SW_RING_IDX_WBM_TQM_RELEASE_RING, 1107 HTT_SW_RING_IDX_WBM_REO_RELEASE_RING, 1108 HTT_SW_RING_IDX_WBM_WBM2SW0_RELEASE_RING, 1109 HTT_SW_RING_IDX_WBM_WBM2SW1_RELEASE_RING, 1110 HTT_SW_RING_IDX_WBM_WBM2SW2_RELEASE_RING, 1111 HTT_SW_RING_IDX_WBM_WBM2SW3_RELEASE_RING, 1112 HTT_SW_RING_IDX_REO_REO_CMD_RING, 1113 HTT_SW_RING_IDX_REO_REO_STATUS_RING, 1114 HTT_SW_UMAC_RING_IDX_MAX, 1115}; 1116 1117enum htt_backpressure_lmac_ringid { 1118 HTT_SW_RING_IDX_FW2RXDMA_BUF_RING, 1119 HTT_SW_RING_IDX_FW2RXDMA_STATUS_RING, 1120 HTT_SW_RING_IDX_FW2RXDMA_LINK_RING, 1121 HTT_SW_RING_IDX_SW2RXDMA_BUF_RING, 1122 HTT_SW_RING_IDX_WBM2RXDMA_LINK_RING, 1123 HTT_SW_RING_IDX_RXDMA2FW_RING, 1124 HTT_SW_RING_IDX_RXDMA2SW_RING, 1125 HTT_SW_RING_IDX_RXDMA2RELEASE_RING, 1126 HTT_SW_RING_IDX_RXDMA2REO_RING, 1127 HTT_SW_RING_IDX_MONITOR_STATUS_RING, 1128 HTT_SW_RING_IDX_MONITOR_BUF_RING, 1129 HTT_SW_RING_IDX_MONITOR_DESC_RING, 1130 HTT_SW_RING_IDX_MONITOR_DEST_RING, 1131 HTT_SW_LMAC_RING_IDX_MAX, 1132}; 1133 1134/* ppdu stats 1135 * 1136 * @details 1137 * The following field definitions describe the format of the HTT target 1138 * to host ppdu stats indication message. 1139 * 1140 * 1141 * |31 16|15 12|11 10|9 8|7 0 | 1142 * |----------------------------------------------------------------------| 1143 * | payload_size | rsvd |pdev_id|mac_id | msg type | 1144 * |----------------------------------------------------------------------| 1145 * | ppdu_id | 1146 * |----------------------------------------------------------------------| 1147 * | Timestamp in us | 1148 * |----------------------------------------------------------------------| 1149 * | reserved | 1150 * |----------------------------------------------------------------------| 1151 * | type-specific stats info | 1152 * | (see htt_ppdu_stats.h) | 1153 * |----------------------------------------------------------------------| 1154 * Header fields: 1155 * - MSG_TYPE 1156 * Bits 7:0 1157 * Purpose: Identifies this is a PPDU STATS indication 1158 * message. 1159 * Value: 0x1d 1160 * - mac_id 1161 * Bits 9:8 1162 * Purpose: mac_id of this ppdu_id 1163 * Value: 0-3 1164 * - pdev_id 1165 * Bits 11:10 1166 * Purpose: pdev_id of this ppdu_id 1167 * Value: 0-3 1168 * 0 (for rings at SOC level), 1169 * 1/2/3 PDEV -> 0/1/2 1170 * - payload_size 1171 * Bits 31:16 1172 * Purpose: total tlv size 1173 * Value: payload_size in bytes 1174 */ 1175 1176#define HTT_T2H_PPDU_STATS_INFO_PDEV_ID GENMASK(11, 10) 1177#define HTT_T2H_PPDU_STATS_INFO_PAYLOAD_SIZE GENMASK(31, 16) 1178 1179struct ath11k_htt_ppdu_stats_msg { 1180 u32 info; 1181 u32 ppdu_id; 1182 u32 timestamp; 1183 u32 rsvd; 1184 u8 data[]; 1185} __packed; 1186 1187struct htt_tlv { 1188 u32 header; 1189 u8 value[]; 1190} __packed; 1191 1192#define HTT_TLV_TAG GENMASK(11, 0) 1193#define HTT_TLV_LEN GENMASK(23, 12) 1194 1195enum HTT_PPDU_STATS_BW { 1196 HTT_PPDU_STATS_BANDWIDTH_5MHZ = 0, 1197 HTT_PPDU_STATS_BANDWIDTH_10MHZ = 1, 1198 HTT_PPDU_STATS_BANDWIDTH_20MHZ = 2, 1199 HTT_PPDU_STATS_BANDWIDTH_40MHZ = 3, 1200 HTT_PPDU_STATS_BANDWIDTH_80MHZ = 4, 1201 HTT_PPDU_STATS_BANDWIDTH_160MHZ = 5, /* includes 80+80 */ 1202 HTT_PPDU_STATS_BANDWIDTH_DYN = 6, 1203}; 1204 1205#define HTT_PPDU_STATS_CMN_FLAGS_FRAME_TYPE_M GENMASK(7, 0) 1206#define HTT_PPDU_STATS_CMN_FLAGS_QUEUE_TYPE_M GENMASK(15, 8) 1207/* bw - HTT_PPDU_STATS_BW */ 1208#define HTT_PPDU_STATS_CMN_FLAGS_BW_M GENMASK(19, 16) 1209 1210struct htt_ppdu_stats_common { 1211 u32 ppdu_id; 1212 u16 sched_cmdid; 1213 u8 ring_id; 1214 u8 num_users; 1215 u32 flags; /* %HTT_PPDU_STATS_COMMON_FLAGS_*/ 1216 u32 chain_mask; 1217 u32 fes_duration_us; /* frame exchange sequence */ 1218 u32 ppdu_sch_eval_start_tstmp_us; 1219 u32 ppdu_sch_end_tstmp_us; 1220 u32 ppdu_start_tstmp_us; 1221 /* BIT [15 : 0] - phy mode (WLAN_PHY_MODE) with which ppdu was transmitted 1222 * BIT [31 : 16] - bandwidth (in MHz) with which ppdu was transmitted 1223 */ 1224 u16 phy_mode; 1225 u16 bw_mhz; 1226} __packed; 1227 1228enum htt_ppdu_stats_gi { 1229 HTT_PPDU_STATS_SGI_0_8_US, 1230 HTT_PPDU_STATS_SGI_0_4_US, 1231 HTT_PPDU_STATS_SGI_1_6_US, 1232 HTT_PPDU_STATS_SGI_3_2_US, 1233}; 1234 1235#define HTT_PPDU_STATS_USER_RATE_INFO0_USER_POS_M GENMASK(3, 0) 1236#define HTT_PPDU_STATS_USER_RATE_INFO0_MU_GROUP_ID_M GENMASK(11, 4) 1237 1238#define HTT_PPDU_STATS_USER_RATE_INFO1_RESP_TYPE_VALD_M BIT(0) 1239#define HTT_PPDU_STATS_USER_RATE_INFO1_PPDU_TYPE_M GENMASK(5, 1) 1240 1241#define HTT_PPDU_STATS_USER_RATE_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1242#define HTT_PPDU_STATS_USER_RATE_FLAGS_STBC_M BIT(2) 1243#define HTT_PPDU_STATS_USER_RATE_FLAGS_HE_RE_M BIT(3) 1244#define HTT_PPDU_STATS_USER_RATE_FLAGS_TXBF_M GENMASK(7, 4) 1245#define HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M GENMASK(11, 8) 1246#define HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M GENMASK(15, 12) 1247#define HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M GENMASK(19, 16) 1248#define HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M GENMASK(23, 20) 1249#define HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M GENMASK(27, 24) 1250#define HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M BIT(28) 1251#define HTT_PPDU_STATS_USER_RATE_FLAGS_LDPC_M BIT(29) 1252 1253#define HTT_USR_RATE_PREAMBLE(_val) \ 1254 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_PREAMBLE_M, _val) 1255#define HTT_USR_RATE_BW(_val) \ 1256 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_BW_M, _val) 1257#define HTT_USR_RATE_NSS(_val) \ 1258 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_NSS_M, _val) 1259#define HTT_USR_RATE_MCS(_val) \ 1260 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_MCS_M, _val) 1261#define HTT_USR_RATE_GI(_val) \ 1262 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_GI_M, _val) 1263#define HTT_USR_RATE_DCM(_val) \ 1264 FIELD_GET(HTT_PPDU_STATS_USER_RATE_FLAGS_DCM_M, _val) 1265 1266#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LTF_SIZE_M GENMASK(1, 0) 1267#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_STBC_M BIT(2) 1268#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_HE_RE_M BIT(3) 1269#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_TXBF_M GENMASK(7, 4) 1270#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_BW_M GENMASK(11, 8) 1271#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_NSS_M GENMASK(15, 12) 1272#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_MCS_M GENMASK(19, 16) 1273#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_PREAMBLE_M GENMASK(23, 20) 1274#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_GI_M GENMASK(27, 24) 1275#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_DCM_M BIT(28) 1276#define HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_LDPC_M BIT(29) 1277 1278struct htt_ppdu_stats_user_rate { 1279 u8 tid_num; 1280 u8 reserved0; 1281 u16 sw_peer_id; 1282 u32 info0; /* %HTT_PPDU_STATS_USER_RATE_INFO0_*/ 1283 u16 ru_end; 1284 u16 ru_start; 1285 u16 resp_ru_end; 1286 u16 resp_ru_start; 1287 u32 info1; /* %HTT_PPDU_STATS_USER_RATE_INFO1_ */ 1288 u32 rate_flags; /* %HTT_PPDU_STATS_USER_RATE_FLAGS_ */ 1289 /* Note: resp_rate_info is only valid for if resp_type is UL */ 1290 u32 resp_rate_flags; /* %HTT_PPDU_STATS_USER_RATE_RESP_FLAGS_ */ 1291} __packed; 1292 1293#define HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M GENMASK(7, 0) 1294#define HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M BIT(8) 1295#define HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M GENMASK(10, 9) 1296#define HTT_PPDU_STATS_TX_INFO_FLAGS_BW_M GENMASK(13, 11) 1297#define HTT_PPDU_STATS_TX_INFO_FLAGS_SGI_M BIT(14) 1298#define HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M GENMASK(31, 16) 1299 1300#define HTT_TX_INFO_IS_AMSDU(_flags) \ 1301 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_IS_AMPDU_M, _flags) 1302#define HTT_TX_INFO_BA_ACK_FAILED(_flags) \ 1303 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_BA_ACK_FAILED_M, _flags) 1304#define HTT_TX_INFO_RATECODE(_flags) \ 1305 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_RATECODE_M, _flags) 1306#define HTT_TX_INFO_PEERID(_flags) \ 1307 FIELD_GET(HTT_PPDU_STATS_TX_INFO_FLAGS_PEERID_M, _flags) 1308 1309enum htt_ppdu_stats_usr_compln_status { 1310 HTT_PPDU_STATS_USER_STATUS_OK, 1311 HTT_PPDU_STATS_USER_STATUS_FILTERED, 1312 HTT_PPDU_STATS_USER_STATUS_RESP_TIMEOUT, 1313 HTT_PPDU_STATS_USER_STATUS_RESP_MISMATCH, 1314 HTT_PPDU_STATS_USER_STATUS_ABORT, 1315}; 1316 1317#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M GENMASK(3, 0) 1318#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M GENMASK(7, 4) 1319#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M BIT(8) 1320#define HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_RESP_TYPE_M GENMASK(12, 9) 1321 1322#define HTT_USR_CMPLTN_IS_AMPDU(_val) \ 1323 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_IS_AMPDU_M, _val) 1324#define HTT_USR_CMPLTN_LONG_RETRY(_val) \ 1325 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRY_M, _val) 1326#define HTT_USR_CMPLTN_SHORT_RETRY(_val) \ 1327 FIELD_GET(HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_SHORT_RETRY_M, _val) 1328 1329struct htt_ppdu_stats_usr_cmpltn_cmn { 1330 u8 status; 1331 u8 tid_num; 1332 u16 sw_peer_id; 1333 /* RSSI value of last ack packet (units = dB above noise floor) */ 1334 u32 ack_rssi; 1335 u16 mpdu_tried; 1336 u16 mpdu_success; 1337 u32 flags; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_FLAGS_LONG_RETRIES*/ 1338} __packed; 1339 1340#define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MPDU_M GENMASK(8, 0) 1341#define HTT_PPDU_STATS_ACK_BA_INFO_NUM_MSDU_M GENMASK(24, 9) 1342#define HTT_PPDU_STATS_ACK_BA_INFO_TID_NUM GENMASK(31, 25) 1343 1344#define HTT_PPDU_STATS_NON_QOS_TID 16 1345 1346struct htt_ppdu_stats_usr_cmpltn_ack_ba_status { 1347 u32 ppdu_id; 1348 u16 sw_peer_id; 1349 u16 reserved0; 1350 u32 info; /* %HTT_PPDU_STATS_USR_CMPLTN_CMN_INFO_ */ 1351 u16 current_seq; 1352 u16 start_seq; 1353 u32 success_bytes; 1354} __packed; 1355 1356struct htt_ppdu_user_stats { 1357 u16 peer_id; 1358 u32 tlv_flags; 1359 bool is_valid_peer_id; 1360 struct htt_ppdu_stats_user_rate rate; 1361 struct htt_ppdu_stats_usr_cmpltn_cmn cmpltn_cmn; 1362 struct htt_ppdu_stats_usr_cmpltn_ack_ba_status ack_ba; 1363}; 1364 1365#define HTT_PPDU_STATS_MAX_USERS 8 1366#define HTT_PPDU_DESC_MAX_DEPTH 16 1367 1368struct htt_ppdu_stats { 1369 struct htt_ppdu_stats_common common; 1370 struct htt_ppdu_user_stats user_stats[HTT_PPDU_STATS_MAX_USERS]; 1371}; 1372 1373struct htt_ppdu_stats_info { 1374 u32 ppdu_id; 1375 struct htt_ppdu_stats ppdu_stats; 1376 struct list_head list; 1377}; 1378 1379/* @brief target -> host packet log message 1380 * 1381 * @details 1382 * The following field definitions describe the format of the packet log 1383 * message sent from the target to the host. 1384 * The message consists of a 4-octet header,followed by a variable number 1385 * of 32-bit character values. 1386 * 1387 * |31 16|15 12|11 10|9 8|7 0| 1388 * |------------------------------------------------------------------| 1389 * | payload_size | rsvd |pdev_id|mac_id| msg type | 1390 * |------------------------------------------------------------------| 1391 * | payload | 1392 * |------------------------------------------------------------------| 1393 * - MSG_TYPE 1394 * Bits 7:0 1395 * Purpose: identifies this as a pktlog message 1396 * Value: HTT_T2H_MSG_TYPE_PKTLOG 1397 * - mac_id 1398 * Bits 9:8 1399 * Purpose: identifies which MAC/PHY instance generated this pktlog info 1400 * Value: 0-3 1401 * - pdev_id 1402 * Bits 11:10 1403 * Purpose: pdev_id 1404 * Value: 0-3 1405 * 0 (for rings at SOC level), 1406 * 1/2/3 PDEV -> 0/1/2 1407 * - payload_size 1408 * Bits 31:16 1409 * Purpose: explicitly specify the payload size 1410 * Value: payload size in bytes (payload size is a multiple of 4 bytes) 1411 */ 1412struct htt_pktlog_msg { 1413 u32 hdr; 1414 u8 payload[]; 1415}; 1416 1417/* @brief host -> target FW extended statistics retrieve 1418 * 1419 * @details 1420 * The following field definitions describe the format of the HTT host 1421 * to target FW extended stats retrieve message. 1422 * The message specifies the type of stats the host wants to retrieve. 1423 * 1424 * |31 24|23 16|15 8|7 0| 1425 * |-----------------------------------------------------------| 1426 * | reserved | stats type | pdev_mask | msg type | 1427 * |-----------------------------------------------------------| 1428 * | config param [0] | 1429 * |-----------------------------------------------------------| 1430 * | config param [1] | 1431 * |-----------------------------------------------------------| 1432 * | config param [2] | 1433 * |-----------------------------------------------------------| 1434 * | config param [3] | 1435 * |-----------------------------------------------------------| 1436 * | reserved | 1437 * |-----------------------------------------------------------| 1438 * | cookie LSBs | 1439 * |-----------------------------------------------------------| 1440 * | cookie MSBs | 1441 * |-----------------------------------------------------------| 1442 * Header fields: 1443 * - MSG_TYPE 1444 * Bits 7:0 1445 * Purpose: identifies this is a extended stats upload request message 1446 * Value: 0x10 1447 * - PDEV_MASK 1448 * Bits 8:15 1449 * Purpose: identifies the mask of PDEVs to retrieve stats from 1450 * Value: This is a overloaded field, refer to usage and interpretation of 1451 * PDEV in interface document. 1452 * Bit 8 : Reserved for SOC stats 1453 * Bit 9 - 15 : Indicates PDEV_MASK in DBDC 1454 * Indicates MACID_MASK in DBS 1455 * - STATS_TYPE 1456 * Bits 23:16 1457 * Purpose: identifies which FW statistics to upload 1458 * Value: Defined by htt_dbg_ext_stats_type (see htt_stats.h) 1459 * - Reserved 1460 * Bits 31:24 1461 * - CONFIG_PARAM [0] 1462 * Bits 31:0 1463 * Purpose: give an opaque configuration value to the specified stats type 1464 * Value: stats-type specific configuration value 1465 * Refer to htt_stats.h for interpretation for each stats sub_type 1466 * - CONFIG_PARAM [1] 1467 * Bits 31:0 1468 * Purpose: give an opaque configuration value to the specified stats type 1469 * Value: stats-type specific configuration value 1470 * Refer to htt_stats.h for interpretation for each stats sub_type 1471 * - CONFIG_PARAM [2] 1472 * Bits 31:0 1473 * Purpose: give an opaque configuration value to the specified stats type 1474 * Value: stats-type specific configuration value 1475 * Refer to htt_stats.h for interpretation for each stats sub_type 1476 * - CONFIG_PARAM [3] 1477 * Bits 31:0 1478 * Purpose: give an opaque configuration value to the specified stats type 1479 * Value: stats-type specific configuration value 1480 * Refer to htt_stats.h for interpretation for each stats sub_type 1481 * - Reserved [31:0] for future use. 1482 * - COOKIE_LSBS 1483 * Bits 31:0 1484 * Purpose: Provide a mechanism to match a target->host stats confirmation 1485 * message with its preceding host->target stats request message. 1486 * Value: LSBs of the opaque cookie specified by the host-side requestor 1487 * - COOKIE_MSBS 1488 * Bits 31:0 1489 * Purpose: Provide a mechanism to match a target->host stats confirmation 1490 * message with its preceding host->target stats request message. 1491 * Value: MSBs of the opaque cookie specified by the host-side requestor 1492 */ 1493 1494struct htt_ext_stats_cfg_hdr { 1495 u8 msg_type; 1496 u8 pdev_mask; 1497 u8 stats_type; 1498 u8 reserved; 1499} __packed; 1500 1501struct htt_ext_stats_cfg_cmd { 1502 struct htt_ext_stats_cfg_hdr hdr; 1503 u32 cfg_param0; 1504 u32 cfg_param1; 1505 u32 cfg_param2; 1506 u32 cfg_param3; 1507 u32 reserved; 1508 u32 cookie_lsb; 1509 u32 cookie_msb; 1510} __packed; 1511 1512/* htt stats config default params */ 1513#define HTT_STAT_DEFAULT_RESET_START_OFFSET 0 1514#define HTT_STAT_DEFAULT_CFG0_ALL_HWQS 0xffffffff 1515#define HTT_STAT_DEFAULT_CFG0_ALL_TXQS 0xffffffff 1516#define HTT_STAT_DEFAULT_CFG0_ALL_CMDQS 0xffff 1517#define HTT_STAT_DEFAULT_CFG0_ALL_RINGS 0xffff 1518#define HTT_STAT_DEFAULT_CFG0_ACTIVE_PEERS 0xff 1519#define HTT_STAT_DEFAULT_CFG0_CCA_CUMULATIVE 0x00 1520#define HTT_STAT_DEFAULT_CFG0_ACTIVE_VDEVS 0x00 1521 1522/* HTT_DBG_EXT_STATS_PEER_INFO 1523 * PARAMS: 1524 * @config_param0: 1525 * [Bit0] - [0] for sw_peer_id, [1] for mac_addr based request 1526 * [Bit15 : Bit 1] htt_peer_stats_req_mode_t 1527 * [Bit31 : Bit16] sw_peer_id 1528 * @config_param1: 1529 * peer_stats_req_type_mask:32 (enum htt_peer_stats_tlv_enum) 1530 * 0 bit htt_peer_stats_cmn_tlv 1531 * 1 bit htt_peer_details_tlv 1532 * 2 bit htt_tx_peer_rate_stats_tlv 1533 * 3 bit htt_rx_peer_rate_stats_tlv 1534 * 4 bit htt_tx_tid_stats_tlv/htt_tx_tid_stats_v1_tlv 1535 * 5 bit htt_rx_tid_stats_tlv 1536 * 6 bit htt_msdu_flow_stats_tlv 1537 * @config_param2: [Bit31 : Bit0] mac_addr31to0 1538 * @config_param3: [Bit15 : Bit0] mac_addr47to32 1539 * [Bit31 : Bit16] reserved 1540 */ 1541#define HTT_STAT_PEER_INFO_MAC_ADDR BIT(0) 1542#define HTT_STAT_DEFAULT_PEER_REQ_TYPE 0x7f 1543 1544/* Used to set different configs to the specified stats type.*/ 1545struct htt_ext_stats_cfg_params { 1546 u32 cfg0; 1547 u32 cfg1; 1548 u32 cfg2; 1549 u32 cfg3; 1550}; 1551 1552/* @brief target -> host extended statistics upload 1553 * 1554 * @details 1555 * The following field definitions describe the format of the HTT target 1556 * to host stats upload confirmation message. 1557 * The message contains a cookie echoed from the HTT host->target stats 1558 * upload request, which identifies which request the confirmation is 1559 * for, and a single stats can span over multiple HTT stats indication 1560 * due to the HTT message size limitation so every HTT ext stats indication 1561 * will have tag-length-value stats information elements. 1562 * The tag-length header for each HTT stats IND message also includes a 1563 * status field, to indicate whether the request for the stat type in 1564 * question was fully met, partially met, unable to be met, or invalid 1565 * (if the stat type in question is disabled in the target). 1566 * A Done bit 1's indicate the end of the of stats info elements. 1567 * 1568 * 1569 * |31 16|15 12|11|10 8|7 5|4 0| 1570 * |--------------------------------------------------------------| 1571 * | reserved | msg type | 1572 * |--------------------------------------------------------------| 1573 * | cookie LSBs | 1574 * |--------------------------------------------------------------| 1575 * | cookie MSBs | 1576 * |--------------------------------------------------------------| 1577 * | stats entry length | rsvd | D| S | stat type | 1578 * |--------------------------------------------------------------| 1579 * | type-specific stats info | 1580 * | (see htt_stats.h) | 1581 * |--------------------------------------------------------------| 1582 * Header fields: 1583 * - MSG_TYPE 1584 * Bits 7:0 1585 * Purpose: Identifies this is a extended statistics upload confirmation 1586 * message. 1587 * Value: 0x1c 1588 * - COOKIE_LSBS 1589 * Bits 31:0 1590 * Purpose: Provide a mechanism to match a target->host stats confirmation 1591 * message with its preceding host->target stats request message. 1592 * Value: LSBs of the opaque cookie specified by the host-side requestor 1593 * - COOKIE_MSBS 1594 * Bits 31:0 1595 * Purpose: Provide a mechanism to match a target->host stats confirmation 1596 * message with its preceding host->target stats request message. 1597 * Value: MSBs of the opaque cookie specified by the host-side requestor 1598 * 1599 * Stats Information Element tag-length header fields: 1600 * - STAT_TYPE 1601 * Bits 7:0 1602 * Purpose: identifies the type of statistics info held in the 1603 * following information element 1604 * Value: htt_dbg_ext_stats_type 1605 * - STATUS 1606 * Bits 10:8 1607 * Purpose: indicate whether the requested stats are present 1608 * Value: htt_dbg_ext_stats_status 1609 * - DONE 1610 * Bits 11 1611 * Purpose: 1612 * Indicates the completion of the stats entry, this will be the last 1613 * stats conf HTT segment for the requested stats type. 1614 * Value: 1615 * 0 -> the stats retrieval is ongoing 1616 * 1 -> the stats retrieval is complete 1617 * - LENGTH 1618 * Bits 31:16 1619 * Purpose: indicate the stats information size 1620 * Value: This field specifies the number of bytes of stats information 1621 * that follows the element tag-length header. 1622 * It is expected but not required that this length is a multiple of 1623 * 4 bytes. 1624 */ 1625 1626#define HTT_T2H_EXT_STATS_INFO1_DONE BIT(11) 1627#define HTT_T2H_EXT_STATS_INFO1_LENGTH GENMASK(31, 16) 1628 1629struct ath11k_htt_extd_stats_msg { 1630 u32 info0; 1631 u64 cookie; 1632 u32 info1; 1633 u8 data[]; 1634} __packed; 1635 1636#define HTT_MAC_ADDR_L32_0 GENMASK(7, 0) 1637#define HTT_MAC_ADDR_L32_1 GENMASK(15, 8) 1638#define HTT_MAC_ADDR_L32_2 GENMASK(23, 16) 1639#define HTT_MAC_ADDR_L32_3 GENMASK(31, 24) 1640#define HTT_MAC_ADDR_H16_0 GENMASK(7, 0) 1641#define HTT_MAC_ADDR_H16_1 GENMASK(15, 8) 1642 1643struct htt_mac_addr { 1644 u32 mac_addr_l32; 1645 u32 mac_addr_h16; 1646}; 1647 1648static inline void ath11k_dp_get_mac_addr(u32 addr_l32, u16 addr_h16, u8 *addr) 1649{ 1650 if (IS_ENABLED(CONFIG_CPU_BIG_ENDIAN)) { 1651 addr_l32 = swab32(addr_l32); 1652 addr_h16 = swab16(addr_h16); 1653 } 1654 1655 memcpy(addr, &addr_l32, 4); 1656 memcpy(addr + 4, &addr_h16, ETH_ALEN - 4); 1657} 1658 1659int ath11k_dp_service_srng(struct ath11k_base *ab, 1660 struct ath11k_ext_irq_grp *irq_grp, 1661 int budget); 1662int ath11k_dp_htt_connect(struct ath11k_dp *dp); 1663void ath11k_dp_vdev_tx_attach(struct ath11k *ar, struct ath11k_vif *arvif); 1664void ath11k_dp_free(struct ath11k_base *ab); 1665int ath11k_dp_alloc(struct ath11k_base *ab); 1666int ath11k_dp_pdev_alloc(struct ath11k_base *ab); 1667void ath11k_dp_pdev_pre_alloc(struct ath11k_base *ab); 1668void ath11k_dp_pdev_free(struct ath11k_base *ab); 1669int ath11k_dp_tx_htt_srng_setup(struct ath11k_base *ab, u32 ring_id, 1670 int mac_id, enum hal_ring_type ring_type); 1671int ath11k_dp_peer_setup(struct ath11k *ar, int vdev_id, const u8 *addr); 1672void ath11k_dp_peer_cleanup(struct ath11k *ar, int vdev_id, const u8 *addr); 1673void ath11k_dp_srng_cleanup(struct ath11k_base *ab, struct dp_srng *ring); 1674int ath11k_dp_srng_setup(struct ath11k_base *ab, struct dp_srng *ring, 1675 enum hal_ring_type type, int ring_num, 1676 int mac_id, int num_entries); 1677void ath11k_dp_link_desc_cleanup(struct ath11k_base *ab, 1678 struct dp_link_desc_bank *desc_bank, 1679 u32 ring_type, struct dp_srng *ring); 1680int ath11k_dp_link_desc_setup(struct ath11k_base *ab, 1681 struct dp_link_desc_bank *link_desc_banks, 1682 u32 ring_type, struct hal_srng *srng, 1683 u32 n_link_desc); 1684void ath11k_dp_shadow_start_timer(struct ath11k_base *ab, 1685 struct hal_srng *srng, 1686 struct ath11k_hp_update_timer *update_timer); 1687void ath11k_dp_shadow_stop_timer(struct ath11k_base *ab, 1688 struct ath11k_hp_update_timer *update_timer); 1689void ath11k_dp_shadow_init_timer(struct ath11k_base *ab, 1690 struct ath11k_hp_update_timer *update_timer, 1691 u32 interval, u32 ring_id); 1692void ath11k_dp_stop_shadow_timers(struct ath11k_base *ab); 1693 1694#endif
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