hw.h

   1/* SPDX-License-Identifier: ISC */
   2/*
   3 * Copyright (c) 2005-2011 Atheros Communications Inc.
   4 * Copyright (c) 2011-2017 Qualcomm Atheros, Inc.
   5 * Copyright (c) 2018 The Linux Foundation. All rights reserved.
   6 * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved.
   7 */
   8
   9#ifndef _HW_H_
  10#define _HW_H_
  11
  12#include "targaddrs.h"
  13
  14enum ath10k_bus {
  15	ATH10K_BUS_PCI,
  16	ATH10K_BUS_AHB,
  17	ATH10K_BUS_SDIO,
  18	ATH10K_BUS_USB,
  19	ATH10K_BUS_SNOC,
  20};
  21
  22#define ATH10K_FW_DIR			"ath10k"
  23
  24#define QCA988X_2_0_DEVICE_ID_UBNT   (0x11ac)
  25#define QCA988X_2_0_DEVICE_ID   (0x003c)
  26#define QCA6164_2_1_DEVICE_ID   (0x0041)
  27#define QCA6174_2_1_DEVICE_ID   (0x003e)
  28#define QCA6174_3_2_DEVICE_ID   (0x0042)
  29#define QCA99X0_2_0_DEVICE_ID   (0x0040)
  30#define QCA9888_2_0_DEVICE_ID	(0x0056)
  31#define QCA9984_1_0_DEVICE_ID	(0x0046)
  32#define QCA9377_1_0_DEVICE_ID   (0x0042)
  33#define QCA9887_1_0_DEVICE_ID   (0x0050)
  34
  35/* QCA988X 1.0 definitions (unsupported) */
  36#define QCA988X_HW_1_0_CHIP_ID_REV	0x0
  37
  38/* QCA988X 2.0 definitions */
  39#define QCA988X_HW_2_0_VERSION		0x4100016c
  40#define QCA988X_HW_2_0_CHIP_ID_REV	0x2
  41#define QCA988X_HW_2_0_FW_DIR		ATH10K_FW_DIR "/QCA988X/hw2.0"
  42#define QCA988X_HW_2_0_PATCH_LOAD_ADDR	0x1234
  43
  44/* QCA9887 1.0 definitions */
  45#define QCA9887_HW_1_0_VERSION		0x4100016d
  46#define QCA9887_HW_1_0_CHIP_ID_REV	0
  47#define QCA9887_HW_1_0_FW_DIR		ATH10K_FW_DIR "/QCA9887/hw1.0"
  48#define QCA9887_HW_1_0_PATCH_LOAD_ADDR	0x1234
  49
  50/* QCA6174 target BMI version signatures */
  51#define QCA6174_HW_1_0_VERSION		0x05000000
  52#define QCA6174_HW_1_1_VERSION		0x05000001
  53#define QCA6174_HW_1_3_VERSION		0x05000003
  54#define QCA6174_HW_2_1_VERSION		0x05010000
  55#define QCA6174_HW_3_0_VERSION		0x05020000
  56#define QCA6174_HW_3_2_VERSION		0x05030000
  57
  58/* QCA9377 target BMI version signatures */
  59#define QCA9377_HW_1_0_DEV_VERSION	0x05020000
  60#define QCA9377_HW_1_1_DEV_VERSION	0x05020001
  61
  62enum qca6174_pci_rev {
  63	QCA6174_PCI_REV_1_1 = 0x11,
  64	QCA6174_PCI_REV_1_3 = 0x13,
  65	QCA6174_PCI_REV_2_0 = 0x20,
  66	QCA6174_PCI_REV_3_0 = 0x30,
  67};
  68
  69enum qca6174_chip_id_rev {
  70	QCA6174_HW_1_0_CHIP_ID_REV = 0,
  71	QCA6174_HW_1_1_CHIP_ID_REV = 1,
  72	QCA6174_HW_1_3_CHIP_ID_REV = 2,
  73	QCA6174_HW_2_1_CHIP_ID_REV = 4,
  74	QCA6174_HW_2_2_CHIP_ID_REV = 5,
  75	QCA6174_HW_3_0_CHIP_ID_REV = 8,
  76	QCA6174_HW_3_1_CHIP_ID_REV = 9,
  77	QCA6174_HW_3_2_CHIP_ID_REV = 10,
  78};
  79
  80enum qca9377_chip_id_rev {
  81	QCA9377_HW_1_0_CHIP_ID_REV = 0x0,
  82	QCA9377_HW_1_1_CHIP_ID_REV = 0x1,
  83};
  84
  85#define QCA6174_HW_2_1_FW_DIR		ATH10K_FW_DIR "/QCA6174/hw2.1"
  86#define QCA6174_HW_2_1_PATCH_LOAD_ADDR	0x1234
  87
  88#define QCA6174_HW_3_0_FW_DIR		ATH10K_FW_DIR "/QCA6174/hw3.0"
  89#define QCA6174_HW_3_0_PATCH_LOAD_ADDR	0x1234
  90
  91/* QCA99X0 1.0 definitions (unsupported) */
  92#define QCA99X0_HW_1_0_CHIP_ID_REV     0x0
  93
  94/* QCA99X0 2.0 definitions */
  95#define QCA99X0_HW_2_0_DEV_VERSION     0x01000000
  96#define QCA99X0_HW_2_0_CHIP_ID_REV     0x1
  97#define QCA99X0_HW_2_0_FW_DIR          ATH10K_FW_DIR "/QCA99X0/hw2.0"
  98#define QCA99X0_HW_2_0_PATCH_LOAD_ADDR	0x1234
  99
 100/* QCA9984 1.0 defines */
 101#define QCA9984_HW_1_0_DEV_VERSION	0x1000000
 102#define QCA9984_HW_DEV_TYPE		0xa
 103#define QCA9984_HW_1_0_CHIP_ID_REV	0x0
 104#define QCA9984_HW_1_0_FW_DIR		ATH10K_FW_DIR "/QCA9984/hw1.0"
 105#define QCA9984_HW_1_0_PATCH_LOAD_ADDR	0x1234
 106
 107/* QCA9888 2.0 defines */
 108#define QCA9888_HW_2_0_DEV_VERSION	0x1000000
 109#define QCA9888_HW_DEV_TYPE		0xc
 110#define QCA9888_HW_2_0_CHIP_ID_REV	0x0
 111#define QCA9888_HW_2_0_FW_DIR		ATH10K_FW_DIR "/QCA9888/hw2.0"
 112#define QCA9888_HW_2_0_PATCH_LOAD_ADDR	0x1234
 113
 114/* QCA9377 1.0 definitions */
 115#define QCA9377_HW_1_0_FW_DIR          ATH10K_FW_DIR "/QCA9377/hw1.0"
 116#define QCA9377_HW_1_0_PATCH_LOAD_ADDR	0x1234
 117
 118/* QCA4019 1.0 definitions */
 119#define QCA4019_HW_1_0_DEV_VERSION     0x01000000
 120#define QCA4019_HW_1_0_FW_DIR          ATH10K_FW_DIR "/QCA4019/hw1.0"
 121#define QCA4019_HW_1_0_PATCH_LOAD_ADDR  0x1234
 122
 123/* WCN3990 1.0 definitions */
 124#define WCN3990_HW_1_0_DEV_VERSION	ATH10K_HW_WCN3990
 125#define WCN3990_HW_1_0_FW_DIR		ATH10K_FW_DIR "/WCN3990/hw1.0"
 126
 127#define ATH10K_FW_FILE_BASE		"firmware"
 128#define ATH10K_FW_API_MAX		6
 129#define ATH10K_FW_API_MIN		2
 130
 131#define ATH10K_FW_API2_FILE		"firmware-2.bin"
 132#define ATH10K_FW_API3_FILE		"firmware-3.bin"
 133
 134/* added support for ATH10K_FW_IE_WMI_OP_VERSION */
 135#define ATH10K_FW_API4_FILE		"firmware-4.bin"
 136
 137/* HTT id conflict fix for management frames over HTT */
 138#define ATH10K_FW_API5_FILE		"firmware-5.bin"
 139
 140/* the firmware-6.bin blob */
 141#define ATH10K_FW_API6_FILE		"firmware-6.bin"
 142
 143#define ATH10K_FW_UTF_FILE		"utf.bin"
 144#define ATH10K_FW_UTF_API2_FILE		"utf-2.bin"
 145
 146#define ATH10K_FW_UTF_FILE_BASE		"utf"
 147
 148/* includes also the null byte */
 149#define ATH10K_FIRMWARE_MAGIC               "QCA-ATH10K"
 150#define ATH10K_BOARD_MAGIC                  "QCA-ATH10K-BOARD"
 151
 152#define ATH10K_BOARD_DATA_FILE         "board.bin"
 153#define ATH10K_BOARD_API2_FILE         "board-2.bin"
 154#define ATH10K_EBOARD_DATA_FILE        "eboard.bin"
 155
 156#define REG_DUMP_COUNT_QCA988X 60
 157
 158struct ath10k_fw_ie {
 159	__le32 id;
 160	__le32 len;
 161	u8 data[];
 162};
 163
 164enum ath10k_fw_ie_type {
 165	ATH10K_FW_IE_FW_VERSION = 0,
 166	ATH10K_FW_IE_TIMESTAMP = 1,
 167	ATH10K_FW_IE_FEATURES = 2,
 168	ATH10K_FW_IE_FW_IMAGE = 3,
 169	ATH10K_FW_IE_OTP_IMAGE = 4,
 170
 171	/* WMI "operations" interface version, 32 bit value. Supported from
 172	 * FW API 4 and above.
 173	 */
 174	ATH10K_FW_IE_WMI_OP_VERSION = 5,
 175
 176	/* HTT "operations" interface version, 32 bit value. Supported from
 177	 * FW API 5 and above.
 178	 */
 179	ATH10K_FW_IE_HTT_OP_VERSION = 6,
 180
 181	/* Code swap image for firmware binary */
 182	ATH10K_FW_IE_FW_CODE_SWAP_IMAGE = 7,
 183};
 184
 185enum ath10k_fw_wmi_op_version {
 186	ATH10K_FW_WMI_OP_VERSION_UNSET = 0,
 187
 188	ATH10K_FW_WMI_OP_VERSION_MAIN = 1,
 189	ATH10K_FW_WMI_OP_VERSION_10_1 = 2,
 190	ATH10K_FW_WMI_OP_VERSION_10_2 = 3,
 191	ATH10K_FW_WMI_OP_VERSION_TLV = 4,
 192	ATH10K_FW_WMI_OP_VERSION_10_2_4 = 5,
 193	ATH10K_FW_WMI_OP_VERSION_10_4 = 6,
 194
 195	/* keep last */
 196	ATH10K_FW_WMI_OP_VERSION_MAX,
 197};
 198
 199enum ath10k_fw_htt_op_version {
 200	ATH10K_FW_HTT_OP_VERSION_UNSET = 0,
 201
 202	ATH10K_FW_HTT_OP_VERSION_MAIN = 1,
 203
 204	/* also used in 10.2 and 10.2.4 branches */
 205	ATH10K_FW_HTT_OP_VERSION_10_1 = 2,
 206
 207	ATH10K_FW_HTT_OP_VERSION_TLV = 3,
 208
 209	ATH10K_FW_HTT_OP_VERSION_10_4 = 4,
 210
 211	/* keep last */
 212	ATH10K_FW_HTT_OP_VERSION_MAX,
 213};
 214
 215enum ath10k_bd_ie_type {
 216	/* contains sub IEs of enum ath10k_bd_ie_board_type */
 217	ATH10K_BD_IE_BOARD = 0,
 218	ATH10K_BD_IE_BOARD_EXT = 1,
 219};
 220
 221enum ath10k_bd_ie_board_type {
 222	ATH10K_BD_IE_BOARD_NAME = 0,
 223	ATH10K_BD_IE_BOARD_DATA = 1,
 224};
 225
 226enum ath10k_hw_rev {
 227	ATH10K_HW_QCA988X,
 228	ATH10K_HW_QCA6174,
 229	ATH10K_HW_QCA99X0,
 230	ATH10K_HW_QCA9888,
 231	ATH10K_HW_QCA9984,
 232	ATH10K_HW_QCA9377,
 233	ATH10K_HW_QCA4019,
 234	ATH10K_HW_QCA9887,
 235	ATH10K_HW_WCN3990,
 236};
 237
 238struct ath10k_hw_regs {
 239	u32 rtc_soc_base_address;
 240	u32 rtc_wmac_base_address;
 241	u32 soc_core_base_address;
 242	u32 wlan_mac_base_address;
 243	u32 ce_wrapper_base_address;
 244	u32 ce0_base_address;
 245	u32 ce1_base_address;
 246	u32 ce2_base_address;
 247	u32 ce3_base_address;
 248	u32 ce4_base_address;
 249	u32 ce5_base_address;
 250	u32 ce6_base_address;
 251	u32 ce7_base_address;
 252	u32 ce8_base_address;
 253	u32 ce9_base_address;
 254	u32 ce10_base_address;
 255	u32 ce11_base_address;
 256	u32 soc_reset_control_si0_rst_mask;
 257	u32 soc_reset_control_ce_rst_mask;
 258	u32 soc_chip_id_address;
 259	u32 scratch_3_address;
 260	u32 fw_indicator_address;
 261	u32 pcie_local_base_address;
 262	u32 ce_wrap_intr_sum_host_msi_lsb;
 263	u32 ce_wrap_intr_sum_host_msi_mask;
 264	u32 pcie_intr_fw_mask;
 265	u32 pcie_intr_ce_mask_all;
 266	u32 pcie_intr_clr_address;
 267	u32 cpu_pll_init_address;
 268	u32 cpu_speed_address;
 269	u32 core_clk_div_address;
 270};
 271
 272extern const struct ath10k_hw_regs qca988x_regs;
 273extern const struct ath10k_hw_regs qca6174_regs;
 274extern const struct ath10k_hw_regs qca99x0_regs;
 275extern const struct ath10k_hw_regs qca4019_regs;
 276extern const struct ath10k_hw_regs wcn3990_regs;
 277
 278struct ath10k_hw_ce_regs_addr_map {
 279	u32 msb;
 280	u32 lsb;
 281	u32 mask;
 282};
 283
 284struct ath10k_hw_ce_ctrl1 {
 285	u32 addr;
 286	u32 hw_mask;
 287	u32 sw_mask;
 288	u32 hw_wr_mask;
 289	u32 sw_wr_mask;
 290	u32 reset_mask;
 291	u32 reset;
 292	const struct ath10k_hw_ce_regs_addr_map *src_ring;
 293	const struct ath10k_hw_ce_regs_addr_map *dst_ring;
 294	const struct ath10k_hw_ce_regs_addr_map *dmax;
 295};
 296
 297struct ath10k_hw_ce_cmd_halt {
 298	u32 status_reset;
 299	u32 msb;
 300	u32 mask;
 301	const struct ath10k_hw_ce_regs_addr_map *status;
 302};
 303
 304struct ath10k_hw_ce_host_ie {
 305	u32 copy_complete_reset;
 306	const struct ath10k_hw_ce_regs_addr_map *copy_complete;
 307};
 308
 309struct ath10k_hw_ce_host_wm_regs {
 310	u32 dstr_lmask;
 311	u32 dstr_hmask;
 312	u32 srcr_lmask;
 313	u32 srcr_hmask;
 314	u32 cc_mask;
 315	u32 wm_mask;
 316	u32 addr;
 317};
 318
 319struct ath10k_hw_ce_misc_regs {
 320	u32 axi_err;
 321	u32 dstr_add_err;
 322	u32 srcr_len_err;
 323	u32 dstr_mlen_vio;
 324	u32 dstr_overflow;
 325	u32 srcr_overflow;
 326	u32 err_mask;
 327	u32 addr;
 328};
 329
 330struct ath10k_hw_ce_dst_src_wm_regs {
 331	u32 addr;
 332	u32 low_rst;
 333	u32 high_rst;
 334	const struct ath10k_hw_ce_regs_addr_map *wm_low;
 335	const struct ath10k_hw_ce_regs_addr_map *wm_high;
 336};
 337
 338struct ath10k_hw_ce_ctrl1_upd {
 339	u32 shift;
 340	u32 mask;
 341	u32 enable;
 342};
 343
 344struct ath10k_hw_ce_regs {
 345	u32 sr_base_addr_lo;
 346	u32 sr_base_addr_hi;
 347	u32 sr_size_addr;
 348	u32 dr_base_addr_lo;
 349	u32 dr_base_addr_hi;
 350	u32 dr_size_addr;
 351	u32 ce_cmd_addr;
 352	u32 misc_ie_addr;
 353	u32 sr_wr_index_addr;
 354	u32 dst_wr_index_addr;
 355	u32 current_srri_addr;
 356	u32 current_drri_addr;
 357	u32 ddr_addr_for_rri_low;
 358	u32 ddr_addr_for_rri_high;
 359	u32 ce_rri_low;
 360	u32 ce_rri_high;
 361	u32 host_ie_addr;
 362	const struct ath10k_hw_ce_host_wm_regs *wm_regs;
 363	const struct ath10k_hw_ce_misc_regs *misc_regs;
 364	const struct ath10k_hw_ce_ctrl1 *ctrl1_regs;
 365	const struct ath10k_hw_ce_cmd_halt *cmd_halt;
 366	const struct ath10k_hw_ce_host_ie *host_ie;
 367	const struct ath10k_hw_ce_dst_src_wm_regs *wm_srcr;
 368	const struct ath10k_hw_ce_dst_src_wm_regs *wm_dstr;
 369	const struct ath10k_hw_ce_ctrl1_upd *upd;
 370};
 371
 372struct ath10k_hw_values {
 373	u32 rtc_state_val_on;
 374	u8 ce_count;
 375	u8 msi_assign_ce_max;
 376	u8 num_target_ce_config_wlan;
 377	u16 ce_desc_meta_data_mask;
 378	u8 ce_desc_meta_data_lsb;
 379	u32 rfkill_pin;
 380	u32 rfkill_cfg;
 381	bool rfkill_on_level;
 382};
 383
 384extern const struct ath10k_hw_values qca988x_values;
 385extern const struct ath10k_hw_values qca6174_values;
 386extern const struct ath10k_hw_values qca99x0_values;
 387extern const struct ath10k_hw_values qca9888_values;
 388extern const struct ath10k_hw_values qca4019_values;
 389extern const struct ath10k_hw_values wcn3990_values;
 390extern const struct ath10k_hw_ce_regs wcn3990_ce_regs;
 391extern const struct ath10k_hw_ce_regs qcax_ce_regs;
 392
 393void ath10k_hw_fill_survey_time(struct ath10k *ar, struct survey_info *survey,
 394				u32 cc, u32 rcc, u32 cc_prev, u32 rcc_prev);
 395
 396int ath10k_hw_diag_fast_download(struct ath10k *ar,
 397				 u32 address,
 398				 const void *buffer,
 399				 u32 length);
 400
 401#define QCA_REV_988X(ar) ((ar)->hw_rev == ATH10K_HW_QCA988X)
 402#define QCA_REV_9887(ar) ((ar)->hw_rev == ATH10K_HW_QCA9887)
 403#define QCA_REV_6174(ar) ((ar)->hw_rev == ATH10K_HW_QCA6174)
 404#define QCA_REV_99X0(ar) ((ar)->hw_rev == ATH10K_HW_QCA99X0)
 405#define QCA_REV_9888(ar) ((ar)->hw_rev == ATH10K_HW_QCA9888)
 406#define QCA_REV_9984(ar) ((ar)->hw_rev == ATH10K_HW_QCA9984)
 407#define QCA_REV_9377(ar) ((ar)->hw_rev == ATH10K_HW_QCA9377)
 408#define QCA_REV_40XX(ar) ((ar)->hw_rev == ATH10K_HW_QCA4019)
 409#define QCA_REV_WCN3990(ar) ((ar)->hw_rev == ATH10K_HW_WCN3990)
 410
 411/* Known peculiarities:
 412 *  - raw appears in nwifi decap, raw and nwifi appear in ethernet decap
 413 *  - raw have FCS, nwifi doesn't
 414 *  - ethernet frames have 802.11 header decapped and parts (base hdr, cipher
 415 *    param, llc/snap) are aligned to 4byte boundaries each
 416 */
 417enum ath10k_hw_txrx_mode {
 418	ATH10K_HW_TXRX_RAW = 0,
 419
 420	/* Native Wifi decap mode is used to align IP frames to 4-byte
 421	 * boundaries and avoid a very expensive re-alignment in mac80211.
 422	 */
 423	ATH10K_HW_TXRX_NATIVE_WIFI = 1,
 424	ATH10K_HW_TXRX_ETHERNET = 2,
 425
 426	/* Valid for HTT >= 3.0. Used for management frames in TX_FRM. */
 427	ATH10K_HW_TXRX_MGMT = 3,
 428};
 429
 430enum ath10k_mcast2ucast_mode {
 431	ATH10K_MCAST2UCAST_DISABLED = 0,
 432	ATH10K_MCAST2UCAST_ENABLED = 1,
 433};
 434
 435enum ath10k_hw_rate_ofdm {
 436	ATH10K_HW_RATE_OFDM_48M = 0,
 437	ATH10K_HW_RATE_OFDM_24M,
 438	ATH10K_HW_RATE_OFDM_12M,
 439	ATH10K_HW_RATE_OFDM_6M,
 440	ATH10K_HW_RATE_OFDM_54M,
 441	ATH10K_HW_RATE_OFDM_36M,
 442	ATH10K_HW_RATE_OFDM_18M,
 443	ATH10K_HW_RATE_OFDM_9M,
 444};
 445
 446enum ath10k_hw_rate_cck {
 447	ATH10K_HW_RATE_CCK_LP_11M = 0,
 448	ATH10K_HW_RATE_CCK_LP_5_5M,
 449	ATH10K_HW_RATE_CCK_LP_2M,
 450	ATH10K_HW_RATE_CCK_LP_1M,
 451	ATH10K_HW_RATE_CCK_SP_11M,
 452	ATH10K_HW_RATE_CCK_SP_5_5M,
 453	ATH10K_HW_RATE_CCK_SP_2M,
 454};
 455
 456enum ath10k_hw_rate_rev2_cck {
 457	ATH10K_HW_RATE_REV2_CCK_LP_1M = 1,
 458	ATH10K_HW_RATE_REV2_CCK_LP_2M,
 459	ATH10K_HW_RATE_REV2_CCK_LP_5_5M,
 460	ATH10K_HW_RATE_REV2_CCK_LP_11M,
 461	ATH10K_HW_RATE_REV2_CCK_SP_2M,
 462	ATH10K_HW_RATE_REV2_CCK_SP_5_5M,
 463	ATH10K_HW_RATE_REV2_CCK_SP_11M,
 464};
 465
 466enum ath10k_hw_cc_wraparound_type {
 467	ATH10K_HW_CC_WRAP_DISABLED = 0,
 468
 469	/* This type is when the HW chip has a quirky Cycle Counter
 470	 * wraparound which resets to 0x7fffffff instead of 0. All
 471	 * other CC related counters (e.g. Rx Clear Count) are divided
 472	 * by 2 so they never wraparound themselves.
 473	 */
 474	ATH10K_HW_CC_WRAP_SHIFTED_ALL = 1,
 475
 476	/* Each hw counter wraps around independently. When the
 477	 * counter overflows the respective counter is right shifted
 478	 * by 1, i.e reset to 0x7fffffff, and other counters will be
 479	 * running unaffected. In this type of wraparound, it should
 480	 * be possible to report accurate Rx busy time unlike the
 481	 * first type.
 482	 */
 483	ATH10K_HW_CC_WRAP_SHIFTED_EACH = 2,
 484};
 485
 486enum ath10k_hw_refclk_speed {
 487	ATH10K_HW_REFCLK_UNKNOWN = -1,
 488	ATH10K_HW_REFCLK_48_MHZ = 0,
 489	ATH10K_HW_REFCLK_19_2_MHZ = 1,
 490	ATH10K_HW_REFCLK_24_MHZ = 2,
 491	ATH10K_HW_REFCLK_26_MHZ = 3,
 492	ATH10K_HW_REFCLK_37_4_MHZ = 4,
 493	ATH10K_HW_REFCLK_38_4_MHZ = 5,
 494	ATH10K_HW_REFCLK_40_MHZ = 6,
 495	ATH10K_HW_REFCLK_52_MHZ = 7,
 496
 497	/* must be the last one */
 498	ATH10K_HW_REFCLK_COUNT,
 499};
 500
 501struct ath10k_hw_clk_params {
 502	u32 refclk;
 503	u32 div;
 504	u32 rnfrac;
 505	u32 settle_time;
 506	u32 refdiv;
 507	u32 outdiv;
 508};
 509
 510struct htt_rx_desc_ops;
 511
 512struct ath10k_hw_params {
 513	u32 id;
 514	u16 dev_id;
 515	enum ath10k_bus bus;
 516	const char *name;
 517	u32 patch_load_addr;
 518	int uart_pin;
 519	int led_pin;
 520	u32 otp_exe_param;
 521
 522	/* Type of hw cycle counter wraparound logic, for more info
 523	 * refer enum ath10k_hw_cc_wraparound_type.
 524	 */
 525	enum ath10k_hw_cc_wraparound_type cc_wraparound_type;
 526
 527	/* Some of chip expects fragment descriptor to be continuous
 528	 * memory for any TX operation. Set continuous_frag_desc flag
 529	 * for the hardware which have such requirement.
 530	 */
 531	bool continuous_frag_desc;
 532
 533	/* CCK hardware rate table mapping for the newer chipsets
 534	 * like QCA99X0, QCA4019 got revised. The CCK h/w rate values
 535	 * are in a proper order with respect to the rate/preamble
 536	 */
 537	bool cck_rate_map_rev2;
 538
 539	u32 channel_counters_freq_hz;
 540
 541	/* Mgmt tx descriptors threshold for limiting probe response
 542	 * frames.
 543	 */
 544	u32 max_probe_resp_desc_thres;
 545
 546	u32 tx_chain_mask;
 547	u32 rx_chain_mask;
 548	u32 max_spatial_stream;
 549	u32 cal_data_len;
 550
 551	struct ath10k_hw_params_fw {
 552		const char *dir;
 553		size_t board_size;
 554		size_t ext_board_size;
 555		size_t board_ext_size;
 556	} fw;
 557
 558	/* qca99x0 family chips deliver broadcast/multicast management
 559	 * frames encrypted and expect software do decryption.
 560	 */
 561	bool sw_decrypt_mcast_mgmt;
 562
 563	/* Rx descriptor abstraction */
 564	const struct ath10k_htt_rx_desc_ops *rx_desc_ops;
 565
 566	const struct ath10k_hw_ops *hw_ops;
 567
 568	/* Number of bytes used for alignment in rx_hdr_status of rx desc. */
 569	int decap_align_bytes;
 570
 571	/* hw specific clock control parameters */
 572	const struct ath10k_hw_clk_params *hw_clk;
 573	int target_cpu_freq;
 574
 575	/* Number of bytes to be discarded for each FFT sample */
 576	int spectral_bin_discard;
 577
 578	/* The board may have a restricted NSS for 160 or 80+80 vs what it
 579	 * can do for 80Mhz.
 580	 */
 581	int vht160_mcs_rx_highest;
 582	int vht160_mcs_tx_highest;
 583
 584	/* Number of ciphers supported (i.e First N) in cipher_suites array */
 585	int n_cipher_suites;
 586
 587	u32 num_peers;
 588	u32 ast_skid_limit;
 589	u32 num_wds_entries;
 590
 591	/* Targets supporting physical addressing capability above 32-bits */
 592	bool target_64bit;
 593
 594	/* Target rx ring fill level */
 595	u32 rx_ring_fill_level;
 596
 597	/* target supporting shadow register for ce write */
 598	bool shadow_reg_support;
 599
 600	/* target supporting retention restore on ddr */
 601	bool rri_on_ddr;
 602
 603	/* Number of bytes to be the offset for each FFT sample */
 604	int spectral_bin_offset;
 605
 606	/* targets which require hw filter reset during boot up,
 607	 * to avoid it sending spurious acks.
 608	 */
 609	bool hw_filter_reset_required;
 610
 611	/* target supporting fw download via diag ce */
 612	bool fw_diag_ce_download;
 613
 614	/* target supporting fw download via large size BMI */
 615	bool bmi_large_size_download;
 616
 617	/* need to set uart pin if disable uart print, workaround for a
 618	 * firmware bug
 619	 */
 620	bool uart_pin_workaround;
 621
 622	/* Workaround for the credit size calculation */
 623	bool credit_size_workaround;
 624
 625	/* tx stats support over pktlog */
 626	bool tx_stats_over_pktlog;
 627
 628	/* provides bitrates for sta_statistics using WMI_TLV_PEER_STATS_INFO_EVENTID */
 629	bool supports_peer_stats_info;
 630
 631	bool dynamic_sar_support;
 632
 633	bool hw_restart_disconnect;
 634
 635	bool use_fw_tx_credits;
 636
 637	bool delay_unmap_buffer;
 638
 639	/* The hardware support multicast frame registrations */
 640	bool mcast_frame_registration;
 641};
 642
 643struct htt_resp;
 644struct htt_data_tx_completion_ext;
 645struct htt_rx_ring_rx_desc_offsets;
 646
 647/* Defines needed for Rx descriptor abstraction */
 648struct ath10k_hw_ops {
 649	void (*set_coverage_class)(struct ath10k *ar, int radio_idx, s16 value);
 650	int (*enable_pll_clk)(struct ath10k *ar);
 651	int (*tx_data_rssi_pad_bytes)(struct htt_resp *htt);
 652	int (*is_rssi_enable)(struct htt_resp *resp);
 653};
 654
 655extern const struct ath10k_hw_ops qca988x_ops;
 656extern const struct ath10k_hw_ops qca99x0_ops;
 657extern const struct ath10k_hw_ops qca6174_ops;
 658extern const struct ath10k_hw_ops qca6174_sdio_ops;
 659extern const struct ath10k_hw_ops wcn3990_ops;
 660
 661extern const struct ath10k_hw_clk_params qca6174_clk[];
 662
 663static inline int
 664ath10k_tx_data_rssi_get_pad_bytes(struct ath10k_hw_params *hw,
 665				  struct htt_resp *htt)
 666{
 667	if (hw->hw_ops->tx_data_rssi_pad_bytes)
 668		return hw->hw_ops->tx_data_rssi_pad_bytes(htt);
 669	return 0;
 670}
 671
 672static inline int
 673ath10k_is_rssi_enable(struct ath10k_hw_params *hw,
 674		      struct htt_resp *resp)
 675{
 676	if (hw->hw_ops->is_rssi_enable)
 677		return hw->hw_ops->is_rssi_enable(resp);
 678	return 0;
 679}
 680
 681/* Target specific defines for MAIN firmware */
 682#define TARGET_NUM_VDEVS			8
 683#define TARGET_NUM_PEER_AST			2
 684#define TARGET_NUM_WDS_ENTRIES			32
 685#define TARGET_DMA_BURST_SIZE			0
 686#define TARGET_MAC_AGGR_DELIM			0
 687#define TARGET_AST_SKID_LIMIT			16
 688#define TARGET_NUM_STATIONS			16
 689#define TARGET_NUM_PEERS			((TARGET_NUM_STATIONS) + \
 690						 (TARGET_NUM_VDEVS))
 691#define TARGET_NUM_OFFLOAD_PEERS		0
 692#define TARGET_NUM_OFFLOAD_REORDER_BUFS         0
 693#define TARGET_NUM_PEER_KEYS			2
 694#define TARGET_NUM_TIDS				((TARGET_NUM_PEERS) * 2)
 695#define TARGET_TX_CHAIN_MASK			(BIT(0) | BIT(1) | BIT(2))
 696#define TARGET_RX_CHAIN_MASK			(BIT(0) | BIT(1) | BIT(2))
 697#define TARGET_RX_TIMEOUT_LO_PRI		100
 698#define TARGET_RX_TIMEOUT_HI_PRI		40
 699
 700#define TARGET_SCAN_MAX_PENDING_REQS		4
 701#define TARGET_BMISS_OFFLOAD_MAX_VDEV		3
 702#define TARGET_ROAM_OFFLOAD_MAX_VDEV		3
 703#define TARGET_ROAM_OFFLOAD_MAX_AP_PROFILES	8
 704#define TARGET_GTK_OFFLOAD_MAX_VDEV		3
 705#define TARGET_NUM_MCAST_GROUPS			0
 706#define TARGET_NUM_MCAST_TABLE_ELEMS		0
 707#define TARGET_MCAST2UCAST_MODE			ATH10K_MCAST2UCAST_DISABLED
 708#define TARGET_TX_DBG_LOG_SIZE			1024
 709#define TARGET_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 0
 710#define TARGET_VOW_CONFIG			0
 711#define TARGET_NUM_MSDU_DESC			(1024 + 400)
 712#define TARGET_MAX_FRAG_ENTRIES			0
 713
 714/* Target specific defines for 10.X firmware */
 715#define TARGET_10X_NUM_VDEVS			16
 716#define TARGET_10X_NUM_PEER_AST			2
 717#define TARGET_10X_NUM_WDS_ENTRIES		32
 718#define TARGET_10X_DMA_BURST_SIZE		0
 719#define TARGET_10X_MAC_AGGR_DELIM		0
 720#define TARGET_10X_AST_SKID_LIMIT		128
 721#define TARGET_10X_NUM_STATIONS			128
 722#define TARGET_10X_TX_STATS_NUM_STATIONS	118
 723#define TARGET_10X_NUM_PEERS			((TARGET_10X_NUM_STATIONS) + \
 724						 (TARGET_10X_NUM_VDEVS))
 725#define TARGET_10X_TX_STATS_NUM_PEERS		((TARGET_10X_TX_STATS_NUM_STATIONS) + \
 726						 (TARGET_10X_NUM_VDEVS))
 727#define TARGET_10X_NUM_OFFLOAD_PEERS		0
 728#define TARGET_10X_NUM_OFFLOAD_REORDER_BUFS	0
 729#define TARGET_10X_NUM_PEER_KEYS		2
 730#define TARGET_10X_NUM_TIDS_MAX			256
 731#define TARGET_10X_NUM_TIDS			min((TARGET_10X_NUM_TIDS_MAX), \
 732						    (TARGET_10X_NUM_PEERS) * 2)
 733#define TARGET_10X_TX_STATS_NUM_TIDS		min((TARGET_10X_NUM_TIDS_MAX), \
 734						    (TARGET_10X_TX_STATS_NUM_PEERS) * 2)
 735#define TARGET_10X_TX_CHAIN_MASK		(BIT(0) | BIT(1) | BIT(2))
 736#define TARGET_10X_RX_CHAIN_MASK		(BIT(0) | BIT(1) | BIT(2))
 737#define TARGET_10X_RX_TIMEOUT_LO_PRI		100
 738#define TARGET_10X_RX_TIMEOUT_HI_PRI		40
 739#define TARGET_10X_SCAN_MAX_PENDING_REQS	4
 740#define TARGET_10X_BMISS_OFFLOAD_MAX_VDEV	2
 741#define TARGET_10X_ROAM_OFFLOAD_MAX_VDEV	2
 742#define TARGET_10X_ROAM_OFFLOAD_MAX_AP_PROFILES	8
 743#define TARGET_10X_GTK_OFFLOAD_MAX_VDEV		3
 744#define TARGET_10X_NUM_MCAST_GROUPS		0
 745#define TARGET_10X_NUM_MCAST_TABLE_ELEMS	0
 746#define TARGET_10X_MCAST2UCAST_MODE		ATH10K_MCAST2UCAST_DISABLED
 747#define TARGET_10X_TX_DBG_LOG_SIZE		1024
 748#define TARGET_10X_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
 749#define TARGET_10X_VOW_CONFIG			0
 750#define TARGET_10X_NUM_MSDU_DESC		(1024 + 400)
 751#define TARGET_10X_MAX_FRAG_ENTRIES		0
 752
 753/* 10.2 parameters */
 754#define TARGET_10_2_DMA_BURST_SIZE		0
 755
 756/* Target specific defines for WMI-TLV firmware */
 757#define TARGET_TLV_NUM_VDEVS			4
 758#define TARGET_TLV_NUM_STATIONS			32
 759#define TARGET_TLV_NUM_PEERS			33
 760#define TARGET_TLV_NUM_TDLS_VDEVS		1
 761#define TARGET_TLV_NUM_TIDS			((TARGET_TLV_NUM_PEERS) * 2)
 762#define TARGET_TLV_NUM_MSDU_DESC		(1024 + 32)
 763#define TARGET_TLV_NUM_MSDU_DESC_HL		1024
 764#define TARGET_TLV_NUM_WOW_PATTERNS		22
 765#define TARGET_TLV_MGMT_NUM_MSDU_DESC		(50)
 766
 767/* Target specific defines for WMI-HL-1.0 firmware */
 768#define TARGET_HL_TLV_NUM_PEERS			33
 769#define TARGET_HL_TLV_AST_SKID_LIMIT		16
 770#define TARGET_HL_TLV_NUM_WDS_ENTRIES		2
 771
 772/* Target specific defines for QCA9377 high latency firmware */
 773#define TARGET_QCA9377_HL_NUM_PEERS		15
 774
 775/* Diagnostic Window */
 776#define CE_DIAG_PIPE	7
 777
 778#define NUM_TARGET_CE_CONFIG_WLAN ar->hw_values->num_target_ce_config_wlan
 779
 780/* Target specific defines for 10.4 firmware */
 781#define TARGET_10_4_NUM_VDEVS			16
 782#define TARGET_10_4_NUM_STATIONS		32
 783#define TARGET_10_4_NUM_PEERS			((TARGET_10_4_NUM_STATIONS) + \
 784						 (TARGET_10_4_NUM_VDEVS))
 785#define TARGET_10_4_ACTIVE_PEERS		0
 786
 787#define TARGET_10_4_NUM_QCACHE_PEERS_MAX	512
 788#define TARGET_10_4_QCACHE_ACTIVE_PEERS		50
 789#define TARGET_10_4_QCACHE_ACTIVE_PEERS_PFC	35
 790#define TARGET_10_4_NUM_OFFLOAD_PEERS		0
 791#define TARGET_10_4_NUM_OFFLOAD_REORDER_BUFFS	0
 792#define TARGET_10_4_NUM_PEER_KEYS		2
 793#define TARGET_10_4_TGT_NUM_TIDS		((TARGET_10_4_NUM_PEERS) * 2)
 794#define TARGET_10_4_NUM_MSDU_DESC		(1024 + 400)
 795#define TARGET_10_4_NUM_MSDU_DESC_PFC		2500
 796#define TARGET_10_4_AST_SKID_LIMIT		32
 797
 798/* 100 ms for video, best-effort, and background */
 799#define TARGET_10_4_RX_TIMEOUT_LO_PRI		100
 800
 801/* 40 ms for voice */
 802#define TARGET_10_4_RX_TIMEOUT_HI_PRI		40
 803
 804#define TARGET_10_4_RX_DECAP_MODE		ATH10K_HW_TXRX_NATIVE_WIFI
 805#define TARGET_10_4_SCAN_MAX_REQS		4
 806#define TARGET_10_4_BMISS_OFFLOAD_MAX_VDEV	3
 807#define TARGET_10_4_ROAM_OFFLOAD_MAX_VDEV	3
 808#define TARGET_10_4_ROAM_OFFLOAD_MAX_PROFILES   8
 809
 810/* Note: mcast to ucast is disabled by default */
 811#define TARGET_10_4_NUM_MCAST_GROUPS		0
 812#define TARGET_10_4_NUM_MCAST_TABLE_ELEMS	0
 813#define TARGET_10_4_MCAST2UCAST_MODE		0
 814
 815#define TARGET_10_4_TX_DBG_LOG_SIZE		1024
 816#define TARGET_10_4_NUM_WDS_ENTRIES		32
 817#define TARGET_10_4_DMA_BURST_SIZE		1
 818#define TARGET_10_4_MAC_AGGR_DELIM		0
 819#define TARGET_10_4_RX_SKIP_DEFRAG_TIMEOUT_DUP_DETECTION_CHECK 1
 820#define TARGET_10_4_VOW_CONFIG			0
 821#define TARGET_10_4_GTK_OFFLOAD_MAX_VDEV	3
 822#define TARGET_10_4_11AC_TX_MAX_FRAGS		2
 823#define TARGET_10_4_MAX_PEER_EXT_STATS		16
 824#define TARGET_10_4_SMART_ANT_CAP		0
 825#define TARGET_10_4_BK_MIN_FREE			0
 826#define TARGET_10_4_BE_MIN_FREE			0
 827#define TARGET_10_4_VI_MIN_FREE			0
 828#define TARGET_10_4_VO_MIN_FREE			0
 829#define TARGET_10_4_RX_BATCH_MODE		1
 830#define TARGET_10_4_THERMAL_THROTTLING_CONFIG	0
 831#define TARGET_10_4_ATF_CONFIG			0
 832#define TARGET_10_4_IPHDR_PAD_CONFIG		1
 833#define TARGET_10_4_QWRAP_CONFIG		0
 834
 835/* TDLS config */
 836#define TARGET_10_4_NUM_TDLS_VDEVS		1
 837#define TARGET_10_4_NUM_TDLS_BUFFER_STA		1
 838#define TARGET_10_4_NUM_TDLS_SLEEP_STA		1
 839
 840/* Maximum number of Copy Engines supported */
 841#define CE_COUNT_MAX 12
 842
 843/* Number of Copy Engines supported */
 844#define CE_COUNT ar->hw_values->ce_count
 845
 846/*
 847 * Granted MSIs are assigned as follows:
 848 * Firmware uses the first
 849 * Remaining MSIs, if any, are used by Copy Engines
 850 * This mapping is known to both Target firmware and Host software.
 851 * It may be changed as long as Host and Target are kept in sync.
 852 */
 853/* MSI for firmware (errors, etc.) */
 854#define MSI_ASSIGN_FW		0
 855
 856/* MSIs for Copy Engines */
 857#define MSI_ASSIGN_CE_INITIAL	1
 858#define MSI_ASSIGN_CE_MAX	ar->hw_values->msi_assign_ce_max
 859
 860/* as of IP3.7.1 */
 861#define RTC_STATE_V_ON				ar->hw_values->rtc_state_val_on
 862
 863#define RTC_STATE_V_LSB				0
 864#define RTC_STATE_V_MASK			0x00000007
 865#define RTC_STATE_ADDRESS			0x0000
 866#define PCIE_SOC_WAKE_V_MASK			0x00000001
 867#define PCIE_SOC_WAKE_ADDRESS			0x0004
 868#define PCIE_SOC_WAKE_RESET			0x00000000
 869#define SOC_GLOBAL_RESET_ADDRESS		0x0008
 870
 871#define RTC_SOC_BASE_ADDRESS			ar->regs->rtc_soc_base_address
 872#define RTC_WMAC_BASE_ADDRESS			ar->regs->rtc_wmac_base_address
 873#define MAC_COEX_BASE_ADDRESS			0x00006000
 874#define BT_COEX_BASE_ADDRESS			0x00007000
 875#define SOC_PCIE_BASE_ADDRESS			0x00008000
 876#define SOC_CORE_BASE_ADDRESS			ar->regs->soc_core_base_address
 877#define WLAN_UART_BASE_ADDRESS			0x0000c000
 878#define WLAN_SI_BASE_ADDRESS			0x00010000
 879#define WLAN_GPIO_BASE_ADDRESS			0x00014000
 880#define WLAN_ANALOG_INTF_BASE_ADDRESS		0x0001c000
 881#define WLAN_MAC_BASE_ADDRESS			ar->regs->wlan_mac_base_address
 882#define EFUSE_BASE_ADDRESS			0x00030000
 883#define FPGA_REG_BASE_ADDRESS			0x00039000
 884#define WLAN_UART2_BASE_ADDRESS			0x00054c00
 885#define CE_WRAPPER_BASE_ADDRESS			ar->regs->ce_wrapper_base_address
 886#define CE0_BASE_ADDRESS			ar->regs->ce0_base_address
 887#define CE1_BASE_ADDRESS			ar->regs->ce1_base_address
 888#define CE2_BASE_ADDRESS			ar->regs->ce2_base_address
 889#define CE3_BASE_ADDRESS			ar->regs->ce3_base_address
 890#define CE4_BASE_ADDRESS			ar->regs->ce4_base_address
 891#define CE5_BASE_ADDRESS			ar->regs->ce5_base_address
 892#define CE6_BASE_ADDRESS			ar->regs->ce6_base_address
 893#define CE7_BASE_ADDRESS			ar->regs->ce7_base_address
 894#define DBI_BASE_ADDRESS			0x00060000
 895#define WLAN_ANALOG_INTF_PCIE_BASE_ADDRESS	0x0006c000
 896#define PCIE_LOCAL_BASE_ADDRESS		ar->regs->pcie_local_base_address
 897
 898#define SOC_RESET_CONTROL_ADDRESS		0x00000000
 899#define SOC_RESET_CONTROL_OFFSET		0x00000000
 900#define SOC_RESET_CONTROL_SI0_RST_MASK		ar->regs->soc_reset_control_si0_rst_mask
 901#define SOC_RESET_CONTROL_CE_RST_MASK		ar->regs->soc_reset_control_ce_rst_mask
 902#define SOC_RESET_CONTROL_CPU_WARM_RST_MASK	0x00000040
 903#define SOC_CPU_CLOCK_OFFSET			0x00000020
 904#define SOC_CPU_CLOCK_STANDARD_LSB		0
 905#define SOC_CPU_CLOCK_STANDARD_MASK		0x00000003
 906#define SOC_CLOCK_CONTROL_OFFSET		0x00000028
 907#define SOC_CLOCK_CONTROL_SI0_CLK_MASK		0x00000001
 908#define SOC_SYSTEM_SLEEP_OFFSET			0x000000c4
 909#define SOC_LPO_CAL_OFFSET			0x000000e0
 910#define SOC_LPO_CAL_ENABLE_LSB			20
 911#define SOC_LPO_CAL_ENABLE_MASK			0x00100000
 912#define SOC_LF_TIMER_CONTROL0_ADDRESS		0x00000050
 913#define SOC_LF_TIMER_CONTROL0_ENABLE_MASK	0x00000004
 914
 915#define SOC_CHIP_ID_ADDRESS			ar->regs->soc_chip_id_address
 916#define SOC_CHIP_ID_REV_LSB			8
 917#define SOC_CHIP_ID_REV_MASK			0x00000f00
 918
 919#define WLAN_RESET_CONTROL_COLD_RST_MASK	0x00000008
 920#define WLAN_RESET_CONTROL_WARM_RST_MASK	0x00000004
 921#define WLAN_SYSTEM_SLEEP_DISABLE_LSB		0
 922#define WLAN_SYSTEM_SLEEP_DISABLE_MASK		0x00000001
 923
 924#define WLAN_GPIO_PIN0_ADDRESS			0x00000028
 925#define WLAN_GPIO_PIN0_CONFIG_LSB		11
 926#define WLAN_GPIO_PIN0_CONFIG_MASK		0x00007800
 927#define WLAN_GPIO_PIN0_PAD_PULL_LSB		5
 928#define WLAN_GPIO_PIN0_PAD_PULL_MASK		0x00000060
 929#define WLAN_GPIO_PIN1_ADDRESS			0x0000002c
 930#define WLAN_GPIO_PIN1_CONFIG_MASK		0x00007800
 931#define WLAN_GPIO_PIN10_ADDRESS			0x00000050
 932#define WLAN_GPIO_PIN11_ADDRESS			0x00000054
 933#define WLAN_GPIO_PIN12_ADDRESS			0x00000058
 934#define WLAN_GPIO_PIN13_ADDRESS			0x0000005c
 935
 936#define CLOCK_GPIO_OFFSET			0xffffffff
 937#define CLOCK_GPIO_BT_CLK_OUT_EN_LSB		0
 938#define CLOCK_GPIO_BT_CLK_OUT_EN_MASK		0
 939
 940#define SI_CONFIG_OFFSET			0x00000000
 941#define SI_CONFIG_ERR_INT_LSB			19
 942#define SI_CONFIG_ERR_INT_MASK			0x00080000
 943#define SI_CONFIG_BIDIR_OD_DATA_LSB		18
 944#define SI_CONFIG_BIDIR_OD_DATA_MASK		0x00040000
 945#define SI_CONFIG_I2C_LSB			16
 946#define SI_CONFIG_I2C_MASK			0x00010000
 947#define SI_CONFIG_POS_SAMPLE_LSB		7
 948#define SI_CONFIG_POS_SAMPLE_MASK		0x00000080
 949#define SI_CONFIG_INACTIVE_DATA_LSB		5
 950#define SI_CONFIG_INACTIVE_DATA_MASK		0x00000020
 951#define SI_CONFIG_INACTIVE_CLK_LSB		4
 952#define SI_CONFIG_INACTIVE_CLK_MASK		0x00000010
 953#define SI_CONFIG_DIVIDER_LSB			0
 954#define SI_CONFIG_DIVIDER_MASK			0x0000000f
 955#define SI_CS_OFFSET				0x00000004
 956#define SI_CS_DONE_ERR_LSB			10
 957#define SI_CS_DONE_ERR_MASK			0x00000400
 958#define SI_CS_DONE_INT_LSB			9
 959#define SI_CS_DONE_INT_MASK			0x00000200
 960#define SI_CS_START_LSB				8
 961#define SI_CS_START_MASK			0x00000100
 962#define SI_CS_RX_CNT_LSB			4
 963#define SI_CS_RX_CNT_MASK			0x000000f0
 964#define SI_CS_TX_CNT_LSB			0
 965#define SI_CS_TX_CNT_MASK			0x0000000f
 966
 967#define SI_TX_DATA0_OFFSET			0x00000008
 968#define SI_TX_DATA1_OFFSET			0x0000000c
 969#define SI_RX_DATA0_OFFSET			0x00000010
 970#define SI_RX_DATA1_OFFSET			0x00000014
 971
 972#define CORE_CTRL_CPU_INTR_MASK			0x00002000
 973#define CORE_CTRL_PCIE_REG_31_MASK		0x00000800
 974#define CORE_CTRL_ADDRESS			0x0000
 975#define PCIE_INTR_ENABLE_ADDRESS		0x0008
 976#define PCIE_INTR_CAUSE_ADDRESS			0x000c
 977#define PCIE_INTR_CLR_ADDRESS			ar->regs->pcie_intr_clr_address
 978#define SCRATCH_3_ADDRESS			ar->regs->scratch_3_address
 979#define CPU_INTR_ADDRESS			0x0010
 980#define FW_RAM_CONFIG_ADDRESS			0x0018
 981
 982#define CCNT_TO_MSEC(ar, x) ((x) / ar->hw_params.channel_counters_freq_hz)
 983
 984/* Firmware indications to the Host via SCRATCH_3 register. */
 985#define FW_INDICATOR_ADDRESS			ar->regs->fw_indicator_address
 986#define FW_IND_EVENT_PENDING			1
 987#define FW_IND_INITIALIZED			2
 988#define FW_IND_HOST_READY			0x80000000
 989
 990/* HOST_REG interrupt from firmware */
 991#define PCIE_INTR_FIRMWARE_MASK			ar->regs->pcie_intr_fw_mask
 992#define PCIE_INTR_CE_MASK_ALL			ar->regs->pcie_intr_ce_mask_all
 993
 994#define DRAM_BASE_ADDRESS			0x00400000
 995
 996#define PCIE_BAR_REG_ADDRESS			0x40030
 997
 998#define MISSING 0
 999
1000#define SYSTEM_SLEEP_OFFSET			SOC_SYSTEM_SLEEP_OFFSET
1001#define WLAN_SYSTEM_SLEEP_OFFSET		SOC_SYSTEM_SLEEP_OFFSET
1002#define WLAN_RESET_CONTROL_OFFSET		SOC_RESET_CONTROL_OFFSET
1003#define CLOCK_CONTROL_OFFSET			SOC_CLOCK_CONTROL_OFFSET
1004#define CLOCK_CONTROL_SI0_CLK_MASK		SOC_CLOCK_CONTROL_SI0_CLK_MASK
1005#define RESET_CONTROL_MBOX_RST_MASK		MISSING
1006#define RESET_CONTROL_SI0_RST_MASK		SOC_RESET_CONTROL_SI0_RST_MASK
1007#define GPIO_BASE_ADDRESS			WLAN_GPIO_BASE_ADDRESS
1008#define GPIO_PIN0_OFFSET			WLAN_GPIO_PIN0_ADDRESS
1009#define GPIO_PIN1_OFFSET			WLAN_GPIO_PIN1_ADDRESS
1010#define GPIO_PIN0_CONFIG_LSB			WLAN_GPIO_PIN0_CONFIG_LSB
1011#define GPIO_PIN0_CONFIG_MASK			WLAN_GPIO_PIN0_CONFIG_MASK
1012#define GPIO_PIN0_PAD_PULL_LSB			WLAN_GPIO_PIN0_PAD_PULL_LSB
1013#define GPIO_PIN0_PAD_PULL_MASK			WLAN_GPIO_PIN0_PAD_PULL_MASK
1014#define GPIO_PIN1_CONFIG_MASK			WLAN_GPIO_PIN1_CONFIG_MASK
1015#define SI_BASE_ADDRESS				WLAN_SI_BASE_ADDRESS
1016#define SCRATCH_BASE_ADDRESS			SOC_CORE_BASE_ADDRESS
1017#define LOCAL_SCRATCH_OFFSET			0x18
1018#define CPU_CLOCK_OFFSET			SOC_CPU_CLOCK_OFFSET
1019#define LPO_CAL_OFFSET				SOC_LPO_CAL_OFFSET
1020#define GPIO_PIN10_OFFSET			WLAN_GPIO_PIN10_ADDRESS
1021#define GPIO_PIN11_OFFSET			WLAN_GPIO_PIN11_ADDRESS
1022#define GPIO_PIN12_OFFSET			WLAN_GPIO_PIN12_ADDRESS
1023#define GPIO_PIN13_OFFSET			WLAN_GPIO_PIN13_ADDRESS
1024#define CPU_CLOCK_STANDARD_LSB			SOC_CPU_CLOCK_STANDARD_LSB
1025#define CPU_CLOCK_STANDARD_MASK			SOC_CPU_CLOCK_STANDARD_MASK
1026#define LPO_CAL_ENABLE_LSB			SOC_LPO_CAL_ENABLE_LSB
1027#define LPO_CAL_ENABLE_MASK			SOC_LPO_CAL_ENABLE_MASK
1028#define ANALOG_INTF_BASE_ADDRESS		WLAN_ANALOG_INTF_BASE_ADDRESS
1029#define MBOX_BASE_ADDRESS			MISSING
1030#define INT_STATUS_ENABLE_ERROR_LSB		MISSING
1031#define INT_STATUS_ENABLE_ERROR_MASK		MISSING
1032#define INT_STATUS_ENABLE_CPU_LSB		MISSING
1033#define INT_STATUS_ENABLE_CPU_MASK		MISSING
1034#define INT_STATUS_ENABLE_COUNTER_LSB		MISSING
1035#define INT_STATUS_ENABLE_COUNTER_MASK		MISSING
1036#define INT_STATUS_ENABLE_MBOX_DATA_LSB		MISSING
1037#define INT_STATUS_ENABLE_MBOX_DATA_MASK	MISSING
1038#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB	MISSING
1039#define ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK	MISSING
1040#define ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB	MISSING
1041#define ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK	MISSING
1042#define COUNTER_INT_STATUS_ENABLE_BIT_LSB	MISSING
1043#define COUNTER_INT_STATUS_ENABLE_BIT_MASK	MISSING
1044#define INT_STATUS_ENABLE_ADDRESS		MISSING
1045#define CPU_INT_STATUS_ENABLE_BIT_LSB		MISSING
1046#define CPU_INT_STATUS_ENABLE_BIT_MASK		MISSING
1047#define HOST_INT_STATUS_ADDRESS			MISSING
1048#define CPU_INT_STATUS_ADDRESS			MISSING
1049#define ERROR_INT_STATUS_ADDRESS		MISSING
1050#define ERROR_INT_STATUS_WAKEUP_MASK		MISSING
1051#define ERROR_INT_STATUS_WAKEUP_LSB		MISSING
1052#define ERROR_INT_STATUS_RX_UNDERFLOW_MASK	MISSING
1053#define ERROR_INT_STATUS_RX_UNDERFLOW_LSB	MISSING
1054#define ERROR_INT_STATUS_TX_OVERFLOW_MASK	MISSING
1055#define ERROR_INT_STATUS_TX_OVERFLOW_LSB	MISSING
1056#define COUNT_DEC_ADDRESS			MISSING
1057#define HOST_INT_STATUS_CPU_MASK		MISSING
1058#define HOST_INT_STATUS_CPU_LSB			MISSING
1059#define HOST_INT_STATUS_ERROR_MASK		MISSING
1060#define HOST_INT_STATUS_ERROR_LSB		MISSING
1061#define HOST_INT_STATUS_COUNTER_MASK		MISSING
1062#define HOST_INT_STATUS_COUNTER_LSB		MISSING
1063#define RX_LOOKAHEAD_VALID_ADDRESS		MISSING
1064#define WINDOW_DATA_ADDRESS			MISSING
1065#define WINDOW_READ_ADDR_ADDRESS		MISSING
1066#define WINDOW_WRITE_ADDR_ADDRESS		MISSING
1067
1068#define QCA9887_1_0_I2C_SDA_GPIO_PIN		5
1069#define QCA9887_1_0_I2C_SDA_PIN_CONFIG		3
1070#define QCA9887_1_0_SI_CLK_GPIO_PIN		17
1071#define QCA9887_1_0_SI_CLK_PIN_CONFIG		3
1072#define QCA9887_1_0_GPIO_ENABLE_W1TS_LOW_ADDRESS 0x00000010
1073
1074#define QCA9887_EEPROM_SELECT_READ		0xa10000a0
1075#define QCA9887_EEPROM_ADDR_HI_MASK		0x0000ff00
1076#define QCA9887_EEPROM_ADDR_HI_LSB		8
1077#define QCA9887_EEPROM_ADDR_LO_MASK		0x00ff0000
1078#define QCA9887_EEPROM_ADDR_LO_LSB		16
1079
1080#define MBOX_RESET_CONTROL_ADDRESS		0x00000000
1081#define MBOX_HOST_INT_STATUS_ADDRESS		0x00000800
1082#define MBOX_HOST_INT_STATUS_ERROR_LSB		7
1083#define MBOX_HOST_INT_STATUS_ERROR_MASK		0x00000080
1084#define MBOX_HOST_INT_STATUS_CPU_LSB		6
1085#define MBOX_HOST_INT_STATUS_CPU_MASK		0x00000040
1086#define MBOX_HOST_INT_STATUS_COUNTER_LSB	4
1087#define MBOX_HOST_INT_STATUS_COUNTER_MASK	0x00000010
1088#define MBOX_CPU_INT_STATUS_ADDRESS		0x00000801
1089#define MBOX_ERROR_INT_STATUS_ADDRESS		0x00000802
1090#define MBOX_ERROR_INT_STATUS_WAKEUP_LSB	2
1091#define MBOX_ERROR_INT_STATUS_WAKEUP_MASK	0x00000004
1092#define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_LSB	1
1093#define MBOX_ERROR_INT_STATUS_RX_UNDERFLOW_MASK	0x00000002
1094#define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_LSB	0
1095#define MBOX_ERROR_INT_STATUS_TX_OVERFLOW_MASK	0x00000001
1096#define MBOX_COUNTER_INT_STATUS_ADDRESS		0x00000803
1097#define MBOX_COUNTER_INT_STATUS_COUNTER_LSB	0
1098#define MBOX_COUNTER_INT_STATUS_COUNTER_MASK	0x000000ff
1099#define MBOX_RX_LOOKAHEAD_VALID_ADDRESS		0x00000805
1100#define MBOX_INT_STATUS_ENABLE_ADDRESS		0x00000828
1101#define MBOX_INT_STATUS_ENABLE_ERROR_LSB	7
1102#define MBOX_INT_STATUS_ENABLE_ERROR_MASK	0x00000080
1103#define MBOX_INT_STATUS_ENABLE_CPU_LSB		6
1104#define MBOX_INT_STATUS_ENABLE_CPU_MASK		0x00000040
1105#define MBOX_INT_STATUS_ENABLE_INT_LSB		5
1106#define MBOX_INT_STATUS_ENABLE_INT_MASK		0x00000020
1107#define MBOX_INT_STATUS_ENABLE_COUNTER_LSB	4
1108#define MBOX_INT_STATUS_ENABLE_COUNTER_MASK	0x00000010
1109#define MBOX_INT_STATUS_ENABLE_MBOX_DATA_LSB	0
1110#define MBOX_INT_STATUS_ENABLE_MBOX_DATA_MASK	0x0000000f
1111#define MBOX_CPU_INT_STATUS_ENABLE_ADDRESS	0x00000819
1112#define MBOX_CPU_INT_STATUS_ENABLE_BIT_LSB	0
1113#define MBOX_CPU_INT_STATUS_ENABLE_BIT_MASK	0x000000ff
1114#define MBOX_CPU_STATUS_ENABLE_ASSERT_MASK 0x00000001
1115#define MBOX_ERROR_STATUS_ENABLE_ADDRESS	0x0000081a
1116#define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_LSB  1
1117#define MBOX_ERROR_STATUS_ENABLE_RX_UNDERFLOW_MASK 0x00000002
1118#define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_LSB   0
1119#define MBOX_ERROR_STATUS_ENABLE_TX_OVERFLOW_MASK  0x00000001
1120#define MBOX_COUNTER_INT_STATUS_ENABLE_ADDRESS	0x0000081b
1121#define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_LSB	0
1122#define MBOX_COUNTER_INT_STATUS_ENABLE_BIT_MASK	0x000000ff
1123#define MBOX_COUNT_ADDRESS			0x00000820
1124#define MBOX_COUNT_DEC_ADDRESS			0x00000840
1125#define MBOX_WINDOW_DATA_ADDRESS		0x00000874
1126#define MBOX_WINDOW_WRITE_ADDR_ADDRESS		0x00000878
1127#define MBOX_WINDOW_READ_ADDR_ADDRESS		0x0000087c
1128#define MBOX_CPU_DBG_SEL_ADDRESS		0x00000883
1129#define MBOX_CPU_DBG_ADDRESS			0x00000884
1130#define MBOX_RTC_BASE_ADDRESS			0x00000000
1131#define MBOX_GPIO_BASE_ADDRESS			0x00005000
1132#define MBOX_MBOX_BASE_ADDRESS			0x00008000
1133
1134#define RTC_STATE_V_GET(x) (((x) & RTC_STATE_V_MASK) >> RTC_STATE_V_LSB)
1135
1136/* Register definitions for first generation ath10k cards. These cards include
1137 * a mac which has a register allocation similar to ath9k and at least some
1138 * registers including the ones relevant for modifying the coverage class are
1139 * identical to the ath9k definitions.
1140 * These registers are usually managed by the ath10k firmware. However by
1141 * overriding them it is possible to support coverage class modifications.
1142 */
1143#define WAVE1_PCU_ACK_CTS_TIMEOUT		0x8014
1144#define WAVE1_PCU_ACK_CTS_TIMEOUT_MAX		0x00003FFF
1145#define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_MASK	0x00003FFF
1146#define WAVE1_PCU_ACK_CTS_TIMEOUT_ACK_LSB	0
1147#define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_MASK	0x3FFF0000
1148#define WAVE1_PCU_ACK_CTS_TIMEOUT_CTS_LSB	16
1149
1150#define WAVE1_PCU_GBL_IFS_SLOT			0x1070
1151#define WAVE1_PCU_GBL_IFS_SLOT_MASK		0x0000FFFF
1152#define WAVE1_PCU_GBL_IFS_SLOT_MAX		0x0000FFFF
1153#define WAVE1_PCU_GBL_IFS_SLOT_LSB		0
1154#define WAVE1_PCU_GBL_IFS_SLOT_RESV0		0xFFFF0000
1155
1156#define WAVE1_PHYCLK				0x801C
1157#define WAVE1_PHYCLK_USEC_MASK			0x0000007F
1158#define WAVE1_PHYCLK_USEC_LSB			0
1159
1160/* qca6174 PLL offset/mask */
1161#define SOC_CORE_CLK_CTRL_OFFSET		0x00000114
1162#define SOC_CORE_CLK_CTRL_DIV_LSB		0
1163#define SOC_CORE_CLK_CTRL_DIV_MASK		0x00000007
1164
1165#define EFUSE_OFFSET				0x0000032c
1166#define EFUSE_XTAL_SEL_LSB			8
1167#define EFUSE_XTAL_SEL_MASK			0x00000700
1168
1169#define BB_PLL_CONFIG_OFFSET			0x000002f4
1170#define BB_PLL_CONFIG_FRAC_LSB			0
1171#define BB_PLL_CONFIG_FRAC_MASK			0x0003ffff
1172#define BB_PLL_CONFIG_OUTDIV_LSB		18
1173#define BB_PLL_CONFIG_OUTDIV_MASK		0x001c0000
1174
1175#define WLAN_PLL_SETTLE_OFFSET			0x0018
1176#define WLAN_PLL_SETTLE_TIME_LSB		0
1177#define WLAN_PLL_SETTLE_TIME_MASK		0x000007ff
1178
1179#define WLAN_PLL_CONTROL_OFFSET			0x0014
1180#define WLAN_PLL_CONTROL_DIV_LSB		0
1181#define WLAN_PLL_CONTROL_DIV_MASK		0x000003ff
1182#define WLAN_PLL_CONTROL_REFDIV_LSB		10
1183#define WLAN_PLL_CONTROL_REFDIV_MASK		0x00003c00
1184#define WLAN_PLL_CONTROL_BYPASS_LSB		16
1185#define WLAN_PLL_CONTROL_BYPASS_MASK		0x00010000
1186#define WLAN_PLL_CONTROL_NOPWD_LSB		18
1187#define WLAN_PLL_CONTROL_NOPWD_MASK		0x00040000
1188
1189#define RTC_SYNC_STATUS_OFFSET			0x0244
1190#define RTC_SYNC_STATUS_PLL_CHANGING_LSB	5
1191#define RTC_SYNC_STATUS_PLL_CHANGING_MASK	0x00000020
1192/* qca6174 PLL offset/mask end */
1193
1194/* CPU_ADDR_MSB is a register, bit[3:0] is to specify which memory
1195 * region is accessed. The memory region size is 1M.
1196 * If host wants to access 0xX12345 at target, then CPU_ADDR_MSB[3:0]
1197 * is 0xX.
1198 * The following MACROs are defined to get the 0xX and the size limit.
1199 */
1200#define CPU_ADDR_MSB_REGION_MASK	GENMASK(23, 20)
1201#define CPU_ADDR_MSB_REGION_VAL(X)	FIELD_GET(CPU_ADDR_MSB_REGION_MASK, X)
1202#define REGION_ACCESS_SIZE_LIMIT	0x100000
1203#define REGION_ACCESS_SIZE_MASK		(REGION_ACCESS_SIZE_LIMIT - 1)
1204
1205#endif /* _HW_H_ */