pef2256.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * PEF2256 also known as FALC56 driver
  4 *
  5 * Copyright 2023 CS GROUP France
  6 *
  7 * Author: Herve Codina <herve.codina@bootlin.com>
  8 */
  9
 10#include <linux/framer/pef2256.h>
 11#include <linux/clk.h>
 12#include <linux/framer/framer-provider.h>
 13#include <linux/gpio/consumer.h>
 14#include <linux/interrupt.h>
 15#include <linux/io.h>
 16#include <linux/mfd/core.h>
 17#include <linux/module.h>
 18#include <linux/notifier.h>
 19#include <linux/of.h>
 20#include <linux/of_platform.h>
 21#include <linux/platform_device.h>
 22#include <linux/regmap.h>
 23#include <linux/slab.h>
 24#include "pef2256-regs.h"
 25
 26enum pef2256_frame_type {
 27	PEF2256_FRAME_E1_DOUBLEFRAME,
 28	PEF2256_FRAME_E1_CRC4_MULTIFRAME,
 29	PEF2256_FRAME_E1_AUTO_MULTIFRAME,
 30	PEF2256_FRAME_T1J1_4FRAME,
 31	PEF2256_FRAME_T1J1_12FRAME,
 32	PEF2256_FRAME_T1J1_24FRAME,
 33	PEF2256_FRAME_T1J1_72FRAME,
 34};
 35
 36struct pef2256 {
 37	struct device *dev;
 38	struct regmap *regmap;
 39	enum pef2256_version version;
 40	const char *version_txt;
 41	struct clk *mclk;
 42	struct clk *sclkr;
 43	struct clk *sclkx;
 44	struct gpio_desc *reset_gpio;
 45	unsigned long sysclk_rate;
 46	u32 data_rate;
 47	bool is_tx_falling_edge;
 48	bool is_subordinate;
 49	enum pef2256_frame_type frame_type;
 50	u8 channel_phase;
 51	atomic_t carrier;
 52	struct framer *framer;
 53};
 54
 55static u8 pef2256_read8(struct pef2256 *pef2256, int offset)
 56{
 57	int val;
 58
 59	regmap_read(pef2256->regmap, offset, &val);
 60	return val;
 61}
 62
 63static void pef2256_write8(struct pef2256 *pef2256, int offset, u8 val)
 64{
 65	regmap_write(pef2256->regmap, offset, val);
 66}
 67
 68static void pef2256_clrbits8(struct pef2256 *pef2256, int offset, u8 clr)
 69{
 70	regmap_clear_bits(pef2256->regmap, offset, clr);
 71}
 72
 73static void pef2256_setbits8(struct pef2256 *pef2256, int offset, u8 set)
 74{
 75	regmap_set_bits(pef2256->regmap, offset, set);
 76}
 77
 78static void pef2256_clrsetbits8(struct pef2256 *pef2256, int offset, u8 clr, u8 set)
 79{
 80	regmap_update_bits(pef2256->regmap, offset, clr | set, set);
 81}
 82
 83enum pef2256_version pef2256_get_version(struct pef2256 *pef2256)
 84{
 85	enum pef2256_version version = PEF2256_VERSION_UNKNOWN;
 86	u8 vstr, wid;
 87
 88	vstr = pef2256_read8(pef2256, PEF2256_VSTR);
 89	wid = pef2256_read8(pef2256, PEF2256_WID);
 90
 91	switch (vstr) {
 92	case PEF2256_VSTR_VERSION_12:
 93		if ((wid & PEF2256_12_WID_MASK) == PEF2256_12_WID_VERSION_12)
 94			version = PEF2256_VERSION_1_2;
 95		break;
 96	case PEF2256_VSTR_VERSION_2x:
 97		switch (wid & PEF2256_2X_WID_MASK) {
 98		case PEF2256_2X_WID_VERSION_21:
 99			version = PEF2256_VERSION_2_1;
100			break;
101		case PEF2256_2X_WID_VERSION_22:
102			version = PEF2256_VERSION_2_2;
103			break;
104		}
105		break;
106	case PEF2256_VSTR_VERSION_21:
107		version = PEF2256_VERSION_2_1;
108		break;
109	}
110
111	if (version == PEF2256_VERSION_UNKNOWN)
112		dev_err(pef2256->dev, "Unknown version (0x%02x, 0x%02x)\n", vstr, wid);
113
114	return version;
115}
116EXPORT_SYMBOL_GPL(pef2256_get_version);
117
118static ssize_t version_show(struct device *dev, struct device_attribute *attr,
119			    char *buf)
120{
121	struct pef2256 *pef2256 = dev_get_drvdata(dev);
122
123	return sysfs_emit(buf, "%s\n", pef2256->version_txt);
124}
125
126static DEVICE_ATTR_RO(version);
127
128enum pef2256_gcm_config_item {
129	PEF2256_GCM_CONFIG_1544000 = 0,
130	PEF2256_GCM_CONFIG_2048000,
131	PEF2256_GCM_CONFIG_8192000,
132	PEF2256_GCM_CONFIG_10000000,
133	PEF2256_GCM_CONFIG_12352000,
134	PEF2256_GCM_CONFIG_16384000,
135};
136
137struct pef2256_gcm_config {
138	u8 gcm_12[6];
139	u8 gcm_2x[8];
140};
141
142static const struct pef2256_gcm_config pef2256_gcm_configs[] = {
143	[PEF2256_GCM_CONFIG_1544000] = {
144		.gcm_12 = {0xF0, 0x51, 0x00, 0x80, 0x00, 0x15},
145		.gcm_2x = {0x00, 0x15, 0x00, 0x08, 0x00, 0x3F, 0x9C, 0xDF},
146	},
147	[PEF2256_GCM_CONFIG_2048000] = {
148		.gcm_12 = {0x00, 0x58, 0xD2, 0xC2, 0x00, 0x10},
149		.gcm_2x = {0x00, 0x18, 0xFB, 0x0B, 0x00, 0x2F, 0xDB, 0xDF},
150	},
151	[PEF2256_GCM_CONFIG_8192000] = {
152		.gcm_12 = {0x00, 0x58, 0xD2, 0xC2, 0x03, 0x10},
153		.gcm_2x = {0x00, 0x18, 0xFB, 0x0B, 0x00, 0x0B, 0xDB, 0xDF},
154	},
155	[PEF2256_GCM_CONFIG_10000000] = {
156		.gcm_12 = {0x90, 0x51, 0x81, 0x8F, 0x04, 0x10},
157		.gcm_2x = {0x40, 0x1B, 0x3D, 0x0A, 0x00, 0x07, 0xC9, 0xDC},
158	},
159	[PEF2256_GCM_CONFIG_12352000] = {
160		.gcm_12 = {0xF0, 0x51, 0x00, 0x80, 0x07, 0x15},
161		.gcm_2x = {0x00, 0x19, 0x00, 0x08, 0x01, 0x0A, 0x98, 0xDA},
162	},
163	[PEF2256_GCM_CONFIG_16384000] = {
164		.gcm_12 = {0x00, 0x58, 0xD2, 0xC2, 0x07, 0x10},
165		.gcm_2x = {0x00, 0x18, 0xFB, 0x0B, 0x01, 0x0B, 0xDB, 0xDF},
166	},
167};
168
169static int pef2256_setup_gcm(struct pef2256 *pef2256)
170{
171	enum pef2256_gcm_config_item item;
172	unsigned long mclk_rate;
173	const u8 *gcm;
174	int i, count;
175
176	mclk_rate = clk_get_rate(pef2256->mclk);
177	switch (mclk_rate) {
178	case 1544000:
179		item = PEF2256_GCM_CONFIG_1544000;
180		break;
181	case 2048000:
182		item = PEF2256_GCM_CONFIG_2048000;
183		break;
184	case 8192000:
185		item = PEF2256_GCM_CONFIG_8192000;
186		break;
187	case 10000000:
188		item = PEF2256_GCM_CONFIG_10000000;
189		break;
190	case 12352000:
191		item = PEF2256_GCM_CONFIG_12352000;
192		break;
193	case 16384000:
194		item = PEF2256_GCM_CONFIG_16384000;
195		break;
196	default:
197		dev_err(pef2256->dev, "Unsupported v2.x MCLK rate %lu\n", mclk_rate);
198		return -EINVAL;
199	}
200
201	BUILD_BUG_ON(item >= ARRAY_SIZE(pef2256_gcm_configs));
202
203	if (pef2256->version == PEF2256_VERSION_1_2) {
204		gcm = pef2256_gcm_configs[item].gcm_12;
205		count = ARRAY_SIZE(pef2256_gcm_configs[item].gcm_12);
206	} else {
207		gcm = pef2256_gcm_configs[item].gcm_2x;
208		count = ARRAY_SIZE(pef2256_gcm_configs[item].gcm_2x);
209	}
210
211	for (i = 0; i < count; i++)
212		pef2256_write8(pef2256, PEF2256_GCM(i + 1), *(gcm + i));
213
214	return 0;
215}
216
217static int pef2256_setup_e1_line(struct pef2256 *pef2256)
218{
219	u8 fmr1, fmr2;
220
221	/* RCLK output : DPLL clock, DCO-X enabled, DCO-X internal ref clock */
222	pef2256_write8(pef2256, PEF2256_CMR1, 0x00);
223
224	/* SCLKR selected, SCLKX selected,
225	 * receive synchro pulse sourced by SYPR,
226	 * transmit synchro pulse sourced by SYPX,
227	 * DCO-X center frequency enabled
228	 */
229	pef2256_write8(pef2256, PEF2256_CMR2, PEF2256_CMR2_DCOXC);
230
231	if (pef2256->is_subordinate) {
232		/* select RCLK source = 2M,  disable switching from RCLK to SYNC */
233		pef2256_clrsetbits8(pef2256, PEF2256_CMR1, PEF2256_CMR1_RS_MASK,
234				    PEF2256_CMR1_RS_DCOR_2048 | PEF2256_CMR1_DCS);
235	}
236
237	/* slave mode, local loop off, mode short-haul
238	 * In v2.x, bit3 is a forced 1 bit in the datasheet -> Need to be set.
239	 */
240	if (pef2256->version == PEF2256_VERSION_1_2)
241		pef2256_write8(pef2256, PEF2256_LIM0, 0x00);
242	else
243		pef2256_write8(pef2256, PEF2256_LIM0, PEF2256_2X_LIM0_BIT3);
244
245	/* "master" mode */
246	if (!pef2256->is_subordinate)
247		pef2256_setbits8(pef2256, PEF2256_LIM0, PEF2256_LIM0_MAS);
248
249	/* analog interface selected, remote loop off */
250	pef2256_write8(pef2256, PEF2256_LIM1, 0x00);
251
252	/* receive input threshold = 0,21V */
253	if (pef2256->version == PEF2256_VERSION_1_2)
254		pef2256_clrsetbits8(pef2256, PEF2256_LIM1, PEF2256_12_LIM1_RIL_MASK,
255				    PEF2256_12_LIM1_RIL_210);
256	else
257		pef2256_clrsetbits8(pef2256, PEF2256_LIM1, PEF2256_2X_LIM1_RIL_MASK,
258				    PEF2256_2X_LIM1_RIL_210);
259
260	/* transmit pulse mask, default value from datasheet
261	 * transmit line in normal operation
262	 */
263	if (pef2256->version == PEF2256_VERSION_1_2)
264		pef2256_write8(pef2256, PEF2256_XPM0, 0x7B);
265	else
266		pef2256_write8(pef2256, PEF2256_XPM0, 0x9C);
267	pef2256_write8(pef2256, PEF2256_XPM1, 0x03);
268	pef2256_write8(pef2256, PEF2256_XPM2, 0x00);
269
270	/* HDB3 coding, no alarm simulation */
271	pef2256_write8(pef2256, PEF2256_FMR0, PEF2256_FMR0_XC_HDB3 | PEF2256_FMR0_RC_HDB3);
272
273	/* E1, frame format, 2 Mbit/s system data rate, no AIS
274	 * transmission to remote end or system interface, payload loop
275	 * off, transmit remote alarm on
276	 */
277	fmr1 = 0x00;
278	fmr2 = PEF2256_FMR2_AXRA;
279	switch (pef2256->frame_type) {
280	case PEF2256_FRAME_E1_DOUBLEFRAME:
281		fmr2 |= PEF2256_FMR2_RFS_DOUBLEFRAME;
282		break;
283	case PEF2256_FRAME_E1_CRC4_MULTIFRAME:
284		fmr1 |= PEF2256_FMR1_XFS;
285		fmr2 |= PEF2256_FMR2_RFS_CRC4_MULTIFRAME;
286		break;
287	case PEF2256_FRAME_E1_AUTO_MULTIFRAME:
288		fmr1 |= PEF2256_FMR1_XFS;
289		fmr2 |= PEF2256_FMR2_RFS_AUTO_MULTIFRAME;
290		break;
291	default:
292		dev_err(pef2256->dev, "Unsupported frame type %d\n", pef2256->frame_type);
293		return -EINVAL;
294	}
295	pef2256_clrsetbits8(pef2256, PEF2256_FMR1, PEF2256_FMR1_XFS, fmr1);
296	pef2256_write8(pef2256, PEF2256_FMR2, fmr2);
297
298	if (!pef2256->is_subordinate) {
299		/* SEC input, active high */
300		pef2256_write8(pef2256, PEF2256_GPC1, PEF2256_GPC1_CSFP_SEC_IN_HIGH);
301	} else {
302		/* FSC output, active high */
303		pef2256_write8(pef2256, PEF2256_GPC1, PEF2256_GPC1_CSFP_FSC_OUT_HIGH);
304	}
305
306	/* SCLKR, SCLKX, RCLK configured to inputs,
307	 * XFMS active low, CLK1 and CLK2 pin configuration
308	 */
309	pef2256_write8(pef2256, PEF2256_PC5, 0x00);
310	pef2256_write8(pef2256, PEF2256_PC6, 0x00);
311
312	/* port RCLK is output */
313	pef2256_setbits8(pef2256, PEF2256_PC5, PEF2256_PC5_CRP);
314
315	return 0;
316}
317
318static void pef2256_setup_e1_los(struct pef2256 *pef2256)
319{
320	/* detection of LOS alarm = 176 pulses (ie (10 + 1) * 16) */
321	pef2256_write8(pef2256, PEF2256_PCD, 10);
322	/* recovery of LOS alarm = 22 pulses (ie 21 + 1) */
323	pef2256_write8(pef2256, PEF2256_PCR, 21);
324	/* E1 default for the receive slicer threshold */
325	pef2256_write8(pef2256, PEF2256_LIM2, PEF2256_LIM2_SLT_THR50);
326	if (pef2256->is_subordinate) {
327		/* Loop-timed */
328		pef2256_setbits8(pef2256, PEF2256_LIM2, PEF2256_LIM2_ELT);
329	}
330}
331
332static int pef2256_setup_e1_system(struct pef2256 *pef2256)
333{
334	u8 sic1, fmr1;
335
336	/* 2.048 MHz system clocking rate, receive buffer 2 frames, transmit
337	 * buffer bypass, data sampled and transmitted on the falling edge of
338	 * SCLKR/X, automatic freeze signaling, data is active in the first
339	 * channel phase
340	 */
341	pef2256_write8(pef2256, PEF2256_SIC1, 0x00);
342	pef2256_write8(pef2256, PEF2256_SIC2, 0x00);
343	pef2256_write8(pef2256, PEF2256_SIC3, 0x00);
344
345	if (pef2256->is_subordinate) {
346		/* transmit buffer size = 2 frames, transparent mode */
347		pef2256_clrsetbits8(pef2256, PEF2256_SIC1, PEF2256_SIC1_XBS_MASK,
348				    PEF2256_SIC1_XBS_2FRAMES);
349	}
350
351	if (pef2256->version != PEF2256_VERSION_1_2) {
352		/* during inactive channel phase switch RDO/RSIG into tri-state */
353		pef2256_setbits8(pef2256, PEF2256_SIC3, PEF2256_SIC3_RTRI);
354	}
355
356	if (pef2256->is_tx_falling_edge) {
357		/* falling edge sync pulse transmit, rising edge sync pulse receive */
358		pef2256_clrsetbits8(pef2256, PEF2256_SIC3, PEF2256_SIC3_RESX, PEF2256_SIC3_RESR);
359	} else {
360		/* rising edge sync pulse transmit, falling edge sync pulse receive */
361		pef2256_clrsetbits8(pef2256, PEF2256_SIC3, PEF2256_SIC3_RESR, PEF2256_SIC3_RESX);
362	}
363
364	/* transmit offset counter (XCO10..0) = 4 */
365	pef2256_write8(pef2256, PEF2256_XC0, 0);
366	pef2256_write8(pef2256, PEF2256_XC1, 4);
367	/* receive offset counter (RCO10..0) = 4 */
368	pef2256_write8(pef2256, PEF2256_RC0, 0);
369	pef2256_write8(pef2256, PEF2256_RC1, 4);
370
371	/* system clock rate */
372	switch (pef2256->sysclk_rate) {
373	case 2048000:
374		sic1 = PEF2256_SIC1_SSC_2048;
375		break;
376	case 4096000:
377		sic1 = PEF2256_SIC1_SSC_4096;
378		break;
379	case 8192000:
380		sic1 = PEF2256_SIC1_SSC_8192;
381		break;
382	case 16384000:
383		sic1 = PEF2256_SIC1_SSC_16384;
384		break;
385	default:
386		dev_err(pef2256->dev, "Unsupported sysclk rate %lu\n", pef2256->sysclk_rate);
387		return -EINVAL;
388	}
389	pef2256_clrsetbits8(pef2256, PEF2256_SIC1, PEF2256_SIC1_SSC_MASK, sic1);
390
391	/* data clock rate */
392	switch (pef2256->data_rate) {
393	case 2048000:
394		fmr1 = PEF2256_FMR1_SSD_2048;
395		sic1 = PEF2256_SIC1_SSD_2048;
396		break;
397	case 4096000:
398		fmr1 = PEF2256_FMR1_SSD_4096;
399		sic1 = PEF2256_SIC1_SSD_4096;
400		break;
401	case 8192000:
402		fmr1 = PEF2256_FMR1_SSD_8192;
403		sic1 = PEF2256_SIC1_SSD_8192;
404		break;
405	case 16384000:
406		fmr1 = PEF2256_FMR1_SSD_16384;
407		sic1 = PEF2256_SIC1_SSD_16384;
408		break;
409	default:
410		dev_err(pef2256->dev, "Unsupported data rate %u\n", pef2256->data_rate);
411		return -EINVAL;
412	}
413	pef2256_clrsetbits8(pef2256, PEF2256_FMR1, PEF2256_FMR1_SSD_MASK, fmr1);
414	pef2256_clrsetbits8(pef2256, PEF2256_SIC1, PEF2256_SIC1_SSD_MASK, sic1);
415
416	/* channel phase */
417	pef2256_clrsetbits8(pef2256, PEF2256_SIC2, PEF2256_SIC2_SICS_MASK,
418			    PEF2256_SIC2_SICS(pef2256->channel_phase));
419
420	return 0;
421}
422
423static void pef2256_setup_e1_signaling(struct pef2256 *pef2256)
424{
425	/* All bits of the transmitted service word are cleared */
426	pef2256_write8(pef2256, PEF2256_XSW, PEF2256_XSW_XY(0x1F));
427
428	/* CAS disabled and clear spare bit values */
429	pef2256_write8(pef2256, PEF2256_XSP, 0x00);
430
431	if (pef2256->is_subordinate) {
432		/* transparent mode */
433		pef2256_setbits8(pef2256, PEF2256_XSW, PEF2256_XSW_XTM);
434	}
435
436	/* Si-Bit, Spare bit For International, FAS word */
437	pef2256_setbits8(pef2256, PEF2256_XSW, PEF2256_XSW_XSIS);
438	pef2256_setbits8(pef2256, PEF2256_XSP, PEF2256_XSP_XSIF);
439
440	/* no transparent mode active */
441	pef2256_write8(pef2256, PEF2256_TSWM, 0x00);
442}
443
444static void pef2256_setup_e1_errors(struct pef2256 *pef2256)
445{
446	/* error counter latched every 1s */
447	pef2256_setbits8(pef2256, PEF2256_FMR1, PEF2256_FMR1_ECM);
448
449	/* error counter mode COFA */
450	pef2256_setbits8(pef2256, PEF2256_GCR, PEF2256_GCR_ECMC);
451
452	/* errors in service words have no influence */
453	pef2256_setbits8(pef2256, PEF2256_RC0, PEF2256_RC0_SWD);
454
455	/* 4 consecutive incorrect FAS causes loss of sync */
456	pef2256_setbits8(pef2256, PEF2256_RC0, PEF2256_RC0_ASY4);
457}
458
459static int pef2256_setup_e1(struct pef2256 *pef2256)
460{
461	int ret;
462
463	/* Setup, Master clocking mode (GCM8..1) */
464	ret = pef2256_setup_gcm(pef2256);
465	if (ret)
466		return ret;
467
468	/* Select E1 mode */
469	pef2256_write8(pef2256, PEF2256_FMR1, 0x00);
470
471	/* internal second timer, power on */
472	pef2256_write8(pef2256, PEF2256_GCR, 0x00);
473
474	/* Setup line interface */
475	ret = pef2256_setup_e1_line(pef2256);
476	if (ret)
477		return ret;
478
479	/* Setup Loss-of-signal detection and recovery */
480	pef2256_setup_e1_los(pef2256);
481
482	/* Setup system interface */
483	ret = pef2256_setup_e1_system(pef2256);
484	if (ret)
485		return ret;
486
487	/* Setup signaling */
488	pef2256_setup_e1_signaling(pef2256);
489
490	/* Setup errors counters and condition */
491	pef2256_setup_e1_errors(pef2256);
492
493	/* status changed interrupt at both up and down */
494	pef2256_setbits8(pef2256, PEF2256_GCR, PEF2256_GCR_SCI);
495
496	/* Clear any ISR2 pending interrupts and unmask needed interrupts */
497	pef2256_read8(pef2256, PEF2256_ISR2);
498	pef2256_clrbits8(pef2256, PEF2256_IMR2, PEF2256_INT2_LOS | PEF2256_INT2_AIS);
499
500	/* reset lines */
501	pef2256_write8(pef2256, PEF2256_CMDR, PEF2256_CMDR_RRES | PEF2256_CMDR_XRES);
502	return 0;
503}
504
505static void pef2256_isr_default_handler(struct pef2256 *pef2256, u8 nbr, u8 isr)
506{
507	dev_warn_ratelimited(pef2256->dev, "ISR%u: 0x%02x not handled\n", nbr, isr);
508}
509
510static bool pef2256_is_carrier_on(struct pef2256 *pef2256)
511{
512	u8 frs0;
513
514	frs0 = pef2256_read8(pef2256, PEF2256_FRS0);
515	return !(frs0 & (PEF2256_FRS0_LOS | PEF2256_FRS0_AIS));
516}
517
518static void pef2256_isr2_handler(struct pef2256 *pef2256, u8 nbr, u8 isr)
519{
520	bool carrier;
521
522	if (isr & (PEF2256_INT2_LOS | PEF2256_INT2_AIS)) {
523		carrier = pef2256_is_carrier_on(pef2256);
524		if (atomic_xchg(&pef2256->carrier, carrier) != carrier)
525			framer_notify_status_change(pef2256->framer);
526	}
527}
528
529static irqreturn_t pef2256_irq_handler(int irq, void *priv)
530{
531	static void (*pef2256_isr_handler[])(struct pef2256 *, u8, u8) = {
532		[0] = pef2256_isr_default_handler,
533		[1] = pef2256_isr_default_handler,
534		[2] = pef2256_isr2_handler,
535		[3] = pef2256_isr_default_handler,
536		[4] = pef2256_isr_default_handler,
537		[5] = pef2256_isr_default_handler
538	};
539	struct pef2256 *pef2256 = (struct pef2256 *)priv;
540	u8 gis;
541	u8 isr;
542	u8 n;
543
544	gis = pef2256_read8(pef2256, PEF2256_GIS);
545
546	for (n = 0; n < ARRAY_SIZE(pef2256_isr_handler); n++) {
547		if (gis & PEF2256_GIS_ISR(n)) {
548			isr = pef2256_read8(pef2256, PEF2256_ISR(n));
549			pef2256_isr_handler[n](pef2256, n, isr);
550		}
551	}
552
553	return IRQ_HANDLED;
554}
555
556static int pef2256_check_rates(struct pef2256 *pef2256, unsigned long sysclk_rate,
557			       unsigned long data_rate)
558{
559	unsigned long rate;
560
561	switch (sysclk_rate) {
562	case 2048000:
563	case 4096000:
564	case 8192000:
565	case 16384000:
566		break;
567	default:
568		dev_err(pef2256->dev, "Unsupported system clock rate %lu\n", sysclk_rate);
569		return -EINVAL;
570	}
571
572	for (rate = data_rate; rate <= data_rate * 4; rate *= 2) {
573		if (rate == sysclk_rate)
574			return 0;
575	}
576	dev_err(pef2256->dev, "Unsupported data rate %lu with system clock rate %lu\n",
577		data_rate, sysclk_rate);
578	return -EINVAL;
579}
580
581static int pef2556_of_parse(struct pef2256 *pef2256, struct device_node *np)
582{
583	int ret;
584
585	pef2256->data_rate = 2048000;
586	ret = of_property_read_u32(np, "lantiq,data-rate-bps", &pef2256->data_rate);
587	if (ret && ret != -EINVAL) {
588		dev_err(pef2256->dev, "%pOF: failed to read lantiq,data-rate-bps\n", np);
589		return ret;
590	}
591
592	ret =  pef2256_check_rates(pef2256, pef2256->sysclk_rate, pef2256->data_rate);
593	if (ret)
594		return ret;
595
596	pef2256->is_tx_falling_edge = of_property_read_bool(np, "lantiq,clock-falling-edge");
597
598	pef2256->channel_phase = 0;
599	ret = of_property_read_u8(np, "lantiq,channel-phase", &pef2256->channel_phase);
600	if (ret && ret != -EINVAL) {
601		dev_err(pef2256->dev, "%pOF: failed to read lantiq,channel-phase\n",
602			np);
603		return ret;
604	}
605	if (pef2256->channel_phase >= pef2256->sysclk_rate / pef2256->data_rate) {
606		dev_err(pef2256->dev, "%pOF: Invalid lantiq,channel-phase %u\n",
607			np, pef2256->channel_phase);
608		return -EINVAL;
609	}
610
611	return 0;
612}
613
614static const struct regmap_config pef2256_regmap_config = {
615	.reg_bits = 32,
616	.val_bits = 8,
617	.max_register = 0xff,
618};
619
620static const struct mfd_cell pef2256_devs[] = {
621	{ .name = "lantiq-pef2256-pinctrl", },
622};
623
624static int pef2256_add_audio_devices(struct pef2256 *pef2256)
625{
626	const char *compatible = "lantiq,pef2256-codec";
627	struct mfd_cell *audio_devs;
628	struct device_node *np;
629	unsigned int count = 0;
630	unsigned int i;
631	int ret;
632
633	for_each_available_child_of_node(pef2256->dev->of_node, np) {
634		if (of_device_is_compatible(np, compatible))
635			count++;
636	}
637
638	if (!count)
639		return 0;
640
641	audio_devs = kcalloc(count, sizeof(*audio_devs), GFP_KERNEL);
642	if (!audio_devs)
643		return -ENOMEM;
644
645	for (i = 0; i < count; i++) {
646		audio_devs[i].name = "framer-codec";
647		audio_devs[i].of_compatible = compatible;
648		audio_devs[i].id = i;
649	}
650
651	ret = devm_mfd_add_devices(pef2256->dev, 0, audio_devs, count,
652				   NULL, 0, NULL);
653	kfree(audio_devs);
654	return ret;
655}
656
657static int pef2256_framer_get_status(struct framer *framer, struct framer_status *status)
658{
659	struct pef2256 *pef2256 = framer_get_drvdata(framer);
660
661	status->link_is_on = !!atomic_read(&pef2256->carrier);
662	return 0;
663}
664
665static int pef2256_framer_set_config(struct framer *framer, const struct framer_config *config)
666{
667	struct pef2256 *pef2256 = framer_get_drvdata(framer);
668
669	if (config->iface != FRAMER_IFACE_E1) {
670		dev_err(pef2256->dev, "Only E1 line is currently supported\n");
671		return -EOPNOTSUPP;
672	}
673
674	switch (config->clock_type) {
675	case FRAMER_CLOCK_EXT:
676		pef2256->is_subordinate = true;
677		break;
678	case FRAMER_CLOCK_INT:
679		pef2256->is_subordinate = false;
680		break;
681	default:
682		return -EINVAL;
683	}
684
685	/* Apply the new settings */
686	return pef2256_setup_e1(pef2256);
687}
688
689static int pef2256_framer_get_config(struct framer *framer, struct framer_config *config)
690{
691	struct pef2256 *pef2256 = framer_get_drvdata(framer);
692
693	config->iface = FRAMER_IFACE_E1;
694	config->clock_type = pef2256->is_subordinate ? FRAMER_CLOCK_EXT : FRAMER_CLOCK_INT;
695	config->line_clock_rate = 2048000;
696	return 0;
697}
698
699static const struct framer_ops pef2256_framer_ops = {
700	.owner = THIS_MODULE,
701	.get_status = pef2256_framer_get_status,
702	.get_config = pef2256_framer_get_config,
703	.set_config = pef2256_framer_set_config,
704};
705
706static int pef2256_probe(struct platform_device *pdev)
707{
708	struct device_node *np = pdev->dev.of_node;
709	unsigned long sclkr_rate, sclkx_rate;
710	struct framer_provider *framer_provider;
711	struct pef2256 *pef2256;
712	void __iomem *iomem;
713	int ret;
714	int irq;
715
716	pef2256 = devm_kzalloc(&pdev->dev, sizeof(*pef2256), GFP_KERNEL);
717	if (!pef2256)
718		return -ENOMEM;
719
720	pef2256->dev = &pdev->dev;
721	atomic_set(&pef2256->carrier, 0);
722
723	pef2256->is_subordinate = true;
724	pef2256->frame_type = PEF2256_FRAME_E1_DOUBLEFRAME;
725
726	iomem = devm_platform_ioremap_resource(pdev, 0);
727	if (IS_ERR(iomem))
728		return PTR_ERR(iomem);
729
730	pef2256->regmap = devm_regmap_init_mmio(&pdev->dev, iomem,
731						&pef2256_regmap_config);
732	if (IS_ERR(pef2256->regmap)) {
733		dev_err(&pdev->dev, "Failed to initialise Regmap (%pe)\n",
734			pef2256->regmap);
735		return PTR_ERR(pef2256->regmap);
736	}
737
738	pef2256->mclk = devm_clk_get_enabled(&pdev->dev, "mclk");
739	if (IS_ERR(pef2256->mclk))
740		return PTR_ERR(pef2256->mclk);
741
742	pef2256->sclkr = devm_clk_get_enabled(&pdev->dev, "sclkr");
743	if (IS_ERR(pef2256->sclkr))
744		return PTR_ERR(pef2256->sclkr);
745
746	pef2256->sclkx = devm_clk_get_enabled(&pdev->dev, "sclkx");
747	if (IS_ERR(pef2256->sclkx))
748		return PTR_ERR(pef2256->sclkx);
749
750	/* Both SCLKR (receive) and SCLKX (transmit) must have the same rate,
751	 * stored as sysclk_rate.
752	 * The exact value will be checked at pef2256_check_rates()
753	 */
754	sclkr_rate = clk_get_rate(pef2256->sclkr);
755	sclkx_rate = clk_get_rate(pef2256->sclkx);
756	if (sclkr_rate != sclkx_rate) {
757		dev_err(pef2256->dev, "clk rate mismatch. sclkr %lu Hz, sclkx %lu Hz\n",
758			sclkr_rate, sclkx_rate);
759		return -EINVAL;
760	}
761	pef2256->sysclk_rate = sclkr_rate;
762
763	/* Reset the component. The MCLK clock must be active during reset */
764	pef2256->reset_gpio = devm_gpiod_get_optional(&pdev->dev, "reset", GPIOD_OUT_LOW);
765	if (IS_ERR(pef2256->reset_gpio))
766		return PTR_ERR(pef2256->reset_gpio);
767	if (pef2256->reset_gpio) {
768		gpiod_set_value_cansleep(pef2256->reset_gpio, 1);
769		usleep_range(10, 20);
770		gpiod_set_value_cansleep(pef2256->reset_gpio, 0);
771		usleep_range(10, 20);
772	}
773
774	pef2256->version = pef2256_get_version(pef2256);
775	switch (pef2256->version) {
776	case PEF2256_VERSION_1_2:
777		pef2256->version_txt = "1.2";
778		break;
779	case PEF2256_VERSION_2_1:
780		pef2256->version_txt = "2.1";
781		break;
782	case PEF2256_VERSION_2_2:
783		pef2256->version_txt = "2.2";
784		break;
785	default:
786		return -ENODEV;
787	}
788	dev_info(pef2256->dev, "Version %s detected\n", pef2256->version_txt);
789
790	ret = pef2556_of_parse(pef2256, np);
791	if (ret)
792		return ret;
793
794	/* Create the framer. It can be used on interrupts */
795	pef2256->framer = devm_framer_create(pef2256->dev, NULL, &pef2256_framer_ops);
796	if (IS_ERR(pef2256->framer))
797		return PTR_ERR(pef2256->framer);
798
799	framer_set_drvdata(pef2256->framer, pef2256);
800
801	/* Disable interrupts */
802	pef2256_write8(pef2256, PEF2256_IMR0, 0xff);
803	pef2256_write8(pef2256, PEF2256_IMR1, 0xff);
804	pef2256_write8(pef2256, PEF2256_IMR2, 0xff);
805	pef2256_write8(pef2256, PEF2256_IMR3, 0xff);
806	pef2256_write8(pef2256, PEF2256_IMR4, 0xff);
807	pef2256_write8(pef2256, PEF2256_IMR5, 0xff);
808
809	/* Clear any pending interrupts */
810	pef2256_read8(pef2256, PEF2256_ISR0);
811	pef2256_read8(pef2256, PEF2256_ISR1);
812	pef2256_read8(pef2256, PEF2256_ISR2);
813	pef2256_read8(pef2256, PEF2256_ISR3);
814	pef2256_read8(pef2256, PEF2256_ISR4);
815	pef2256_read8(pef2256, PEF2256_ISR5);
816
817	irq = platform_get_irq(pdev, 0);
818	if (irq < 0)
819		return irq;
820	ret = devm_request_irq(pef2256->dev, irq, pef2256_irq_handler, 0, "pef2256", pef2256);
821	if (ret < 0)
822		return ret;
823
824	platform_set_drvdata(pdev, pef2256);
825
826	ret = devm_mfd_add_devices(pef2256->dev, 0, pef2256_devs,
827				   ARRAY_SIZE(pef2256_devs), NULL, 0, NULL);
828	if (ret) {
829		dev_err(pef2256->dev, "add devices failed (%d)\n", ret);
830		return ret;
831	}
832
833	ret = pef2256_setup_e1(pef2256);
834	if (ret)
835		return ret;
836
837	framer_provider = devm_framer_provider_of_register(pef2256->dev,
838							   framer_provider_simple_of_xlate);
839	if (IS_ERR(framer_provider))
840		return PTR_ERR(framer_provider);
841
842	/* Add audio devices */
843	ret = pef2256_add_audio_devices(pef2256);
844	if (ret < 0) {
845		dev_err(pef2256->dev, "add audio devices failed (%d)\n", ret);
846		return ret;
847	}
848
849	device_create_file(pef2256->dev, &dev_attr_version);
850
851	return 0;
852}
853
854static void pef2256_remove(struct platform_device *pdev)
855{
856	struct pef2256 *pef2256 = platform_get_drvdata(pdev);
857
858	/* Disable interrupts */
859	pef2256_write8(pef2256, PEF2256_IMR0, 0xff);
860	pef2256_write8(pef2256, PEF2256_IMR1, 0xff);
861	pef2256_write8(pef2256, PEF2256_IMR2, 0xff);
862	pef2256_write8(pef2256, PEF2256_IMR3, 0xff);
863	pef2256_write8(pef2256, PEF2256_IMR4, 0xff);
864	pef2256_write8(pef2256, PEF2256_IMR5, 0xff);
865
866	device_remove_file(pef2256->dev, &dev_attr_version);
867}
868
869static const struct of_device_id pef2256_id_table[] = {
870	{ .compatible = "lantiq,pef2256" },
871	{} /* sentinel */
872};
873MODULE_DEVICE_TABLE(of, pef2256_id_table);
874
875static struct platform_driver pef2256_driver = {
876	.driver = {
877		.name = "lantiq-pef2256",
878		.of_match_table = pef2256_id_table,
879	},
880	.probe = pef2256_probe,
881	.remove = pef2256_remove,
882};
883module_platform_driver(pef2256_driver);
884
885struct regmap *pef2256_get_regmap(struct pef2256 *pef2256)
886{
887	return pef2256->regmap;
888}
889EXPORT_SYMBOL_GPL(pef2256_get_regmap);
890
891MODULE_AUTHOR("Herve Codina <herve.codina@bootlin.com>");
892MODULE_DESCRIPTION("PEF2256 driver");
893MODULE_LICENSE("GPL");