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r8152.c
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linux-6.19.14/drivers/net/usb/r8152.c
1// SPDX-License-Identifier: GPL-2.0-only 2/* 3 * Copyright (c) 2014 Realtek Semiconductor Corp. All rights reserved. 4 */ 5 6#include <linux/signal.h> 7#include <linux/slab.h> 8#include <linux/module.h> 9#include <linux/netdevice.h> 10#include <linux/etherdevice.h> 11#include <linux/mii.h> 12#include <linux/ethtool.h> 13#include <linux/phy.h> 14#include <linux/usb.h> 15#include <linux/crc32.h> 16#include <linux/if_vlan.h> 17#include <linux/uaccess.h> 18#include <linux/list.h> 19#include <linux/ip.h> 20#include <linux/ipv6.h> 21#include <net/ip6_checksum.h> 22#include <uapi/linux/mdio.h> 23#include <linux/mdio.h> 24#include <linux/usb/cdc.h> 25#include <linux/suspend.h> 26#include <linux/atomic.h> 27#include <linux/acpi.h> 28#include <linux/firmware.h> 29#include <crypto/sha2.h> 30#include <linux/usb/r8152.h> 31#include <net/gso.h> 32 33/* Information for net-next */ 34#define NETNEXT_VERSION "12" 35 36/* Information for net */ 37#define NET_VERSION "13" 38 39#define DRIVER_VERSION "v1." NETNEXT_VERSION "." NET_VERSION 40#define DRIVER_AUTHOR "Realtek linux nic maintainers <nic_swsd@realtek.com>" 41#define DRIVER_DESC "Realtek RTL8152/RTL8153 Based USB Ethernet Adapters" 42#define MODULENAME "r8152" 43 44#define R8152_PHY_ID 32 45 46#define PLA_IDR 0xc000 47#define PLA_RCR 0xc010 48#define PLA_RCR1 0xc012 49#define PLA_RMS 0xc016 50#define PLA_RXFIFO_CTRL0 0xc0a0 51#define PLA_RXFIFO_FULL 0xc0a2 52#define PLA_RXFIFO_CTRL1 0xc0a4 53#define PLA_RX_FIFO_FULL 0xc0a6 54#define PLA_RXFIFO_CTRL2 0xc0a8 55#define PLA_RX_FIFO_EMPTY 0xc0aa 56#define PLA_DMY_REG0 0xc0b0 57#define PLA_FMC 0xc0b4 58#define PLA_CFG_WOL 0xc0b6 59#define PLA_TEREDO_CFG 0xc0bc 60#define PLA_TEREDO_WAKE_BASE 0xc0c4 61#define PLA_MAR 0xcd00 62#define PLA_BACKUP 0xd000 63#define PLA_BDC_CR 0xd1a0 64#define PLA_TEREDO_TIMER 0xd2cc 65#define PLA_REALWOW_TIMER 0xd2e8 66#define PLA_UPHY_TIMER 0xd388 67#define PLA_SUSPEND_FLAG 0xd38a 68#define PLA_INDICATE_FALG 0xd38c 69#define PLA_MACDBG_PRE 0xd38c /* RTL_VER_04 only */ 70#define PLA_MACDBG_POST 0xd38e /* RTL_VER_04 only */ 71#define PLA_EXTRA_STATUS 0xd398 72#define PLA_GPHY_CTRL 0xd3ae 73#define PLA_POL_GPIO_CTRL 0xdc6a 74#define PLA_EFUSE_DATA 0xdd00 75#define PLA_EFUSE_CMD 0xdd02 76#define PLA_LEDSEL 0xdd90 77#define PLA_LED_FEATURE 0xdd92 78#define PLA_PHYAR 0xde00 79#define PLA_BOOT_CTRL 0xe004 80#define PLA_LWAKE_CTRL_REG 0xe007 81#define PLA_GPHY_INTR_IMR 0xe022 82#define PLA_EEE_CR 0xe040 83#define PLA_EEE_TXTWSYS 0xe04c 84#define PLA_EEE_TXTWSYS_2P5G 0xe058 85#define PLA_EEEP_CR 0xe080 86#define PLA_MAC_PWR_CTRL 0xe0c0 87#define PLA_MAC_PWR_CTRL2 0xe0ca 88#define PLA_MAC_PWR_CTRL3 0xe0cc 89#define PLA_MAC_PWR_CTRL4 0xe0ce 90#define PLA_WDT6_CTRL 0xe428 91#define PLA_TCR0 0xe610 92#define PLA_TCR1 0xe612 93#define PLA_MTPS 0xe615 94#define PLA_TXFIFO_CTRL 0xe618 95#define PLA_TXFIFO_FULL 0xe61a 96#define PLA_RSTTALLY 0xe800 97#define PLA_CR 0xe813 98#define PLA_CRWECR 0xe81c 99#define PLA_CONFIG12 0xe81e /* CONFIG1, CONFIG2 */ 100#define PLA_CONFIG34 0xe820 /* CONFIG3, CONFIG4 */ 101#define PLA_CONFIG5 0xe822 102#define PLA_PHY_PWR 0xe84c 103#define PLA_OOB_CTRL 0xe84f 104#define PLA_CPCR 0xe854 105#define PLA_MISC_0 0xe858 106#define PLA_MISC_1 0xe85a 107#define PLA_OCP_GPHY_BASE 0xe86c 108#define PLA_TALLYCNT 0xe890 109#define PLA_SFF_STS_7 0xe8de 110#define PLA_PHYSTATUS 0xe908 111#define PLA_CONFIG6 0xe90a /* CONFIG6 */ 112#define PLA_USB_CFG 0xe952 113#define PLA_BP_BA 0xfc26 114#define PLA_BP_0 0xfc28 115#define PLA_BP_1 0xfc2a 116#define PLA_BP_2 0xfc2c 117#define PLA_BP_3 0xfc2e 118#define PLA_BP_4 0xfc30 119#define PLA_BP_5 0xfc32 120#define PLA_BP_6 0xfc34 121#define PLA_BP_7 0xfc36 122#define PLA_BP_EN 0xfc38 123 124#define USB_USB2PHY 0xb41e 125#define USB_SSPHYLINK1 0xb426 126#define USB_SSPHYLINK2 0xb428 127#define USB_L1_CTRL 0xb45e 128#define USB_U2P3_CTRL 0xb460 129#define USB_CSR_DUMMY1 0xb464 130#define USB_CSR_DUMMY2 0xb466 131#define USB_DEV_STAT 0xb808 132#define USB_CONNECT_TIMER 0xcbf8 133#define USB_MSC_TIMER 0xcbfc 134#define USB_BURST_SIZE 0xcfc0 135#define USB_FW_FIX_EN0 0xcfca 136#define USB_FW_FIX_EN1 0xcfcc 137#define USB_LPM_CONFIG 0xcfd8 138#define USB_ECM_OPTION 0xcfee 139#define USB_CSTMR 0xcfef /* RTL8153A */ 140#define USB_MISC_2 0xcfff 141#define USB_ECM_OP 0xd26b 142#define USB_GPHY_CTRL 0xd284 143#define USB_SPEED_OPTION 0xd32a 144#define USB_FW_CTRL 0xd334 /* RTL8153B */ 145#define USB_FC_TIMER 0xd340 146#define USB_USB_CTRL 0xd406 147#define USB_PHY_CTRL 0xd408 148#define USB_TX_AGG 0xd40a 149#define USB_RX_BUF_TH 0xd40c 150#define USB_USB_TIMER 0xd428 151#define USB_RX_EARLY_TIMEOUT 0xd42c 152#define USB_RX_EARLY_SIZE 0xd42e 153#define USB_PM_CTRL_STATUS 0xd432 /* RTL8153A */ 154#define USB_RX_EXTRA_AGGR_TMR 0xd432 /* RTL8153B */ 155#define USB_TX_DMA 0xd434 156#define USB_UPT_RXDMA_OWN 0xd437 157#define USB_UPHY3_MDCMDIO 0xd480 158#define USB_TOLERANCE 0xd490 159#define USB_LPM_CTRL 0xd41a 160#define USB_BMU_RESET 0xd4b0 161#define USB_BMU_CONFIG 0xd4b4 162#define USB_U1U2_TIMER 0xd4da 163#define USB_FW_TASK 0xd4e8 /* RTL8153B */ 164#define USB_RX_AGGR_NUM 0xd4ee 165#define USB_UPS_CTRL 0xd800 166#define USB_POWER_CUT 0xd80a 167#define USB_MISC_0 0xd81a 168#define USB_MISC_1 0xd81f 169#define USB_AFE_CTRL2 0xd824 170#define USB_UPHY_XTAL 0xd826 171#define USB_UPS_CFG 0xd842 172#define USB_UPS_FLAGS 0xd848 173#define USB_WDT1_CTRL 0xe404 174#define USB_WDT11_CTRL 0xe43c 175#define USB_BP_BA PLA_BP_BA 176#define USB_BP_0 PLA_BP_0 177#define USB_BP_1 PLA_BP_1 178#define USB_BP_2 PLA_BP_2 179#define USB_BP_3 PLA_BP_3 180#define USB_BP_4 PLA_BP_4 181#define USB_BP_5 PLA_BP_5 182#define USB_BP_6 PLA_BP_6 183#define USB_BP_7 PLA_BP_7 184#define USB_BP_EN PLA_BP_EN /* RTL8153A */ 185#define USB_BP_8 0xfc38 /* RTL8153B */ 186#define USB_BP_9 0xfc3a 187#define USB_BP_10 0xfc3c 188#define USB_BP_11 0xfc3e 189#define USB_BP_12 0xfc40 190#define USB_BP_13 0xfc42 191#define USB_BP_14 0xfc44 192#define USB_BP_15 0xfc46 193#define USB_BP2_EN 0xfc48 194 195/* OCP Registers */ 196#define OCP_ALDPS_CONFIG 0x2010 197#define OCP_EEE_CONFIG1 0x2080 198#define OCP_EEE_CONFIG2 0x2092 199#define OCP_EEE_CONFIG3 0x2094 200#define OCP_BASE_MII 0xa400 201#define OCP_EEE_AR 0xa41a 202#define OCP_EEE_DATA 0xa41c 203#define OCP_PHY_STATUS 0xa420 204#define OCP_INTR_EN 0xa424 205#define OCP_NCTL_CFG 0xa42c 206#define OCP_POWER_CFG 0xa430 207#define OCP_EEE_CFG 0xa432 208#define OCP_SRAM_ADDR 0xa436 209#define OCP_SRAM_DATA 0xa438 210#define OCP_DOWN_SPEED 0xa442 211#define OCP_EEE_ABLE 0xa5c4 212#define OCP_EEE_ADV 0xa5d0 213#define OCP_EEE_LPABLE 0xa5d2 214#define OCP_10GBT_CTRL 0xa5d4 215#define OCP_10GBT_STAT 0xa5d6 216#define OCP_EEE_ADV2 0xa6d4 217#define OCP_PHY_STATE 0xa708 /* nway state for 8153 */ 218#define OCP_PHY_PATCH_STAT 0xb800 219#define OCP_PHY_PATCH_CMD 0xb820 220#define OCP_PHY_LOCK 0xb82e 221#define OCP_ADC_IOFFSET 0xbcfc 222#define OCP_ADC_CFG 0xbc06 223#define OCP_SYSCLK_CFG 0xc416 224 225/* SRAM Register */ 226#define SRAM_GREEN_CFG 0x8011 227#define SRAM_LPF_CFG 0x8012 228#define SRAM_GPHY_FW_VER 0x801e 229#define SRAM_10M_AMP1 0x8080 230#define SRAM_10M_AMP2 0x8082 231#define SRAM_IMPEDANCE 0x8084 232#define SRAM_PHY_LOCK 0xb82e 233 234/* PLA_RCR */ 235#define RCR_AAP 0x00000001 236#define RCR_APM 0x00000002 237#define RCR_AM 0x00000004 238#define RCR_AB 0x00000008 239#define RCR_ACPT_ALL (RCR_AAP | RCR_APM | RCR_AM | RCR_AB) 240#define SLOT_EN BIT(11) 241 242/* PLA_RCR1 */ 243#define OUTER_VLAN BIT(7) 244#define INNER_VLAN BIT(6) 245 246/* PLA_RXFIFO_CTRL0 */ 247#define RXFIFO_THR1_NORMAL 0x00080002 248#define RXFIFO_THR1_OOB 0x01800003 249 250/* PLA_RXFIFO_FULL */ 251#define RXFIFO_FULL_MASK 0xfff 252 253/* PLA_RXFIFO_CTRL1 */ 254#define RXFIFO_THR2_FULL 0x00000060 255#define RXFIFO_THR2_HIGH 0x00000038 256#define RXFIFO_THR2_OOB 0x0000004a 257#define RXFIFO_THR2_NORMAL 0x00a0 258 259/* PLA_RXFIFO_CTRL2 */ 260#define RXFIFO_THR3_FULL 0x00000078 261#define RXFIFO_THR3_HIGH 0x00000048 262#define RXFIFO_THR3_OOB 0x0000005a 263#define RXFIFO_THR3_NORMAL 0x0110 264 265/* PLA_TXFIFO_CTRL */ 266#define TXFIFO_THR_NORMAL 0x00400008 267#define TXFIFO_THR_NORMAL2 0x01000008 268 269/* PLA_DMY_REG0 */ 270#define ECM_ALDPS 0x0002 271 272/* PLA_FMC */ 273#define FMC_FCR_MCU_EN 0x0001 274 275/* PLA_EEEP_CR */ 276#define EEEP_CR_EEEP_TX 0x0002 277 278/* PLA_WDT6_CTRL */ 279#define WDT6_SET_MODE 0x0010 280 281/* PLA_TCR0 */ 282#define TCR0_TX_EMPTY 0x0800 283#define TCR0_AUTO_FIFO 0x0080 284 285/* PLA_TCR1 */ 286#define VERSION_MASK 0x7cf0 287#define IFG_MASK (BIT(3) | BIT(9) | BIT(8)) 288#define IFG_144NS BIT(9) 289#define IFG_96NS (BIT(9) | BIT(8)) 290 291/* PLA_MTPS */ 292#define MTPS_JUMBO (12 * 1024 / 64) 293#define MTPS_DEFAULT (6 * 1024 / 64) 294 295/* PLA_RSTTALLY */ 296#define TALLY_RESET 0x0001 297 298/* PLA_CR */ 299#define CR_RST 0x10 300#define CR_RE 0x08 301#define CR_TE 0x04 302 303/* PLA_CRWECR */ 304#define CRWECR_NORAML 0x00 305#define CRWECR_CONFIG 0xc0 306 307/* PLA_OOB_CTRL */ 308#define NOW_IS_OOB 0x80 309#define TXFIFO_EMPTY 0x20 310#define RXFIFO_EMPTY 0x10 311#define LINK_LIST_READY 0x02 312#define DIS_MCU_CLROOB 0x01 313#define FIFO_EMPTY (TXFIFO_EMPTY | RXFIFO_EMPTY) 314 315/* PLA_MISC_1 */ 316#define RXDY_GATED_EN 0x0008 317 318/* PLA_SFF_STS_7 */ 319#define RE_INIT_LL 0x8000 320#define MCU_BORW_EN 0x4000 321 322/* PLA_CPCR */ 323#define FLOW_CTRL_EN BIT(0) 324#define CPCR_RX_VLAN 0x0040 325 326/* PLA_CFG_WOL */ 327#define MAGIC_EN 0x0001 328 329/* PLA_TEREDO_CFG */ 330#define TEREDO_SEL 0x8000 331#define TEREDO_WAKE_MASK 0x7f00 332#define TEREDO_RS_EVENT_MASK 0x00fe 333#define OOB_TEREDO_EN 0x0001 334 335/* PLA_BDC_CR */ 336#define ALDPS_PROXY_MODE 0x0001 337 338/* PLA_EFUSE_CMD */ 339#define EFUSE_READ_CMD BIT(15) 340#define EFUSE_DATA_BIT16 BIT(7) 341 342/* PLA_CONFIG34 */ 343#define LINK_ON_WAKE_EN 0x0010 344#define LINK_OFF_WAKE_EN 0x0008 345 346/* PLA_CONFIG6 */ 347#define LANWAKE_CLR_EN BIT(0) 348 349/* PLA_USB_CFG */ 350#define EN_XG_LIP BIT(1) 351#define EN_G_LIP BIT(2) 352 353/* PLA_CONFIG5 */ 354#define BWF_EN 0x0040 355#define MWF_EN 0x0020 356#define UWF_EN 0x0010 357#define LAN_WAKE_EN 0x0002 358 359/* PLA_LED_FEATURE */ 360#define LED_MODE_MASK 0x0700 361 362/* PLA_PHY_PWR */ 363#define TX_10M_IDLE_EN 0x0080 364#define PFM_PWM_SWITCH 0x0040 365#define TEST_IO_OFF BIT(4) 366 367/* PLA_MAC_PWR_CTRL */ 368#define D3_CLK_GATED_EN 0x00004000 369#define MCU_CLK_RATIO 0x07010f07 370#define MCU_CLK_RATIO_MASK 0x0f0f0f0f 371#define ALDPS_SPDWN_RATIO 0x0f87 372 373/* PLA_MAC_PWR_CTRL2 */ 374#define EEE_SPDWN_RATIO 0x8007 375#define MAC_CLK_SPDWN_EN BIT(15) 376#define EEE_SPDWN_RATIO_MASK 0xff 377 378/* PLA_MAC_PWR_CTRL3 */ 379#define PLA_MCU_SPDWN_EN BIT(14) 380#define PKT_AVAIL_SPDWN_EN 0x0100 381#define SUSPEND_SPDWN_EN 0x0004 382#define U1U2_SPDWN_EN 0x0002 383#define L1_SPDWN_EN 0x0001 384 385/* PLA_MAC_PWR_CTRL4 */ 386#define PWRSAVE_SPDWN_EN 0x1000 387#define RXDV_SPDWN_EN 0x0800 388#define TX10MIDLE_EN 0x0100 389#define IDLE_SPDWN_EN BIT(6) 390#define TP100_SPDWN_EN 0x0020 391#define TP500_SPDWN_EN 0x0010 392#define TP1000_SPDWN_EN 0x0008 393#define EEE_SPDWN_EN 0x0001 394 395/* PLA_GPHY_INTR_IMR */ 396#define GPHY_STS_MSK 0x0001 397#define SPEED_DOWN_MSK 0x0002 398#define SPDWN_RXDV_MSK 0x0004 399#define SPDWN_LINKCHG_MSK 0x0008 400 401/* PLA_PHYAR */ 402#define PHYAR_FLAG 0x80000000 403 404/* PLA_EEE_CR */ 405#define EEE_RX_EN 0x0001 406#define EEE_TX_EN 0x0002 407 408/* PLA_BOOT_CTRL */ 409#define AUTOLOAD_DONE 0x0002 410 411/* PLA_LWAKE_CTRL_REG */ 412#define LANWAKE_PIN BIT(7) 413 414/* PLA_SUSPEND_FLAG */ 415#define LINK_CHG_EVENT BIT(0) 416 417/* PLA_INDICATE_FALG */ 418#define UPCOMING_RUNTIME_D3 BIT(0) 419 420/* PLA_MACDBG_PRE and PLA_MACDBG_POST */ 421#define DEBUG_OE BIT(0) 422#define DEBUG_LTSSM 0x0082 423 424/* PLA_EXTRA_STATUS */ 425#define CUR_LINK_OK BIT(15) 426#define U3P3_CHECK_EN BIT(7) /* RTL_VER_05 only */ 427#define LINK_CHANGE_FLAG BIT(8) 428#define POLL_LINK_CHG BIT(0) 429 430/* PLA_GPHY_CTRL */ 431#define GPHY_FLASH BIT(1) 432 433/* PLA_POL_GPIO_CTRL */ 434#define DACK_DET_EN BIT(15) 435#define POL_GPHY_PATCH BIT(4) 436 437/* USB_USB2PHY */ 438#define USB2PHY_SUSPEND 0x0001 439#define USB2PHY_L1 0x0002 440 441/* USB_SSPHYLINK1 */ 442#define DELAY_PHY_PWR_CHG BIT(1) 443 444/* USB_SSPHYLINK2 */ 445#define pwd_dn_scale_mask 0x3ffe 446#define pwd_dn_scale(x) ((x) << 1) 447 448/* USB_CSR_DUMMY1 */ 449#define DYNAMIC_BURST 0x0001 450 451/* USB_CSR_DUMMY2 */ 452#define EP4_FULL_FC 0x0001 453 454/* USB_DEV_STAT */ 455#define STAT_SPEED_MASK 0x0006 456#define STAT_SPEED_HIGH 0x0000 457#define STAT_SPEED_FULL 0x0002 458 459/* USB_FW_FIX_EN0 */ 460#define FW_FIX_SUSPEND BIT(14) 461 462/* USB_FW_FIX_EN1 */ 463#define FW_IP_RESET_EN BIT(9) 464 465/* USB_LPM_CONFIG */ 466#define LPM_U1U2_EN BIT(0) 467 468/* USB_TX_AGG */ 469#define TX_AGG_MAX_THRESHOLD 0x03 470 471/* USB_RX_BUF_TH */ 472#define RX_THR_SUPPER 0x0c350180 473#define RX_THR_HIGH 0x7a120180 474#define RX_THR_SLOW 0xffff0180 475#define RX_THR_B 0x00010001 476 477/* USB_TX_DMA */ 478#define TEST_MODE_DISABLE 0x00000001 479#define TX_SIZE_ADJUST1 0x00000100 480 481/* USB_BMU_RESET */ 482#define BMU_RESET_EP_IN 0x01 483#define BMU_RESET_EP_OUT 0x02 484 485/* USB_BMU_CONFIG */ 486#define ACT_ODMA BIT(1) 487 488/* USB_UPT_RXDMA_OWN */ 489#define OWN_UPDATE BIT(0) 490#define OWN_CLEAR BIT(1) 491 492/* USB_FW_TASK */ 493#define FC_PATCH_TASK BIT(1) 494 495/* USB_RX_AGGR_NUM */ 496#define RX_AGGR_NUM_MASK 0x1ff 497 498/* USB_UPS_CTRL */ 499#define POWER_CUT 0x0100 500 501/* USB_PM_CTRL_STATUS */ 502#define RESUME_INDICATE 0x0001 503 504/* USB_ECM_OPTION */ 505#define BYPASS_MAC_RESET BIT(5) 506 507/* USB_CSTMR */ 508#define FORCE_SUPER BIT(0) 509 510/* USB_MISC_2 */ 511#define UPS_FORCE_PWR_DOWN BIT(0) 512 513/* USB_ECM_OP */ 514#define EN_ALL_SPEED BIT(0) 515 516/* USB_GPHY_CTRL */ 517#define GPHY_PATCH_DONE BIT(2) 518#define BYPASS_FLASH BIT(5) 519#define BACKUP_RESTRORE BIT(6) 520 521/* USB_SPEED_OPTION */ 522#define RG_PWRDN_EN BIT(8) 523#define ALL_SPEED_OFF BIT(9) 524 525/* USB_FW_CTRL */ 526#define FLOW_CTRL_PATCH_OPT BIT(1) 527#define AUTO_SPEEDUP BIT(3) 528#define FLOW_CTRL_PATCH_2 BIT(8) 529 530/* USB_FC_TIMER */ 531#define CTRL_TIMER_EN BIT(15) 532 533/* USB_USB_CTRL */ 534#define CDC_ECM_EN BIT(3) 535#define RX_AGG_DISABLE 0x0010 536#define RX_ZERO_EN 0x0080 537 538/* USB_U2P3_CTRL */ 539#define U2P3_ENABLE 0x0001 540#define RX_DETECT8 BIT(3) 541 542/* USB_POWER_CUT */ 543#define PWR_EN 0x0001 544#define PHASE2_EN 0x0008 545#define UPS_EN BIT(4) 546#define USP_PREWAKE BIT(5) 547 548/* USB_MISC_0 */ 549#define PCUT_STATUS 0x0001 550 551/* USB_RX_EARLY_TIMEOUT */ 552#define COALESCE_SUPER 85000U 553#define COALESCE_HIGH 250000U 554#define COALESCE_SLOW 524280U 555 556/* USB_WDT1_CTRL */ 557#define WTD1_EN BIT(0) 558 559/* USB_WDT11_CTRL */ 560#define TIMER11_EN 0x0001 561 562/* USB_LPM_CTRL */ 563/* bit 4 ~ 5: fifo empty boundary */ 564#define FIFO_EMPTY_1FB 0x30 /* 0x1fb * 64 = 32448 bytes */ 565/* bit 2 ~ 3: LMP timer */ 566#define LPM_TIMER_MASK 0x0c 567#define LPM_TIMER_500MS 0x04 /* 500 ms */ 568#define LPM_TIMER_500US 0x0c /* 500 us */ 569#define ROK_EXIT_LPM 0x02 570 571/* USB_AFE_CTRL2 */ 572#define SEN_VAL_MASK 0xf800 573#define SEN_VAL_NORMAL 0xa000 574#define SEL_RXIDLE 0x0100 575 576/* USB_UPHY_XTAL */ 577#define OOBS_POLLING BIT(8) 578 579/* USB_UPS_CFG */ 580#define SAW_CNT_1MS_MASK 0x0fff 581#define MID_REVERSE BIT(5) /* RTL8156A */ 582 583/* USB_UPS_FLAGS */ 584#define UPS_FLAGS_R_TUNE BIT(0) 585#define UPS_FLAGS_EN_10M_CKDIV BIT(1) 586#define UPS_FLAGS_250M_CKDIV BIT(2) 587#define UPS_FLAGS_EN_ALDPS BIT(3) 588#define UPS_FLAGS_CTAP_SHORT_DIS BIT(4) 589#define UPS_FLAGS_SPEED_MASK (0xf << 16) 590#define ups_flags_speed(x) ((x) << 16) 591#define UPS_FLAGS_EN_EEE BIT(20) 592#define UPS_FLAGS_EN_500M_EEE BIT(21) 593#define UPS_FLAGS_EN_EEE_CKDIV BIT(22) 594#define UPS_FLAGS_EEE_PLLOFF_100 BIT(23) 595#define UPS_FLAGS_EEE_PLLOFF_GIGA BIT(24) 596#define UPS_FLAGS_EEE_CMOD_LV_EN BIT(25) 597#define UPS_FLAGS_EN_GREEN BIT(26) 598#define UPS_FLAGS_EN_FLOW_CTR BIT(27) 599 600enum spd_duplex { 601 NWAY_10M_HALF, 602 NWAY_10M_FULL, 603 NWAY_100M_HALF, 604 NWAY_100M_FULL, 605 NWAY_1000M_FULL, 606 FORCE_10M_HALF, 607 FORCE_10M_FULL, 608 FORCE_100M_HALF, 609 FORCE_100M_FULL, 610 FORCE_1000M_FULL, 611 NWAY_2500M_FULL, 612}; 613 614/* OCP_ALDPS_CONFIG */ 615#define ENPWRSAVE 0x8000 616#define ENPDNPS 0x0200 617#define LINKENA 0x0100 618#define DIS_SDSAVE 0x0010 619 620/* OCP_PHY_STATUS */ 621#define PHY_STAT_MASK 0x0007 622#define PHY_STAT_EXT_INIT 2 623#define PHY_STAT_LAN_ON 3 624#define PHY_STAT_PWRDN 5 625 626/* OCP_INTR_EN */ 627#define INTR_SPEED_FORCE BIT(3) 628 629/* OCP_NCTL_CFG */ 630#define PGA_RETURN_EN BIT(1) 631 632/* OCP_POWER_CFG */ 633#define EEE_CLKDIV_EN 0x8000 634#define EN_ALDPS 0x0004 635#define EN_10M_PLLOFF 0x0001 636 637/* OCP_EEE_CONFIG1 */ 638#define RG_TXLPI_MSK_HFDUP 0x8000 639#define RG_MATCLR_EN 0x4000 640#define EEE_10_CAP 0x2000 641#define EEE_NWAY_EN 0x1000 642#define TX_QUIET_EN 0x0200 643#define RX_QUIET_EN 0x0100 644#define sd_rise_time_mask 0x0070 645#define sd_rise_time(x) (min(x, 7) << 4) /* bit 4 ~ 6 */ 646#define RG_RXLPI_MSK_HFDUP 0x0008 647#define SDFALLTIME 0x0007 /* bit 0 ~ 2 */ 648 649/* OCP_EEE_CONFIG2 */ 650#define RG_LPIHYS_NUM 0x7000 /* bit 12 ~ 15 */ 651#define RG_DACQUIET_EN 0x0400 652#define RG_LDVQUIET_EN 0x0200 653#define RG_CKRSEL 0x0020 654#define RG_EEEPRG_EN 0x0010 655 656/* OCP_EEE_CONFIG3 */ 657#define fast_snr_mask 0xff80 658#define fast_snr(x) (min(x, 0x1ff) << 7) /* bit 7 ~ 15 */ 659#define RG_LFS_SEL 0x0060 /* bit 6 ~ 5 */ 660#define MSK_PH 0x0006 /* bit 0 ~ 3 */ 661 662/* OCP_EEE_AR */ 663/* bit[15:14] function */ 664#define FUN_ADDR 0x0000 665#define FUN_DATA 0x4000 666/* bit[4:0] device addr */ 667 668/* OCP_EEE_CFG */ 669#define CTAP_SHORT_EN 0x0040 670#define EEE10_EN 0x0010 671 672/* OCP_DOWN_SPEED */ 673#define EN_EEE_CMODE BIT(14) 674#define EN_EEE_1000 BIT(13) 675#define EN_EEE_100 BIT(12) 676#define EN_10M_CLKDIV BIT(11) 677#define EN_10M_BGOFF 0x0080 678 679/* OCP_10GBT_CTRL */ 680#define RTL_ADV2_5G_F_R BIT(5) /* Advertise 2.5GBASE-T fast-retrain */ 681 682/* OCP_PHY_STATE */ 683#define TXDIS_STATE 0x01 684#define ABD_STATE 0x02 685 686/* OCP_PHY_PATCH_STAT */ 687#define PATCH_READY BIT(6) 688 689/* OCP_PHY_PATCH_CMD */ 690#define PATCH_REQUEST BIT(4) 691 692/* OCP_PHY_LOCK */ 693#define PATCH_LOCK BIT(0) 694 695/* OCP_ADC_CFG */ 696#define CKADSEL_L 0x0100 697#define ADC_EN 0x0080 698#define EN_EMI_L 0x0040 699 700/* OCP_SYSCLK_CFG */ 701#define sysclk_div_expo(x) (min(x, 5) << 8) 702#define clk_div_expo(x) (min(x, 5) << 4) 703 704/* SRAM_GREEN_CFG */ 705#define GREEN_ETH_EN BIT(15) 706#define R_TUNE_EN BIT(11) 707 708/* SRAM_LPF_CFG */ 709#define LPF_AUTO_TUNE 0x8000 710 711/* SRAM_10M_AMP1 */ 712#define GDAC_IB_UPALL 0x0008 713 714/* SRAM_10M_AMP2 */ 715#define AMP_DN 0x0200 716 717/* SRAM_IMPEDANCE */ 718#define RX_DRIVING_MASK 0x6000 719 720/* SRAM_PHY_LOCK */ 721#define PHY_PATCH_LOCK 0x0001 722 723/* MAC PASSTHRU */ 724#define AD_MASK 0xfee0 725#define BND_MASK 0x0004 726#define BD_MASK 0x0001 727#define EFUSE 0xcfdb 728#define PASS_THRU_MASK 0x1 729 730#define BP4_SUPER_ONLY 0x1578 /* RTL_VER_04 only */ 731 732enum rtl_register_content { 733 _2500bps = BIT(10), 734 _1250bps = BIT(9), 735 _500bps = BIT(8), 736 _tx_flow = BIT(6), 737 _rx_flow = BIT(5), 738 _1000bps = 0x10, 739 _100bps = 0x08, 740 _10bps = 0x04, 741 LINK_STATUS = 0x02, 742 FULL_DUP = 0x01, 743}; 744 745#define is_speed_2500(_speed) (((_speed) & (_2500bps | LINK_STATUS)) == (_2500bps | LINK_STATUS)) 746#define is_flow_control(_speed) (((_speed) & (_tx_flow | _rx_flow)) == (_tx_flow | _rx_flow)) 747 748#define RTL8152_MAX_TX 4 749#define RTL8152_MAX_RX 10 750#define INTBUFSIZE 2 751#define TX_ALIGN 4 752#define RX_ALIGN 8 753 754#define RTL8152_RX_MAX_PENDING 4096 755#define RTL8152_RXFG_HEADSZ 256 756 757#define INTR_LINK 0x0004 758 759#define RTL8152_RMS (VLAN_ETH_FRAME_LEN + ETH_FCS_LEN) 760#define RTL8153_RMS RTL8153_MAX_PACKET 761#define RTL8152_TX_TIMEOUT (5 * HZ) 762#define mtu_to_size(m) ((m) + VLAN_ETH_HLEN + ETH_FCS_LEN) 763#define size_to_mtu(s) ((s) - VLAN_ETH_HLEN - ETH_FCS_LEN) 764#define rx_reserved_size(x) (mtu_to_size(x) + sizeof(struct rx_desc) + RX_ALIGN) 765 766/* rtl8152 flags */ 767enum rtl8152_flags { 768 RTL8152_INACCESSIBLE = 0, 769 RTL8152_SET_RX_MODE, 770 WORK_ENABLE, 771 RTL8152_LINK_CHG, 772 SELECTIVE_SUSPEND, 773 PHY_RESET, 774 SCHEDULE_TASKLET, 775 GREEN_ETHERNET, 776 RX_EPROTO, 777 IN_PRE_RESET, 778 PROBED_WITH_NO_ERRORS, 779 PROBE_SHOULD_RETRY, 780}; 781 782#define DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB 0x721e 783#define DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK 0x3054 784#define DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2 0x3082 785#define DEVICE_ID_THINKPAD_USB_C_DONGLE 0x720c 786#define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2 0xa387 787#define DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3 0x3062 788#define DEVICE_ID_THINKPAD_HYBRID_USB_C_DOCK 0xa359 789 790struct tally_counter { 791 __le64 tx_packets; 792 __le64 rx_packets; 793 __le64 tx_errors; 794 __le32 rx_errors; 795 __le16 rx_missed; 796 __le16 align_errors; 797 __le32 tx_one_collision; 798 __le32 tx_multi_collision; 799 __le64 rx_unicast; 800 __le64 rx_broadcast; 801 __le32 rx_multicast; 802 __le16 tx_aborted; 803 __le16 tx_underrun; 804}; 805 806struct rx_desc { 807 __le32 opts1; 808#define RX_LEN_MASK 0x7fff 809 810 __le32 opts2; 811#define RD_UDP_CS BIT(23) 812#define RD_TCP_CS BIT(22) 813#define RD_IPV6_CS BIT(20) 814#define RD_IPV4_CS BIT(19) 815 816 __le32 opts3; 817#define IPF BIT(23) /* IP checksum fail */ 818#define UDPF BIT(22) /* UDP checksum fail */ 819#define TCPF BIT(21) /* TCP checksum fail */ 820#define RX_VLAN_TAG BIT(16) 821 822 __le32 opts4; 823 __le32 opts5; 824 __le32 opts6; 825}; 826 827struct tx_desc { 828 __le32 opts1; 829#define TX_FS BIT(31) /* First segment of a packet */ 830#define TX_LS BIT(30) /* Final segment of a packet */ 831#define GTSENDV4 BIT(28) 832#define GTSENDV6 BIT(27) 833#define GTTCPHO_SHIFT 18 834#define GTTCPHO_MAX 0x7fU 835#define TX_LEN_MAX 0x3ffffU 836 837 __le32 opts2; 838#define UDP_CS BIT(31) /* Calculate UDP/IP checksum */ 839#define TCP_CS BIT(30) /* Calculate TCP/IP checksum */ 840#define IPV4_CS BIT(29) /* Calculate IPv4 checksum */ 841#define IPV6_CS BIT(28) /* Calculate IPv6 checksum */ 842#define MSS_SHIFT 17 843#define MSS_MAX 0x7ffU 844#define TCPHO_SHIFT 17 845#define TCPHO_MAX 0x7ffU 846#define TX_VLAN_TAG BIT(16) 847}; 848 849struct r8152; 850 851struct rx_agg { 852 struct list_head list, info_list; 853 struct urb *urb; 854 struct r8152 *context; 855 struct page *page; 856 void *buffer; 857}; 858 859struct tx_agg { 860 struct list_head list; 861 struct urb *urb; 862 struct r8152 *context; 863 void *buffer; 864 void *head; 865 u32 skb_num; 866 u32 skb_len; 867}; 868 869struct r8152 { 870 unsigned long flags; 871 struct usb_device *udev; 872 struct napi_struct napi; 873 struct usb_interface *intf; 874 struct net_device *netdev; 875 struct urb *intr_urb; 876 struct tx_agg tx_info[RTL8152_MAX_TX]; 877 struct list_head rx_info, rx_used; 878 struct list_head rx_done, tx_free; 879 struct sk_buff_head tx_queue, rx_queue; 880 spinlock_t rx_lock, tx_lock; 881 struct delayed_work schedule, hw_phy_work; 882 struct mii_if_info mii; 883 struct mutex control; /* use for hw setting */ 884#ifdef CONFIG_PM_SLEEP 885 struct notifier_block pm_notifier; 886#endif 887 struct tasklet_struct tx_tl; 888 889 struct rtl_ops { 890 void (*init)(struct r8152 *tp); 891 int (*enable)(struct r8152 *tp); 892 void (*disable)(struct r8152 *tp); 893 void (*up)(struct r8152 *tp); 894 void (*down)(struct r8152 *tp); 895 void (*unload)(struct r8152 *tp); 896 int (*eee_get)(struct r8152 *tp, struct ethtool_keee *eee); 897 int (*eee_set)(struct r8152 *tp, struct ethtool_keee *eee); 898 bool (*in_nway)(struct r8152 *tp); 899 void (*hw_phy_cfg)(struct r8152 *tp); 900 void (*autosuspend_en)(struct r8152 *tp, bool enable); 901 void (*change_mtu)(struct r8152 *tp); 902 } rtl_ops; 903 904 struct ups_info { 905 u32 r_tune:1; 906 u32 _10m_ckdiv:1; 907 u32 _250m_ckdiv:1; 908 u32 aldps:1; 909 u32 lite_mode:2; 910 u32 speed_duplex:4; 911 u32 eee:1; 912 u32 eee_lite:1; 913 u32 eee_ckdiv:1; 914 u32 eee_plloff_100:1; 915 u32 eee_plloff_giga:1; 916 u32 eee_cmod_lv:1; 917 u32 green:1; 918 u32 flow_control:1; 919 u32 ctap_short_off:1; 920 } ups_info; 921 922#define RTL_VER_SIZE 32 923 924 struct rtl_fw { 925 const char *fw_name; 926 const struct firmware *fw; 927 928 char version[RTL_VER_SIZE]; 929 int (*pre_fw)(struct r8152 *tp); 930 int (*post_fw)(struct r8152 *tp); 931 932 bool retry; 933 } rtl_fw; 934 935 atomic_t rx_count; 936 937 bool eee_en; 938 int intr_interval; 939 u32 saved_wolopts; 940 u32 msg_enable; 941 u32 tx_qlen; 942 u32 coalesce; 943 u32 advertising; 944 u32 rx_buf_sz; 945 u32 rx_copybreak; 946 u32 rx_pending; 947 u32 fc_pause_on, fc_pause_off; 948 949 unsigned int pipe_in, pipe_out, pipe_intr, pipe_ctrl_in, pipe_ctrl_out; 950 951 u32 support_2500full:1; 952 u32 lenovo_macpassthru:1; 953 u32 dell_tb_rx_agg_bug:1; 954 u16 ocp_base; 955 u16 speed; 956 u16 eee_adv; 957 u8 *intr_buff; 958 u8 version; 959 u8 duplex; 960 u8 autoneg; 961 962 unsigned int reg_access_reset_count; 963}; 964 965/** 966 * struct fw_block - block type and total length 967 * @type: type of the current block, such as RTL_FW_END, RTL_FW_PLA, 968 * RTL_FW_USB and so on. 969 * @length: total length of the current block. 970 */ 971struct fw_block { 972 __le32 type; 973 __le32 length; 974} __packed; 975 976/** 977 * struct fw_header - header of the firmware file 978 * @checksum: checksum of sha256 which is calculated from the whole file 979 * except the checksum field of the file. That is, calculate sha256 980 * from the version field to the end of the file. 981 * @version: version of this firmware. 982 * @blocks: the first firmware block of the file 983 */ 984struct fw_header { 985 u8 checksum[32]; 986 char version[RTL_VER_SIZE]; 987 struct fw_block blocks[]; 988} __packed; 989 990enum rtl8152_fw_flags { 991 FW_FLAGS_USB = 0, 992 FW_FLAGS_PLA, 993 FW_FLAGS_START, 994 FW_FLAGS_STOP, 995 FW_FLAGS_NC, 996 FW_FLAGS_NC1, 997 FW_FLAGS_NC2, 998 FW_FLAGS_UC2, 999 FW_FLAGS_UC, 1000 FW_FLAGS_SPEED_UP, 1001 FW_FLAGS_VER, 1002}; 1003 1004enum rtl8152_fw_fixup_cmd { 1005 FW_FIXUP_AND = 0, 1006 FW_FIXUP_OR, 1007 FW_FIXUP_NOT, 1008 FW_FIXUP_XOR, 1009}; 1010 1011struct fw_phy_set { 1012 __le16 addr; 1013 __le16 data; 1014} __packed; 1015 1016struct fw_phy_speed_up { 1017 struct fw_block blk_hdr; 1018 __le16 fw_offset; 1019 __le16 version; 1020 __le16 fw_reg; 1021 __le16 reserved; 1022 char info[]; 1023} __packed; 1024 1025struct fw_phy_ver { 1026 struct fw_block blk_hdr; 1027 struct fw_phy_set ver; 1028 __le32 reserved; 1029} __packed; 1030 1031struct fw_phy_fixup { 1032 struct fw_block blk_hdr; 1033 struct fw_phy_set setting; 1034 __le16 bit_cmd; 1035 __le16 reserved; 1036} __packed; 1037 1038struct fw_phy_union { 1039 struct fw_block blk_hdr; 1040 __le16 fw_offset; 1041 __le16 fw_reg; 1042 struct fw_phy_set pre_set[2]; 1043 struct fw_phy_set bp[8]; 1044 struct fw_phy_set bp_en; 1045 u8 pre_num; 1046 u8 bp_num; 1047 char info[]; 1048} __packed; 1049 1050/** 1051 * struct fw_mac - a firmware block used by RTL_FW_PLA and RTL_FW_USB. 1052 * The layout of the firmware block is: 1053 * <struct fw_mac> + <info> + <firmware data>. 1054 * @blk_hdr: firmware descriptor (type, length) 1055 * @fw_offset: offset of the firmware binary data. The start address of 1056 * the data would be the address of struct fw_mac + @fw_offset. 1057 * @fw_reg: the register to load the firmware. Depends on chip. 1058 * @bp_ba_addr: the register to write break point base address. Depends on 1059 * chip. 1060 * @bp_ba_value: break point base address. Depends on chip. 1061 * @bp_en_addr: the register to write break point enabled mask. Depends 1062 * on chip. 1063 * @bp_en_value: break point enabled mask. Depends on the firmware. 1064 * @bp_start: the start register of break points. Depends on chip. 1065 * @bp_num: the break point number which needs to be set for this firmware. 1066 * Depends on the firmware. 1067 * @bp: break points. Depends on firmware. 1068 * @reserved: reserved space (unused) 1069 * @fw_ver_reg: the register to store the fw version. 1070 * @fw_ver_data: the firmware version of the current type. 1071 * @info: additional information for debugging, and is followed by the 1072 * binary data of firmware. 1073 */ 1074struct fw_mac { 1075 struct fw_block blk_hdr; 1076 __le16 fw_offset; 1077 __le16 fw_reg; 1078 __le16 bp_ba_addr; 1079 __le16 bp_ba_value; 1080 __le16 bp_en_addr; 1081 __le16 bp_en_value; 1082 __le16 bp_start; 1083 __le16 bp_num; 1084 __le16 bp[16]; /* any value determined by firmware */ 1085 __le32 reserved; 1086 __le16 fw_ver_reg; 1087 u8 fw_ver_data; 1088 char info[]; 1089} __packed; 1090 1091/** 1092 * struct fw_phy_patch_key - a firmware block used by RTL_FW_PHY_START. 1093 * This is used to set patch key when loading the firmware of PHY. 1094 * @blk_hdr: firmware descriptor (type, length) 1095 * @key_reg: the register to write the patch key. 1096 * @key_data: patch key. 1097 * @reserved: reserved space (unused) 1098 */ 1099struct fw_phy_patch_key { 1100 struct fw_block blk_hdr; 1101 __le16 key_reg; 1102 __le16 key_data; 1103 __le32 reserved; 1104} __packed; 1105 1106/** 1107 * struct fw_phy_nc - a firmware block used by RTL_FW_PHY_NC. 1108 * The layout of the firmware block is: 1109 * <struct fw_phy_nc> + <info> + <firmware data>. 1110 * @blk_hdr: firmware descriptor (type, length) 1111 * @fw_offset: offset of the firmware binary data. The start address of 1112 * the data would be the address of struct fw_phy_nc + @fw_offset. 1113 * @fw_reg: the register to load the firmware. Depends on chip. 1114 * @ba_reg: the register to write the base address. Depends on chip. 1115 * @ba_data: base address. Depends on chip. 1116 * @patch_en_addr: the register of enabling patch mode. Depends on chip. 1117 * @patch_en_value: patch mode enabled mask. Depends on the firmware. 1118 * @mode_reg: the regitster of switching the mode. 1119 * @mode_pre: the mode needing to be set before loading the firmware. 1120 * @mode_post: the mode to be set when finishing to load the firmware. 1121 * @reserved: reserved space (unused) 1122 * @bp_start: the start register of break points. Depends on chip. 1123 * @bp_num: the break point number which needs to be set for this firmware. 1124 * Depends on the firmware. 1125 * @bp: break points. Depends on firmware. 1126 * @info: additional information for debugging, and is followed by the 1127 * binary data of firmware. 1128 */ 1129struct fw_phy_nc { 1130 struct fw_block blk_hdr; 1131 __le16 fw_offset; 1132 __le16 fw_reg; 1133 __le16 ba_reg; 1134 __le16 ba_data; 1135 __le16 patch_en_addr; 1136 __le16 patch_en_value; 1137 __le16 mode_reg; 1138 __le16 mode_pre; 1139 __le16 mode_post; 1140 __le16 reserved; 1141 __le16 bp_start; 1142 __le16 bp_num; 1143 __le16 bp[4]; 1144 char info[]; 1145} __packed; 1146 1147enum rtl_fw_type { 1148 RTL_FW_END = 0, 1149 RTL_FW_PLA, 1150 RTL_FW_USB, 1151 RTL_FW_PHY_START, 1152 RTL_FW_PHY_STOP, 1153 RTL_FW_PHY_NC, 1154 RTL_FW_PHY_FIXUP, 1155 RTL_FW_PHY_UNION_NC, 1156 RTL_FW_PHY_UNION_NC1, 1157 RTL_FW_PHY_UNION_NC2, 1158 RTL_FW_PHY_UNION_UC2, 1159 RTL_FW_PHY_UNION_UC, 1160 RTL_FW_PHY_UNION_MISC, 1161 RTL_FW_PHY_SPEED_UP, 1162 RTL_FW_PHY_VER, 1163}; 1164 1165enum rtl_version { 1166 RTL_VER_UNKNOWN = 0, 1167 RTL_VER_01, 1168 RTL_VER_02, 1169 RTL_VER_03, 1170 RTL_VER_04, 1171 RTL_VER_05, 1172 RTL_VER_06, 1173 RTL_VER_07, 1174 RTL_VER_08, 1175 RTL_VER_09, 1176 1177 RTL_TEST_01, 1178 RTL_VER_10, 1179 RTL_VER_11, 1180 RTL_VER_12, 1181 RTL_VER_13, 1182 RTL_VER_14, 1183 RTL_VER_15, 1184 1185 RTL_VER_MAX 1186}; 1187 1188enum tx_csum_stat { 1189 TX_CSUM_SUCCESS = 0, 1190 TX_CSUM_TSO, 1191 TX_CSUM_NONE 1192}; 1193 1194#define RTL_ADVERTISED_10_HALF BIT(0) 1195#define RTL_ADVERTISED_10_FULL BIT(1) 1196#define RTL_ADVERTISED_100_HALF BIT(2) 1197#define RTL_ADVERTISED_100_FULL BIT(3) 1198#define RTL_ADVERTISED_1000_HALF BIT(4) 1199#define RTL_ADVERTISED_1000_FULL BIT(5) 1200#define RTL_ADVERTISED_2500_FULL BIT(6) 1201 1202/* Maximum number of multicast addresses to filter (vs. Rx-all-multicast). 1203 * The RTL chips use a 64 element hash table based on the Ethernet CRC. 1204 */ 1205static const int multicast_filter_limit = 32; 1206static unsigned int agg_buf_sz = 16384; 1207 1208#define RTL_LIMITED_TSO_SIZE (size_to_mtu(agg_buf_sz) - sizeof(struct tx_desc)) 1209 1210/* If register access fails then we block access and issue a reset. If this 1211 * happens too many times in a row without a successful access then we stop 1212 * trying to reset and just leave access blocked. 1213 */ 1214#define REGISTER_ACCESS_MAX_RESETS 3 1215 1216static void rtl_set_inaccessible(struct r8152 *tp) 1217{ 1218 set_bit(RTL8152_INACCESSIBLE, &tp->flags); 1219 smp_mb__after_atomic(); 1220} 1221 1222static void rtl_set_accessible(struct r8152 *tp) 1223{ 1224 clear_bit(RTL8152_INACCESSIBLE, &tp->flags); 1225 smp_mb__after_atomic(); 1226} 1227 1228static 1229int r8152_control_msg(struct r8152 *tp, unsigned int pipe, __u8 request, 1230 __u8 requesttype, __u16 value, __u16 index, void *data, 1231 __u16 size, const char *msg_tag) 1232{ 1233 struct usb_device *udev = tp->udev; 1234 int ret; 1235 1236 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 1237 return -ENODEV; 1238 1239 ret = usb_control_msg(udev, pipe, request, requesttype, 1240 value, index, data, size, 1241 USB_CTRL_GET_TIMEOUT); 1242 1243 /* No need to issue a reset to report an error if the USB device got 1244 * unplugged; just return immediately. 1245 */ 1246 if (ret == -ENODEV) 1247 return ret; 1248 1249 /* If the write was successful then we're done */ 1250 if (ret >= 0) { 1251 tp->reg_access_reset_count = 0; 1252 return ret; 1253 } 1254 1255 dev_err(&udev->dev, 1256 "Failed to %s %d bytes at %#06x/%#06x (%d)\n", 1257 msg_tag, size, value, index, ret); 1258 1259 /* Block all future register access until we reset. Much of the code 1260 * in the driver doesn't check for errors. Notably, many parts of the 1261 * driver do a read/modify/write of a register value without 1262 * confirming that the read succeeded. Writing back modified garbage 1263 * like this can fully wedge the adapter, requiring a power cycle. 1264 */ 1265 rtl_set_inaccessible(tp); 1266 1267 /* If probe hasn't yet finished, then we'll request a retry of the 1268 * whole probe routine if we get any control transfer errors. We 1269 * never have to clear this bit since we free/reallocate the whole "tp" 1270 * structure if we retry probe. 1271 */ 1272 if (!test_bit(PROBED_WITH_NO_ERRORS, &tp->flags)) { 1273 set_bit(PROBE_SHOULD_RETRY, &tp->flags); 1274 return ret; 1275 } 1276 1277 /* Failing to access registers in pre-reset is not surprising since we 1278 * wouldn't be resetting if things were behaving normally. The register 1279 * access we do in pre-reset isn't truly mandatory--we're just reusing 1280 * the disable() function and trying to be nice by powering the 1281 * adapter down before resetting it. Thus, if we're in pre-reset, 1282 * we'll return right away and not try to queue up yet another reset. 1283 * We know the post-reset is already coming. 1284 */ 1285 if (test_bit(IN_PRE_RESET, &tp->flags)) 1286 return ret; 1287 1288 if (tp->reg_access_reset_count < REGISTER_ACCESS_MAX_RESETS) { 1289 usb_queue_reset_device(tp->intf); 1290 tp->reg_access_reset_count++; 1291 } else if (tp->reg_access_reset_count == REGISTER_ACCESS_MAX_RESETS) { 1292 dev_err(&udev->dev, 1293 "Tried to reset %d times; giving up.\n", 1294 REGISTER_ACCESS_MAX_RESETS); 1295 } 1296 1297 return ret; 1298} 1299 1300static 1301int get_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 1302{ 1303 int ret; 1304 void *tmp; 1305 1306 tmp = kmalloc(size, GFP_KERNEL); 1307 if (!tmp) 1308 return -ENOMEM; 1309 1310 ret = r8152_control_msg(tp, tp->pipe_ctrl_in, 1311 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 1312 value, index, tmp, size, "read"); 1313 1314 if (ret < 0) 1315 memset(data, 0xff, size); 1316 else 1317 memcpy(data, tmp, size); 1318 1319 kfree(tmp); 1320 1321 return ret; 1322} 1323 1324static 1325int set_registers(struct r8152 *tp, u16 value, u16 index, u16 size, void *data) 1326{ 1327 int ret; 1328 void *tmp; 1329 1330 tmp = kmemdup(data, size, GFP_KERNEL); 1331 if (!tmp) 1332 return -ENOMEM; 1333 1334 ret = r8152_control_msg(tp, tp->pipe_ctrl_out, 1335 RTL8152_REQ_SET_REGS, RTL8152_REQT_WRITE, 1336 value, index, tmp, size, "write"); 1337 1338 kfree(tmp); 1339 1340 return ret; 1341} 1342 1343static void rtl_set_unplug(struct r8152 *tp) 1344{ 1345 if (tp->udev->state == USB_STATE_NOTATTACHED) 1346 rtl_set_inaccessible(tp); 1347} 1348 1349static int generic_ocp_read(struct r8152 *tp, u16 index, u16 size, 1350 void *data, u16 type) 1351{ 1352 u16 limit = 64; 1353 int ret = 0; 1354 1355 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 1356 return -ENODEV; 1357 1358 /* both size and indix must be 4 bytes align */ 1359 if ((size & 3) || !size || (index & 3) || !data) 1360 return -EPERM; 1361 1362 if ((u32)index + (u32)size > 0xffff) 1363 return -EPERM; 1364 1365 while (size) { 1366 if (size > limit) { 1367 ret = get_registers(tp, index, type, limit, data); 1368 if (ret < 0) 1369 break; 1370 1371 index += limit; 1372 data += limit; 1373 size -= limit; 1374 } else { 1375 ret = get_registers(tp, index, type, size, data); 1376 if (ret < 0) 1377 break; 1378 1379 index += size; 1380 data += size; 1381 size = 0; 1382 break; 1383 } 1384 } 1385 1386 if (ret == -ENODEV) 1387 rtl_set_unplug(tp); 1388 1389 return ret; 1390} 1391 1392static int generic_ocp_write(struct r8152 *tp, u16 index, u16 byteen, 1393 u16 size, void *data, u16 type) 1394{ 1395 int ret; 1396 u16 byteen_start, byteen_end, byen; 1397 u16 limit = 512; 1398 1399 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 1400 return -ENODEV; 1401 1402 /* both size and indix must be 4 bytes align */ 1403 if ((size & 3) || !size || (index & 3) || !data) 1404 return -EPERM; 1405 1406 if ((u32)index + (u32)size > 0xffff) 1407 return -EPERM; 1408 1409 byteen_start = byteen & BYTE_EN_START_MASK; 1410 byteen_end = byteen & BYTE_EN_END_MASK; 1411 1412 byen = byteen_start | (byteen_start << 4); 1413 1414 /* Split the first DWORD if the byte_en is not 0xff */ 1415 if (byen != BYTE_EN_DWORD) { 1416 ret = set_registers(tp, index, type | byen, 4, data); 1417 if (ret < 0) 1418 goto error1; 1419 1420 index += 4; 1421 data += 4; 1422 size -= 4; 1423 } 1424 1425 if (size) { 1426 byen = byteen_end | (byteen_end >> 4); 1427 1428 /* Split the last DWORD if the byte_en is not 0xff */ 1429 if (byen != BYTE_EN_DWORD) 1430 size -= 4; 1431 1432 while (size) { 1433 if (size > limit) { 1434 ret = set_registers(tp, index, 1435 type | BYTE_EN_DWORD, 1436 limit, data); 1437 if (ret < 0) 1438 goto error1; 1439 1440 index += limit; 1441 data += limit; 1442 size -= limit; 1443 } else { 1444 ret = set_registers(tp, index, 1445 type | BYTE_EN_DWORD, 1446 size, data); 1447 if (ret < 0) 1448 goto error1; 1449 1450 index += size; 1451 data += size; 1452 size = 0; 1453 break; 1454 } 1455 } 1456 1457 /* Set the last DWORD */ 1458 if (byen != BYTE_EN_DWORD) 1459 ret = set_registers(tp, index, type | byen, 4, data); 1460 } 1461 1462error1: 1463 if (ret == -ENODEV) 1464 rtl_set_unplug(tp); 1465 1466 return ret; 1467} 1468 1469static inline 1470int pla_ocp_read(struct r8152 *tp, u16 index, u16 size, void *data) 1471{ 1472 return generic_ocp_read(tp, index, size, data, MCU_TYPE_PLA); 1473} 1474 1475static inline 1476int pla_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 1477{ 1478 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_PLA); 1479} 1480 1481static inline 1482int usb_ocp_write(struct r8152 *tp, u16 index, u16 byteen, u16 size, void *data) 1483{ 1484 return generic_ocp_write(tp, index, byteen, size, data, MCU_TYPE_USB); 1485} 1486 1487static u32 ocp_read_dword(struct r8152 *tp, u16 type, u16 index) 1488{ 1489 __le32 data; 1490 1491 generic_ocp_read(tp, index, sizeof(data), &data, type); 1492 1493 return __le32_to_cpu(data); 1494} 1495 1496static void ocp_write_dword(struct r8152 *tp, u16 type, u16 index, u32 data) 1497{ 1498 __le32 tmp = __cpu_to_le32(data); 1499 1500 generic_ocp_write(tp, index, BYTE_EN_DWORD, sizeof(tmp), &tmp, type); 1501} 1502 1503static u16 ocp_read_word(struct r8152 *tp, u16 type, u16 index) 1504{ 1505 u32 data; 1506 __le32 tmp; 1507 u16 byen = BYTE_EN_WORD; 1508 u8 shift = index & 2; 1509 1510 index &= ~3; 1511 byen <<= shift; 1512 1513 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type | byen); 1514 1515 data = __le32_to_cpu(tmp); 1516 data >>= (shift * 8); 1517 data &= 0xffff; 1518 1519 return (u16)data; 1520} 1521 1522static void ocp_write_word(struct r8152 *tp, u16 type, u16 index, u32 data) 1523{ 1524 u32 mask = 0xffff; 1525 __le32 tmp; 1526 u16 byen = BYTE_EN_WORD; 1527 u8 shift = index & 2; 1528 1529 data &= mask; 1530 1531 if (index & 2) { 1532 byen <<= shift; 1533 mask <<= (shift * 8); 1534 data <<= (shift * 8); 1535 index &= ~3; 1536 } 1537 1538 tmp = __cpu_to_le32(data); 1539 1540 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 1541} 1542 1543static u8 ocp_read_byte(struct r8152 *tp, u16 type, u16 index) 1544{ 1545 u32 data; 1546 __le32 tmp; 1547 u8 shift = index & 3; 1548 1549 index &= ~3; 1550 1551 generic_ocp_read(tp, index, sizeof(tmp), &tmp, type); 1552 1553 data = __le32_to_cpu(tmp); 1554 data >>= (shift * 8); 1555 data &= 0xff; 1556 1557 return (u8)data; 1558} 1559 1560static void ocp_write_byte(struct r8152 *tp, u16 type, u16 index, u32 data) 1561{ 1562 u32 mask = 0xff; 1563 __le32 tmp; 1564 u16 byen = BYTE_EN_BYTE; 1565 u8 shift = index & 3; 1566 1567 data &= mask; 1568 1569 if (index & 3) { 1570 byen <<= shift; 1571 mask <<= (shift * 8); 1572 data <<= (shift * 8); 1573 index &= ~3; 1574 } 1575 1576 tmp = __cpu_to_le32(data); 1577 1578 generic_ocp_write(tp, index, byen, sizeof(tmp), &tmp, type); 1579} 1580 1581static u16 ocp_reg_read(struct r8152 *tp, u16 addr) 1582{ 1583 u16 ocp_base, ocp_index; 1584 1585 ocp_base = addr & 0xf000; 1586 if (ocp_base != tp->ocp_base) { 1587 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 1588 tp->ocp_base = ocp_base; 1589 } 1590 1591 ocp_index = (addr & 0x0fff) | 0xb000; 1592 return ocp_read_word(tp, MCU_TYPE_PLA, ocp_index); 1593} 1594 1595static void ocp_reg_write(struct r8152 *tp, u16 addr, u16 data) 1596{ 1597 u16 ocp_base, ocp_index; 1598 1599 ocp_base = addr & 0xf000; 1600 if (ocp_base != tp->ocp_base) { 1601 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, ocp_base); 1602 tp->ocp_base = ocp_base; 1603 } 1604 1605 ocp_index = (addr & 0x0fff) | 0xb000; 1606 ocp_write_word(tp, MCU_TYPE_PLA, ocp_index, data); 1607} 1608 1609static inline void r8152_mdio_write(struct r8152 *tp, u32 reg_addr, u32 value) 1610{ 1611 ocp_reg_write(tp, OCP_BASE_MII + reg_addr * 2, value); 1612} 1613 1614static inline int r8152_mdio_read(struct r8152 *tp, u32 reg_addr) 1615{ 1616 return ocp_reg_read(tp, OCP_BASE_MII + reg_addr * 2); 1617} 1618 1619static void sram_write(struct r8152 *tp, u16 addr, u16 data) 1620{ 1621 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 1622 ocp_reg_write(tp, OCP_SRAM_DATA, data); 1623} 1624 1625static u16 sram_read(struct r8152 *tp, u16 addr) 1626{ 1627 ocp_reg_write(tp, OCP_SRAM_ADDR, addr); 1628 return ocp_reg_read(tp, OCP_SRAM_DATA); 1629} 1630 1631static int read_mii_word(struct net_device *netdev, int phy_id, int reg) 1632{ 1633 struct r8152 *tp = netdev_priv(netdev); 1634 int ret; 1635 1636 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 1637 return -ENODEV; 1638 1639 if (phy_id != R8152_PHY_ID) 1640 return -EINVAL; 1641 1642 ret = r8152_mdio_read(tp, reg); 1643 1644 return ret; 1645} 1646 1647static 1648void write_mii_word(struct net_device *netdev, int phy_id, int reg, int val) 1649{ 1650 struct r8152 *tp = netdev_priv(netdev); 1651 1652 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 1653 return; 1654 1655 if (phy_id != R8152_PHY_ID) 1656 return; 1657 1658 r8152_mdio_write(tp, reg, val); 1659} 1660 1661static int 1662r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags); 1663 1664static int 1665rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex, 1666 u32 advertising); 1667 1668static int __rtl8152_set_mac_address(struct net_device *netdev, 1669 struct sockaddr_storage *addr, 1670 bool in_resume) 1671{ 1672 struct r8152 *tp = netdev_priv(netdev); 1673 int ret = -EADDRNOTAVAIL; 1674 1675 if (!is_valid_ether_addr(addr->__data)) 1676 goto out1; 1677 1678 if (!in_resume) { 1679 ret = usb_autopm_get_interface(tp->intf); 1680 if (ret < 0) 1681 goto out1; 1682 } 1683 1684 mutex_lock(&tp->control); 1685 1686 eth_hw_addr_set(netdev, addr->__data); 1687 1688 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 1689 pla_ocp_write(tp, PLA_IDR, BYTE_EN_SIX_BYTES, 8, addr->__data); 1690 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 1691 1692 mutex_unlock(&tp->control); 1693 1694 if (!in_resume) 1695 usb_autopm_put_interface(tp->intf); 1696out1: 1697 return ret; 1698} 1699 1700static int rtl8152_set_mac_address(struct net_device *netdev, void *p) 1701{ 1702 return __rtl8152_set_mac_address(netdev, p, false); 1703} 1704 1705/* Devices containing proper chips can support a persistent 1706 * host system provided MAC address. 1707 * Examples of this are Dell TB15 and Dell WD15 docks 1708 */ 1709static int vendor_mac_passthru_addr_read(struct r8152 *tp, 1710 struct sockaddr_storage *ss) 1711{ 1712 acpi_status status; 1713 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL }; 1714 union acpi_object *obj; 1715 int ret = -EINVAL; 1716 u32 ocp_data; 1717 unsigned char buf[6]; 1718 char *mac_obj_name; 1719 acpi_object_type mac_obj_type; 1720 int mac_strlen; 1721 1722 if (tp->lenovo_macpassthru) { 1723 mac_obj_name = "\\MACA"; 1724 mac_obj_type = ACPI_TYPE_STRING; 1725 mac_strlen = 0x16; 1726 } else { 1727 /* test for -AD variant of RTL8153 */ 1728 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 1729 if ((ocp_data & AD_MASK) == 0x1000) { 1730 /* test for MAC address pass-through bit */ 1731 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, EFUSE); 1732 if ((ocp_data & PASS_THRU_MASK) != 1) { 1733 netif_dbg(tp, probe, tp->netdev, 1734 "No efuse for RTL8153-AD MAC pass through\n"); 1735 return -ENODEV; 1736 } 1737 } else { 1738 /* test for RTL8153-BND and RTL8153-BD */ 1739 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1); 1740 if ((ocp_data & BND_MASK) == 0 && (ocp_data & BD_MASK) == 0) { 1741 netif_dbg(tp, probe, tp->netdev, 1742 "Invalid variant for MAC pass through\n"); 1743 return -ENODEV; 1744 } 1745 } 1746 1747 mac_obj_name = "\\_SB.AMAC"; 1748 mac_obj_type = ACPI_TYPE_BUFFER; 1749 mac_strlen = 0x17; 1750 } 1751 1752 /* returns _AUXMAC_#AABBCCDDEEFF# */ 1753 status = acpi_evaluate_object(NULL, mac_obj_name, NULL, &buffer); 1754 obj = (union acpi_object *)buffer.pointer; 1755 if (!ACPI_SUCCESS(status)) 1756 return -ENODEV; 1757 if (obj->type != mac_obj_type || obj->string.length != mac_strlen) { 1758 netif_warn(tp, probe, tp->netdev, 1759 "Invalid buffer for pass-thru MAC addr: (%d, %d)\n", 1760 obj->type, obj->string.length); 1761 goto amacout; 1762 } 1763 1764 if (strncmp(obj->string.pointer, "_AUXMAC_#", 9) != 0 || 1765 strncmp(obj->string.pointer + 0x15, "#", 1) != 0) { 1766 netif_warn(tp, probe, tp->netdev, 1767 "Invalid header when reading pass-thru MAC addr\n"); 1768 goto amacout; 1769 } 1770 ret = hex2bin(buf, obj->string.pointer + 9, 6); 1771 if (!(ret == 0 && is_valid_ether_addr(buf))) { 1772 netif_warn(tp, probe, tp->netdev, 1773 "Invalid MAC for pass-thru MAC addr: %d, %pM\n", 1774 ret, buf); 1775 ret = -EINVAL; 1776 goto amacout; 1777 } 1778 memcpy(ss->__data, buf, 6); 1779 tp->netdev->addr_assign_type = NET_ADDR_STOLEN; 1780 netif_info(tp, probe, tp->netdev, 1781 "Using pass-thru MAC addr %pM\n", ss->__data); 1782 1783amacout: 1784 kfree(obj); 1785 return ret; 1786} 1787 1788static int determine_ethernet_addr(struct r8152 *tp, 1789 struct sockaddr_storage *ss) 1790{ 1791 struct net_device *dev = tp->netdev; 1792 int ret; 1793 1794 ss->ss_family = dev->type; 1795 1796 ret = eth_platform_get_mac_address(&tp->udev->dev, ss->__data); 1797 if (ret < 0) { 1798 if (tp->version == RTL_VER_01) { 1799 ret = pla_ocp_read(tp, PLA_IDR, 8, ss->__data); 1800 } else { 1801 /* if device doesn't support MAC pass through this will 1802 * be expected to be non-zero 1803 */ 1804 ret = vendor_mac_passthru_addr_read(tp, ss); 1805 if (ret < 0) 1806 ret = pla_ocp_read(tp, PLA_BACKUP, 8, 1807 ss->__data); 1808 } 1809 } 1810 1811 if (ret < 0) { 1812 netif_err(tp, probe, dev, "Get ether addr fail\n"); 1813 } else if (!is_valid_ether_addr(ss->__data)) { 1814 netif_err(tp, probe, dev, "Invalid ether addr %pM\n", 1815 ss->__data); 1816 eth_hw_addr_random(dev); 1817 ether_addr_copy(ss->__data, dev->dev_addr); 1818 netif_info(tp, probe, dev, "Random ether addr %pM\n", 1819 ss->__data); 1820 return 0; 1821 } 1822 1823 return ret; 1824} 1825 1826static int set_ethernet_addr(struct r8152 *tp, bool in_resume) 1827{ 1828 struct net_device *dev = tp->netdev; 1829 struct sockaddr_storage ss; 1830 int ret; 1831 1832 ret = determine_ethernet_addr(tp, &ss); 1833 if (ret < 0) 1834 return ret; 1835 1836 if (tp->version == RTL_VER_01) 1837 eth_hw_addr_set(dev, ss.__data); 1838 else 1839 ret = __rtl8152_set_mac_address(dev, &ss, in_resume); 1840 1841 return ret; 1842} 1843 1844static void read_bulk_callback(struct urb *urb) 1845{ 1846 struct net_device *netdev; 1847 int status = urb->status; 1848 struct rx_agg *agg; 1849 struct r8152 *tp; 1850 unsigned long flags; 1851 1852 agg = urb->context; 1853 if (!agg) 1854 return; 1855 1856 tp = agg->context; 1857 if (!tp) 1858 return; 1859 1860 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 1861 return; 1862 1863 if (!test_bit(WORK_ENABLE, &tp->flags)) 1864 return; 1865 1866 netdev = tp->netdev; 1867 1868 /* When link down, the driver would cancel all bulks. */ 1869 /* This avoid the re-submitting bulk */ 1870 if (!netif_carrier_ok(netdev)) 1871 return; 1872 1873 usb_mark_last_busy(tp->udev); 1874 1875 switch (status) { 1876 case 0: 1877 if (urb->actual_length < ETH_ZLEN) 1878 break; 1879 1880 spin_lock_irqsave(&tp->rx_lock, flags); 1881 list_add_tail(&agg->list, &tp->rx_done); 1882 spin_unlock_irqrestore(&tp->rx_lock, flags); 1883 napi_schedule(&tp->napi); 1884 return; 1885 case -ESHUTDOWN: 1886 rtl_set_unplug(tp); 1887 netif_device_detach(tp->netdev); 1888 return; 1889 case -EPROTO: 1890 urb->actual_length = 0; 1891 spin_lock_irqsave(&tp->rx_lock, flags); 1892 list_add_tail(&agg->list, &tp->rx_done); 1893 spin_unlock_irqrestore(&tp->rx_lock, flags); 1894 set_bit(RX_EPROTO, &tp->flags); 1895 schedule_delayed_work(&tp->schedule, 1); 1896 return; 1897 case -ENOENT: 1898 return; /* the urb is in unlink state */ 1899 case -ETIME: 1900 if (net_ratelimit()) 1901 netdev_warn(netdev, "maybe reset is needed?\n"); 1902 break; 1903 default: 1904 if (net_ratelimit()) 1905 netdev_warn(netdev, "Rx status %d\n", status); 1906 break; 1907 } 1908 1909 r8152_submit_rx(tp, agg, GFP_ATOMIC); 1910} 1911 1912static void write_bulk_callback(struct urb *urb) 1913{ 1914 struct net_device_stats *stats; 1915 struct net_device *netdev; 1916 struct tx_agg *agg; 1917 struct r8152 *tp; 1918 unsigned long flags; 1919 int status = urb->status; 1920 1921 agg = urb->context; 1922 if (!agg) 1923 return; 1924 1925 tp = agg->context; 1926 if (!tp) 1927 return; 1928 1929 netdev = tp->netdev; 1930 stats = &netdev->stats; 1931 if (status) { 1932 if (net_ratelimit()) 1933 netdev_warn(netdev, "Tx status %d\n", status); 1934 stats->tx_errors += agg->skb_num; 1935 } else { 1936 stats->tx_packets += agg->skb_num; 1937 stats->tx_bytes += agg->skb_len; 1938 } 1939 1940 spin_lock_irqsave(&tp->tx_lock, flags); 1941 list_add_tail(&agg->list, &tp->tx_free); 1942 spin_unlock_irqrestore(&tp->tx_lock, flags); 1943 1944 usb_autopm_put_interface_async(tp->intf); 1945 1946 if (!netif_carrier_ok(netdev)) 1947 return; 1948 1949 if (!test_bit(WORK_ENABLE, &tp->flags)) 1950 return; 1951 1952 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 1953 return; 1954 1955 if (!skb_queue_empty(&tp->tx_queue)) 1956 tasklet_schedule(&tp->tx_tl); 1957} 1958 1959static void intr_callback(struct urb *urb) 1960{ 1961 struct r8152 *tp; 1962 __le16 *d; 1963 int status = urb->status; 1964 int res; 1965 1966 tp = urb->context; 1967 if (!tp) 1968 return; 1969 1970 if (!test_bit(WORK_ENABLE, &tp->flags)) 1971 return; 1972 1973 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 1974 return; 1975 1976 switch (status) { 1977 case 0: /* success */ 1978 break; 1979 case -ECONNRESET: /* unlink */ 1980 case -ESHUTDOWN: 1981 netif_device_detach(tp->netdev); 1982 fallthrough; 1983 case -ENOENT: 1984 case -EPROTO: 1985 netif_info(tp, intr, tp->netdev, 1986 "Stop submitting intr, status %d\n", status); 1987 return; 1988 case -EOVERFLOW: 1989 if (net_ratelimit()) 1990 netif_info(tp, intr, tp->netdev, 1991 "intr status -EOVERFLOW\n"); 1992 goto resubmit; 1993 /* -EPIPE: should clear the halt */ 1994 default: 1995 netif_info(tp, intr, tp->netdev, "intr status %d\n", status); 1996 goto resubmit; 1997 } 1998 1999 d = urb->transfer_buffer; 2000 if (INTR_LINK & __le16_to_cpu(d[0])) { 2001 if (!netif_carrier_ok(tp->netdev)) { 2002 set_bit(RTL8152_LINK_CHG, &tp->flags); 2003 schedule_delayed_work(&tp->schedule, 0); 2004 } 2005 } else { 2006 if (netif_carrier_ok(tp->netdev)) { 2007 netif_stop_queue(tp->netdev); 2008 set_bit(RTL8152_LINK_CHG, &tp->flags); 2009 schedule_delayed_work(&tp->schedule, 0); 2010 } 2011 } 2012 2013resubmit: 2014 res = usb_submit_urb(urb, GFP_ATOMIC); 2015 if (res == -ENODEV) { 2016 rtl_set_unplug(tp); 2017 netif_device_detach(tp->netdev); 2018 } else if (res) { 2019 netif_err(tp, intr, tp->netdev, 2020 "can't resubmit intr, status %d\n", res); 2021 } 2022} 2023 2024static inline void *rx_agg_align(void *data) 2025{ 2026 return (void *)ALIGN((uintptr_t)data, RX_ALIGN); 2027} 2028 2029static inline void *tx_agg_align(void *data) 2030{ 2031 return (void *)ALIGN((uintptr_t)data, TX_ALIGN); 2032} 2033 2034static void free_rx_agg(struct r8152 *tp, struct rx_agg *agg) 2035{ 2036 list_del(&agg->info_list); 2037 2038 usb_free_urb(agg->urb); 2039 put_page(agg->page); 2040 kfree(agg); 2041 2042 atomic_dec(&tp->rx_count); 2043} 2044 2045static struct rx_agg *alloc_rx_agg(struct r8152 *tp, gfp_t mflags) 2046{ 2047 struct net_device *netdev = tp->netdev; 2048 int node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 2049 unsigned int order = get_order(tp->rx_buf_sz); 2050 struct rx_agg *rx_agg; 2051 unsigned long flags; 2052 2053 rx_agg = kmalloc_node(sizeof(*rx_agg), mflags, node); 2054 if (!rx_agg) 2055 return NULL; 2056 2057 rx_agg->page = alloc_pages(mflags | __GFP_COMP | __GFP_NOWARN, order); 2058 if (!rx_agg->page) 2059 goto free_rx; 2060 2061 rx_agg->buffer = page_address(rx_agg->page); 2062 2063 rx_agg->urb = usb_alloc_urb(0, mflags); 2064 if (!rx_agg->urb) 2065 goto free_buf; 2066 2067 rx_agg->context = tp; 2068 2069 INIT_LIST_HEAD(&rx_agg->list); 2070 INIT_LIST_HEAD(&rx_agg->info_list); 2071 spin_lock_irqsave(&tp->rx_lock, flags); 2072 list_add_tail(&rx_agg->info_list, &tp->rx_info); 2073 spin_unlock_irqrestore(&tp->rx_lock, flags); 2074 2075 atomic_inc(&tp->rx_count); 2076 2077 return rx_agg; 2078 2079free_buf: 2080 __free_pages(rx_agg->page, order); 2081free_rx: 2082 kfree(rx_agg); 2083 return NULL; 2084} 2085 2086static void free_all_mem(struct r8152 *tp) 2087{ 2088 struct rx_agg *agg, *agg_next; 2089 unsigned long flags; 2090 int i; 2091 2092 spin_lock_irqsave(&tp->rx_lock, flags); 2093 2094 list_for_each_entry_safe(agg, agg_next, &tp->rx_info, info_list) 2095 free_rx_agg(tp, agg); 2096 2097 spin_unlock_irqrestore(&tp->rx_lock, flags); 2098 2099 WARN_ON(atomic_read(&tp->rx_count)); 2100 2101 for (i = 0; i < RTL8152_MAX_TX; i++) { 2102 usb_free_urb(tp->tx_info[i].urb); 2103 tp->tx_info[i].urb = NULL; 2104 2105 kfree(tp->tx_info[i].buffer); 2106 tp->tx_info[i].buffer = NULL; 2107 tp->tx_info[i].head = NULL; 2108 } 2109 2110 usb_free_urb(tp->intr_urb); 2111 tp->intr_urb = NULL; 2112 2113 kfree(tp->intr_buff); 2114 tp->intr_buff = NULL; 2115} 2116 2117static int alloc_all_mem(struct r8152 *tp) 2118{ 2119 struct net_device *netdev = tp->netdev; 2120 struct usb_interface *intf = tp->intf; 2121 struct usb_host_interface *alt = intf->cur_altsetting; 2122 struct usb_host_endpoint *ep_intr = alt->endpoint + 2; 2123 int node, i; 2124 2125 node = netdev->dev.parent ? dev_to_node(netdev->dev.parent) : -1; 2126 2127 spin_lock_init(&tp->rx_lock); 2128 spin_lock_init(&tp->tx_lock); 2129 INIT_LIST_HEAD(&tp->rx_info); 2130 INIT_LIST_HEAD(&tp->tx_free); 2131 INIT_LIST_HEAD(&tp->rx_done); 2132 skb_queue_head_init(&tp->tx_queue); 2133 skb_queue_head_init(&tp->rx_queue); 2134 atomic_set(&tp->rx_count, 0); 2135 2136 for (i = 0; i < RTL8152_MAX_RX; i++) { 2137 if (!alloc_rx_agg(tp, GFP_KERNEL)) 2138 goto err1; 2139 } 2140 2141 for (i = 0; i < RTL8152_MAX_TX; i++) { 2142 struct urb *urb; 2143 u8 *buf; 2144 2145 buf = kmalloc_node(agg_buf_sz, GFP_KERNEL, node); 2146 if (!buf) 2147 goto err1; 2148 2149 if (buf != tx_agg_align(buf)) { 2150 kfree(buf); 2151 buf = kmalloc_node(agg_buf_sz + TX_ALIGN, GFP_KERNEL, 2152 node); 2153 if (!buf) 2154 goto err1; 2155 } 2156 2157 urb = usb_alloc_urb(0, GFP_KERNEL); 2158 if (!urb) { 2159 kfree(buf); 2160 goto err1; 2161 } 2162 2163 INIT_LIST_HEAD(&tp->tx_info[i].list); 2164 tp->tx_info[i].context = tp; 2165 tp->tx_info[i].urb = urb; 2166 tp->tx_info[i].buffer = buf; 2167 tp->tx_info[i].head = tx_agg_align(buf); 2168 2169 list_add_tail(&tp->tx_info[i].list, &tp->tx_free); 2170 } 2171 2172 tp->intr_urb = usb_alloc_urb(0, GFP_KERNEL); 2173 if (!tp->intr_urb) 2174 goto err1; 2175 2176 tp->intr_buff = kmalloc(INTBUFSIZE, GFP_KERNEL); 2177 if (!tp->intr_buff) 2178 goto err1; 2179 2180 tp->intr_interval = (int)ep_intr->desc.bInterval; 2181 usb_fill_int_urb(tp->intr_urb, tp->udev, tp->pipe_intr, 2182 tp->intr_buff, INTBUFSIZE, intr_callback, 2183 tp, tp->intr_interval); 2184 2185 return 0; 2186 2187err1: 2188 free_all_mem(tp); 2189 return -ENOMEM; 2190} 2191 2192static struct tx_agg *r8152_get_tx_agg(struct r8152 *tp) 2193{ 2194 struct tx_agg *agg = NULL; 2195 unsigned long flags; 2196 2197 if (list_empty(&tp->tx_free)) 2198 return NULL; 2199 2200 spin_lock_irqsave(&tp->tx_lock, flags); 2201 if (!list_empty(&tp->tx_free)) { 2202 struct list_head *cursor; 2203 2204 cursor = tp->tx_free.next; 2205 list_del_init(cursor); 2206 agg = list_entry(cursor, struct tx_agg, list); 2207 } 2208 spin_unlock_irqrestore(&tp->tx_lock, flags); 2209 2210 return agg; 2211} 2212 2213/* r8152_csum_workaround() 2214 * The hw limits the value of the transport offset. When the offset is out of 2215 * range, calculate the checksum by sw. 2216 */ 2217static void r8152_csum_workaround(struct r8152 *tp, struct sk_buff *skb, 2218 struct sk_buff_head *list) 2219{ 2220 if (skb_shinfo(skb)->gso_size) { 2221 netdev_features_t features = tp->netdev->features; 2222 struct sk_buff *segs, *seg, *next; 2223 struct sk_buff_head seg_list; 2224 2225 features &= ~(NETIF_F_SG | NETIF_F_IPV6_CSUM | NETIF_F_TSO6); 2226 segs = skb_gso_segment(skb, features); 2227 if (IS_ERR(segs) || !segs) 2228 goto drop; 2229 2230 __skb_queue_head_init(&seg_list); 2231 2232 skb_list_walk_safe(segs, seg, next) { 2233 skb_mark_not_on_list(seg); 2234 __skb_queue_tail(&seg_list, seg); 2235 } 2236 2237 skb_queue_splice(&seg_list, list); 2238 dev_kfree_skb(skb); 2239 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 2240 if (skb_checksum_help(skb) < 0) 2241 goto drop; 2242 2243 __skb_queue_head(list, skb); 2244 } else { 2245 struct net_device_stats *stats; 2246 2247drop: 2248 stats = &tp->netdev->stats; 2249 stats->tx_dropped++; 2250 dev_kfree_skb(skb); 2251 } 2252} 2253 2254static inline void rtl_tx_vlan_tag(struct tx_desc *desc, struct sk_buff *skb) 2255{ 2256 if (skb_vlan_tag_present(skb)) { 2257 u32 opts2; 2258 2259 opts2 = TX_VLAN_TAG | swab16(skb_vlan_tag_get(skb)); 2260 desc->opts2 |= cpu_to_le32(opts2); 2261 } 2262} 2263 2264static inline void rtl_rx_vlan_tag(struct rx_desc *desc, struct sk_buff *skb) 2265{ 2266 u32 opts2 = le32_to_cpu(desc->opts2); 2267 2268 if (opts2 & RX_VLAN_TAG) 2269 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), 2270 swab16(opts2 & 0xffff)); 2271} 2272 2273static int r8152_tx_csum(struct r8152 *tp, struct tx_desc *desc, 2274 struct sk_buff *skb, u32 len) 2275{ 2276 u32 mss = skb_shinfo(skb)->gso_size; 2277 u32 opts1, opts2 = 0; 2278 int ret = TX_CSUM_SUCCESS; 2279 2280 WARN_ON_ONCE(len > TX_LEN_MAX); 2281 2282 opts1 = len | TX_FS | TX_LS; 2283 2284 if (mss) { 2285 u32 transport_offset = (u32)skb_transport_offset(skb); 2286 2287 if (transport_offset > GTTCPHO_MAX) { 2288 netif_warn(tp, tx_err, tp->netdev, 2289 "Invalid transport offset 0x%x for TSO\n", 2290 transport_offset); 2291 ret = TX_CSUM_TSO; 2292 goto unavailable; 2293 } 2294 2295 switch (vlan_get_protocol(skb)) { 2296 case htons(ETH_P_IP): 2297 opts1 |= GTSENDV4; 2298 break; 2299 2300 case htons(ETH_P_IPV6): 2301 if (skb_cow_head(skb, 0)) { 2302 ret = TX_CSUM_TSO; 2303 goto unavailable; 2304 } 2305 tcp_v6_gso_csum_prep(skb); 2306 opts1 |= GTSENDV6; 2307 break; 2308 2309 default: 2310 WARN_ON_ONCE(1); 2311 break; 2312 } 2313 2314 opts1 |= transport_offset << GTTCPHO_SHIFT; 2315 opts2 |= min(mss, MSS_MAX) << MSS_SHIFT; 2316 } else if (skb->ip_summed == CHECKSUM_PARTIAL) { 2317 u32 transport_offset = (u32)skb_transport_offset(skb); 2318 u8 ip_protocol; 2319 2320 if (transport_offset > TCPHO_MAX) { 2321 netif_warn(tp, tx_err, tp->netdev, 2322 "Invalid transport offset 0x%x\n", 2323 transport_offset); 2324 ret = TX_CSUM_NONE; 2325 goto unavailable; 2326 } 2327 2328 switch (vlan_get_protocol(skb)) { 2329 case htons(ETH_P_IP): 2330 opts2 |= IPV4_CS; 2331 ip_protocol = ip_hdr(skb)->protocol; 2332 break; 2333 2334 case htons(ETH_P_IPV6): 2335 opts2 |= IPV6_CS; 2336 ip_protocol = ipv6_hdr(skb)->nexthdr; 2337 break; 2338 2339 default: 2340 ip_protocol = IPPROTO_RAW; 2341 break; 2342 } 2343 2344 if (ip_protocol == IPPROTO_TCP) 2345 opts2 |= TCP_CS; 2346 else if (ip_protocol == IPPROTO_UDP) 2347 opts2 |= UDP_CS; 2348 else 2349 WARN_ON_ONCE(1); 2350 2351 opts2 |= transport_offset << TCPHO_SHIFT; 2352 } 2353 2354 desc->opts2 = cpu_to_le32(opts2); 2355 desc->opts1 = cpu_to_le32(opts1); 2356 2357unavailable: 2358 return ret; 2359} 2360 2361static int r8152_tx_agg_fill(struct r8152 *tp, struct tx_agg *agg) 2362{ 2363 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 2364 int remain, ret; 2365 u8 *tx_data; 2366 2367 __skb_queue_head_init(&skb_head); 2368 spin_lock(&tx_queue->lock); 2369 skb_queue_splice_init(tx_queue, &skb_head); 2370 spin_unlock(&tx_queue->lock); 2371 2372 tx_data = agg->head; 2373 agg->skb_num = 0; 2374 agg->skb_len = 0; 2375 remain = agg_buf_sz; 2376 2377 while (remain >= ETH_ZLEN + sizeof(struct tx_desc)) { 2378 struct tx_desc *tx_desc; 2379 struct sk_buff *skb; 2380 unsigned int len; 2381 2382 skb = __skb_dequeue(&skb_head); 2383 if (!skb) 2384 break; 2385 2386 len = skb->len + sizeof(*tx_desc); 2387 2388 if (len > remain) { 2389 __skb_queue_head(&skb_head, skb); 2390 break; 2391 } 2392 2393 tx_data = tx_agg_align(tx_data); 2394 tx_desc = (struct tx_desc *)tx_data; 2395 2396 if (r8152_tx_csum(tp, tx_desc, skb, skb->len)) { 2397 r8152_csum_workaround(tp, skb, &skb_head); 2398 continue; 2399 } 2400 2401 rtl_tx_vlan_tag(tx_desc, skb); 2402 2403 tx_data += sizeof(*tx_desc); 2404 2405 len = skb->len; 2406 if (skb_copy_bits(skb, 0, tx_data, len) < 0) { 2407 struct net_device_stats *stats = &tp->netdev->stats; 2408 2409 stats->tx_dropped++; 2410 dev_kfree_skb_any(skb); 2411 tx_data -= sizeof(*tx_desc); 2412 continue; 2413 } 2414 2415 tx_data += len; 2416 agg->skb_len += len; 2417 agg->skb_num += skb_shinfo(skb)->gso_segs ?: 1; 2418 2419 dev_kfree_skb_any(skb); 2420 2421 remain = agg_buf_sz - (int)(tx_agg_align(tx_data) - agg->head); 2422 2423 if (tp->dell_tb_rx_agg_bug) 2424 break; 2425 } 2426 2427 if (!skb_queue_empty(&skb_head)) { 2428 spin_lock(&tx_queue->lock); 2429 skb_queue_splice(&skb_head, tx_queue); 2430 spin_unlock(&tx_queue->lock); 2431 } 2432 2433 netif_tx_lock(tp->netdev); 2434 2435 if (netif_queue_stopped(tp->netdev) && 2436 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) 2437 netif_wake_queue(tp->netdev); 2438 2439 netif_tx_unlock(tp->netdev); 2440 2441 ret = usb_autopm_get_interface_async(tp->intf); 2442 if (ret < 0) 2443 goto out_tx_fill; 2444 2445 usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_out, 2446 agg->head, (int)(tx_data - (u8 *)agg->head), 2447 (usb_complete_t)write_bulk_callback, agg); 2448 2449 ret = usb_submit_urb(agg->urb, GFP_ATOMIC); 2450 if (ret < 0) 2451 usb_autopm_put_interface_async(tp->intf); 2452 else 2453 netif_trans_update(tp->netdev); 2454 2455out_tx_fill: 2456 return ret; 2457} 2458 2459static u8 r8152_rx_csum(struct r8152 *tp, struct rx_desc *rx_desc) 2460{ 2461 u8 checksum = CHECKSUM_NONE; 2462 u32 opts2, opts3; 2463 2464 if (!(tp->netdev->features & NETIF_F_RXCSUM)) 2465 goto return_result; 2466 2467 opts2 = le32_to_cpu(rx_desc->opts2); 2468 opts3 = le32_to_cpu(rx_desc->opts3); 2469 2470 if (opts2 & RD_IPV4_CS) { 2471 if (opts3 & IPF) 2472 checksum = CHECKSUM_NONE; 2473 else if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 2474 checksum = CHECKSUM_UNNECESSARY; 2475 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 2476 checksum = CHECKSUM_UNNECESSARY; 2477 } else if (opts2 & RD_IPV6_CS) { 2478 if ((opts2 & RD_UDP_CS) && !(opts3 & UDPF)) 2479 checksum = CHECKSUM_UNNECESSARY; 2480 else if ((opts2 & RD_TCP_CS) && !(opts3 & TCPF)) 2481 checksum = CHECKSUM_UNNECESSARY; 2482 } 2483 2484return_result: 2485 return checksum; 2486} 2487 2488static inline bool rx_count_exceed(struct r8152 *tp) 2489{ 2490 return atomic_read(&tp->rx_count) > RTL8152_MAX_RX; 2491} 2492 2493static inline int agg_offset(struct rx_agg *agg, void *addr) 2494{ 2495 return (int)(addr - agg->buffer); 2496} 2497 2498static struct rx_agg *rtl_get_free_rx(struct r8152 *tp, gfp_t mflags) 2499{ 2500 struct rx_agg *agg, *agg_next, *agg_free = NULL; 2501 unsigned long flags; 2502 2503 spin_lock_irqsave(&tp->rx_lock, flags); 2504 2505 list_for_each_entry_safe(agg, agg_next, &tp->rx_used, list) { 2506 if (page_count(agg->page) == 1) { 2507 if (!agg_free) { 2508 list_del_init(&agg->list); 2509 agg_free = agg; 2510 continue; 2511 } 2512 if (rx_count_exceed(tp)) { 2513 list_del_init(&agg->list); 2514 free_rx_agg(tp, agg); 2515 } 2516 break; 2517 } 2518 } 2519 2520 spin_unlock_irqrestore(&tp->rx_lock, flags); 2521 2522 if (!agg_free && atomic_read(&tp->rx_count) < tp->rx_pending) 2523 agg_free = alloc_rx_agg(tp, mflags); 2524 2525 return agg_free; 2526} 2527 2528static int rx_bottom(struct r8152 *tp, int budget) 2529{ 2530 unsigned long flags; 2531 struct list_head *cursor, *next, rx_queue; 2532 int ret = 0, work_done = 0; 2533 struct napi_struct *napi = &tp->napi; 2534 2535 if (!skb_queue_empty(&tp->rx_queue)) { 2536 while (work_done < budget) { 2537 struct sk_buff *skb = __skb_dequeue(&tp->rx_queue); 2538 struct net_device *netdev = tp->netdev; 2539 struct net_device_stats *stats = &netdev->stats; 2540 unsigned int pkt_len; 2541 2542 if (!skb) 2543 break; 2544 2545 pkt_len = skb->len; 2546 napi_gro_receive(napi, skb); 2547 work_done++; 2548 stats->rx_packets++; 2549 stats->rx_bytes += pkt_len; 2550 } 2551 } 2552 2553 if (list_empty(&tp->rx_done) || work_done >= budget) 2554 goto out1; 2555 2556 clear_bit(RX_EPROTO, &tp->flags); 2557 INIT_LIST_HEAD(&rx_queue); 2558 spin_lock_irqsave(&tp->rx_lock, flags); 2559 list_splice_init(&tp->rx_done, &rx_queue); 2560 spin_unlock_irqrestore(&tp->rx_lock, flags); 2561 2562 list_for_each_safe(cursor, next, &rx_queue) { 2563 struct rx_desc *rx_desc; 2564 struct rx_agg *agg, *agg_free; 2565 int len_used = 0; 2566 struct urb *urb; 2567 u8 *rx_data; 2568 2569 /* A bulk transfer of USB may contain may packets, so the 2570 * total packets may more than the budget. Deal with all 2571 * packets in current bulk transfer, and stop to handle the 2572 * next bulk transfer until next schedule, if budget is 2573 * exhausted. 2574 */ 2575 if (work_done >= budget) 2576 break; 2577 2578 list_del_init(cursor); 2579 2580 agg = list_entry(cursor, struct rx_agg, list); 2581 urb = agg->urb; 2582 if (urb->status != 0 || urb->actual_length < ETH_ZLEN) 2583 goto submit; 2584 2585 agg_free = rtl_get_free_rx(tp, GFP_ATOMIC); 2586 2587 rx_desc = agg->buffer; 2588 rx_data = agg->buffer; 2589 len_used += sizeof(struct rx_desc); 2590 2591 while (urb->actual_length > len_used) { 2592 struct net_device *netdev = tp->netdev; 2593 struct net_device_stats *stats = &netdev->stats; 2594 unsigned int pkt_len, rx_frag_head_sz, len; 2595 struct sk_buff *skb; 2596 bool use_frags; 2597 2598 WARN_ON_ONCE(skb_queue_len(&tp->rx_queue) >= 1000); 2599 2600 pkt_len = le32_to_cpu(rx_desc->opts1) & RX_LEN_MASK; 2601 if (pkt_len < ETH_ZLEN) 2602 break; 2603 2604 len_used += pkt_len; 2605 if (urb->actual_length < len_used) 2606 break; 2607 2608 pkt_len -= ETH_FCS_LEN; 2609 len = pkt_len; 2610 rx_data += sizeof(struct rx_desc); 2611 2612 if (!agg_free || tp->rx_copybreak > len) 2613 use_frags = false; 2614 else 2615 use_frags = true; 2616 2617 if (use_frags) { 2618 /* If the budget is exhausted, the packet 2619 * would be queued in the driver. That is, 2620 * napi_gro_frags() wouldn't be called, so 2621 * we couldn't use napi_get_frags(). 2622 */ 2623 if (work_done >= budget) { 2624 rx_frag_head_sz = tp->rx_copybreak; 2625 skb = napi_alloc_skb(napi, 2626 rx_frag_head_sz); 2627 } else { 2628 rx_frag_head_sz = 0; 2629 skb = napi_get_frags(napi); 2630 } 2631 } else { 2632 rx_frag_head_sz = 0; 2633 skb = napi_alloc_skb(napi, len); 2634 } 2635 2636 if (!skb) { 2637 stats->rx_dropped++; 2638 goto find_next_rx; 2639 } 2640 2641 skb->ip_summed = r8152_rx_csum(tp, rx_desc); 2642 rtl_rx_vlan_tag(rx_desc, skb); 2643 2644 if (use_frags) { 2645 if (rx_frag_head_sz) { 2646 memcpy(skb->data, rx_data, 2647 rx_frag_head_sz); 2648 skb_put(skb, rx_frag_head_sz); 2649 len -= rx_frag_head_sz; 2650 rx_data += rx_frag_head_sz; 2651 skb->protocol = eth_type_trans(skb, 2652 netdev); 2653 } 2654 2655 skb_add_rx_frag(skb, 0, agg->page, 2656 agg_offset(agg, rx_data), 2657 len, SKB_DATA_ALIGN(len)); 2658 get_page(agg->page); 2659 } else { 2660 memcpy(skb->data, rx_data, len); 2661 skb_put(skb, len); 2662 skb->protocol = eth_type_trans(skb, netdev); 2663 } 2664 2665 if (work_done < budget) { 2666 if (use_frags) 2667 napi_gro_frags(napi); 2668 else 2669 napi_gro_receive(napi, skb); 2670 2671 work_done++; 2672 stats->rx_packets++; 2673 stats->rx_bytes += pkt_len; 2674 } else { 2675 __skb_queue_tail(&tp->rx_queue, skb); 2676 } 2677 2678find_next_rx: 2679 rx_data = rx_agg_align(rx_data + len + ETH_FCS_LEN); 2680 rx_desc = (struct rx_desc *)rx_data; 2681 len_used = agg_offset(agg, rx_data); 2682 len_used += sizeof(struct rx_desc); 2683 } 2684 2685 WARN_ON(!agg_free && page_count(agg->page) > 1); 2686 2687 if (agg_free) { 2688 spin_lock_irqsave(&tp->rx_lock, flags); 2689 if (page_count(agg->page) == 1) { 2690 list_add(&agg_free->list, &tp->rx_used); 2691 } else { 2692 list_add_tail(&agg->list, &tp->rx_used); 2693 agg = agg_free; 2694 urb = agg->urb; 2695 } 2696 spin_unlock_irqrestore(&tp->rx_lock, flags); 2697 } 2698 2699submit: 2700 if (!ret) { 2701 ret = r8152_submit_rx(tp, agg, GFP_ATOMIC); 2702 } else { 2703 urb->actual_length = 0; 2704 list_add_tail(&agg->list, next); 2705 } 2706 } 2707 2708 /* Splice the remained list back to rx_done for next schedule */ 2709 if (!list_empty(&rx_queue)) { 2710 spin_lock_irqsave(&tp->rx_lock, flags); 2711 list_splice(&rx_queue, &tp->rx_done); 2712 spin_unlock_irqrestore(&tp->rx_lock, flags); 2713 } 2714 2715out1: 2716 return work_done; 2717} 2718 2719static void tx_bottom(struct r8152 *tp) 2720{ 2721 int res; 2722 2723 do { 2724 struct net_device *netdev = tp->netdev; 2725 struct tx_agg *agg; 2726 2727 if (skb_queue_empty(&tp->tx_queue)) 2728 break; 2729 2730 agg = r8152_get_tx_agg(tp); 2731 if (!agg) 2732 break; 2733 2734 res = r8152_tx_agg_fill(tp, agg); 2735 if (!res) 2736 continue; 2737 2738 if (res == -ENODEV) { 2739 rtl_set_unplug(tp); 2740 netif_device_detach(netdev); 2741 } else { 2742 struct net_device_stats *stats = &netdev->stats; 2743 unsigned long flags; 2744 2745 netif_warn(tp, tx_err, netdev, 2746 "failed tx_urb %d\n", res); 2747 stats->tx_dropped += agg->skb_num; 2748 2749 spin_lock_irqsave(&tp->tx_lock, flags); 2750 list_add_tail(&agg->list, &tp->tx_free); 2751 spin_unlock_irqrestore(&tp->tx_lock, flags); 2752 } 2753 } while (res == 0); 2754} 2755 2756static void bottom_half(struct tasklet_struct *t) 2757{ 2758 struct r8152 *tp = from_tasklet(tp, t, tx_tl); 2759 2760 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 2761 return; 2762 2763 if (!test_bit(WORK_ENABLE, &tp->flags)) 2764 return; 2765 2766 /* When link down, the driver would cancel all bulks. */ 2767 /* This avoid the re-submitting bulk */ 2768 if (!netif_carrier_ok(tp->netdev)) 2769 return; 2770 2771 clear_bit(SCHEDULE_TASKLET, &tp->flags); 2772 2773 tx_bottom(tp); 2774} 2775 2776static int r8152_poll(struct napi_struct *napi, int budget) 2777{ 2778 struct r8152 *tp = container_of(napi, struct r8152, napi); 2779 int work_done; 2780 2781 if (!budget) 2782 return 0; 2783 2784 work_done = rx_bottom(tp, budget); 2785 2786 if (work_done < budget) { 2787 if (!napi_complete_done(napi, work_done)) 2788 goto out; 2789 if (!list_empty(&tp->rx_done)) 2790 napi_schedule(napi); 2791 } 2792 2793out: 2794 return work_done; 2795} 2796 2797static 2798int r8152_submit_rx(struct r8152 *tp, struct rx_agg *agg, gfp_t mem_flags) 2799{ 2800 int ret; 2801 2802 /* The rx would be stopped, so skip submitting */ 2803 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) || 2804 !test_bit(WORK_ENABLE, &tp->flags) || !netif_carrier_ok(tp->netdev)) 2805 return 0; 2806 2807 usb_fill_bulk_urb(agg->urb, tp->udev, tp->pipe_in, 2808 agg->buffer, tp->rx_buf_sz, 2809 (usb_complete_t)read_bulk_callback, agg); 2810 2811 ret = usb_submit_urb(agg->urb, mem_flags); 2812 if (ret == -ENODEV) { 2813 rtl_set_unplug(tp); 2814 netif_device_detach(tp->netdev); 2815 } else if (ret) { 2816 struct urb *urb = agg->urb; 2817 unsigned long flags; 2818 2819 urb->actual_length = 0; 2820 spin_lock_irqsave(&tp->rx_lock, flags); 2821 list_add_tail(&agg->list, &tp->rx_done); 2822 spin_unlock_irqrestore(&tp->rx_lock, flags); 2823 2824 netif_err(tp, rx_err, tp->netdev, 2825 "Couldn't submit rx[%p], ret = %d\n", agg, ret); 2826 2827 napi_schedule(&tp->napi); 2828 } 2829 2830 return ret; 2831} 2832 2833static void rtl_drop_queued_tx(struct r8152 *tp) 2834{ 2835 struct net_device_stats *stats = &tp->netdev->stats; 2836 struct sk_buff_head skb_head, *tx_queue = &tp->tx_queue; 2837 struct sk_buff *skb; 2838 2839 if (skb_queue_empty(tx_queue)) 2840 return; 2841 2842 __skb_queue_head_init(&skb_head); 2843 spin_lock_bh(&tx_queue->lock); 2844 skb_queue_splice_init(tx_queue, &skb_head); 2845 spin_unlock_bh(&tx_queue->lock); 2846 2847 while ((skb = __skb_dequeue(&skb_head))) { 2848 dev_kfree_skb(skb); 2849 stats->tx_dropped++; 2850 } 2851} 2852 2853static void rtl8152_tx_timeout(struct net_device *netdev, unsigned int txqueue) 2854{ 2855 struct r8152 *tp = netdev_priv(netdev); 2856 2857 netif_warn(tp, tx_err, netdev, "Tx timeout\n"); 2858 2859 usb_queue_reset_device(tp->intf); 2860} 2861 2862static void rtl8152_set_rx_mode(struct net_device *netdev) 2863{ 2864 struct r8152 *tp = netdev_priv(netdev); 2865 2866 if (netif_carrier_ok(netdev)) { 2867 set_bit(RTL8152_SET_RX_MODE, &tp->flags); 2868 schedule_delayed_work(&tp->schedule, 0); 2869 } 2870} 2871 2872static void _rtl8152_set_rx_mode(struct net_device *netdev) 2873{ 2874 struct r8152 *tp = netdev_priv(netdev); 2875 u32 mc_filter[2]; /* Multicast hash filter */ 2876 __le32 tmp[2]; 2877 u32 ocp_data; 2878 2879 netif_stop_queue(netdev); 2880 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 2881 ocp_data &= ~RCR_ACPT_ALL; 2882 ocp_data |= RCR_AB | RCR_APM; 2883 2884 if (netdev->flags & IFF_PROMISC) { 2885 /* Unconditionally log net taps. */ 2886 netif_notice(tp, link, netdev, "Promiscuous mode enabled\n"); 2887 ocp_data |= RCR_AM | RCR_AAP; 2888 mc_filter[1] = 0xffffffff; 2889 mc_filter[0] = 0xffffffff; 2890 } else if ((netdev->flags & IFF_MULTICAST && 2891 netdev_mc_count(netdev) > multicast_filter_limit) || 2892 (netdev->flags & IFF_ALLMULTI)) { 2893 /* Too many to filter perfectly -- accept all multicasts. */ 2894 ocp_data |= RCR_AM; 2895 mc_filter[1] = 0xffffffff; 2896 mc_filter[0] = 0xffffffff; 2897 } else { 2898 mc_filter[1] = 0; 2899 mc_filter[0] = 0; 2900 2901 if (netdev->flags & IFF_MULTICAST) { 2902 struct netdev_hw_addr *ha; 2903 2904 netdev_for_each_mc_addr(ha, netdev) { 2905 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 2906 2907 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 2908 ocp_data |= RCR_AM; 2909 } 2910 } 2911 } 2912 2913 tmp[0] = __cpu_to_le32(swab32(mc_filter[1])); 2914 tmp[1] = __cpu_to_le32(swab32(mc_filter[0])); 2915 2916 pla_ocp_write(tp, PLA_MAR, BYTE_EN_DWORD, sizeof(tmp), tmp); 2917 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 2918 netif_wake_queue(netdev); 2919} 2920 2921static netdev_features_t 2922rtl8152_features_check(struct sk_buff *skb, struct net_device *dev, 2923 netdev_features_t features) 2924{ 2925 u32 mss = skb_shinfo(skb)->gso_size; 2926 int max_offset = mss ? GTTCPHO_MAX : TCPHO_MAX; 2927 2928 if ((mss || skb->ip_summed == CHECKSUM_PARTIAL) && 2929 skb_transport_offset(skb) > max_offset) 2930 features &= ~(NETIF_F_CSUM_MASK | NETIF_F_GSO_MASK); 2931 else if ((skb->len + sizeof(struct tx_desc)) > agg_buf_sz) 2932 features &= ~NETIF_F_GSO_MASK; 2933 2934 return features; 2935} 2936 2937static netdev_tx_t rtl8152_start_xmit(struct sk_buff *skb, 2938 struct net_device *netdev) 2939{ 2940 struct r8152 *tp = netdev_priv(netdev); 2941 2942 skb_tx_timestamp(skb); 2943 2944 skb_queue_tail(&tp->tx_queue, skb); 2945 2946 if (!list_empty(&tp->tx_free)) { 2947 if (test_bit(SELECTIVE_SUSPEND, &tp->flags)) { 2948 set_bit(SCHEDULE_TASKLET, &tp->flags); 2949 schedule_delayed_work(&tp->schedule, 0); 2950 } else { 2951 usb_mark_last_busy(tp->udev); 2952 tasklet_schedule(&tp->tx_tl); 2953 } 2954 } else if (skb_queue_len(&tp->tx_queue) > tp->tx_qlen) { 2955 netif_stop_queue(netdev); 2956 } 2957 2958 return NETDEV_TX_OK; 2959} 2960 2961static void r8152b_reset_packet_filter(struct r8152 *tp) 2962{ 2963 u32 ocp_data; 2964 2965 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_FMC); 2966 ocp_data &= ~FMC_FCR_MCU_EN; 2967 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2968 ocp_data |= FMC_FCR_MCU_EN; 2969 ocp_write_word(tp, MCU_TYPE_PLA, PLA_FMC, ocp_data); 2970} 2971 2972static void rtl8152_nic_reset(struct r8152 *tp) 2973{ 2974 u32 ocp_data; 2975 int i; 2976 2977 switch (tp->version) { 2978 case RTL_TEST_01: 2979 case RTL_VER_10: 2980 case RTL_VER_11: 2981 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 2982 ocp_data &= ~CR_TE; 2983 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 2984 2985 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET); 2986 ocp_data &= ~BMU_RESET_EP_IN; 2987 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 2988 2989 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 2990 ocp_data |= CDC_ECM_EN; 2991 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 2992 2993 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 2994 ocp_data &= ~CR_RE; 2995 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 2996 2997 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_RESET); 2998 ocp_data |= BMU_RESET_EP_IN; 2999 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 3000 3001 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 3002 ocp_data &= ~CDC_ECM_EN; 3003 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 3004 break; 3005 3006 default: 3007 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, CR_RST); 3008 3009 for (i = 0; i < 1000; i++) { 3010 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 3011 break; 3012 if (!(ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR) & CR_RST)) 3013 break; 3014 usleep_range(100, 400); 3015 } 3016 break; 3017 } 3018} 3019 3020static void set_tx_qlen(struct r8152 *tp) 3021{ 3022 tp->tx_qlen = agg_buf_sz / (mtu_to_size(tp->netdev->mtu) + sizeof(struct tx_desc)); 3023} 3024 3025static inline u16 rtl8152_get_speed(struct r8152 *tp) 3026{ 3027 return ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHYSTATUS); 3028} 3029 3030static void rtl_eee_plus_en(struct r8152 *tp, bool enable) 3031{ 3032 u32 ocp_data; 3033 3034 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR); 3035 if (enable) 3036 ocp_data |= EEEP_CR_EEEP_TX; 3037 else 3038 ocp_data &= ~EEEP_CR_EEEP_TX; 3039 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEEP_CR, ocp_data); 3040} 3041 3042static void rtl_set_eee_plus(struct r8152 *tp) 3043{ 3044 if (rtl8152_get_speed(tp) & _10bps) 3045 rtl_eee_plus_en(tp, true); 3046 else 3047 rtl_eee_plus_en(tp, false); 3048} 3049 3050static void rxdy_gated_en(struct r8152 *tp, bool enable) 3051{ 3052 u32 ocp_data; 3053 3054 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MISC_1); 3055 if (enable) 3056 ocp_data |= RXDY_GATED_EN; 3057 else 3058 ocp_data &= ~RXDY_GATED_EN; 3059 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MISC_1, ocp_data); 3060} 3061 3062static int rtl_start_rx(struct r8152 *tp) 3063{ 3064 struct rx_agg *agg, *agg_next; 3065 struct list_head tmp_list; 3066 unsigned long flags; 3067 int ret = 0, i = 0; 3068 3069 INIT_LIST_HEAD(&tmp_list); 3070 3071 spin_lock_irqsave(&tp->rx_lock, flags); 3072 3073 INIT_LIST_HEAD(&tp->rx_done); 3074 INIT_LIST_HEAD(&tp->rx_used); 3075 3076 list_splice_init(&tp->rx_info, &tmp_list); 3077 3078 spin_unlock_irqrestore(&tp->rx_lock, flags); 3079 3080 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) { 3081 INIT_LIST_HEAD(&agg->list); 3082 3083 /* Only RTL8152_MAX_RX rx_agg need to be submitted. */ 3084 if (++i > RTL8152_MAX_RX) { 3085 spin_lock_irqsave(&tp->rx_lock, flags); 3086 list_add_tail(&agg->list, &tp->rx_used); 3087 spin_unlock_irqrestore(&tp->rx_lock, flags); 3088 } else if (unlikely(ret < 0)) { 3089 spin_lock_irqsave(&tp->rx_lock, flags); 3090 list_add_tail(&agg->list, &tp->rx_done); 3091 spin_unlock_irqrestore(&tp->rx_lock, flags); 3092 } else { 3093 ret = r8152_submit_rx(tp, agg, GFP_KERNEL); 3094 } 3095 } 3096 3097 spin_lock_irqsave(&tp->rx_lock, flags); 3098 WARN_ON(!list_empty(&tp->rx_info)); 3099 list_splice(&tmp_list, &tp->rx_info); 3100 spin_unlock_irqrestore(&tp->rx_lock, flags); 3101 3102 return ret; 3103} 3104 3105static int rtl_stop_rx(struct r8152 *tp) 3106{ 3107 struct rx_agg *agg, *agg_next; 3108 struct list_head tmp_list; 3109 unsigned long flags; 3110 3111 INIT_LIST_HEAD(&tmp_list); 3112 3113 /* The usb_kill_urb() couldn't be used in atomic. 3114 * Therefore, move the list of rx_info to a tmp one. 3115 * Then, list_for_each_entry_safe could be used without 3116 * spin lock. 3117 */ 3118 3119 spin_lock_irqsave(&tp->rx_lock, flags); 3120 list_splice_init(&tp->rx_info, &tmp_list); 3121 spin_unlock_irqrestore(&tp->rx_lock, flags); 3122 3123 list_for_each_entry_safe(agg, agg_next, &tmp_list, info_list) { 3124 /* At least RTL8152_MAX_RX rx_agg have the page_count being 3125 * equal to 1, so the other ones could be freed safely. 3126 */ 3127 if (page_count(agg->page) > 1) 3128 free_rx_agg(tp, agg); 3129 else 3130 usb_kill_urb(agg->urb); 3131 } 3132 3133 /* Move back the list of temp to the rx_info */ 3134 spin_lock_irqsave(&tp->rx_lock, flags); 3135 WARN_ON(!list_empty(&tp->rx_info)); 3136 list_splice(&tmp_list, &tp->rx_info); 3137 spin_unlock_irqrestore(&tp->rx_lock, flags); 3138 3139 while (!skb_queue_empty(&tp->rx_queue)) 3140 dev_kfree_skb(__skb_dequeue(&tp->rx_queue)); 3141 3142 return 0; 3143} 3144 3145static void rtl_set_ifg(struct r8152 *tp, u16 speed) 3146{ 3147 u32 ocp_data; 3148 3149 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR1); 3150 ocp_data &= ~IFG_MASK; 3151 if ((speed & (_10bps | _100bps)) && !(speed & FULL_DUP)) { 3152 ocp_data |= IFG_144NS; 3153 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data); 3154 3155 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); 3156 ocp_data &= ~TX10MIDLE_EN; 3157 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); 3158 } else { 3159 ocp_data |= IFG_96NS; 3160 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR1, ocp_data); 3161 3162 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); 3163 ocp_data |= TX10MIDLE_EN; 3164 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); 3165 } 3166} 3167 3168static inline void r8153b_rx_agg_chg_indicate(struct r8152 *tp) 3169{ 3170 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPT_RXDMA_OWN, 3171 OWN_UPDATE | OWN_CLEAR); 3172} 3173 3174static int rtl_enable(struct r8152 *tp) 3175{ 3176 u32 ocp_data; 3177 3178 r8152b_reset_packet_filter(tp); 3179 3180 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CR); 3181 ocp_data |= CR_RE | CR_TE; 3182 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, ocp_data); 3183 3184 switch (tp->version) { 3185 case RTL_VER_01: 3186 case RTL_VER_02: 3187 case RTL_VER_03: 3188 case RTL_VER_04: 3189 case RTL_VER_05: 3190 case RTL_VER_06: 3191 case RTL_VER_07: 3192 break; 3193 default: 3194 r8153b_rx_agg_chg_indicate(tp); 3195 break; 3196 } 3197 3198 rxdy_gated_en(tp, false); 3199 3200 return 0; 3201} 3202 3203static int rtl8152_enable(struct r8152 *tp) 3204{ 3205 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 3206 return -ENODEV; 3207 3208 set_tx_qlen(tp); 3209 rtl_set_eee_plus(tp); 3210 3211 return rtl_enable(tp); 3212} 3213 3214static void r8153_set_rx_early_timeout(struct r8152 *tp) 3215{ 3216 u32 ocp_data = tp->coalesce / 8; 3217 3218 switch (tp->version) { 3219 case RTL_VER_03: 3220 case RTL_VER_04: 3221 case RTL_VER_05: 3222 case RTL_VER_06: 3223 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 3224 ocp_data); 3225 break; 3226 3227 case RTL_VER_08: 3228 case RTL_VER_09: 3229 case RTL_VER_14: 3230 /* The RTL8153B uses USB_RX_EXTRA_AGGR_TMR for rx timeout 3231 * primarily. For USB_RX_EARLY_TIMEOUT, we fix it to 128ns. 3232 */ 3233 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 3234 128 / 8); 3235 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR, 3236 ocp_data); 3237 break; 3238 3239 case RTL_VER_10: 3240 case RTL_VER_11: 3241 case RTL_VER_12: 3242 case RTL_VER_13: 3243 case RTL_VER_15: 3244 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_TIMEOUT, 3245 640 / 8); 3246 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EXTRA_AGGR_TMR, 3247 ocp_data); 3248 break; 3249 3250 default: 3251 break; 3252 } 3253} 3254 3255static void r8153_set_rx_early_size(struct r8152 *tp) 3256{ 3257 u32 ocp_data = tp->rx_buf_sz - rx_reserved_size(tp->netdev->mtu); 3258 3259 switch (tp->version) { 3260 case RTL_VER_03: 3261 case RTL_VER_04: 3262 case RTL_VER_05: 3263 case RTL_VER_06: 3264 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 3265 ocp_data / 4); 3266 break; 3267 case RTL_VER_08: 3268 case RTL_VER_09: 3269 case RTL_VER_14: 3270 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 3271 ocp_data / 8); 3272 break; 3273 case RTL_TEST_01: 3274 case RTL_VER_10: 3275 case RTL_VER_11: 3276 case RTL_VER_12: 3277 case RTL_VER_13: 3278 case RTL_VER_15: 3279 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_EARLY_SIZE, 3280 ocp_data / 8); 3281 break; 3282 default: 3283 WARN_ON_ONCE(1); 3284 break; 3285 } 3286} 3287 3288static int rtl8153_enable(struct r8152 *tp) 3289{ 3290 u32 ocp_data; 3291 3292 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 3293 return -ENODEV; 3294 3295 set_tx_qlen(tp); 3296 rtl_set_eee_plus(tp); 3297 r8153_set_rx_early_timeout(tp); 3298 r8153_set_rx_early_size(tp); 3299 3300 rtl_set_ifg(tp, rtl8152_get_speed(tp)); 3301 3302 switch (tp->version) { 3303 case RTL_VER_09: 3304 case RTL_VER_14: 3305 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); 3306 ocp_data &= ~FC_PATCH_TASK; 3307 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); 3308 usleep_range(1000, 2000); 3309 ocp_data |= FC_PATCH_TASK; 3310 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); 3311 break; 3312 default: 3313 break; 3314 } 3315 3316 return rtl_enable(tp); 3317} 3318 3319static void rtl_disable(struct r8152 *tp) 3320{ 3321 u32 ocp_data; 3322 int i; 3323 3324 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { 3325 rtl_drop_queued_tx(tp); 3326 return; 3327 } 3328 3329 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 3330 ocp_data &= ~RCR_ACPT_ALL; 3331 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 3332 3333 rtl_drop_queued_tx(tp); 3334 3335 for (i = 0; i < RTL8152_MAX_TX; i++) 3336 usb_kill_urb(tp->tx_info[i].urb); 3337 3338 rxdy_gated_en(tp, true); 3339 3340 for (i = 0; i < 1000; i++) { 3341 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 3342 break; 3343 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 3344 if ((ocp_data & FIFO_EMPTY) == FIFO_EMPTY) 3345 break; 3346 usleep_range(1000, 2000); 3347 } 3348 3349 for (i = 0; i < 1000; i++) { 3350 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 3351 break; 3352 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0) & TCR0_TX_EMPTY) 3353 break; 3354 usleep_range(1000, 2000); 3355 } 3356 3357 rtl_stop_rx(tp); 3358 3359 rtl8152_nic_reset(tp); 3360} 3361 3362static void r8152_power_cut_en(struct r8152 *tp, bool enable) 3363{ 3364 u32 ocp_data; 3365 3366 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CTRL); 3367 if (enable) 3368 ocp_data |= POWER_CUT; 3369 else 3370 ocp_data &= ~POWER_CUT; 3371 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CTRL, ocp_data); 3372 3373 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS); 3374 ocp_data &= ~RESUME_INDICATE; 3375 ocp_write_word(tp, MCU_TYPE_USB, USB_PM_CTRL_STATUS, ocp_data); 3376} 3377 3378static void rtl_rx_vlan_en(struct r8152 *tp, bool enable) 3379{ 3380 u32 ocp_data; 3381 3382 switch (tp->version) { 3383 case RTL_VER_01: 3384 case RTL_VER_02: 3385 case RTL_VER_03: 3386 case RTL_VER_04: 3387 case RTL_VER_05: 3388 case RTL_VER_06: 3389 case RTL_VER_07: 3390 case RTL_VER_08: 3391 case RTL_VER_09: 3392 case RTL_VER_14: 3393 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 3394 if (enable) 3395 ocp_data |= CPCR_RX_VLAN; 3396 else 3397 ocp_data &= ~CPCR_RX_VLAN; 3398 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 3399 break; 3400 3401 case RTL_TEST_01: 3402 case RTL_VER_10: 3403 case RTL_VER_11: 3404 case RTL_VER_12: 3405 case RTL_VER_13: 3406 case RTL_VER_15: 3407 default: 3408 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR1); 3409 if (enable) 3410 ocp_data |= OUTER_VLAN | INNER_VLAN; 3411 else 3412 ocp_data &= ~(OUTER_VLAN | INNER_VLAN); 3413 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR1, ocp_data); 3414 break; 3415 } 3416} 3417 3418static int rtl8152_set_features(struct net_device *dev, 3419 netdev_features_t features) 3420{ 3421 netdev_features_t changed = features ^ dev->features; 3422 struct r8152 *tp = netdev_priv(dev); 3423 int ret; 3424 3425 ret = usb_autopm_get_interface(tp->intf); 3426 if (ret < 0) 3427 goto out; 3428 3429 mutex_lock(&tp->control); 3430 3431 if (changed & NETIF_F_HW_VLAN_CTAG_RX) { 3432 if (features & NETIF_F_HW_VLAN_CTAG_RX) 3433 rtl_rx_vlan_en(tp, true); 3434 else 3435 rtl_rx_vlan_en(tp, false); 3436 } 3437 3438 mutex_unlock(&tp->control); 3439 3440 usb_autopm_put_interface(tp->intf); 3441 3442out: 3443 return ret; 3444} 3445 3446#define WAKE_ANY (WAKE_PHY | WAKE_MAGIC | WAKE_UCAST | WAKE_BCAST | WAKE_MCAST) 3447 3448static u32 __rtl_get_wol(struct r8152 *tp) 3449{ 3450 u32 ocp_data; 3451 u32 wolopts = 0; 3452 3453 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 3454 if (ocp_data & LINK_ON_WAKE_EN) 3455 wolopts |= WAKE_PHY; 3456 3457 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 3458 if (ocp_data & UWF_EN) 3459 wolopts |= WAKE_UCAST; 3460 if (ocp_data & BWF_EN) 3461 wolopts |= WAKE_BCAST; 3462 if (ocp_data & MWF_EN) 3463 wolopts |= WAKE_MCAST; 3464 3465 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 3466 if (ocp_data & MAGIC_EN) 3467 wolopts |= WAKE_MAGIC; 3468 3469 return wolopts; 3470} 3471 3472static void __rtl_set_wol(struct r8152 *tp, u32 wolopts) 3473{ 3474 u32 ocp_data; 3475 3476 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 3477 3478 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 3479 ocp_data &= ~LINK_ON_WAKE_EN; 3480 if (wolopts & WAKE_PHY) 3481 ocp_data |= LINK_ON_WAKE_EN; 3482 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 3483 3484 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 3485 ocp_data &= ~(UWF_EN | BWF_EN | MWF_EN); 3486 if (wolopts & WAKE_UCAST) 3487 ocp_data |= UWF_EN; 3488 if (wolopts & WAKE_BCAST) 3489 ocp_data |= BWF_EN; 3490 if (wolopts & WAKE_MCAST) 3491 ocp_data |= MWF_EN; 3492 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); 3493 3494 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 3495 3496 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL); 3497 ocp_data &= ~MAGIC_EN; 3498 if (wolopts & WAKE_MAGIC) 3499 ocp_data |= MAGIC_EN; 3500 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CFG_WOL, ocp_data); 3501 3502 if (wolopts & WAKE_ANY) 3503 device_set_wakeup_enable(&tp->udev->dev, true); 3504 else 3505 device_set_wakeup_enable(&tp->udev->dev, false); 3506} 3507 3508static void r8153_mac_clk_speed_down(struct r8152 *tp, bool enable) 3509{ 3510 u32 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); 3511 3512 /* MAC clock speed down */ 3513 if (enable) 3514 ocp_data |= MAC_CLK_SPDWN_EN; 3515 else 3516 ocp_data &= ~MAC_CLK_SPDWN_EN; 3517 3518 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); 3519} 3520 3521static void r8156_mac_clk_spd(struct r8152 *tp, bool enable) 3522{ 3523 u32 ocp_data; 3524 3525 /* MAC clock speed down */ 3526 if (enable) { 3527 /* aldps_spdwn_ratio, tp10_spdwn_ratio */ 3528 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, 3529 0x0403); 3530 3531 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); 3532 ocp_data &= ~EEE_SPDWN_RATIO_MASK; 3533 ocp_data |= MAC_CLK_SPDWN_EN | 0x03; /* eee_spdwn_ratio */ 3534 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); 3535 } else { 3536 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2); 3537 ocp_data &= ~MAC_CLK_SPDWN_EN; 3538 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL2, ocp_data); 3539 } 3540} 3541 3542static void r8153_u1u2en(struct r8152 *tp, bool enable) 3543{ 3544 u8 u1u2[8]; 3545 3546 if (enable) 3547 memset(u1u2, 0xff, sizeof(u1u2)); 3548 else 3549 memset(u1u2, 0x00, sizeof(u1u2)); 3550 3551 usb_ocp_write(tp, USB_TOLERANCE, BYTE_EN_SIX_BYTES, sizeof(u1u2), u1u2); 3552} 3553 3554static void r8153b_u1u2en(struct r8152 *tp, bool enable) 3555{ 3556 u32 ocp_data; 3557 3558 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG); 3559 if (enable) 3560 ocp_data |= LPM_U1U2_EN; 3561 else 3562 ocp_data &= ~LPM_U1U2_EN; 3563 3564 ocp_write_word(tp, MCU_TYPE_USB, USB_LPM_CONFIG, ocp_data); 3565} 3566 3567static void r8153_u2p3en(struct r8152 *tp, bool enable) 3568{ 3569 u32 ocp_data; 3570 3571 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); 3572 if (enable) 3573 ocp_data |= U2P3_ENABLE; 3574 else 3575 ocp_data &= ~U2P3_ENABLE; 3576 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); 3577} 3578 3579static void r8153b_ups_flags(struct r8152 *tp) 3580{ 3581 u32 ups_flags = 0; 3582 3583 if (tp->ups_info.green) 3584 ups_flags |= UPS_FLAGS_EN_GREEN; 3585 3586 if (tp->ups_info.aldps) 3587 ups_flags |= UPS_FLAGS_EN_ALDPS; 3588 3589 if (tp->ups_info.eee) 3590 ups_flags |= UPS_FLAGS_EN_EEE; 3591 3592 if (tp->ups_info.flow_control) 3593 ups_flags |= UPS_FLAGS_EN_FLOW_CTR; 3594 3595 if (tp->ups_info.eee_ckdiv) 3596 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV; 3597 3598 if (tp->ups_info.eee_cmod_lv) 3599 ups_flags |= UPS_FLAGS_EEE_CMOD_LV_EN; 3600 3601 if (tp->ups_info.r_tune) 3602 ups_flags |= UPS_FLAGS_R_TUNE; 3603 3604 if (tp->ups_info._10m_ckdiv) 3605 ups_flags |= UPS_FLAGS_EN_10M_CKDIV; 3606 3607 if (tp->ups_info.eee_plloff_100) 3608 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100; 3609 3610 if (tp->ups_info.eee_plloff_giga) 3611 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA; 3612 3613 if (tp->ups_info._250m_ckdiv) 3614 ups_flags |= UPS_FLAGS_250M_CKDIV; 3615 3616 if (tp->ups_info.ctap_short_off) 3617 ups_flags |= UPS_FLAGS_CTAP_SHORT_DIS; 3618 3619 switch (tp->ups_info.speed_duplex) { 3620 case NWAY_10M_HALF: 3621 ups_flags |= ups_flags_speed(1); 3622 break; 3623 case NWAY_10M_FULL: 3624 ups_flags |= ups_flags_speed(2); 3625 break; 3626 case NWAY_100M_HALF: 3627 ups_flags |= ups_flags_speed(3); 3628 break; 3629 case NWAY_100M_FULL: 3630 ups_flags |= ups_flags_speed(4); 3631 break; 3632 case NWAY_1000M_FULL: 3633 ups_flags |= ups_flags_speed(5); 3634 break; 3635 case FORCE_10M_HALF: 3636 ups_flags |= ups_flags_speed(6); 3637 break; 3638 case FORCE_10M_FULL: 3639 ups_flags |= ups_flags_speed(7); 3640 break; 3641 case FORCE_100M_HALF: 3642 ups_flags |= ups_flags_speed(8); 3643 break; 3644 case FORCE_100M_FULL: 3645 ups_flags |= ups_flags_speed(9); 3646 break; 3647 default: 3648 break; 3649 } 3650 3651 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags); 3652} 3653 3654static void r8156_ups_flags(struct r8152 *tp) 3655{ 3656 u32 ups_flags = 0; 3657 3658 if (tp->ups_info.green) 3659 ups_flags |= UPS_FLAGS_EN_GREEN; 3660 3661 if (tp->ups_info.aldps) 3662 ups_flags |= UPS_FLAGS_EN_ALDPS; 3663 3664 if (tp->ups_info.eee) 3665 ups_flags |= UPS_FLAGS_EN_EEE; 3666 3667 if (tp->ups_info.flow_control) 3668 ups_flags |= UPS_FLAGS_EN_FLOW_CTR; 3669 3670 if (tp->ups_info.eee_ckdiv) 3671 ups_flags |= UPS_FLAGS_EN_EEE_CKDIV; 3672 3673 if (tp->ups_info._10m_ckdiv) 3674 ups_flags |= UPS_FLAGS_EN_10M_CKDIV; 3675 3676 if (tp->ups_info.eee_plloff_100) 3677 ups_flags |= UPS_FLAGS_EEE_PLLOFF_100; 3678 3679 if (tp->ups_info.eee_plloff_giga) 3680 ups_flags |= UPS_FLAGS_EEE_PLLOFF_GIGA; 3681 3682 if (tp->ups_info._250m_ckdiv) 3683 ups_flags |= UPS_FLAGS_250M_CKDIV; 3684 3685 switch (tp->ups_info.speed_duplex) { 3686 case FORCE_10M_HALF: 3687 ups_flags |= ups_flags_speed(0); 3688 break; 3689 case FORCE_10M_FULL: 3690 ups_flags |= ups_flags_speed(1); 3691 break; 3692 case FORCE_100M_HALF: 3693 ups_flags |= ups_flags_speed(2); 3694 break; 3695 case FORCE_100M_FULL: 3696 ups_flags |= ups_flags_speed(3); 3697 break; 3698 case NWAY_10M_HALF: 3699 ups_flags |= ups_flags_speed(4); 3700 break; 3701 case NWAY_10M_FULL: 3702 ups_flags |= ups_flags_speed(5); 3703 break; 3704 case NWAY_100M_HALF: 3705 ups_flags |= ups_flags_speed(6); 3706 break; 3707 case NWAY_100M_FULL: 3708 ups_flags |= ups_flags_speed(7); 3709 break; 3710 case NWAY_1000M_FULL: 3711 ups_flags |= ups_flags_speed(8); 3712 break; 3713 case NWAY_2500M_FULL: 3714 ups_flags |= ups_flags_speed(9); 3715 break; 3716 default: 3717 break; 3718 } 3719 3720 switch (tp->ups_info.lite_mode) { 3721 case 1: 3722 ups_flags |= 0 << 5; 3723 break; 3724 case 2: 3725 ups_flags |= 2 << 5; 3726 break; 3727 case 0: 3728 default: 3729 ups_flags |= 1 << 5; 3730 break; 3731 } 3732 3733 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPS_FLAGS, ups_flags); 3734} 3735 3736static void rtl_green_en(struct r8152 *tp, bool enable) 3737{ 3738 u16 data; 3739 3740 data = sram_read(tp, SRAM_GREEN_CFG); 3741 if (enable) 3742 data |= GREEN_ETH_EN; 3743 else 3744 data &= ~GREEN_ETH_EN; 3745 sram_write(tp, SRAM_GREEN_CFG, data); 3746 3747 tp->ups_info.green = enable; 3748} 3749 3750static void r8153b_green_en(struct r8152 *tp, bool enable) 3751{ 3752 if (enable) { 3753 sram_write(tp, 0x8045, 0); /* 10M abiq&ldvbias */ 3754 sram_write(tp, 0x804d, 0x1222); /* 100M short abiq&ldvbias */ 3755 sram_write(tp, 0x805d, 0x0022); /* 1000M short abiq&ldvbias */ 3756 } else { 3757 sram_write(tp, 0x8045, 0x2444); /* 10M abiq&ldvbias */ 3758 sram_write(tp, 0x804d, 0x2444); /* 100M short abiq&ldvbias */ 3759 sram_write(tp, 0x805d, 0x2444); /* 1000M short abiq&ldvbias */ 3760 } 3761 3762 rtl_green_en(tp, true); 3763} 3764 3765static u16 r8153_phy_status(struct r8152 *tp, u16 desired) 3766{ 3767 u16 data; 3768 int i; 3769 3770 for (i = 0; i < 500; i++) { 3771 data = ocp_reg_read(tp, OCP_PHY_STATUS); 3772 data &= PHY_STAT_MASK; 3773 if (desired) { 3774 if (data == desired) 3775 break; 3776 } else if (data == PHY_STAT_LAN_ON || data == PHY_STAT_PWRDN || 3777 data == PHY_STAT_EXT_INIT) { 3778 break; 3779 } 3780 3781 msleep(20); 3782 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 3783 break; 3784 } 3785 3786 return data; 3787} 3788 3789static void r8153b_ups_en(struct r8152 *tp, bool enable) 3790{ 3791 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); 3792 3793 if (enable) { 3794 r8153b_ups_flags(tp); 3795 3796 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; 3797 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 3798 3799 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); 3800 ocp_data |= UPS_FORCE_PWR_DOWN; 3801 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); 3802 } else { 3803 ocp_data &= ~(UPS_EN | USP_PREWAKE); 3804 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 3805 3806 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); 3807 ocp_data &= ~UPS_FORCE_PWR_DOWN; 3808 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); 3809 3810 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) { 3811 int i; 3812 3813 for (i = 0; i < 500; i++) { 3814 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 3815 return; 3816 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 3817 AUTOLOAD_DONE) 3818 break; 3819 msleep(20); 3820 } 3821 3822 tp->rtl_ops.hw_phy_cfg(tp); 3823 3824 rtl8152_set_speed(tp, tp->autoneg, tp->speed, 3825 tp->duplex, tp->advertising); 3826 } 3827 } 3828} 3829 3830static void r8153c_ups_en(struct r8152 *tp, bool enable) 3831{ 3832 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); 3833 3834 if (enable) { 3835 r8153b_ups_flags(tp); 3836 3837 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; 3838 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 3839 3840 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); 3841 ocp_data |= UPS_FORCE_PWR_DOWN; 3842 ocp_data &= ~BIT(7); 3843 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); 3844 } else { 3845 ocp_data &= ~(UPS_EN | USP_PREWAKE); 3846 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 3847 3848 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); 3849 ocp_data &= ~UPS_FORCE_PWR_DOWN; 3850 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); 3851 3852 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) { 3853 int i; 3854 3855 for (i = 0; i < 500; i++) { 3856 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 3857 return; 3858 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 3859 AUTOLOAD_DONE) 3860 break; 3861 msleep(20); 3862 } 3863 3864 tp->rtl_ops.hw_phy_cfg(tp); 3865 3866 rtl8152_set_speed(tp, tp->autoneg, tp->speed, 3867 tp->duplex, tp->advertising); 3868 } 3869 3870 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 3871 3872 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 3873 ocp_data |= BIT(8); 3874 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 3875 3876 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 3877 } 3878} 3879 3880static void r8156_ups_en(struct r8152 *tp, bool enable) 3881{ 3882 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_POWER_CUT); 3883 3884 if (enable) { 3885 r8156_ups_flags(tp); 3886 3887 ocp_data |= UPS_EN | USP_PREWAKE | PHASE2_EN; 3888 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 3889 3890 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); 3891 ocp_data |= UPS_FORCE_PWR_DOWN; 3892 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); 3893 3894 switch (tp->version) { 3895 case RTL_VER_13: 3896 case RTL_VER_15: 3897 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPHY_XTAL); 3898 ocp_data &= ~OOBS_POLLING; 3899 ocp_write_byte(tp, MCU_TYPE_USB, USB_UPHY_XTAL, ocp_data); 3900 break; 3901 default: 3902 break; 3903 } 3904 } else { 3905 ocp_data &= ~(UPS_EN | USP_PREWAKE); 3906 ocp_write_byte(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 3907 3908 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); 3909 ocp_data &= ~UPS_FORCE_PWR_DOWN; 3910 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); 3911 3912 if (ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0) & PCUT_STATUS) { 3913 tp->rtl_ops.hw_phy_cfg(tp); 3914 3915 rtl8152_set_speed(tp, tp->autoneg, tp->speed, 3916 tp->duplex, tp->advertising); 3917 } 3918 } 3919} 3920 3921static void r8153_power_cut_en(struct r8152 *tp, bool enable) 3922{ 3923 u32 ocp_data; 3924 3925 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 3926 if (enable) 3927 ocp_data |= PWR_EN | PHASE2_EN; 3928 else 3929 ocp_data &= ~(PWR_EN | PHASE2_EN); 3930 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 3931 3932 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 3933 ocp_data &= ~PCUT_STATUS; 3934 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 3935} 3936 3937static void r8153b_power_cut_en(struct r8152 *tp, bool enable) 3938{ 3939 u32 ocp_data; 3940 3941 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_POWER_CUT); 3942 if (enable) 3943 ocp_data |= PWR_EN | PHASE2_EN; 3944 else 3945 ocp_data &= ~PWR_EN; 3946 ocp_write_word(tp, MCU_TYPE_USB, USB_POWER_CUT, ocp_data); 3947 3948 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 3949 ocp_data &= ~PCUT_STATUS; 3950 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 3951} 3952 3953static void r8153_queue_wake(struct r8152 *tp, bool enable) 3954{ 3955 u32 ocp_data; 3956 3957 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG); 3958 if (enable) 3959 ocp_data |= UPCOMING_RUNTIME_D3; 3960 else 3961 ocp_data &= ~UPCOMING_RUNTIME_D3; 3962 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_INDICATE_FALG, ocp_data); 3963 3964 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG); 3965 ocp_data &= ~LINK_CHG_EVENT; 3966 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_SUSPEND_FLAG, ocp_data); 3967 3968 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); 3969 ocp_data &= ~LINK_CHANGE_FLAG; 3970 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); 3971} 3972 3973static bool rtl_can_wakeup(struct r8152 *tp) 3974{ 3975 struct usb_device *udev = tp->udev; 3976 3977 return (udev->actconfig->desc.bmAttributes & USB_CONFIG_ATT_WAKEUP); 3978} 3979 3980static void rtl_runtime_suspend_enable(struct r8152 *tp, bool enable) 3981{ 3982 if (enable) { 3983 u32 ocp_data; 3984 3985 __rtl_set_wol(tp, WAKE_ANY); 3986 3987 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 3988 3989 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 3990 ocp_data |= LINK_OFF_WAKE_EN; 3991 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 3992 3993 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 3994 } else { 3995 u32 ocp_data; 3996 3997 __rtl_set_wol(tp, tp->saved_wolopts); 3998 3999 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 4000 4001 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 4002 ocp_data &= ~LINK_OFF_WAKE_EN; 4003 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 4004 4005 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 4006 } 4007} 4008 4009static void rtl8153_runtime_enable(struct r8152 *tp, bool enable) 4010{ 4011 if (enable) { 4012 r8153_u1u2en(tp, false); 4013 r8153_u2p3en(tp, false); 4014 rtl_runtime_suspend_enable(tp, true); 4015 } else { 4016 rtl_runtime_suspend_enable(tp, false); 4017 4018 switch (tp->version) { 4019 case RTL_VER_03: 4020 case RTL_VER_04: 4021 break; 4022 case RTL_VER_05: 4023 case RTL_VER_06: 4024 default: 4025 r8153_u2p3en(tp, true); 4026 break; 4027 } 4028 4029 r8153_u1u2en(tp, true); 4030 } 4031} 4032 4033static void rtl8153b_runtime_enable(struct r8152 *tp, bool enable) 4034{ 4035 if (enable) { 4036 r8153_queue_wake(tp, true); 4037 r8153b_u1u2en(tp, false); 4038 r8153_u2p3en(tp, false); 4039 rtl_runtime_suspend_enable(tp, true); 4040 r8153b_ups_en(tp, true); 4041 } else { 4042 r8153b_ups_en(tp, false); 4043 r8153_queue_wake(tp, false); 4044 rtl_runtime_suspend_enable(tp, false); 4045 if (tp->udev->speed >= USB_SPEED_SUPER) 4046 r8153b_u1u2en(tp, true); 4047 } 4048} 4049 4050static void rtl8153c_runtime_enable(struct r8152 *tp, bool enable) 4051{ 4052 if (enable) { 4053 r8153_queue_wake(tp, true); 4054 r8153b_u1u2en(tp, false); 4055 r8153_u2p3en(tp, false); 4056 rtl_runtime_suspend_enable(tp, true); 4057 r8153c_ups_en(tp, true); 4058 } else { 4059 r8153c_ups_en(tp, false); 4060 r8153_queue_wake(tp, false); 4061 rtl_runtime_suspend_enable(tp, false); 4062 r8153b_u1u2en(tp, true); 4063 } 4064} 4065 4066static void rtl8156_runtime_enable(struct r8152 *tp, bool enable) 4067{ 4068 if (enable) { 4069 r8153_queue_wake(tp, true); 4070 r8153b_u1u2en(tp, false); 4071 r8153_u2p3en(tp, false); 4072 rtl_runtime_suspend_enable(tp, true); 4073 } else { 4074 r8153_queue_wake(tp, false); 4075 rtl_runtime_suspend_enable(tp, false); 4076 r8153_u2p3en(tp, true); 4077 if (tp->udev->speed >= USB_SPEED_SUPER) 4078 r8153b_u1u2en(tp, true); 4079 } 4080} 4081 4082static void r8153_teredo_off(struct r8152 *tp) 4083{ 4084 u32 ocp_data; 4085 4086 switch (tp->version) { 4087 case RTL_VER_01: 4088 case RTL_VER_02: 4089 case RTL_VER_03: 4090 case RTL_VER_04: 4091 case RTL_VER_05: 4092 case RTL_VER_06: 4093 case RTL_VER_07: 4094 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 4095 ocp_data &= ~(TEREDO_SEL | TEREDO_RS_EVENT_MASK | 4096 OOB_TEREDO_EN); 4097 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 4098 break; 4099 4100 case RTL_VER_08: 4101 case RTL_VER_09: 4102 case RTL_TEST_01: 4103 case RTL_VER_10: 4104 case RTL_VER_11: 4105 case RTL_VER_12: 4106 case RTL_VER_13: 4107 case RTL_VER_14: 4108 case RTL_VER_15: 4109 default: 4110 /* The bit 0 ~ 7 are relative with teredo settings. They are 4111 * W1C (write 1 to clear), so set all 1 to disable it. 4112 */ 4113 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, 0xff); 4114 break; 4115 } 4116 4117 ocp_write_word(tp, MCU_TYPE_PLA, PLA_WDT6_CTRL, WDT6_SET_MODE); 4118 ocp_write_word(tp, MCU_TYPE_PLA, PLA_REALWOW_TIMER, 0); 4119 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TEREDO_TIMER, 0); 4120} 4121 4122static void rtl_reset_bmu(struct r8152 *tp) 4123{ 4124 u32 ocp_data; 4125 4126 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_RESET); 4127 ocp_data &= ~(BMU_RESET_EP_IN | BMU_RESET_EP_OUT); 4128 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 4129 ocp_data |= BMU_RESET_EP_IN | BMU_RESET_EP_OUT; 4130 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_RESET, ocp_data); 4131} 4132 4133/* Clear the bp to stop the firmware before loading a new one */ 4134static void rtl_clear_bp(struct r8152 *tp, u16 type) 4135{ 4136 u16 bp[16] = {0}; 4137 u16 bp_num; 4138 4139 switch (tp->version) { 4140 case RTL_VER_08: 4141 case RTL_VER_09: 4142 case RTL_VER_10: 4143 case RTL_VER_11: 4144 case RTL_VER_12: 4145 case RTL_VER_13: 4146 case RTL_VER_15: 4147 if (type == MCU_TYPE_USB) { 4148 ocp_write_word(tp, MCU_TYPE_USB, USB_BP2_EN, 0); 4149 bp_num = 16; 4150 break; 4151 } 4152 fallthrough; 4153 case RTL_VER_03: 4154 case RTL_VER_04: 4155 case RTL_VER_05: 4156 case RTL_VER_06: 4157 ocp_write_byte(tp, type, PLA_BP_EN, 0); 4158 fallthrough; 4159 case RTL_VER_01: 4160 case RTL_VER_02: 4161 case RTL_VER_07: 4162 bp_num = 8; 4163 break; 4164 case RTL_VER_14: 4165 default: 4166 ocp_write_word(tp, type, USB_BP2_EN, 0); 4167 bp_num = 16; 4168 break; 4169 } 4170 4171 generic_ocp_write(tp, PLA_BP_0, BYTE_EN_DWORD, bp_num << 1, bp, type); 4172 4173 /* wait 3 ms to make sure the firmware is stopped */ 4174 usleep_range(3000, 6000); 4175 ocp_write_word(tp, type, PLA_BP_BA, 0); 4176} 4177 4178static inline void rtl_reset_ocp_base(struct r8152 *tp) 4179{ 4180 tp->ocp_base = -1; 4181} 4182 4183static int rtl_phy_patch_request(struct r8152 *tp, bool request, bool wait) 4184{ 4185 u16 data, check; 4186 int i; 4187 4188 data = ocp_reg_read(tp, OCP_PHY_PATCH_CMD); 4189 if (request) { 4190 data |= PATCH_REQUEST; 4191 check = 0; 4192 } else { 4193 data &= ~PATCH_REQUEST; 4194 check = PATCH_READY; 4195 } 4196 ocp_reg_write(tp, OCP_PHY_PATCH_CMD, data); 4197 4198 for (i = 0; wait && i < 5000; i++) { 4199 u32 ocp_data; 4200 4201 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 4202 return -ENODEV; 4203 4204 usleep_range(1000, 2000); 4205 ocp_data = ocp_reg_read(tp, OCP_PHY_PATCH_STAT); 4206 if ((ocp_data & PATCH_READY) ^ check) 4207 break; 4208 } 4209 4210 if (request && wait && 4211 !(ocp_reg_read(tp, OCP_PHY_PATCH_STAT) & PATCH_READY)) { 4212 dev_err(&tp->intf->dev, "PHY patch request fail\n"); 4213 rtl_phy_patch_request(tp, false, false); 4214 return -ETIME; 4215 } else { 4216 return 0; 4217 } 4218} 4219 4220static void rtl_patch_key_set(struct r8152 *tp, u16 key_addr, u16 patch_key) 4221{ 4222 if (patch_key && key_addr) { 4223 sram_write(tp, key_addr, patch_key); 4224 sram_write(tp, SRAM_PHY_LOCK, PHY_PATCH_LOCK); 4225 } else if (key_addr) { 4226 u16 data; 4227 4228 sram_write(tp, 0x0000, 0x0000); 4229 4230 data = ocp_reg_read(tp, OCP_PHY_LOCK); 4231 data &= ~PATCH_LOCK; 4232 ocp_reg_write(tp, OCP_PHY_LOCK, data); 4233 4234 sram_write(tp, key_addr, 0x0000); 4235 } else { 4236 WARN_ON_ONCE(1); 4237 } 4238} 4239 4240static int 4241rtl_pre_ram_code(struct r8152 *tp, u16 key_addr, u16 patch_key, bool wait) 4242{ 4243 if (rtl_phy_patch_request(tp, true, wait)) 4244 return -ETIME; 4245 4246 rtl_patch_key_set(tp, key_addr, patch_key); 4247 4248 return 0; 4249} 4250 4251static int rtl_post_ram_code(struct r8152 *tp, u16 key_addr, bool wait) 4252{ 4253 rtl_patch_key_set(tp, key_addr, 0); 4254 4255 rtl_phy_patch_request(tp, false, wait); 4256 4257 return 0; 4258} 4259 4260static bool rtl8152_is_fw_phy_speed_up_ok(struct r8152 *tp, struct fw_phy_speed_up *phy) 4261{ 4262 u16 fw_offset; 4263 u32 length; 4264 bool rc = false; 4265 4266 switch (tp->version) { 4267 case RTL_VER_01: 4268 case RTL_VER_02: 4269 case RTL_VER_03: 4270 case RTL_VER_04: 4271 case RTL_VER_05: 4272 case RTL_VER_06: 4273 case RTL_VER_07: 4274 case RTL_VER_08: 4275 case RTL_VER_09: 4276 case RTL_VER_10: 4277 case RTL_VER_11: 4278 case RTL_VER_12: 4279 case RTL_VER_14: 4280 goto out; 4281 case RTL_VER_13: 4282 case RTL_VER_15: 4283 default: 4284 break; 4285 } 4286 4287 fw_offset = __le16_to_cpu(phy->fw_offset); 4288 length = __le32_to_cpu(phy->blk_hdr.length); 4289 if (fw_offset < sizeof(*phy) || length <= fw_offset) { 4290 dev_err(&tp->intf->dev, "invalid fw_offset\n"); 4291 goto out; 4292 } 4293 4294 length -= fw_offset; 4295 if (length & 3) { 4296 dev_err(&tp->intf->dev, "invalid block length\n"); 4297 goto out; 4298 } 4299 4300 if (__le16_to_cpu(phy->fw_reg) != 0x9A00) { 4301 dev_err(&tp->intf->dev, "invalid register to load firmware\n"); 4302 goto out; 4303 } 4304 4305 rc = true; 4306out: 4307 return rc; 4308} 4309 4310static bool rtl8152_is_fw_phy_ver_ok(struct r8152 *tp, struct fw_phy_ver *ver) 4311{ 4312 bool rc = false; 4313 4314 switch (tp->version) { 4315 case RTL_VER_10: 4316 case RTL_VER_11: 4317 case RTL_VER_12: 4318 case RTL_VER_13: 4319 case RTL_VER_15: 4320 break; 4321 default: 4322 goto out; 4323 } 4324 4325 if (__le32_to_cpu(ver->blk_hdr.length) != sizeof(*ver)) { 4326 dev_err(&tp->intf->dev, "invalid block length\n"); 4327 goto out; 4328 } 4329 4330 if (__le16_to_cpu(ver->ver.addr) != SRAM_GPHY_FW_VER) { 4331 dev_err(&tp->intf->dev, "invalid phy ver addr\n"); 4332 goto out; 4333 } 4334 4335 rc = true; 4336out: 4337 return rc; 4338} 4339 4340static bool rtl8152_is_fw_phy_fixup_ok(struct r8152 *tp, struct fw_phy_fixup *fix) 4341{ 4342 bool rc = false; 4343 4344 switch (tp->version) { 4345 case RTL_VER_10: 4346 case RTL_VER_11: 4347 case RTL_VER_12: 4348 case RTL_VER_13: 4349 case RTL_VER_15: 4350 break; 4351 default: 4352 goto out; 4353 } 4354 4355 if (__le32_to_cpu(fix->blk_hdr.length) != sizeof(*fix)) { 4356 dev_err(&tp->intf->dev, "invalid block length\n"); 4357 goto out; 4358 } 4359 4360 if (__le16_to_cpu(fix->setting.addr) != OCP_PHY_PATCH_CMD || 4361 __le16_to_cpu(fix->setting.data) != BIT(7)) { 4362 dev_err(&tp->intf->dev, "invalid phy fixup\n"); 4363 goto out; 4364 } 4365 4366 rc = true; 4367out: 4368 return rc; 4369} 4370 4371static bool rtl8152_is_fw_phy_union_ok(struct r8152 *tp, struct fw_phy_union *phy) 4372{ 4373 u16 fw_offset; 4374 u32 length; 4375 bool rc = false; 4376 4377 switch (tp->version) { 4378 case RTL_VER_10: 4379 case RTL_VER_11: 4380 case RTL_VER_12: 4381 case RTL_VER_13: 4382 case RTL_VER_15: 4383 break; 4384 default: 4385 goto out; 4386 } 4387 4388 fw_offset = __le16_to_cpu(phy->fw_offset); 4389 length = __le32_to_cpu(phy->blk_hdr.length); 4390 if (fw_offset < sizeof(*phy) || length <= fw_offset) { 4391 dev_err(&tp->intf->dev, "invalid fw_offset\n"); 4392 goto out; 4393 } 4394 4395 length -= fw_offset; 4396 if (length & 1) { 4397 dev_err(&tp->intf->dev, "invalid block length\n"); 4398 goto out; 4399 } 4400 4401 if (phy->pre_num > 2) { 4402 dev_err(&tp->intf->dev, "invalid pre_num %d\n", phy->pre_num); 4403 goto out; 4404 } 4405 4406 if (phy->bp_num > 8) { 4407 dev_err(&tp->intf->dev, "invalid bp_num %d\n", phy->bp_num); 4408 goto out; 4409 } 4410 4411 rc = true; 4412out: 4413 return rc; 4414} 4415 4416static bool rtl8152_is_fw_phy_nc_ok(struct r8152 *tp, struct fw_phy_nc *phy) 4417{ 4418 u32 length; 4419 u16 fw_offset, fw_reg, ba_reg, patch_en_addr, mode_reg, bp_start; 4420 bool rc = false; 4421 4422 switch (tp->version) { 4423 case RTL_VER_04: 4424 case RTL_VER_05: 4425 case RTL_VER_06: 4426 fw_reg = 0xa014; 4427 ba_reg = 0xa012; 4428 patch_en_addr = 0xa01a; 4429 mode_reg = 0xb820; 4430 bp_start = 0xa000; 4431 break; 4432 default: 4433 goto out; 4434 } 4435 4436 fw_offset = __le16_to_cpu(phy->fw_offset); 4437 if (fw_offset < sizeof(*phy)) { 4438 dev_err(&tp->intf->dev, "fw_offset too small\n"); 4439 goto out; 4440 } 4441 4442 length = __le32_to_cpu(phy->blk_hdr.length); 4443 if (length < fw_offset) { 4444 dev_err(&tp->intf->dev, "invalid fw_offset\n"); 4445 goto out; 4446 } 4447 4448 length -= __le16_to_cpu(phy->fw_offset); 4449 if (!length || (length & 1)) { 4450 dev_err(&tp->intf->dev, "invalid block length\n"); 4451 goto out; 4452 } 4453 4454 if (__le16_to_cpu(phy->fw_reg) != fw_reg) { 4455 dev_err(&tp->intf->dev, "invalid register to load firmware\n"); 4456 goto out; 4457 } 4458 4459 if (__le16_to_cpu(phy->ba_reg) != ba_reg) { 4460 dev_err(&tp->intf->dev, "invalid base address register\n"); 4461 goto out; 4462 } 4463 4464 if (__le16_to_cpu(phy->patch_en_addr) != patch_en_addr) { 4465 dev_err(&tp->intf->dev, 4466 "invalid patch mode enabled register\n"); 4467 goto out; 4468 } 4469 4470 if (__le16_to_cpu(phy->mode_reg) != mode_reg) { 4471 dev_err(&tp->intf->dev, 4472 "invalid register to switch the mode\n"); 4473 goto out; 4474 } 4475 4476 if (__le16_to_cpu(phy->bp_start) != bp_start) { 4477 dev_err(&tp->intf->dev, 4478 "invalid start register of break point\n"); 4479 goto out; 4480 } 4481 4482 if (__le16_to_cpu(phy->bp_num) > 4) { 4483 dev_err(&tp->intf->dev, "invalid break point number\n"); 4484 goto out; 4485 } 4486 4487 rc = true; 4488out: 4489 return rc; 4490} 4491 4492static bool rtl8152_is_fw_mac_ok(struct r8152 *tp, struct fw_mac *mac) 4493{ 4494 u16 fw_reg, bp_ba_addr, bp_en_addr, bp_start, fw_offset; 4495 bool rc = false; 4496 u32 length, type; 4497 int i, max_bp; 4498 4499 type = __le32_to_cpu(mac->blk_hdr.type); 4500 if (type == RTL_FW_PLA) { 4501 switch (tp->version) { 4502 case RTL_VER_01: 4503 case RTL_VER_02: 4504 case RTL_VER_07: 4505 fw_reg = 0xf800; 4506 bp_ba_addr = PLA_BP_BA; 4507 bp_en_addr = 0; 4508 bp_start = PLA_BP_0; 4509 max_bp = 8; 4510 break; 4511 case RTL_VER_03: 4512 case RTL_VER_04: 4513 case RTL_VER_05: 4514 case RTL_VER_06: 4515 case RTL_VER_08: 4516 case RTL_VER_09: 4517 case RTL_VER_11: 4518 case RTL_VER_12: 4519 case RTL_VER_13: 4520 case RTL_VER_15: 4521 fw_reg = 0xf800; 4522 bp_ba_addr = PLA_BP_BA; 4523 bp_en_addr = PLA_BP_EN; 4524 bp_start = PLA_BP_0; 4525 max_bp = 8; 4526 break; 4527 case RTL_VER_14: 4528 fw_reg = 0xf800; 4529 bp_ba_addr = PLA_BP_BA; 4530 bp_en_addr = USB_BP2_EN; 4531 bp_start = PLA_BP_0; 4532 max_bp = 16; 4533 break; 4534 default: 4535 goto out; 4536 } 4537 } else if (type == RTL_FW_USB) { 4538 switch (tp->version) { 4539 case RTL_VER_03: 4540 case RTL_VER_04: 4541 case RTL_VER_05: 4542 case RTL_VER_06: 4543 fw_reg = 0xf800; 4544 bp_ba_addr = USB_BP_BA; 4545 bp_en_addr = USB_BP_EN; 4546 bp_start = USB_BP_0; 4547 max_bp = 8; 4548 break; 4549 case RTL_VER_08: 4550 case RTL_VER_09: 4551 case RTL_VER_11: 4552 case RTL_VER_12: 4553 case RTL_VER_13: 4554 case RTL_VER_14: 4555 case RTL_VER_15: 4556 fw_reg = 0xe600; 4557 bp_ba_addr = USB_BP_BA; 4558 bp_en_addr = USB_BP2_EN; 4559 bp_start = USB_BP_0; 4560 max_bp = 16; 4561 break; 4562 case RTL_VER_01: 4563 case RTL_VER_02: 4564 case RTL_VER_07: 4565 default: 4566 goto out; 4567 } 4568 } else { 4569 goto out; 4570 } 4571 4572 fw_offset = __le16_to_cpu(mac->fw_offset); 4573 if (fw_offset < sizeof(*mac)) { 4574 dev_err(&tp->intf->dev, "fw_offset too small\n"); 4575 goto out; 4576 } 4577 4578 length = __le32_to_cpu(mac->blk_hdr.length); 4579 if (length < fw_offset) { 4580 dev_err(&tp->intf->dev, "invalid fw_offset\n"); 4581 goto out; 4582 } 4583 4584 length -= fw_offset; 4585 if (length < 4 || (length & 3)) { 4586 dev_err(&tp->intf->dev, "invalid block length\n"); 4587 goto out; 4588 } 4589 4590 if (__le16_to_cpu(mac->fw_reg) != fw_reg) { 4591 dev_err(&tp->intf->dev, "invalid register to load firmware\n"); 4592 goto out; 4593 } 4594 4595 if (__le16_to_cpu(mac->bp_ba_addr) != bp_ba_addr) { 4596 dev_err(&tp->intf->dev, "invalid base address register\n"); 4597 goto out; 4598 } 4599 4600 if (__le16_to_cpu(mac->bp_en_addr) != bp_en_addr) { 4601 dev_err(&tp->intf->dev, "invalid enabled mask register\n"); 4602 goto out; 4603 } 4604 4605 if (__le16_to_cpu(mac->bp_start) != bp_start) { 4606 dev_err(&tp->intf->dev, 4607 "invalid start register of break point\n"); 4608 goto out; 4609 } 4610 4611 if (__le16_to_cpu(mac->bp_num) > max_bp) { 4612 dev_err(&tp->intf->dev, "invalid break point number\n"); 4613 goto out; 4614 } 4615 4616 for (i = __le16_to_cpu(mac->bp_num); i < max_bp; i++) { 4617 if (mac->bp[i]) { 4618 dev_err(&tp->intf->dev, "unused bp%u is not zero\n", i); 4619 goto out; 4620 } 4621 } 4622 4623 rc = true; 4624out: 4625 return rc; 4626} 4627 4628/* Verify the checksum for the firmware file. It is calculated from the version 4629 * field to the end of the file. Compare the result with the checksum field to 4630 * make sure the file is correct. 4631 */ 4632static long rtl8152_fw_verify_checksum(struct r8152 *tp, 4633 struct fw_header *fw_hdr, size_t size) 4634{ 4635 u8 checksum[sizeof(fw_hdr->checksum)]; 4636 4637 BUILD_BUG_ON(sizeof(checksum) != SHA256_DIGEST_SIZE); 4638 sha256(fw_hdr->version, size - sizeof(checksum), checksum); 4639 4640 if (memcmp(fw_hdr->checksum, checksum, sizeof(checksum))) { 4641 dev_err(&tp->intf->dev, "checksum fail\n"); 4642 return -EFAULT; 4643 } 4644 return 0; 4645} 4646 4647static long rtl8152_check_firmware(struct r8152 *tp, struct rtl_fw *rtl_fw) 4648{ 4649 const struct firmware *fw = rtl_fw->fw; 4650 struct fw_header *fw_hdr = (struct fw_header *)fw->data; 4651 unsigned long fw_flags = 0; 4652 long ret = -EFAULT; 4653 int i; 4654 4655 if (fw->size < sizeof(*fw_hdr)) { 4656 dev_err(&tp->intf->dev, "file too small\n"); 4657 goto fail; 4658 } 4659 4660 ret = rtl8152_fw_verify_checksum(tp, fw_hdr, fw->size); 4661 if (ret) 4662 goto fail; 4663 4664 ret = -EFAULT; 4665 4666 for (i = sizeof(*fw_hdr); i < fw->size;) { 4667 struct fw_block *block = (struct fw_block *)&fw->data[i]; 4668 u32 type; 4669 4670 if ((i + sizeof(*block)) > fw->size) 4671 goto fail; 4672 4673 type = __le32_to_cpu(block->type); 4674 switch (type) { 4675 case RTL_FW_END: 4676 if (__le32_to_cpu(block->length) != sizeof(*block)) 4677 goto fail; 4678 goto fw_end; 4679 case RTL_FW_PLA: 4680 if (test_bit(FW_FLAGS_PLA, &fw_flags)) { 4681 dev_err(&tp->intf->dev, 4682 "multiple PLA firmware encountered"); 4683 goto fail; 4684 } 4685 4686 if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) { 4687 dev_err(&tp->intf->dev, 4688 "check PLA firmware failed\n"); 4689 goto fail; 4690 } 4691 __set_bit(FW_FLAGS_PLA, &fw_flags); 4692 break; 4693 case RTL_FW_USB: 4694 if (test_bit(FW_FLAGS_USB, &fw_flags)) { 4695 dev_err(&tp->intf->dev, 4696 "multiple USB firmware encountered"); 4697 goto fail; 4698 } 4699 4700 if (!rtl8152_is_fw_mac_ok(tp, (struct fw_mac *)block)) { 4701 dev_err(&tp->intf->dev, 4702 "check USB firmware failed\n"); 4703 goto fail; 4704 } 4705 __set_bit(FW_FLAGS_USB, &fw_flags); 4706 break; 4707 case RTL_FW_PHY_START: 4708 if (test_bit(FW_FLAGS_START, &fw_flags) || 4709 test_bit(FW_FLAGS_NC, &fw_flags) || 4710 test_bit(FW_FLAGS_NC1, &fw_flags) || 4711 test_bit(FW_FLAGS_NC2, &fw_flags) || 4712 test_bit(FW_FLAGS_UC2, &fw_flags) || 4713 test_bit(FW_FLAGS_UC, &fw_flags) || 4714 test_bit(FW_FLAGS_STOP, &fw_flags)) { 4715 dev_err(&tp->intf->dev, 4716 "check PHY_START fail\n"); 4717 goto fail; 4718 } 4719 4720 if (__le32_to_cpu(block->length) != sizeof(struct fw_phy_patch_key)) { 4721 dev_err(&tp->intf->dev, 4722 "Invalid length for PHY_START\n"); 4723 goto fail; 4724 } 4725 __set_bit(FW_FLAGS_START, &fw_flags); 4726 break; 4727 case RTL_FW_PHY_STOP: 4728 if (test_bit(FW_FLAGS_STOP, &fw_flags) || 4729 !test_bit(FW_FLAGS_START, &fw_flags)) { 4730 dev_err(&tp->intf->dev, 4731 "Check PHY_STOP fail\n"); 4732 goto fail; 4733 } 4734 4735 if (__le32_to_cpu(block->length) != sizeof(*block)) { 4736 dev_err(&tp->intf->dev, 4737 "Invalid length for PHY_STOP\n"); 4738 goto fail; 4739 } 4740 __set_bit(FW_FLAGS_STOP, &fw_flags); 4741 break; 4742 case RTL_FW_PHY_NC: 4743 if (!test_bit(FW_FLAGS_START, &fw_flags) || 4744 test_bit(FW_FLAGS_STOP, &fw_flags)) { 4745 dev_err(&tp->intf->dev, 4746 "check PHY_NC fail\n"); 4747 goto fail; 4748 } 4749 4750 if (test_bit(FW_FLAGS_NC, &fw_flags)) { 4751 dev_err(&tp->intf->dev, 4752 "multiple PHY NC encountered\n"); 4753 goto fail; 4754 } 4755 4756 if (!rtl8152_is_fw_phy_nc_ok(tp, (struct fw_phy_nc *)block)) { 4757 dev_err(&tp->intf->dev, 4758 "check PHY NC firmware failed\n"); 4759 goto fail; 4760 } 4761 __set_bit(FW_FLAGS_NC, &fw_flags); 4762 break; 4763 case RTL_FW_PHY_UNION_NC: 4764 if (!test_bit(FW_FLAGS_START, &fw_flags) || 4765 test_bit(FW_FLAGS_NC1, &fw_flags) || 4766 test_bit(FW_FLAGS_NC2, &fw_flags) || 4767 test_bit(FW_FLAGS_UC2, &fw_flags) || 4768 test_bit(FW_FLAGS_UC, &fw_flags) || 4769 test_bit(FW_FLAGS_STOP, &fw_flags)) { 4770 dev_err(&tp->intf->dev, "PHY_UNION_NC out of order\n"); 4771 goto fail; 4772 } 4773 4774 if (test_bit(FW_FLAGS_NC, &fw_flags)) { 4775 dev_err(&tp->intf->dev, "multiple PHY_UNION_NC encountered\n"); 4776 goto fail; 4777 } 4778 4779 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { 4780 dev_err(&tp->intf->dev, "check PHY_UNION_NC failed\n"); 4781 goto fail; 4782 } 4783 __set_bit(FW_FLAGS_NC, &fw_flags); 4784 break; 4785 case RTL_FW_PHY_UNION_NC1: 4786 if (!test_bit(FW_FLAGS_START, &fw_flags) || 4787 test_bit(FW_FLAGS_NC2, &fw_flags) || 4788 test_bit(FW_FLAGS_UC2, &fw_flags) || 4789 test_bit(FW_FLAGS_UC, &fw_flags) || 4790 test_bit(FW_FLAGS_STOP, &fw_flags)) { 4791 dev_err(&tp->intf->dev, "PHY_UNION_NC1 out of order\n"); 4792 goto fail; 4793 } 4794 4795 if (test_bit(FW_FLAGS_NC1, &fw_flags)) { 4796 dev_err(&tp->intf->dev, "multiple PHY NC1 encountered\n"); 4797 goto fail; 4798 } 4799 4800 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { 4801 dev_err(&tp->intf->dev, "check PHY_UNION_NC1 failed\n"); 4802 goto fail; 4803 } 4804 __set_bit(FW_FLAGS_NC1, &fw_flags); 4805 break; 4806 case RTL_FW_PHY_UNION_NC2: 4807 if (!test_bit(FW_FLAGS_START, &fw_flags) || 4808 test_bit(FW_FLAGS_UC2, &fw_flags) || 4809 test_bit(FW_FLAGS_UC, &fw_flags) || 4810 test_bit(FW_FLAGS_STOP, &fw_flags)) { 4811 dev_err(&tp->intf->dev, "PHY_UNION_NC2 out of order\n"); 4812 goto fail; 4813 } 4814 4815 if (test_bit(FW_FLAGS_NC2, &fw_flags)) { 4816 dev_err(&tp->intf->dev, "multiple PHY NC2 encountered\n"); 4817 goto fail; 4818 } 4819 4820 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { 4821 dev_err(&tp->intf->dev, "check PHY_UNION_NC2 failed\n"); 4822 goto fail; 4823 } 4824 __set_bit(FW_FLAGS_NC2, &fw_flags); 4825 break; 4826 case RTL_FW_PHY_UNION_UC2: 4827 if (!test_bit(FW_FLAGS_START, &fw_flags) || 4828 test_bit(FW_FLAGS_UC, &fw_flags) || 4829 test_bit(FW_FLAGS_STOP, &fw_flags)) { 4830 dev_err(&tp->intf->dev, "PHY_UNION_UC2 out of order\n"); 4831 goto fail; 4832 } 4833 4834 if (test_bit(FW_FLAGS_UC2, &fw_flags)) { 4835 dev_err(&tp->intf->dev, "multiple PHY UC2 encountered\n"); 4836 goto fail; 4837 } 4838 4839 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { 4840 dev_err(&tp->intf->dev, "check PHY_UNION_UC2 failed\n"); 4841 goto fail; 4842 } 4843 __set_bit(FW_FLAGS_UC2, &fw_flags); 4844 break; 4845 case RTL_FW_PHY_UNION_UC: 4846 if (!test_bit(FW_FLAGS_START, &fw_flags) || 4847 test_bit(FW_FLAGS_STOP, &fw_flags)) { 4848 dev_err(&tp->intf->dev, "PHY_UNION_UC out of order\n"); 4849 goto fail; 4850 } 4851 4852 if (test_bit(FW_FLAGS_UC, &fw_flags)) { 4853 dev_err(&tp->intf->dev, "multiple PHY UC encountered\n"); 4854 goto fail; 4855 } 4856 4857 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { 4858 dev_err(&tp->intf->dev, "check PHY_UNION_UC failed\n"); 4859 goto fail; 4860 } 4861 __set_bit(FW_FLAGS_UC, &fw_flags); 4862 break; 4863 case RTL_FW_PHY_UNION_MISC: 4864 if (!rtl8152_is_fw_phy_union_ok(tp, (struct fw_phy_union *)block)) { 4865 dev_err(&tp->intf->dev, "check RTL_FW_PHY_UNION_MISC failed\n"); 4866 goto fail; 4867 } 4868 break; 4869 case RTL_FW_PHY_FIXUP: 4870 if (!rtl8152_is_fw_phy_fixup_ok(tp, (struct fw_phy_fixup *)block)) { 4871 dev_err(&tp->intf->dev, "check PHY fixup failed\n"); 4872 goto fail; 4873 } 4874 break; 4875 case RTL_FW_PHY_SPEED_UP: 4876 if (test_bit(FW_FLAGS_SPEED_UP, &fw_flags)) { 4877 dev_err(&tp->intf->dev, "multiple PHY firmware encountered"); 4878 goto fail; 4879 } 4880 4881 if (!rtl8152_is_fw_phy_speed_up_ok(tp, (struct fw_phy_speed_up *)block)) { 4882 dev_err(&tp->intf->dev, "check PHY speed up failed\n"); 4883 goto fail; 4884 } 4885 __set_bit(FW_FLAGS_SPEED_UP, &fw_flags); 4886 break; 4887 case RTL_FW_PHY_VER: 4888 if (test_bit(FW_FLAGS_START, &fw_flags) || 4889 test_bit(FW_FLAGS_NC, &fw_flags) || 4890 test_bit(FW_FLAGS_NC1, &fw_flags) || 4891 test_bit(FW_FLAGS_NC2, &fw_flags) || 4892 test_bit(FW_FLAGS_UC2, &fw_flags) || 4893 test_bit(FW_FLAGS_UC, &fw_flags) || 4894 test_bit(FW_FLAGS_STOP, &fw_flags)) { 4895 dev_err(&tp->intf->dev, "Invalid order to set PHY version\n"); 4896 goto fail; 4897 } 4898 4899 if (test_bit(FW_FLAGS_VER, &fw_flags)) { 4900 dev_err(&tp->intf->dev, "multiple PHY version encountered"); 4901 goto fail; 4902 } 4903 4904 if (!rtl8152_is_fw_phy_ver_ok(tp, (struct fw_phy_ver *)block)) { 4905 dev_err(&tp->intf->dev, "check PHY version failed\n"); 4906 goto fail; 4907 } 4908 __set_bit(FW_FLAGS_VER, &fw_flags); 4909 break; 4910 default: 4911 dev_warn(&tp->intf->dev, "Unknown type %u is found\n", 4912 type); 4913 break; 4914 } 4915 4916 /* next block */ 4917 i += ALIGN(__le32_to_cpu(block->length), 8); 4918 } 4919 4920fw_end: 4921 if (test_bit(FW_FLAGS_START, &fw_flags) && !test_bit(FW_FLAGS_STOP, &fw_flags)) { 4922 dev_err(&tp->intf->dev, "without PHY_STOP\n"); 4923 goto fail; 4924 } 4925 4926 return 0; 4927fail: 4928 return ret; 4929} 4930 4931static void rtl_ram_code_speed_up(struct r8152 *tp, struct fw_phy_speed_up *phy, bool wait) 4932{ 4933 u32 len; 4934 u8 *data; 4935 4936 rtl_reset_ocp_base(tp); 4937 4938 if (sram_read(tp, SRAM_GPHY_FW_VER) >= __le16_to_cpu(phy->version)) { 4939 dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n"); 4940 return; 4941 } 4942 4943 len = __le32_to_cpu(phy->blk_hdr.length); 4944 len -= __le16_to_cpu(phy->fw_offset); 4945 data = (u8 *)phy + __le16_to_cpu(phy->fw_offset); 4946 4947 if (rtl_phy_patch_request(tp, true, wait)) 4948 return; 4949 4950 while (len) { 4951 u32 ocp_data, size; 4952 int i; 4953 4954 if (len < 2048) 4955 size = len; 4956 else 4957 size = 2048; 4958 4959 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL); 4960 ocp_data |= GPHY_PATCH_DONE | BACKUP_RESTRORE; 4961 ocp_write_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL, ocp_data); 4962 4963 generic_ocp_write(tp, __le16_to_cpu(phy->fw_reg), 0xff, size, data, MCU_TYPE_USB); 4964 4965 data += size; 4966 len -= size; 4967 4968 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL); 4969 ocp_data |= POL_GPHY_PATCH; 4970 ocp_write_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL, ocp_data); 4971 4972 for (i = 0; i < 1000; i++) { 4973 if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & POL_GPHY_PATCH)) 4974 break; 4975 } 4976 4977 if (i == 1000) { 4978 dev_err(&tp->intf->dev, "ram code speedup mode timeout\n"); 4979 break; 4980 } 4981 } 4982 4983 rtl_reset_ocp_base(tp); 4984 4985 rtl_phy_patch_request(tp, false, wait); 4986 4987 if (sram_read(tp, SRAM_GPHY_FW_VER) == __le16_to_cpu(phy->version)) 4988 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info); 4989 else 4990 dev_err(&tp->intf->dev, "ram code speedup mode fail\n"); 4991} 4992 4993static int rtl8152_fw_phy_ver(struct r8152 *tp, struct fw_phy_ver *phy_ver) 4994{ 4995 u16 ver_addr, ver; 4996 4997 ver_addr = __le16_to_cpu(phy_ver->ver.addr); 4998 ver = __le16_to_cpu(phy_ver->ver.data); 4999 5000 rtl_reset_ocp_base(tp); 5001 5002 if (sram_read(tp, ver_addr) >= ver) { 5003 dev_dbg(&tp->intf->dev, "PHY firmware has been the newest\n"); 5004 return 0; 5005 } 5006 5007 sram_write(tp, ver_addr, ver); 5008 5009 dev_dbg(&tp->intf->dev, "PHY firmware version %x\n", ver); 5010 5011 return ver; 5012} 5013 5014static void rtl8152_fw_phy_fixup(struct r8152 *tp, struct fw_phy_fixup *fix) 5015{ 5016 u16 addr, data; 5017 5018 rtl_reset_ocp_base(tp); 5019 5020 addr = __le16_to_cpu(fix->setting.addr); 5021 data = ocp_reg_read(tp, addr); 5022 5023 switch (__le16_to_cpu(fix->bit_cmd)) { 5024 case FW_FIXUP_AND: 5025 data &= __le16_to_cpu(fix->setting.data); 5026 break; 5027 case FW_FIXUP_OR: 5028 data |= __le16_to_cpu(fix->setting.data); 5029 break; 5030 case FW_FIXUP_NOT: 5031 data &= ~__le16_to_cpu(fix->setting.data); 5032 break; 5033 case FW_FIXUP_XOR: 5034 data ^= __le16_to_cpu(fix->setting.data); 5035 break; 5036 default: 5037 return; 5038 } 5039 5040 ocp_reg_write(tp, addr, data); 5041 5042 dev_dbg(&tp->intf->dev, "applied ocp %x %x\n", addr, data); 5043} 5044 5045static void rtl8152_fw_phy_union_apply(struct r8152 *tp, struct fw_phy_union *phy) 5046{ 5047 __le16 *data; 5048 u32 length; 5049 int i, num; 5050 5051 rtl_reset_ocp_base(tp); 5052 5053 num = phy->pre_num; 5054 for (i = 0; i < num; i++) 5055 sram_write(tp, __le16_to_cpu(phy->pre_set[i].addr), 5056 __le16_to_cpu(phy->pre_set[i].data)); 5057 5058 length = __le32_to_cpu(phy->blk_hdr.length); 5059 length -= __le16_to_cpu(phy->fw_offset); 5060 num = length / 2; 5061 data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset)); 5062 5063 ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg)); 5064 for (i = 0; i < num; i++) 5065 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i])); 5066 5067 num = phy->bp_num; 5068 for (i = 0; i < num; i++) 5069 sram_write(tp, __le16_to_cpu(phy->bp[i].addr), __le16_to_cpu(phy->bp[i].data)); 5070 5071 if (phy->bp_num && phy->bp_en.addr) 5072 sram_write(tp, __le16_to_cpu(phy->bp_en.addr), __le16_to_cpu(phy->bp_en.data)); 5073 5074 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info); 5075} 5076 5077static void rtl8152_fw_phy_nc_apply(struct r8152 *tp, struct fw_phy_nc *phy) 5078{ 5079 u16 mode_reg, bp_index; 5080 u32 length, i, num; 5081 __le16 *data; 5082 5083 rtl_reset_ocp_base(tp); 5084 5085 mode_reg = __le16_to_cpu(phy->mode_reg); 5086 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_pre)); 5087 sram_write(tp, __le16_to_cpu(phy->ba_reg), 5088 __le16_to_cpu(phy->ba_data)); 5089 5090 length = __le32_to_cpu(phy->blk_hdr.length); 5091 length -= __le16_to_cpu(phy->fw_offset); 5092 num = length / 2; 5093 data = (__le16 *)((u8 *)phy + __le16_to_cpu(phy->fw_offset)); 5094 5095 ocp_reg_write(tp, OCP_SRAM_ADDR, __le16_to_cpu(phy->fw_reg)); 5096 for (i = 0; i < num; i++) 5097 ocp_reg_write(tp, OCP_SRAM_DATA, __le16_to_cpu(data[i])); 5098 5099 sram_write(tp, __le16_to_cpu(phy->patch_en_addr), 5100 __le16_to_cpu(phy->patch_en_value)); 5101 5102 bp_index = __le16_to_cpu(phy->bp_start); 5103 num = __le16_to_cpu(phy->bp_num); 5104 for (i = 0; i < num; i++) { 5105 sram_write(tp, bp_index, __le16_to_cpu(phy->bp[i])); 5106 bp_index += 2; 5107 } 5108 5109 sram_write(tp, mode_reg, __le16_to_cpu(phy->mode_post)); 5110 5111 dev_dbg(&tp->intf->dev, "successfully applied %s\n", phy->info); 5112} 5113 5114static void rtl8152_fw_mac_apply(struct r8152 *tp, struct fw_mac *mac) 5115{ 5116 u16 bp_en_addr, type, fw_ver_reg; 5117 u32 length; 5118 u8 *data; 5119 5120 switch (__le32_to_cpu(mac->blk_hdr.type)) { 5121 case RTL_FW_PLA: 5122 type = MCU_TYPE_PLA; 5123 break; 5124 case RTL_FW_USB: 5125 type = MCU_TYPE_USB; 5126 break; 5127 default: 5128 return; 5129 } 5130 5131 fw_ver_reg = __le16_to_cpu(mac->fw_ver_reg); 5132 if (fw_ver_reg && ocp_read_byte(tp, MCU_TYPE_USB, fw_ver_reg) >= mac->fw_ver_data) { 5133 dev_dbg(&tp->intf->dev, "%s firmware has been the newest\n", type ? "PLA" : "USB"); 5134 return; 5135 } 5136 5137 rtl_clear_bp(tp, type); 5138 5139 /* Enable backup/restore of MACDBG. This is required after clearing PLA 5140 * break points and before applying the PLA firmware. 5141 */ 5142 if (tp->version == RTL_VER_04 && type == MCU_TYPE_PLA && 5143 !(ocp_read_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST) & DEBUG_OE)) { 5144 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_PRE, DEBUG_LTSSM); 5145 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MACDBG_POST, DEBUG_LTSSM); 5146 } 5147 5148 length = __le32_to_cpu(mac->blk_hdr.length); 5149 length -= __le16_to_cpu(mac->fw_offset); 5150 5151 data = (u8 *)mac; 5152 data += __le16_to_cpu(mac->fw_offset); 5153 5154 if (generic_ocp_write(tp, __le16_to_cpu(mac->fw_reg), 0xff, length, 5155 data, type) < 0) { 5156 dev_err(&tp->intf->dev, "Write %s fw fail\n", 5157 type ? "PLA" : "USB"); 5158 return; 5159 } 5160 5161 ocp_write_word(tp, type, __le16_to_cpu(mac->bp_ba_addr), 5162 __le16_to_cpu(mac->bp_ba_value)); 5163 5164 if (generic_ocp_write(tp, __le16_to_cpu(mac->bp_start), BYTE_EN_DWORD, 5165 ALIGN(__le16_to_cpu(mac->bp_num) << 1, 4), 5166 mac->bp, type) < 0) { 5167 dev_err(&tp->intf->dev, "Write %s bp fail\n", 5168 type ? "PLA" : "USB"); 5169 return; 5170 } 5171 5172 bp_en_addr = __le16_to_cpu(mac->bp_en_addr); 5173 if (bp_en_addr) 5174 ocp_write_word(tp, type, bp_en_addr, 5175 __le16_to_cpu(mac->bp_en_value)); 5176 5177 if (fw_ver_reg) 5178 ocp_write_byte(tp, MCU_TYPE_USB, fw_ver_reg, 5179 mac->fw_ver_data); 5180 5181 dev_dbg(&tp->intf->dev, "successfully applied %s\n", mac->info); 5182} 5183 5184static void rtl8152_apply_firmware(struct r8152 *tp, bool power_cut) 5185{ 5186 struct rtl_fw *rtl_fw = &tp->rtl_fw; 5187 const struct firmware *fw; 5188 struct fw_header *fw_hdr; 5189 struct fw_phy_patch_key *key; 5190 u16 key_addr = 0; 5191 int i, patch_phy = 1; 5192 5193 if (IS_ERR_OR_NULL(rtl_fw->fw)) 5194 return; 5195 5196 fw = rtl_fw->fw; 5197 fw_hdr = (struct fw_header *)fw->data; 5198 5199 if (rtl_fw->pre_fw) 5200 rtl_fw->pre_fw(tp); 5201 5202 for (i = offsetof(struct fw_header, blocks); i < fw->size;) { 5203 struct fw_block *block = (struct fw_block *)&fw->data[i]; 5204 5205 switch (__le32_to_cpu(block->type)) { 5206 case RTL_FW_END: 5207 goto post_fw; 5208 case RTL_FW_PLA: 5209 case RTL_FW_USB: 5210 rtl8152_fw_mac_apply(tp, (struct fw_mac *)block); 5211 break; 5212 case RTL_FW_PHY_START: 5213 if (!patch_phy) 5214 break; 5215 key = (struct fw_phy_patch_key *)block; 5216 key_addr = __le16_to_cpu(key->key_reg); 5217 rtl_pre_ram_code(tp, key_addr, __le16_to_cpu(key->key_data), !power_cut); 5218 break; 5219 case RTL_FW_PHY_STOP: 5220 if (!patch_phy) 5221 break; 5222 WARN_ON(!key_addr); 5223 rtl_post_ram_code(tp, key_addr, !power_cut); 5224 break; 5225 case RTL_FW_PHY_NC: 5226 rtl8152_fw_phy_nc_apply(tp, (struct fw_phy_nc *)block); 5227 break; 5228 case RTL_FW_PHY_VER: 5229 patch_phy = rtl8152_fw_phy_ver(tp, (struct fw_phy_ver *)block); 5230 break; 5231 case RTL_FW_PHY_UNION_NC: 5232 case RTL_FW_PHY_UNION_NC1: 5233 case RTL_FW_PHY_UNION_NC2: 5234 case RTL_FW_PHY_UNION_UC2: 5235 case RTL_FW_PHY_UNION_UC: 5236 case RTL_FW_PHY_UNION_MISC: 5237 if (patch_phy) 5238 rtl8152_fw_phy_union_apply(tp, (struct fw_phy_union *)block); 5239 break; 5240 case RTL_FW_PHY_FIXUP: 5241 if (patch_phy) 5242 rtl8152_fw_phy_fixup(tp, (struct fw_phy_fixup *)block); 5243 break; 5244 case RTL_FW_PHY_SPEED_UP: 5245 rtl_ram_code_speed_up(tp, (struct fw_phy_speed_up *)block, !power_cut); 5246 break; 5247 default: 5248 break; 5249 } 5250 5251 i += ALIGN(__le32_to_cpu(block->length), 8); 5252 } 5253 5254post_fw: 5255 if (rtl_fw->post_fw) 5256 rtl_fw->post_fw(tp); 5257 5258 rtl_reset_ocp_base(tp); 5259 strscpy(rtl_fw->version, fw_hdr->version, RTL_VER_SIZE); 5260 dev_dbg(&tp->intf->dev, "load %s successfully\n", rtl_fw->version); 5261} 5262 5263static void rtl8152_release_firmware(struct r8152 *tp) 5264{ 5265 struct rtl_fw *rtl_fw = &tp->rtl_fw; 5266 5267 if (!IS_ERR_OR_NULL(rtl_fw->fw)) { 5268 release_firmware(rtl_fw->fw); 5269 rtl_fw->fw = NULL; 5270 } 5271} 5272 5273static int rtl8152_request_firmware(struct r8152 *tp) 5274{ 5275 struct rtl_fw *rtl_fw = &tp->rtl_fw; 5276 long rc; 5277 5278 if (rtl_fw->fw || !rtl_fw->fw_name) { 5279 dev_info(&tp->intf->dev, "skip request firmware\n"); 5280 rc = 0; 5281 goto result; 5282 } 5283 5284 rc = request_firmware(&rtl_fw->fw, rtl_fw->fw_name, &tp->intf->dev); 5285 if (rc < 0) 5286 goto result; 5287 5288 rc = rtl8152_check_firmware(tp, rtl_fw); 5289 if (rc < 0) 5290 release_firmware(rtl_fw->fw); 5291 5292result: 5293 if (rc) { 5294 rtl_fw->fw = ERR_PTR(rc); 5295 5296 dev_warn(&tp->intf->dev, 5297 "unable to load firmware patch %s (%ld)\n", 5298 rtl_fw->fw_name, rc); 5299 } 5300 5301 return rc; 5302} 5303 5304static void r8152_aldps_en(struct r8152 *tp, bool enable) 5305{ 5306 if (enable) { 5307 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPWRSAVE | ENPDNPS | 5308 LINKENA | DIS_SDSAVE); 5309 } else { 5310 ocp_reg_write(tp, OCP_ALDPS_CONFIG, ENPDNPS | LINKENA | 5311 DIS_SDSAVE); 5312 msleep(20); 5313 } 5314} 5315 5316static inline void r8152_mmd_indirect(struct r8152 *tp, u16 dev, u16 reg) 5317{ 5318 ocp_reg_write(tp, OCP_EEE_AR, FUN_ADDR | dev); 5319 ocp_reg_write(tp, OCP_EEE_DATA, reg); 5320 ocp_reg_write(tp, OCP_EEE_AR, FUN_DATA | dev); 5321} 5322 5323static u16 r8152_mmd_read(struct r8152 *tp, u16 dev, u16 reg) 5324{ 5325 u16 data; 5326 5327 r8152_mmd_indirect(tp, dev, reg); 5328 data = ocp_reg_read(tp, OCP_EEE_DATA); 5329 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 5330 5331 return data; 5332} 5333 5334static void r8152_mmd_write(struct r8152 *tp, u16 dev, u16 reg, u16 data) 5335{ 5336 r8152_mmd_indirect(tp, dev, reg); 5337 ocp_reg_write(tp, OCP_EEE_DATA, data); 5338 ocp_reg_write(tp, OCP_EEE_AR, 0x0000); 5339} 5340 5341static void r8152_eee_en(struct r8152 *tp, bool enable) 5342{ 5343 u16 config1, config2, config3; 5344 u32 ocp_data; 5345 5346 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 5347 config1 = ocp_reg_read(tp, OCP_EEE_CONFIG1) & ~sd_rise_time_mask; 5348 config2 = ocp_reg_read(tp, OCP_EEE_CONFIG2); 5349 config3 = ocp_reg_read(tp, OCP_EEE_CONFIG3) & ~fast_snr_mask; 5350 5351 if (enable) { 5352 ocp_data |= EEE_RX_EN | EEE_TX_EN; 5353 config1 |= EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | RX_QUIET_EN; 5354 config1 |= sd_rise_time(1); 5355 config2 |= RG_DACQUIET_EN | RG_LDVQUIET_EN; 5356 config3 |= fast_snr(42); 5357 } else { 5358 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 5359 config1 &= ~(EEE_10_CAP | EEE_NWAY_EN | TX_QUIET_EN | 5360 RX_QUIET_EN); 5361 config1 |= sd_rise_time(7); 5362 config2 &= ~(RG_DACQUIET_EN | RG_LDVQUIET_EN); 5363 config3 |= fast_snr(511); 5364 } 5365 5366 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 5367 ocp_reg_write(tp, OCP_EEE_CONFIG1, config1); 5368 ocp_reg_write(tp, OCP_EEE_CONFIG2, config2); 5369 ocp_reg_write(tp, OCP_EEE_CONFIG3, config3); 5370} 5371 5372static void r8153_eee_en(struct r8152 *tp, bool enable) 5373{ 5374 u32 ocp_data; 5375 u16 config; 5376 5377 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EEE_CR); 5378 config = ocp_reg_read(tp, OCP_EEE_CFG); 5379 5380 if (enable) { 5381 ocp_data |= EEE_RX_EN | EEE_TX_EN; 5382 config |= EEE10_EN; 5383 } else { 5384 ocp_data &= ~(EEE_RX_EN | EEE_TX_EN); 5385 config &= ~EEE10_EN; 5386 } 5387 5388 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_CR, ocp_data); 5389 ocp_reg_write(tp, OCP_EEE_CFG, config); 5390 5391 tp->ups_info.eee = enable; 5392} 5393 5394static void r8156_eee_en(struct r8152 *tp, bool enable) 5395{ 5396 u16 config; 5397 5398 r8153_eee_en(tp, enable); 5399 5400 config = ocp_reg_read(tp, OCP_EEE_ADV2); 5401 5402 if (enable) 5403 config |= MDIO_EEE_2_5GT; 5404 else 5405 config &= ~MDIO_EEE_2_5GT; 5406 5407 ocp_reg_write(tp, OCP_EEE_ADV2, config); 5408} 5409 5410static void rtl_eee_enable(struct r8152 *tp, bool enable) 5411{ 5412 switch (tp->version) { 5413 case RTL_VER_01: 5414 case RTL_VER_02: 5415 case RTL_VER_07: 5416 if (enable) { 5417 r8152_eee_en(tp, true); 5418 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 5419 tp->eee_adv); 5420 } else { 5421 r8152_eee_en(tp, false); 5422 r8152_mmd_write(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV, 0); 5423 } 5424 break; 5425 case RTL_VER_03: 5426 case RTL_VER_04: 5427 case RTL_VER_05: 5428 case RTL_VER_06: 5429 case RTL_VER_08: 5430 case RTL_VER_09: 5431 case RTL_VER_14: 5432 if (enable) { 5433 r8153_eee_en(tp, true); 5434 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv); 5435 } else { 5436 r8153_eee_en(tp, false); 5437 ocp_reg_write(tp, OCP_EEE_ADV, 0); 5438 } 5439 break; 5440 case RTL_VER_10: 5441 case RTL_VER_11: 5442 case RTL_VER_12: 5443 case RTL_VER_13: 5444 case RTL_VER_15: 5445 if (enable) { 5446 r8156_eee_en(tp, true); 5447 ocp_reg_write(tp, OCP_EEE_ADV, tp->eee_adv); 5448 } else { 5449 r8156_eee_en(tp, false); 5450 ocp_reg_write(tp, OCP_EEE_ADV, 0); 5451 } 5452 break; 5453 default: 5454 break; 5455 } 5456} 5457 5458static void r8152b_enable_fc(struct r8152 *tp) 5459{ 5460 u16 anar; 5461 5462 anar = r8152_mdio_read(tp, MII_ADVERTISE); 5463 anar |= ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM; 5464 r8152_mdio_write(tp, MII_ADVERTISE, anar); 5465 5466 tp->ups_info.flow_control = true; 5467} 5468 5469static void rtl8152_disable(struct r8152 *tp) 5470{ 5471 r8152_aldps_en(tp, false); 5472 rtl_disable(tp); 5473 r8152_aldps_en(tp, true); 5474} 5475 5476static void r8152b_hw_phy_cfg(struct r8152 *tp) 5477{ 5478 rtl8152_apply_firmware(tp, false); 5479 rtl_eee_enable(tp, tp->eee_en); 5480 r8152_aldps_en(tp, true); 5481 r8152b_enable_fc(tp); 5482 5483 set_bit(PHY_RESET, &tp->flags); 5484} 5485 5486static void wait_oob_link_list_ready(struct r8152 *tp) 5487{ 5488 u32 ocp_data; 5489 int i; 5490 5491 for (i = 0; i < 1000; i++) { 5492 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 5493 break; 5494 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 5495 if (ocp_data & LINK_LIST_READY) 5496 break; 5497 usleep_range(1000, 2000); 5498 } 5499} 5500 5501static void r8156b_wait_loading_flash(struct r8152 *tp) 5502{ 5503 if ((ocp_read_word(tp, MCU_TYPE_PLA, PLA_GPHY_CTRL) & GPHY_FLASH) && 5504 !(ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & BYPASS_FLASH)) { 5505 int i; 5506 5507 for (i = 0; i < 100; i++) { 5508 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 5509 break; 5510 if (ocp_read_word(tp, MCU_TYPE_USB, USB_GPHY_CTRL) & GPHY_PATCH_DONE) 5511 break; 5512 usleep_range(1000, 2000); 5513 } 5514 } 5515} 5516 5517static void r8152b_exit_oob(struct r8152 *tp) 5518{ 5519 u32 ocp_data; 5520 5521 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 5522 ocp_data &= ~RCR_ACPT_ALL; 5523 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 5524 5525 rxdy_gated_en(tp, true); 5526 r8153_teredo_off(tp); 5527 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 5528 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CR, 0x00); 5529 5530 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 5531 ocp_data &= ~NOW_IS_OOB; 5532 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 5533 5534 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 5535 ocp_data &= ~MCU_BORW_EN; 5536 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 5537 5538 wait_oob_link_list_ready(tp); 5539 5540 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 5541 ocp_data |= RE_INIT_LL; 5542 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 5543 5544 wait_oob_link_list_ready(tp); 5545 5546 rtl8152_nic_reset(tp); 5547 5548 /* rx share fifo credit full threshold */ 5549 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 5550 5551 if (tp->udev->speed == USB_SPEED_FULL || 5552 tp->udev->speed == USB_SPEED_LOW) { 5553 /* rx share fifo credit near full threshold */ 5554 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 5555 RXFIFO_THR2_FULL); 5556 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 5557 RXFIFO_THR3_FULL); 5558 } else { 5559 /* rx share fifo credit near full threshold */ 5560 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, 5561 RXFIFO_THR2_HIGH); 5562 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, 5563 RXFIFO_THR3_HIGH); 5564 } 5565 5566 /* TX share fifo free credit full threshold */ 5567 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); 5568 5569 ocp_write_byte(tp, MCU_TYPE_USB, USB_TX_AGG, TX_AGG_MAX_THRESHOLD); 5570 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_HIGH); 5571 ocp_write_dword(tp, MCU_TYPE_USB, USB_TX_DMA, 5572 TEST_MODE_DISABLE | TX_SIZE_ADJUST1); 5573 5574 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 5575 5576 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 5577 5578 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 5579 ocp_data |= TCR0_AUTO_FIFO; 5580 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 5581} 5582 5583static void r8152b_enter_oob(struct r8152 *tp) 5584{ 5585 u32 ocp_data; 5586 5587 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 5588 ocp_data &= ~NOW_IS_OOB; 5589 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 5590 5591 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 5592 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 5593 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 5594 5595 rtl_disable(tp); 5596 5597 wait_oob_link_list_ready(tp); 5598 5599 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 5600 ocp_data |= RE_INIT_LL; 5601 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 5602 5603 wait_oob_link_list_ready(tp); 5604 5605 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, RTL8152_RMS); 5606 5607 rtl_rx_vlan_en(tp, true); 5608 5609 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR); 5610 ocp_data |= ALDPS_PROXY_MODE; 5611 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data); 5612 5613 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 5614 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 5615 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 5616 5617 rxdy_gated_en(tp, false); 5618 5619 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 5620 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 5621 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 5622} 5623 5624static int r8153_pre_firmware_1(struct r8152 *tp) 5625{ 5626 int i; 5627 5628 /* Wait till the WTD timer is ready. It would take at most 104 ms. */ 5629 for (i = 0; i < 104; i++) { 5630 u32 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_WDT1_CTRL); 5631 5632 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 5633 return -ENODEV; 5634 if (!(ocp_data & WTD1_EN)) 5635 break; 5636 usleep_range(1000, 2000); 5637 } 5638 5639 return 0; 5640} 5641 5642static int r8153_post_firmware_1(struct r8152 *tp) 5643{ 5644 /* set USB_BP_4 to support USB_SPEED_SUPER only */ 5645 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) 5646 ocp_write_word(tp, MCU_TYPE_USB, USB_BP_4, BP4_SUPER_ONLY); 5647 5648 /* reset UPHY timer to 36 ms */ 5649 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16); 5650 5651 return 0; 5652} 5653 5654static int r8153_pre_firmware_2(struct r8152 *tp) 5655{ 5656 u32 ocp_data; 5657 5658 r8153_pre_firmware_1(tp); 5659 5660 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0); 5661 ocp_data &= ~FW_FIX_SUSPEND; 5662 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data); 5663 5664 return 0; 5665} 5666 5667static int r8153_post_firmware_2(struct r8152 *tp) 5668{ 5669 u32 ocp_data; 5670 5671 /* enable bp0 if support USB_SPEED_SUPER only */ 5672 if (ocp_read_byte(tp, MCU_TYPE_USB, USB_CSTMR) & FORCE_SUPER) { 5673 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN); 5674 ocp_data |= BIT(0); 5675 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data); 5676 } 5677 5678 /* reset UPHY timer to 36 ms */ 5679 ocp_write_word(tp, MCU_TYPE_PLA, PLA_UPHY_TIMER, 36000 / 16); 5680 5681 /* enable U3P3 check, set the counter to 4 */ 5682 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, U3P3_CHECK_EN | 4); 5683 5684 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0); 5685 ocp_data |= FW_FIX_SUSPEND; 5686 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN0, ocp_data); 5687 5688 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); 5689 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; 5690 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); 5691 5692 return 0; 5693} 5694 5695static int r8153_post_firmware_3(struct r8152 *tp) 5696{ 5697 u32 ocp_data; 5698 5699 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); 5700 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; 5701 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); 5702 5703 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1); 5704 ocp_data |= FW_IP_RESET_EN; 5705 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data); 5706 5707 return 0; 5708} 5709 5710static int r8153b_pre_firmware_1(struct r8152 *tp) 5711{ 5712 /* enable fc timer and set timer to 1 second. */ 5713 ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER, 5714 CTRL_TIMER_EN | (1000 / 8)); 5715 5716 return 0; 5717} 5718 5719static int r8153b_post_firmware_1(struct r8152 *tp) 5720{ 5721 u32 ocp_data; 5722 5723 /* enable bp0 for RTL8153-BND */ 5724 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_1); 5725 if (ocp_data & BND_MASK) { 5726 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BP_EN); 5727 ocp_data |= BIT(0); 5728 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BP_EN, ocp_data); 5729 } 5730 5731 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL); 5732 ocp_data |= FLOW_CTRL_PATCH_OPT; 5733 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data); 5734 5735 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); 5736 ocp_data |= FC_PATCH_TASK; 5737 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); 5738 5739 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1); 5740 ocp_data |= FW_IP_RESET_EN; 5741 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data); 5742 5743 return 0; 5744} 5745 5746static int r8153c_post_firmware_1(struct r8152 *tp) 5747{ 5748 u32 ocp_data; 5749 5750 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL); 5751 ocp_data |= FLOW_CTRL_PATCH_2; 5752 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data); 5753 5754 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); 5755 ocp_data |= FC_PATCH_TASK; 5756 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); 5757 5758 return 0; 5759} 5760 5761static int r8156a_post_firmware_1(struct r8152 *tp) 5762{ 5763 u32 ocp_data; 5764 5765 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1); 5766 ocp_data |= FW_IP_RESET_EN; 5767 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_FIX_EN1, ocp_data); 5768 5769 /* Modify U3PHY parameter for compatibility issue */ 5770 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4026840e); 5771 ocp_write_dword(tp, MCU_TYPE_USB, USB_UPHY3_MDCMDIO, 0x4001acc9); 5772 5773 return 0; 5774} 5775 5776static void r8153_aldps_en(struct r8152 *tp, bool enable) 5777{ 5778 u16 data; 5779 5780 data = ocp_reg_read(tp, OCP_POWER_CFG); 5781 if (enable) { 5782 data |= EN_ALDPS; 5783 ocp_reg_write(tp, OCP_POWER_CFG, data); 5784 } else { 5785 int i; 5786 5787 data &= ~EN_ALDPS; 5788 ocp_reg_write(tp, OCP_POWER_CFG, data); 5789 for (i = 0; i < 20; i++) { 5790 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 5791 return; 5792 usleep_range(1000, 2000); 5793 if (ocp_read_word(tp, MCU_TYPE_PLA, 0xe000) & 0x0100) 5794 break; 5795 } 5796 } 5797 5798 tp->ups_info.aldps = enable; 5799} 5800 5801static void r8153_hw_phy_cfg(struct r8152 *tp) 5802{ 5803 u32 ocp_data; 5804 u16 data; 5805 5806 /* disable ALDPS before updating the PHY parameters */ 5807 r8153_aldps_en(tp, false); 5808 5809 /* disable EEE before updating the PHY parameters */ 5810 rtl_eee_enable(tp, false); 5811 5812 rtl8152_apply_firmware(tp, false); 5813 5814 if (tp->version == RTL_VER_03) { 5815 data = ocp_reg_read(tp, OCP_EEE_CFG); 5816 data &= ~CTAP_SHORT_EN; 5817 ocp_reg_write(tp, OCP_EEE_CFG, data); 5818 } 5819 5820 data = ocp_reg_read(tp, OCP_POWER_CFG); 5821 data |= EEE_CLKDIV_EN; 5822 ocp_reg_write(tp, OCP_POWER_CFG, data); 5823 5824 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 5825 data |= EN_10M_BGOFF; 5826 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 5827 data = ocp_reg_read(tp, OCP_POWER_CFG); 5828 data |= EN_10M_PLLOFF; 5829 ocp_reg_write(tp, OCP_POWER_CFG, data); 5830 sram_write(tp, SRAM_IMPEDANCE, 0x0b13); 5831 5832 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 5833 ocp_data |= PFM_PWM_SWITCH; 5834 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 5835 5836 /* Enable LPF corner auto tune */ 5837 sram_write(tp, SRAM_LPF_CFG, 0xf70f); 5838 5839 /* Adjust 10M Amplitude */ 5840 sram_write(tp, SRAM_10M_AMP1, 0x00af); 5841 sram_write(tp, SRAM_10M_AMP2, 0x0208); 5842 5843 if (tp->eee_en) 5844 rtl_eee_enable(tp, true); 5845 5846 r8153_aldps_en(tp, true); 5847 r8152b_enable_fc(tp); 5848 5849 switch (tp->version) { 5850 case RTL_VER_03: 5851 case RTL_VER_04: 5852 break; 5853 case RTL_VER_05: 5854 case RTL_VER_06: 5855 default: 5856 r8153_u2p3en(tp, true); 5857 break; 5858 } 5859 5860 set_bit(PHY_RESET, &tp->flags); 5861} 5862 5863static u32 r8152_efuse_read(struct r8152 *tp, u8 addr) 5864{ 5865 u32 ocp_data; 5866 5867 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD, EFUSE_READ_CMD | addr); 5868 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_CMD); 5869 ocp_data = (ocp_data & EFUSE_DATA_BIT16) << 9; /* data of bit16 */ 5870 ocp_data |= ocp_read_word(tp, MCU_TYPE_PLA, PLA_EFUSE_DATA); 5871 5872 return ocp_data; 5873} 5874 5875static void r8153b_hw_phy_cfg(struct r8152 *tp) 5876{ 5877 u32 ocp_data; 5878 u16 data; 5879 5880 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 5881 if (ocp_data & PCUT_STATUS) { 5882 ocp_data &= ~PCUT_STATUS; 5883 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 5884 } 5885 5886 /* disable ALDPS before updating the PHY parameters */ 5887 r8153_aldps_en(tp, false); 5888 5889 /* disable EEE before updating the PHY parameters */ 5890 rtl_eee_enable(tp, false); 5891 5892 /* U1/U2/L1 idle timer. 500 us */ 5893 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); 5894 5895 data = r8153_phy_status(tp, 0); 5896 5897 switch (data) { 5898 case PHY_STAT_PWRDN: 5899 case PHY_STAT_EXT_INIT: 5900 rtl8152_apply_firmware(tp, true); 5901 5902 data = r8152_mdio_read(tp, MII_BMCR); 5903 data &= ~BMCR_PDOWN; 5904 r8152_mdio_write(tp, MII_BMCR, data); 5905 break; 5906 case PHY_STAT_LAN_ON: 5907 default: 5908 rtl8152_apply_firmware(tp, false); 5909 break; 5910 } 5911 5912 r8153b_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); 5913 5914 data = sram_read(tp, SRAM_GREEN_CFG); 5915 data |= R_TUNE_EN; 5916 sram_write(tp, SRAM_GREEN_CFG, data); 5917 data = ocp_reg_read(tp, OCP_NCTL_CFG); 5918 data |= PGA_RETURN_EN; 5919 ocp_reg_write(tp, OCP_NCTL_CFG, data); 5920 5921 /* ADC Bias Calibration: 5922 * read efuse offset 0x7d to get a 17-bit data. Remove the dummy/fake 5923 * bit (bit3) to rebuild the real 16-bit data. Write the data to the 5924 * ADC ioffset. 5925 */ 5926 ocp_data = r8152_efuse_read(tp, 0x7d); 5927 data = (u16)(((ocp_data & 0x1fff0) >> 1) | (ocp_data & 0x7)); 5928 if (data != 0xffff) 5929 ocp_reg_write(tp, OCP_ADC_IOFFSET, data); 5930 5931 /* ups mode tx-link-pulse timing adjustment: 5932 * rg_saw_cnt = OCP reg 0xC426 Bit[13:0] 5933 * swr_cnt_1ms_ini = 16000000 / rg_saw_cnt 5934 */ 5935 ocp_data = ocp_reg_read(tp, 0xc426); 5936 ocp_data &= 0x3fff; 5937 if (ocp_data) { 5938 u32 swr_cnt_1ms_ini; 5939 5940 swr_cnt_1ms_ini = (16000000 / ocp_data) & SAW_CNT_1MS_MASK; 5941 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG); 5942 ocp_data = (ocp_data & ~SAW_CNT_1MS_MASK) | swr_cnt_1ms_ini; 5943 ocp_write_word(tp, MCU_TYPE_USB, USB_UPS_CFG, ocp_data); 5944 } 5945 5946 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 5947 ocp_data |= PFM_PWM_SWITCH; 5948 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 5949 5950 /* Advnace EEE */ 5951 if (!rtl_phy_patch_request(tp, true, true)) { 5952 data = ocp_reg_read(tp, OCP_POWER_CFG); 5953 data |= EEE_CLKDIV_EN; 5954 ocp_reg_write(tp, OCP_POWER_CFG, data); 5955 tp->ups_info.eee_ckdiv = true; 5956 5957 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 5958 data |= EN_EEE_CMODE | EN_EEE_1000 | EN_10M_CLKDIV; 5959 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 5960 tp->ups_info.eee_cmod_lv = true; 5961 tp->ups_info._10m_ckdiv = true; 5962 tp->ups_info.eee_plloff_giga = true; 5963 5964 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); 5965 ocp_reg_write(tp, OCP_SYSCLK_CFG, clk_div_expo(5)); 5966 tp->ups_info._250m_ckdiv = true; 5967 5968 rtl_phy_patch_request(tp, false, true); 5969 } 5970 5971 if (tp->eee_en) 5972 rtl_eee_enable(tp, true); 5973 5974 r8153_aldps_en(tp, true); 5975 r8152b_enable_fc(tp); 5976 5977 set_bit(PHY_RESET, &tp->flags); 5978} 5979 5980static void r8153c_hw_phy_cfg(struct r8152 *tp) 5981{ 5982 r8153b_hw_phy_cfg(tp); 5983 5984 tp->ups_info.r_tune = true; 5985} 5986 5987static void rtl8153_change_mtu(struct r8152 *tp) 5988{ 5989 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu)); 5990 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); 5991} 5992 5993static void r8153_first_init(struct r8152 *tp) 5994{ 5995 u32 ocp_data; 5996 5997 rxdy_gated_en(tp, true); 5998 r8153_teredo_off(tp); 5999 6000 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 6001 ocp_data &= ~RCR_ACPT_ALL; 6002 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 6003 6004 rtl8152_nic_reset(tp); 6005 rtl_reset_bmu(tp); 6006 6007 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 6008 ocp_data &= ~NOW_IS_OOB; 6009 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 6010 6011 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 6012 ocp_data &= ~MCU_BORW_EN; 6013 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 6014 6015 wait_oob_link_list_ready(tp); 6016 6017 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 6018 ocp_data |= RE_INIT_LL; 6019 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 6020 6021 wait_oob_link_list_ready(tp); 6022 6023 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 6024 6025 rtl8153_change_mtu(tp); 6026 6027 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TCR0); 6028 ocp_data |= TCR0_AUTO_FIFO; 6029 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TCR0, ocp_data); 6030 6031 rtl8152_nic_reset(tp); 6032 6033 /* rx share fifo credit full threshold */ 6034 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_NORMAL); 6035 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); 6036 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); 6037 /* TX share fifo free credit full threshold */ 6038 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, TXFIFO_THR_NORMAL2); 6039} 6040 6041static void r8153_enter_oob(struct r8152 *tp) 6042{ 6043 u32 ocp_data; 6044 6045 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 6046 ocp_data &= ~NOW_IS_OOB; 6047 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 6048 6049 /* RX FIFO settings for OOB */ 6050 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, RXFIFO_THR1_OOB); 6051 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_OOB); 6052 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_OOB); 6053 6054 rtl_disable(tp); 6055 rtl_reset_bmu(tp); 6056 6057 wait_oob_link_list_ready(tp); 6058 6059 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 6060 ocp_data |= RE_INIT_LL; 6061 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 6062 6063 wait_oob_link_list_ready(tp); 6064 6065 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, 1522); 6066 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT); 6067 6068 switch (tp->version) { 6069 case RTL_VER_03: 6070 case RTL_VER_04: 6071 case RTL_VER_05: 6072 case RTL_VER_06: 6073 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG); 6074 ocp_data &= ~TEREDO_WAKE_MASK; 6075 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_CFG, ocp_data); 6076 break; 6077 6078 case RTL_VER_08: 6079 case RTL_VER_09: 6080 case RTL_VER_14: 6081 /* Clear teredo wake event. bit[15:8] is the teredo wakeup 6082 * type. Set it to zero. bits[7:0] are the W1C bits about 6083 * the events. Set them to all 1 to clear them. 6084 */ 6085 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); 6086 break; 6087 6088 default: 6089 break; 6090 } 6091 6092 rtl_rx_vlan_en(tp, true); 6093 6094 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_BDC_CR); 6095 ocp_data |= ALDPS_PROXY_MODE; 6096 ocp_write_word(tp, MCU_TYPE_PLA, PLA_BDC_CR, ocp_data); 6097 6098 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 6099 ocp_data |= NOW_IS_OOB | DIS_MCU_CLROOB; 6100 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 6101 6102 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 6103 ocp_data |= MCU_BORW_EN; 6104 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 6105 6106 rxdy_gated_en(tp, false); 6107 6108 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 6109 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 6110 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 6111} 6112 6113static void rtl8153_disable(struct r8152 *tp) 6114{ 6115 r8153_aldps_en(tp, false); 6116 rtl_disable(tp); 6117 rtl_reset_bmu(tp); 6118 r8153_aldps_en(tp, true); 6119} 6120 6121static u32 fc_pause_on_auto(struct r8152 *tp) 6122{ 6123 return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 6 * 1024); 6124} 6125 6126static u32 fc_pause_off_auto(struct r8152 *tp) 6127{ 6128 return (ALIGN(mtu_to_size(tp->netdev->mtu), 1024) + 14 * 1024); 6129} 6130 6131static void r8156_fc_parameter(struct r8152 *tp) 6132{ 6133 u32 pause_on = tp->fc_pause_on ? tp->fc_pause_on : fc_pause_on_auto(tp); 6134 u32 pause_off = tp->fc_pause_off ? tp->fc_pause_off : fc_pause_off_auto(tp); 6135 6136 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, pause_on / 16); 6137 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, pause_off / 16); 6138} 6139 6140static int rtl8156_enable(struct r8152 *tp) 6141{ 6142 u32 ocp_data; 6143 u16 speed; 6144 6145 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 6146 return -ENODEV; 6147 6148 r8156_fc_parameter(tp); 6149 set_tx_qlen(tp); 6150 rtl_set_eee_plus(tp); 6151 r8153_set_rx_early_timeout(tp); 6152 r8153_set_rx_early_size(tp); 6153 6154 speed = rtl8152_get_speed(tp); 6155 rtl_set_ifg(tp, speed); 6156 6157 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); 6158 if (speed & _2500bps) 6159 ocp_data &= ~IDLE_SPDWN_EN; 6160 else 6161 ocp_data |= IDLE_SPDWN_EN; 6162 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); 6163 6164 if (speed & _1000bps) 6165 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x11); 6166 else if (speed & _500bps) 6167 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS, 0x3d); 6168 6169 if (tp->udev->speed == USB_SPEED_HIGH) { 6170 /* USB 0xb45e[3:0] l1_nyet_hird */ 6171 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL); 6172 ocp_data &= ~0xf; 6173 if (is_flow_control(speed)) 6174 ocp_data |= 0xf; 6175 else 6176 ocp_data |= 0x1; 6177 ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data); 6178 } 6179 6180 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); 6181 ocp_data &= ~FC_PATCH_TASK; 6182 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); 6183 usleep_range(1000, 2000); 6184 ocp_data |= FC_PATCH_TASK; 6185 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); 6186 6187 return rtl_enable(tp); 6188} 6189 6190static void rtl8156_disable(struct r8152 *tp) 6191{ 6192 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, 0); 6193 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, 0); 6194 6195 rtl8153_disable(tp); 6196} 6197 6198static int rtl8156b_enable(struct r8152 *tp) 6199{ 6200 u32 ocp_data; 6201 u16 speed; 6202 6203 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 6204 return -ENODEV; 6205 6206 set_tx_qlen(tp); 6207 rtl_set_eee_plus(tp); 6208 6209 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM); 6210 ocp_data &= ~RX_AGGR_NUM_MASK; 6211 ocp_write_word(tp, MCU_TYPE_USB, USB_RX_AGGR_NUM, ocp_data); 6212 6213 r8153_set_rx_early_timeout(tp); 6214 r8153_set_rx_early_size(tp); 6215 6216 speed = rtl8152_get_speed(tp); 6217 rtl_set_ifg(tp, speed); 6218 6219 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); 6220 if (speed & _2500bps) 6221 ocp_data &= ~IDLE_SPDWN_EN; 6222 else 6223 ocp_data |= IDLE_SPDWN_EN; 6224 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); 6225 6226 if (tp->udev->speed == USB_SPEED_HIGH) { 6227 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_L1_CTRL); 6228 ocp_data &= ~0xf; 6229 if (is_flow_control(speed)) 6230 ocp_data |= 0xf; 6231 else 6232 ocp_data |= 0x1; 6233 ocp_write_word(tp, MCU_TYPE_USB, USB_L1_CTRL, ocp_data); 6234 } 6235 6236 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); 6237 ocp_data &= ~FC_PATCH_TASK; 6238 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); 6239 usleep_range(1000, 2000); 6240 ocp_data |= FC_PATCH_TASK; 6241 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); 6242 6243 return rtl_enable(tp); 6244} 6245 6246static int rtl8152_set_speed(struct r8152 *tp, u8 autoneg, u32 speed, u8 duplex, 6247 u32 advertising) 6248{ 6249 u16 bmcr; 6250 int ret = 0; 6251 6252 if (autoneg == AUTONEG_DISABLE) { 6253 if (duplex != DUPLEX_HALF && duplex != DUPLEX_FULL) 6254 return -EINVAL; 6255 6256 switch (speed) { 6257 case SPEED_10: 6258 bmcr = BMCR_SPEED10; 6259 if (duplex == DUPLEX_FULL) { 6260 bmcr |= BMCR_FULLDPLX; 6261 tp->ups_info.speed_duplex = FORCE_10M_FULL; 6262 } else { 6263 tp->ups_info.speed_duplex = FORCE_10M_HALF; 6264 } 6265 break; 6266 case SPEED_100: 6267 bmcr = BMCR_SPEED100; 6268 if (duplex == DUPLEX_FULL) { 6269 bmcr |= BMCR_FULLDPLX; 6270 tp->ups_info.speed_duplex = FORCE_100M_FULL; 6271 } else { 6272 tp->ups_info.speed_duplex = FORCE_100M_HALF; 6273 } 6274 break; 6275 case SPEED_1000: 6276 if (tp->mii.supports_gmii) { 6277 bmcr = BMCR_SPEED1000 | BMCR_FULLDPLX; 6278 tp->ups_info.speed_duplex = NWAY_1000M_FULL; 6279 break; 6280 } 6281 fallthrough; 6282 default: 6283 ret = -EINVAL; 6284 goto out; 6285 } 6286 6287 if (duplex == DUPLEX_FULL) 6288 tp->mii.full_duplex = 1; 6289 else 6290 tp->mii.full_duplex = 0; 6291 6292 tp->mii.force_media = 1; 6293 } else { 6294 u16 orig, new1; 6295 u32 support; 6296 6297 support = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL | 6298 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL; 6299 6300 if (tp->mii.supports_gmii) { 6301 support |= RTL_ADVERTISED_1000_FULL; 6302 6303 if (tp->support_2500full) 6304 support |= RTL_ADVERTISED_2500_FULL; 6305 } 6306 6307 if (!(advertising & support)) 6308 return -EINVAL; 6309 6310 orig = r8152_mdio_read(tp, MII_ADVERTISE); 6311 new1 = orig & ~(ADVERTISE_10HALF | ADVERTISE_10FULL | 6312 ADVERTISE_100HALF | ADVERTISE_100FULL); 6313 if (advertising & RTL_ADVERTISED_10_HALF) { 6314 new1 |= ADVERTISE_10HALF; 6315 tp->ups_info.speed_duplex = NWAY_10M_HALF; 6316 } 6317 if (advertising & RTL_ADVERTISED_10_FULL) { 6318 new1 |= ADVERTISE_10FULL; 6319 tp->ups_info.speed_duplex = NWAY_10M_FULL; 6320 } 6321 6322 if (advertising & RTL_ADVERTISED_100_HALF) { 6323 new1 |= ADVERTISE_100HALF; 6324 tp->ups_info.speed_duplex = NWAY_100M_HALF; 6325 } 6326 if (advertising & RTL_ADVERTISED_100_FULL) { 6327 new1 |= ADVERTISE_100FULL; 6328 tp->ups_info.speed_duplex = NWAY_100M_FULL; 6329 } 6330 6331 if (orig != new1) { 6332 r8152_mdio_write(tp, MII_ADVERTISE, new1); 6333 tp->mii.advertising = new1; 6334 } 6335 6336 if (tp->mii.supports_gmii) { 6337 orig = r8152_mdio_read(tp, MII_CTRL1000); 6338 new1 = orig & ~(ADVERTISE_1000FULL | 6339 ADVERTISE_1000HALF); 6340 6341 if (advertising & RTL_ADVERTISED_1000_FULL) { 6342 new1 |= ADVERTISE_1000FULL; 6343 tp->ups_info.speed_duplex = NWAY_1000M_FULL; 6344 } 6345 6346 if (orig != new1) 6347 r8152_mdio_write(tp, MII_CTRL1000, new1); 6348 } 6349 6350 if (tp->support_2500full) { 6351 orig = ocp_reg_read(tp, OCP_10GBT_CTRL); 6352 new1 = orig & ~MDIO_AN_10GBT_CTRL_ADV2_5G; 6353 6354 if (advertising & RTL_ADVERTISED_2500_FULL) { 6355 new1 |= MDIO_AN_10GBT_CTRL_ADV2_5G; 6356 tp->ups_info.speed_duplex = NWAY_2500M_FULL; 6357 } 6358 6359 if (orig != new1) 6360 ocp_reg_write(tp, OCP_10GBT_CTRL, new1); 6361 } 6362 6363 bmcr = BMCR_ANENABLE | BMCR_ANRESTART; 6364 6365 tp->mii.force_media = 0; 6366 } 6367 6368 if (test_and_clear_bit(PHY_RESET, &tp->flags)) 6369 bmcr |= BMCR_RESET; 6370 6371 r8152_mdio_write(tp, MII_BMCR, bmcr); 6372 6373 if (bmcr & BMCR_RESET) { 6374 int i; 6375 6376 for (i = 0; i < 50; i++) { 6377 msleep(20); 6378 if ((r8152_mdio_read(tp, MII_BMCR) & BMCR_RESET) == 0) 6379 break; 6380 } 6381 } 6382 6383out: 6384 return ret; 6385} 6386 6387static void rtl8152_up(struct r8152 *tp) 6388{ 6389 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 6390 return; 6391 6392 r8152_aldps_en(tp, false); 6393 r8152b_exit_oob(tp); 6394 r8152_aldps_en(tp, true); 6395} 6396 6397static void rtl8152_down(struct r8152 *tp) 6398{ 6399 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { 6400 rtl_drop_queued_tx(tp); 6401 return; 6402 } 6403 6404 r8152_power_cut_en(tp, false); 6405 r8152_aldps_en(tp, false); 6406 r8152b_enter_oob(tp); 6407 r8152_aldps_en(tp, true); 6408} 6409 6410static void rtl8153_up(struct r8152 *tp) 6411{ 6412 u32 ocp_data; 6413 6414 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 6415 return; 6416 6417 r8153_u1u2en(tp, false); 6418 r8153_u2p3en(tp, false); 6419 r8153_aldps_en(tp, false); 6420 r8153_first_init(tp); 6421 6422 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6); 6423 ocp_data |= LANWAKE_CLR_EN; 6424 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data); 6425 6426 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG); 6427 ocp_data &= ~LANWAKE_PIN; 6428 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data); 6429 6430 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1); 6431 ocp_data &= ~DELAY_PHY_PWR_CHG; 6432 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK1, ocp_data); 6433 6434 r8153_aldps_en(tp, true); 6435 6436 switch (tp->version) { 6437 case RTL_VER_03: 6438 case RTL_VER_04: 6439 break; 6440 case RTL_VER_05: 6441 case RTL_VER_06: 6442 default: 6443 r8153_u2p3en(tp, true); 6444 break; 6445 } 6446 6447 r8153_u1u2en(tp, true); 6448} 6449 6450static void rtl8153_down(struct r8152 *tp) 6451{ 6452 u32 ocp_data; 6453 6454 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { 6455 rtl_drop_queued_tx(tp); 6456 return; 6457 } 6458 6459 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6); 6460 ocp_data &= ~LANWAKE_CLR_EN; 6461 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data); 6462 6463 r8153_u1u2en(tp, false); 6464 r8153_u2p3en(tp, false); 6465 r8153_power_cut_en(tp, false); 6466 r8153_aldps_en(tp, false); 6467 r8153_enter_oob(tp); 6468 r8153_aldps_en(tp, true); 6469} 6470 6471static void rtl8153b_up(struct r8152 *tp) 6472{ 6473 u32 ocp_data; 6474 6475 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 6476 return; 6477 6478 r8153b_u1u2en(tp, false); 6479 r8153_u2p3en(tp, false); 6480 r8153_aldps_en(tp, false); 6481 6482 r8153_first_init(tp); 6483 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B); 6484 6485 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); 6486 ocp_data &= ~PLA_MCU_SPDWN_EN; 6487 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); 6488 6489 r8153_aldps_en(tp, true); 6490 6491 if (tp->udev->speed >= USB_SPEED_SUPER) 6492 r8153b_u1u2en(tp, true); 6493} 6494 6495static void rtl8153b_down(struct r8152 *tp) 6496{ 6497 u32 ocp_data; 6498 6499 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { 6500 rtl_drop_queued_tx(tp); 6501 return; 6502 } 6503 6504 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); 6505 ocp_data |= PLA_MCU_SPDWN_EN; 6506 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); 6507 6508 r8153b_u1u2en(tp, false); 6509 r8153_u2p3en(tp, false); 6510 r8153b_power_cut_en(tp, false); 6511 r8153_aldps_en(tp, false); 6512 r8153_enter_oob(tp); 6513 r8153_aldps_en(tp, true); 6514} 6515 6516static void rtl8153c_change_mtu(struct r8152 *tp) 6517{ 6518 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, mtu_to_size(tp->netdev->mtu)); 6519 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, 10 * 1024 / 64); 6520 6521 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64); 6522 6523 /* Adjust the tx fifo free credit full threshold, otherwise 6524 * the fifo would be too small to send a jumbo frame packet. 6525 */ 6526 if (tp->netdev->mtu < 8000) 6527 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 2048 / 8); 6528 else 6529 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 900 / 8); 6530} 6531 6532static void rtl8153c_up(struct r8152 *tp) 6533{ 6534 u32 ocp_data; 6535 6536 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 6537 return; 6538 6539 r8153b_u1u2en(tp, false); 6540 r8153_u2p3en(tp, false); 6541 r8153_aldps_en(tp, false); 6542 6543 rxdy_gated_en(tp, true); 6544 r8153_teredo_off(tp); 6545 6546 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 6547 ocp_data &= ~RCR_ACPT_ALL; 6548 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 6549 6550 rtl8152_nic_reset(tp); 6551 rtl_reset_bmu(tp); 6552 6553 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 6554 ocp_data &= ~NOW_IS_OOB; 6555 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 6556 6557 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 6558 ocp_data &= ~MCU_BORW_EN; 6559 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 6560 6561 wait_oob_link_list_ready(tp); 6562 6563 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 6564 ocp_data |= RE_INIT_LL; 6565 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 6566 6567 wait_oob_link_list_ready(tp); 6568 6569 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 6570 6571 rtl8153c_change_mtu(tp); 6572 6573 rtl8152_nic_reset(tp); 6574 6575 /* rx share fifo credit full threshold */ 6576 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL0, 0x02); 6577 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 0x08); 6578 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL1, RXFIFO_THR2_NORMAL); 6579 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_CTRL2, RXFIFO_THR3_NORMAL); 6580 6581 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, RX_THR_B); 6582 6583 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 6584 6585 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG34); 6586 ocp_data |= BIT(8); 6587 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG34, ocp_data); 6588 6589 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_NORAML); 6590 6591 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); 6592 ocp_data &= ~PLA_MCU_SPDWN_EN; 6593 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); 6594 6595 r8153_aldps_en(tp, true); 6596 r8153b_u1u2en(tp, true); 6597} 6598 6599static void rtl8156_change_mtu(struct r8152 *tp) 6600{ 6601 u32 rx_max_size = mtu_to_size(tp->netdev->mtu); 6602 6603 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, rx_max_size); 6604 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_JUMBO); 6605 r8156_fc_parameter(tp); 6606 6607 /* TX share fifo free credit full threshold */ 6608 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_CTRL, 512 / 64); 6609 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TXFIFO_FULL, 6610 ALIGN(rx_max_size + sizeof(struct tx_desc), 1024) / 16); 6611} 6612 6613static void rtl8156_up(struct r8152 *tp) 6614{ 6615 u32 ocp_data; 6616 6617 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 6618 return; 6619 6620 r8153b_u1u2en(tp, false); 6621 r8153_u2p3en(tp, false); 6622 r8153_aldps_en(tp, false); 6623 6624 rxdy_gated_en(tp, true); 6625 r8153_teredo_off(tp); 6626 6627 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 6628 ocp_data &= ~RCR_ACPT_ALL; 6629 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 6630 6631 rtl8152_nic_reset(tp); 6632 rtl_reset_bmu(tp); 6633 6634 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 6635 ocp_data &= ~NOW_IS_OOB; 6636 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 6637 6638 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 6639 ocp_data &= ~MCU_BORW_EN; 6640 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 6641 6642 rtl_rx_vlan_en(tp, tp->netdev->features & NETIF_F_HW_VLAN_CTAG_RX); 6643 6644 rtl8156_change_mtu(tp); 6645 6646 switch (tp->version) { 6647 case RTL_TEST_01: 6648 case RTL_VER_10: 6649 case RTL_VER_11: 6650 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG); 6651 ocp_data |= ACT_ODMA; 6652 ocp_write_word(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data); 6653 break; 6654 default: 6655 break; 6656 } 6657 6658 /* share FIFO settings */ 6659 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL); 6660 ocp_data &= ~RXFIFO_FULL_MASK; 6661 ocp_data |= 0x08; 6662 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, ocp_data); 6663 6664 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); 6665 ocp_data &= ~PLA_MCU_SPDWN_EN; 6666 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); 6667 6668 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION); 6669 ocp_data &= ~(RG_PWRDN_EN | ALL_SPEED_OFF); 6670 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, ocp_data); 6671 6672 ocp_write_dword(tp, MCU_TYPE_USB, USB_RX_BUF_TH, 0x00600400); 6673 6674 if (tp->saved_wolopts != __rtl_get_wol(tp)) { 6675 netif_warn(tp, ifup, tp->netdev, "wol setting is changed\n"); 6676 __rtl_set_wol(tp, tp->saved_wolopts); 6677 } 6678 6679 r8153_aldps_en(tp, true); 6680 r8153_u2p3en(tp, true); 6681 6682 if (tp->udev->speed >= USB_SPEED_SUPER) 6683 r8153b_u1u2en(tp, true); 6684} 6685 6686static void rtl8156_down(struct r8152 *tp) 6687{ 6688 u32 ocp_data; 6689 6690 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { 6691 rtl_drop_queued_tx(tp); 6692 return; 6693 } 6694 6695 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); 6696 ocp_data |= PLA_MCU_SPDWN_EN; 6697 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); 6698 6699 r8153b_u1u2en(tp, false); 6700 r8153_u2p3en(tp, false); 6701 r8153b_power_cut_en(tp, false); 6702 r8153_aldps_en(tp, false); 6703 6704 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 6705 ocp_data &= ~NOW_IS_OOB; 6706 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 6707 6708 /* RX FIFO settings for OOB */ 6709 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RXFIFO_FULL, 64 / 16); 6710 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_FULL, 1024 / 16); 6711 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RX_FIFO_EMPTY, 4096 / 16); 6712 6713 rtl_disable(tp); 6714 rtl_reset_bmu(tp); 6715 6716 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RMS, 1522); 6717 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_MTPS, MTPS_DEFAULT); 6718 6719 /* Clear teredo wake event. bit[15:8] is the teredo wakeup 6720 * type. Set it to zero. bits[7:0] are the W1C bits about 6721 * the events. Set them to all 1 to clear them. 6722 */ 6723 ocp_write_word(tp, MCU_TYPE_PLA, PLA_TEREDO_WAKE_BASE, 0x00ff); 6724 6725 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL); 6726 ocp_data |= NOW_IS_OOB; 6727 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_OOB_CTRL, ocp_data); 6728 6729 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7); 6730 ocp_data |= MCU_BORW_EN; 6731 ocp_write_word(tp, MCU_TYPE_PLA, PLA_SFF_STS_7, ocp_data); 6732 6733 rtl_rx_vlan_en(tp, true); 6734 rxdy_gated_en(tp, false); 6735 6736 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 6737 ocp_data |= RCR_APM | RCR_AM | RCR_AB; 6738 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 6739 6740 r8153_aldps_en(tp, true); 6741} 6742 6743static bool rtl8152_in_nway(struct r8152 *tp) 6744{ 6745 u16 nway_state; 6746 6747 ocp_write_word(tp, MCU_TYPE_PLA, PLA_OCP_GPHY_BASE, 0x2000); 6748 tp->ocp_base = 0x2000; 6749 ocp_write_byte(tp, MCU_TYPE_PLA, 0xb014, 0x4c); /* phy state */ 6750 nway_state = ocp_read_word(tp, MCU_TYPE_PLA, 0xb01a); 6751 6752 /* bit 15: TXDIS_STATE, bit 14: ABD_STATE */ 6753 if (nway_state & 0xc000) 6754 return false; 6755 else 6756 return true; 6757} 6758 6759static bool rtl8153_in_nway(struct r8152 *tp) 6760{ 6761 u16 phy_state = ocp_reg_read(tp, OCP_PHY_STATE) & 0xff; 6762 6763 if (phy_state == TXDIS_STATE || phy_state == ABD_STATE) 6764 return false; 6765 else 6766 return true; 6767} 6768 6769static void r8156_mdio_force_mode(struct r8152 *tp) 6770{ 6771 u16 data; 6772 6773 /* Select force mode through 0xa5b4 bit 15 6774 * 0: MDIO force mode 6775 * 1: MMD force mode 6776 */ 6777 data = ocp_reg_read(tp, 0xa5b4); 6778 if (data & BIT(15)) { 6779 data &= ~BIT(15); 6780 ocp_reg_write(tp, 0xa5b4, data); 6781 } 6782} 6783 6784static void set_carrier(struct r8152 *tp) 6785{ 6786 struct net_device *netdev = tp->netdev; 6787 struct napi_struct *napi = &tp->napi; 6788 u16 speed; 6789 6790 speed = rtl8152_get_speed(tp); 6791 6792 if (speed & LINK_STATUS) { 6793 if (!netif_carrier_ok(netdev)) { 6794 tp->rtl_ops.enable(tp); 6795 netif_stop_queue(netdev); 6796 napi_disable(napi); 6797 netif_carrier_on(netdev); 6798 rtl_start_rx(tp); 6799 clear_bit(RTL8152_SET_RX_MODE, &tp->flags); 6800 _rtl8152_set_rx_mode(netdev); 6801 napi_enable(napi); 6802 netif_wake_queue(netdev); 6803 netif_info(tp, link, netdev, "carrier on\n"); 6804 } else if (netif_queue_stopped(netdev) && 6805 skb_queue_len(&tp->tx_queue) < tp->tx_qlen) { 6806 netif_wake_queue(netdev); 6807 } 6808 } else { 6809 if (netif_carrier_ok(netdev)) { 6810 netif_carrier_off(netdev); 6811 tasklet_disable(&tp->tx_tl); 6812 napi_disable(napi); 6813 tp->rtl_ops.disable(tp); 6814 napi_enable(napi); 6815 tasklet_enable(&tp->tx_tl); 6816 netif_info(tp, link, netdev, "carrier off\n"); 6817 } 6818 } 6819} 6820 6821static void rtl_work_func_t(struct work_struct *work) 6822{ 6823 struct r8152 *tp = container_of(work, struct r8152, schedule.work); 6824 6825 /* If the device is unplugged or !netif_running(), the workqueue 6826 * doesn't need to wake the device, and could return directly. 6827 */ 6828 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags) || !netif_running(tp->netdev)) 6829 return; 6830 6831 if (usb_autopm_get_interface(tp->intf) < 0) 6832 return; 6833 6834 if (!test_bit(WORK_ENABLE, &tp->flags)) 6835 goto out1; 6836 6837 if (!mutex_trylock(&tp->control)) { 6838 schedule_delayed_work(&tp->schedule, 0); 6839 goto out1; 6840 } 6841 6842 if (test_and_clear_bit(RTL8152_LINK_CHG, &tp->flags)) 6843 set_carrier(tp); 6844 6845 if (test_and_clear_bit(RTL8152_SET_RX_MODE, &tp->flags)) 6846 _rtl8152_set_rx_mode(tp->netdev); 6847 6848 /* don't schedule tasket before linking */ 6849 if (test_and_clear_bit(SCHEDULE_TASKLET, &tp->flags) && 6850 netif_carrier_ok(tp->netdev)) 6851 tasklet_schedule(&tp->tx_tl); 6852 6853 if (test_and_clear_bit(RX_EPROTO, &tp->flags) && 6854 !list_empty(&tp->rx_done)) 6855 napi_schedule(&tp->napi); 6856 6857 mutex_unlock(&tp->control); 6858 6859out1: 6860 usb_autopm_put_interface(tp->intf); 6861} 6862 6863static void rtl_hw_phy_work_func_t(struct work_struct *work) 6864{ 6865 struct r8152 *tp = container_of(work, struct r8152, hw_phy_work.work); 6866 6867 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 6868 return; 6869 6870 if (usb_autopm_get_interface(tp->intf) < 0) 6871 return; 6872 6873 mutex_lock(&tp->control); 6874 6875 if (rtl8152_request_firmware(tp) == -ENODEV && tp->rtl_fw.retry) { 6876 tp->rtl_fw.retry = false; 6877 tp->rtl_fw.fw = NULL; 6878 6879 /* Delay execution in case request_firmware() is not ready yet. 6880 */ 6881 queue_delayed_work(system_long_wq, &tp->hw_phy_work, HZ * 10); 6882 goto ignore_once; 6883 } 6884 6885 tp->rtl_ops.hw_phy_cfg(tp); 6886 6887 rtl8152_set_speed(tp, tp->autoneg, tp->speed, tp->duplex, 6888 tp->advertising); 6889 6890ignore_once: 6891 mutex_unlock(&tp->control); 6892 6893 usb_autopm_put_interface(tp->intf); 6894} 6895 6896#ifdef CONFIG_PM_SLEEP 6897static int rtl_notifier(struct notifier_block *nb, unsigned long action, 6898 void *data) 6899{ 6900 struct r8152 *tp = container_of(nb, struct r8152, pm_notifier); 6901 6902 switch (action) { 6903 case PM_HIBERNATION_PREPARE: 6904 case PM_SUSPEND_PREPARE: 6905 usb_autopm_get_interface(tp->intf); 6906 break; 6907 6908 case PM_POST_HIBERNATION: 6909 case PM_POST_SUSPEND: 6910 usb_autopm_put_interface(tp->intf); 6911 break; 6912 6913 case PM_POST_RESTORE: 6914 case PM_RESTORE_PREPARE: 6915 default: 6916 break; 6917 } 6918 6919 return NOTIFY_DONE; 6920} 6921#endif 6922 6923static int rtl8152_open(struct net_device *netdev) 6924{ 6925 struct r8152 *tp = netdev_priv(netdev); 6926 int res = 0; 6927 6928 if (work_busy(&tp->hw_phy_work.work) & WORK_BUSY_PENDING) { 6929 cancel_delayed_work_sync(&tp->hw_phy_work); 6930 rtl_hw_phy_work_func_t(&tp->hw_phy_work.work); 6931 } 6932 6933 res = alloc_all_mem(tp); 6934 if (res) 6935 goto out; 6936 6937 res = usb_autopm_get_interface(tp->intf); 6938 if (res < 0) 6939 goto out_free; 6940 6941 mutex_lock(&tp->control); 6942 6943 tp->rtl_ops.up(tp); 6944 6945 netif_carrier_off(netdev); 6946 netif_start_queue(netdev); 6947 set_bit(WORK_ENABLE, &tp->flags); 6948 6949 res = usb_submit_urb(tp->intr_urb, GFP_KERNEL); 6950 if (res) { 6951 if (res == -ENODEV) 6952 netif_device_detach(tp->netdev); 6953 netif_warn(tp, ifup, netdev, "intr_urb submit failed: %d\n", 6954 res); 6955 goto out_unlock; 6956 } 6957 napi_enable(&tp->napi); 6958 tasklet_enable(&tp->tx_tl); 6959 6960 mutex_unlock(&tp->control); 6961 6962 usb_autopm_put_interface(tp->intf); 6963#ifdef CONFIG_PM_SLEEP 6964 tp->pm_notifier.notifier_call = rtl_notifier; 6965 register_pm_notifier(&tp->pm_notifier); 6966#endif 6967 return 0; 6968 6969out_unlock: 6970 mutex_unlock(&tp->control); 6971 usb_autopm_put_interface(tp->intf); 6972out_free: 6973 free_all_mem(tp); 6974out: 6975 return res; 6976} 6977 6978static int rtl8152_close(struct net_device *netdev) 6979{ 6980 struct r8152 *tp = netdev_priv(netdev); 6981 int res = 0; 6982 6983#ifdef CONFIG_PM_SLEEP 6984 unregister_pm_notifier(&tp->pm_notifier); 6985#endif 6986 tasklet_disable(&tp->tx_tl); 6987 clear_bit(WORK_ENABLE, &tp->flags); 6988 usb_kill_urb(tp->intr_urb); 6989 cancel_delayed_work_sync(&tp->schedule); 6990 napi_disable(&tp->napi); 6991 netif_stop_queue(netdev); 6992 6993 res = usb_autopm_get_interface(tp->intf); 6994 if (res < 0 || test_bit(RTL8152_INACCESSIBLE, &tp->flags)) { 6995 rtl_drop_queued_tx(tp); 6996 rtl_stop_rx(tp); 6997 } else { 6998 mutex_lock(&tp->control); 6999 7000 tp->rtl_ops.down(tp); 7001 7002 mutex_unlock(&tp->control); 7003 } 7004 7005 if (!res) 7006 usb_autopm_put_interface(tp->intf); 7007 7008 free_all_mem(tp); 7009 7010 return res; 7011} 7012 7013static void rtl_tally_reset(struct r8152 *tp) 7014{ 7015 u32 ocp_data; 7016 7017 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY); 7018 ocp_data |= TALLY_RESET; 7019 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RSTTALLY, ocp_data); 7020} 7021 7022static void r8152b_init(struct r8152 *tp) 7023{ 7024 u32 ocp_data; 7025 u16 data; 7026 7027 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 7028 return; 7029 7030 data = r8152_mdio_read(tp, MII_BMCR); 7031 if (data & BMCR_PDOWN) { 7032 data &= ~BMCR_PDOWN; 7033 r8152_mdio_write(tp, MII_BMCR, data); 7034 } 7035 7036 r8152_aldps_en(tp, false); 7037 7038 if (tp->version == RTL_VER_01) { 7039 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 7040 ocp_data &= ~LED_MODE_MASK; 7041 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 7042 } 7043 7044 r8152_power_cut_en(tp, false); 7045 7046 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 7047 ocp_data |= TX_10M_IDLE_EN | PFM_PWM_SWITCH; 7048 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 7049 ocp_data = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL); 7050 ocp_data &= ~MCU_CLK_RATIO_MASK; 7051 ocp_data |= MCU_CLK_RATIO | D3_CLK_GATED_EN; 7052 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL, ocp_data); 7053 ocp_data = GPHY_STS_MSK | SPEED_DOWN_MSK | 7054 SPDWN_RXDV_MSK | SPDWN_LINKCHG_MSK; 7055 ocp_write_word(tp, MCU_TYPE_PLA, PLA_GPHY_INTR_IMR, ocp_data); 7056 7057 rtl_tally_reset(tp); 7058 7059 /* enable rx aggregation */ 7060 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 7061 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 7062 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 7063} 7064 7065static void r8153_init(struct r8152 *tp) 7066{ 7067 u32 ocp_data; 7068 u16 data; 7069 int i; 7070 7071 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 7072 return; 7073 7074 r8153_u1u2en(tp, false); 7075 7076 for (i = 0; i < 500; i++) { 7077 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 7078 AUTOLOAD_DONE) 7079 break; 7080 7081 msleep(20); 7082 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 7083 break; 7084 } 7085 7086 data = r8153_phy_status(tp, 0); 7087 7088 if (tp->version == RTL_VER_03 || tp->version == RTL_VER_04 || 7089 tp->version == RTL_VER_05) 7090 ocp_reg_write(tp, OCP_ADC_CFG, CKADSEL_L | ADC_EN | EN_EMI_L); 7091 7092 data = r8152_mdio_read(tp, MII_BMCR); 7093 if (data & BMCR_PDOWN) { 7094 data &= ~BMCR_PDOWN; 7095 r8152_mdio_write(tp, MII_BMCR, data); 7096 } 7097 7098 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 7099 7100 r8153_u2p3en(tp, false); 7101 7102 if (tp->version == RTL_VER_04) { 7103 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2); 7104 ocp_data &= ~pwd_dn_scale_mask; 7105 ocp_data |= pwd_dn_scale(96); 7106 ocp_write_word(tp, MCU_TYPE_USB, USB_SSPHYLINK2, ocp_data); 7107 7108 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_USB2PHY); 7109 ocp_data |= USB2PHY_L1 | USB2PHY_SUSPEND; 7110 ocp_write_byte(tp, MCU_TYPE_USB, USB_USB2PHY, ocp_data); 7111 } else if (tp->version == RTL_VER_05) { 7112 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0); 7113 ocp_data &= ~ECM_ALDPS; 7114 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_DMY_REG0, ocp_data); 7115 7116 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 7117 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 7118 ocp_data &= ~DYNAMIC_BURST; 7119 else 7120 ocp_data |= DYNAMIC_BURST; 7121 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 7122 } else if (tp->version == RTL_VER_06) { 7123 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1); 7124 if (ocp_read_word(tp, MCU_TYPE_USB, USB_BURST_SIZE) == 0) 7125 ocp_data &= ~DYNAMIC_BURST; 7126 else 7127 ocp_data |= DYNAMIC_BURST; 7128 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY1, ocp_data); 7129 7130 r8153_queue_wake(tp, false); 7131 7132 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); 7133 if (rtl8152_get_speed(tp) & LINK_STATUS) 7134 ocp_data |= CUR_LINK_OK; 7135 else 7136 ocp_data &= ~CUR_LINK_OK; 7137 ocp_data |= POLL_LINK_CHG; 7138 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); 7139 } 7140 7141 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2); 7142 ocp_data |= EP4_FULL_FC; 7143 ocp_write_byte(tp, MCU_TYPE_USB, USB_CSR_DUMMY2, ocp_data); 7144 7145 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL); 7146 ocp_data &= ~TIMER11_EN; 7147 ocp_write_word(tp, MCU_TYPE_USB, USB_WDT11_CTRL, ocp_data); 7148 7149 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE); 7150 ocp_data &= ~LED_MODE_MASK; 7151 ocp_write_word(tp, MCU_TYPE_PLA, PLA_LED_FEATURE, ocp_data); 7152 7153 ocp_data = FIFO_EMPTY_1FB | ROK_EXIT_LPM; 7154 if (tp->version == RTL_VER_04 && tp->udev->speed < USB_SPEED_SUPER) 7155 ocp_data |= LPM_TIMER_500MS; 7156 else 7157 ocp_data |= LPM_TIMER_500US; 7158 ocp_write_byte(tp, MCU_TYPE_USB, USB_LPM_CTRL, ocp_data); 7159 7160 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2); 7161 ocp_data &= ~SEN_VAL_MASK; 7162 ocp_data |= SEN_VAL_NORMAL | SEL_RXIDLE; 7163 ocp_write_word(tp, MCU_TYPE_USB, USB_AFE_CTRL2, ocp_data); 7164 7165 ocp_write_word(tp, MCU_TYPE_USB, USB_CONNECT_TIMER, 0x0001); 7166 7167 r8153_power_cut_en(tp, false); 7168 rtl_runtime_suspend_enable(tp, false); 7169 r8153_mac_clk_speed_down(tp, false); 7170 r8153_u1u2en(tp, true); 7171 usb_enable_lpm(tp->udev); 7172 7173 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6); 7174 ocp_data |= LANWAKE_CLR_EN; 7175 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CONFIG6, ocp_data); 7176 7177 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG); 7178 ocp_data &= ~LANWAKE_PIN; 7179 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_LWAKE_CTRL_REG, ocp_data); 7180 7181 /* rx aggregation */ 7182 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 7183 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 7184 if (tp->dell_tb_rx_agg_bug) 7185 ocp_data |= RX_AGG_DISABLE; 7186 7187 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 7188 7189 rtl_tally_reset(tp); 7190 7191 switch (tp->udev->speed) { 7192 case USB_SPEED_SUPER: 7193 case USB_SPEED_SUPER_PLUS: 7194 tp->coalesce = COALESCE_SUPER; 7195 break; 7196 case USB_SPEED_HIGH: 7197 tp->coalesce = COALESCE_HIGH; 7198 break; 7199 default: 7200 tp->coalesce = COALESCE_SLOW; 7201 break; 7202 } 7203} 7204 7205static void r8153b_init(struct r8152 *tp) 7206{ 7207 u32 ocp_data; 7208 u16 data; 7209 int i; 7210 7211 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 7212 return; 7213 7214 r8153b_u1u2en(tp, false); 7215 7216 for (i = 0; i < 500; i++) { 7217 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 7218 AUTOLOAD_DONE) 7219 break; 7220 7221 msleep(20); 7222 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 7223 break; 7224 } 7225 7226 data = r8153_phy_status(tp, 0); 7227 7228 data = r8152_mdio_read(tp, MII_BMCR); 7229 if (data & BMCR_PDOWN) { 7230 data &= ~BMCR_PDOWN; 7231 r8152_mdio_write(tp, MII_BMCR, data); 7232 } 7233 7234 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 7235 7236 r8153_u2p3en(tp, false); 7237 7238 /* MSC timer = 0xfff * 8ms = 32760 ms */ 7239 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); 7240 7241 r8153b_power_cut_en(tp, false); 7242 r8153b_ups_en(tp, false); 7243 r8153_queue_wake(tp, false); 7244 rtl_runtime_suspend_enable(tp, false); 7245 7246 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); 7247 if (rtl8152_get_speed(tp) & LINK_STATUS) 7248 ocp_data |= CUR_LINK_OK; 7249 else 7250 ocp_data &= ~CUR_LINK_OK; 7251 ocp_data |= POLL_LINK_CHG; 7252 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); 7253 7254 if (tp->udev->speed >= USB_SPEED_SUPER) 7255 r8153b_u1u2en(tp, true); 7256 7257 usb_enable_lpm(tp->udev); 7258 7259 /* MAC clock speed down */ 7260 r8153_mac_clk_speed_down(tp, true); 7261 7262 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); 7263 ocp_data &= ~PLA_MCU_SPDWN_EN; 7264 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); 7265 7266 if (tp->version == RTL_VER_09) { 7267 /* Disable Test IO for 32QFN */ 7268 if (ocp_read_byte(tp, MCU_TYPE_PLA, 0xdc00) & BIT(5)) { 7269 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 7270 ocp_data |= TEST_IO_OFF; 7271 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 7272 } 7273 } 7274 7275 set_bit(GREEN_ETHERNET, &tp->flags); 7276 7277 /* rx aggregation */ 7278 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 7279 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 7280 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 7281 7282 rtl_tally_reset(tp); 7283 7284 tp->coalesce = 15000; /* 15 us */ 7285} 7286 7287static void r8153c_init(struct r8152 *tp) 7288{ 7289 u32 ocp_data; 7290 u16 data; 7291 int i; 7292 7293 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 7294 return; 7295 7296 r8153b_u1u2en(tp, false); 7297 7298 /* Disable spi_en */ 7299 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_CRWECR, CRWECR_CONFIG); 7300 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CONFIG5); 7301 ocp_data &= ~BIT(3); 7302 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CONFIG5, ocp_data); 7303 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, 0xcbf0); 7304 ocp_data |= BIT(1); 7305 ocp_write_word(tp, MCU_TYPE_USB, 0xcbf0, ocp_data); 7306 7307 for (i = 0; i < 500; i++) { 7308 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 7309 AUTOLOAD_DONE) 7310 break; 7311 7312 msleep(20); 7313 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 7314 return; 7315 } 7316 7317 data = r8153_phy_status(tp, 0); 7318 7319 data = r8152_mdio_read(tp, MII_BMCR); 7320 if (data & BMCR_PDOWN) { 7321 data &= ~BMCR_PDOWN; 7322 r8152_mdio_write(tp, MII_BMCR, data); 7323 } 7324 7325 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 7326 7327 r8153_u2p3en(tp, false); 7328 7329 /* MSC timer = 0xfff * 8ms = 32760 ms */ 7330 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); 7331 7332 r8153b_power_cut_en(tp, false); 7333 r8153c_ups_en(tp, false); 7334 r8153_queue_wake(tp, false); 7335 rtl_runtime_suspend_enable(tp, false); 7336 7337 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); 7338 if (rtl8152_get_speed(tp) & LINK_STATUS) 7339 ocp_data |= CUR_LINK_OK; 7340 else 7341 ocp_data &= ~CUR_LINK_OK; 7342 7343 ocp_data |= POLL_LINK_CHG; 7344 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); 7345 7346 r8153b_u1u2en(tp, true); 7347 7348 usb_enable_lpm(tp->udev); 7349 7350 /* MAC clock speed down */ 7351 r8153_mac_clk_speed_down(tp, true); 7352 7353 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_MISC_2); 7354 ocp_data &= ~BIT(7); 7355 ocp_write_byte(tp, MCU_TYPE_USB, USB_MISC_2, ocp_data); 7356 7357 set_bit(GREEN_ETHERNET, &tp->flags); 7358 7359 /* rx aggregation */ 7360 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 7361 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 7362 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 7363 7364 rtl_tally_reset(tp); 7365 7366 tp->coalesce = 15000; /* 15 us */ 7367} 7368 7369static void r8156_hw_phy_cfg(struct r8152 *tp) 7370{ 7371 u32 ocp_data; 7372 u16 data; 7373 7374 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 7375 if (ocp_data & PCUT_STATUS) { 7376 ocp_data &= ~PCUT_STATUS; 7377 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 7378 } 7379 7380 data = r8153_phy_status(tp, 0); 7381 switch (data) { 7382 case PHY_STAT_EXT_INIT: 7383 rtl8152_apply_firmware(tp, true); 7384 7385 data = ocp_reg_read(tp, 0xa468); 7386 data &= ~(BIT(3) | BIT(1)); 7387 ocp_reg_write(tp, 0xa468, data); 7388 break; 7389 case PHY_STAT_LAN_ON: 7390 case PHY_STAT_PWRDN: 7391 default: 7392 rtl8152_apply_firmware(tp, false); 7393 break; 7394 } 7395 7396 /* disable ALDPS before updating the PHY parameters */ 7397 r8153_aldps_en(tp, false); 7398 7399 /* disable EEE before updating the PHY parameters */ 7400 rtl_eee_enable(tp, false); 7401 7402 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 7403 WARN_ON_ONCE(data != PHY_STAT_LAN_ON); 7404 7405 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 7406 ocp_data |= PFM_PWM_SWITCH; 7407 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 7408 7409 switch (tp->version) { 7410 case RTL_VER_10: 7411 data = ocp_reg_read(tp, 0xad40); 7412 data &= ~0x3ff; 7413 data |= BIT(7) | BIT(2); 7414 ocp_reg_write(tp, 0xad40, data); 7415 7416 data = ocp_reg_read(tp, 0xad4e); 7417 data |= BIT(4); 7418 ocp_reg_write(tp, 0xad4e, data); 7419 data = ocp_reg_read(tp, 0xad16); 7420 data &= ~0x3ff; 7421 data |= 0x6; 7422 ocp_reg_write(tp, 0xad16, data); 7423 data = ocp_reg_read(tp, 0xad32); 7424 data &= ~0x3f; 7425 data |= 6; 7426 ocp_reg_write(tp, 0xad32, data); 7427 data = ocp_reg_read(tp, 0xac08); 7428 data &= ~(BIT(12) | BIT(8)); 7429 ocp_reg_write(tp, 0xac08, data); 7430 data = ocp_reg_read(tp, 0xac8a); 7431 data |= BIT(12) | BIT(13) | BIT(14); 7432 data &= ~BIT(15); 7433 ocp_reg_write(tp, 0xac8a, data); 7434 data = ocp_reg_read(tp, 0xad18); 7435 data |= BIT(10); 7436 ocp_reg_write(tp, 0xad18, data); 7437 data = ocp_reg_read(tp, 0xad1a); 7438 data |= 0x3ff; 7439 ocp_reg_write(tp, 0xad1a, data); 7440 data = ocp_reg_read(tp, 0xad1c); 7441 data |= 0x3ff; 7442 ocp_reg_write(tp, 0xad1c, data); 7443 7444 data = sram_read(tp, 0x80ea); 7445 data &= ~0xff00; 7446 data |= 0xc400; 7447 sram_write(tp, 0x80ea, data); 7448 data = sram_read(tp, 0x80eb); 7449 data &= ~0x0700; 7450 data |= 0x0300; 7451 sram_write(tp, 0x80eb, data); 7452 data = sram_read(tp, 0x80f8); 7453 data &= ~0xff00; 7454 data |= 0x1c00; 7455 sram_write(tp, 0x80f8, data); 7456 data = sram_read(tp, 0x80f1); 7457 data &= ~0xff00; 7458 data |= 0x3000; 7459 sram_write(tp, 0x80f1, data); 7460 7461 data = sram_read(tp, 0x80fe); 7462 data &= ~0xff00; 7463 data |= 0xa500; 7464 sram_write(tp, 0x80fe, data); 7465 data = sram_read(tp, 0x8102); 7466 data &= ~0xff00; 7467 data |= 0x5000; 7468 sram_write(tp, 0x8102, data); 7469 data = sram_read(tp, 0x8015); 7470 data &= ~0xff00; 7471 data |= 0x3300; 7472 sram_write(tp, 0x8015, data); 7473 data = sram_read(tp, 0x8100); 7474 data &= ~0xff00; 7475 data |= 0x7000; 7476 sram_write(tp, 0x8100, data); 7477 data = sram_read(tp, 0x8014); 7478 data &= ~0xff00; 7479 data |= 0xf000; 7480 sram_write(tp, 0x8014, data); 7481 data = sram_read(tp, 0x8016); 7482 data &= ~0xff00; 7483 data |= 0x6500; 7484 sram_write(tp, 0x8016, data); 7485 data = sram_read(tp, 0x80dc); 7486 data &= ~0xff00; 7487 data |= 0xed00; 7488 sram_write(tp, 0x80dc, data); 7489 data = sram_read(tp, 0x80df); 7490 data |= BIT(8); 7491 sram_write(tp, 0x80df, data); 7492 data = sram_read(tp, 0x80e1); 7493 data &= ~BIT(8); 7494 sram_write(tp, 0x80e1, data); 7495 7496 data = ocp_reg_read(tp, 0xbf06); 7497 data &= ~0x003f; 7498 data |= 0x0038; 7499 ocp_reg_write(tp, 0xbf06, data); 7500 7501 sram_write(tp, 0x819f, 0xddb6); 7502 7503 ocp_reg_write(tp, 0xbc34, 0x5555); 7504 data = ocp_reg_read(tp, 0xbf0a); 7505 data &= ~0x0e00; 7506 data |= 0x0a00; 7507 ocp_reg_write(tp, 0xbf0a, data); 7508 7509 data = ocp_reg_read(tp, 0xbd2c); 7510 data &= ~BIT(13); 7511 ocp_reg_write(tp, 0xbd2c, data); 7512 break; 7513 case RTL_VER_11: 7514 data = ocp_reg_read(tp, 0xad16); 7515 data |= 0x3ff; 7516 ocp_reg_write(tp, 0xad16, data); 7517 data = ocp_reg_read(tp, 0xad32); 7518 data &= ~0x3f; 7519 data |= 6; 7520 ocp_reg_write(tp, 0xad32, data); 7521 data = ocp_reg_read(tp, 0xac08); 7522 data &= ~(BIT(12) | BIT(8)); 7523 ocp_reg_write(tp, 0xac08, data); 7524 data = ocp_reg_read(tp, 0xacc0); 7525 data &= ~0x3; 7526 data |= BIT(1); 7527 ocp_reg_write(tp, 0xacc0, data); 7528 data = ocp_reg_read(tp, 0xad40); 7529 data &= ~0xe7; 7530 data |= BIT(6) | BIT(2); 7531 ocp_reg_write(tp, 0xad40, data); 7532 data = ocp_reg_read(tp, 0xac14); 7533 data &= ~BIT(7); 7534 ocp_reg_write(tp, 0xac14, data); 7535 data = ocp_reg_read(tp, 0xac80); 7536 data &= ~(BIT(8) | BIT(9)); 7537 ocp_reg_write(tp, 0xac80, data); 7538 data = ocp_reg_read(tp, 0xac5e); 7539 data &= ~0x7; 7540 data |= BIT(1); 7541 ocp_reg_write(tp, 0xac5e, data); 7542 ocp_reg_write(tp, 0xad4c, 0x00a8); 7543 ocp_reg_write(tp, 0xac5c, 0x01ff); 7544 data = ocp_reg_read(tp, 0xac8a); 7545 data &= ~0xf0; 7546 data |= BIT(4) | BIT(5); 7547 ocp_reg_write(tp, 0xac8a, data); 7548 ocp_reg_write(tp, 0xb87c, 0x8157); 7549 data = ocp_reg_read(tp, 0xb87e); 7550 data &= ~0xff00; 7551 data |= 0x0500; 7552 ocp_reg_write(tp, 0xb87e, data); 7553 ocp_reg_write(tp, 0xb87c, 0x8159); 7554 data = ocp_reg_read(tp, 0xb87e); 7555 data &= ~0xff00; 7556 data |= 0x0700; 7557 ocp_reg_write(tp, 0xb87e, data); 7558 7559 /* AAGC */ 7560 ocp_reg_write(tp, 0xb87c, 0x80a2); 7561 ocp_reg_write(tp, 0xb87e, 0x0153); 7562 ocp_reg_write(tp, 0xb87c, 0x809c); 7563 ocp_reg_write(tp, 0xb87e, 0x0153); 7564 7565 /* EEE parameter */ 7566 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EEE_TXTWSYS_2P5G, 0x0056); 7567 7568 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_USB_CFG); 7569 ocp_data |= EN_XG_LIP | EN_G_LIP; 7570 ocp_write_word(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data); 7571 7572 sram_write(tp, 0x8257, 0x020f); /* XG PLL */ 7573 sram_write(tp, 0x80ea, 0x7843); /* GIGA Master */ 7574 7575 if (rtl_phy_patch_request(tp, true, true)) 7576 return; 7577 7578 /* Advance EEE */ 7579 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); 7580 ocp_data |= EEE_SPDWN_EN; 7581 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); 7582 7583 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 7584 data &= ~(EN_EEE_100 | EN_EEE_1000); 7585 data |= EN_10M_CLKDIV; 7586 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 7587 tp->ups_info._10m_ckdiv = true; 7588 tp->ups_info.eee_plloff_100 = false; 7589 tp->ups_info.eee_plloff_giga = false; 7590 7591 data = ocp_reg_read(tp, OCP_POWER_CFG); 7592 data &= ~EEE_CLKDIV_EN; 7593 ocp_reg_write(tp, OCP_POWER_CFG, data); 7594 tp->ups_info.eee_ckdiv = false; 7595 7596 ocp_reg_write(tp, OCP_SYSCLK_CFG, 0); 7597 ocp_reg_write(tp, OCP_SYSCLK_CFG, sysclk_div_expo(5)); 7598 tp->ups_info._250m_ckdiv = false; 7599 7600 rtl_phy_patch_request(tp, false, true); 7601 7602 /* enable ADC Ibias Cal */ 7603 data = ocp_reg_read(tp, 0xd068); 7604 data |= BIT(13); 7605 ocp_reg_write(tp, 0xd068, data); 7606 7607 /* enable Thermal Sensor */ 7608 data = sram_read(tp, 0x81a2); 7609 data &= ~BIT(8); 7610 sram_write(tp, 0x81a2, data); 7611 data = ocp_reg_read(tp, 0xb54c); 7612 data &= ~0xff00; 7613 data |= 0xdb00; 7614 ocp_reg_write(tp, 0xb54c, data); 7615 7616 /* Nway 2.5G Lite */ 7617 data = ocp_reg_read(tp, 0xa454); 7618 data &= ~BIT(0); 7619 ocp_reg_write(tp, 0xa454, data); 7620 7621 /* CS DSP solution */ 7622 data = ocp_reg_read(tp, OCP_10GBT_CTRL); 7623 data |= RTL_ADV2_5G_F_R; 7624 ocp_reg_write(tp, OCP_10GBT_CTRL, data); 7625 data = ocp_reg_read(tp, 0xad4e); 7626 data &= ~BIT(4); 7627 ocp_reg_write(tp, 0xad4e, data); 7628 data = ocp_reg_read(tp, 0xa86a); 7629 data &= ~BIT(0); 7630 ocp_reg_write(tp, 0xa86a, data); 7631 7632 /* MDI SWAP */ 7633 if ((ocp_read_word(tp, MCU_TYPE_USB, USB_UPS_CFG) & MID_REVERSE) && 7634 (ocp_reg_read(tp, 0xd068) & BIT(1))) { 7635 u16 swap_a, swap_b; 7636 7637 data = ocp_reg_read(tp, 0xd068); 7638 data &= ~0x1f; 7639 data |= 0x1; /* p0 */ 7640 ocp_reg_write(tp, 0xd068, data); 7641 swap_a = ocp_reg_read(tp, 0xd06a); 7642 data &= ~0x18; 7643 data |= 0x18; /* p3 */ 7644 ocp_reg_write(tp, 0xd068, data); 7645 swap_b = ocp_reg_read(tp, 0xd06a); 7646 data &= ~0x18; /* p0 */ 7647 ocp_reg_write(tp, 0xd068, data); 7648 ocp_reg_write(tp, 0xd06a, 7649 (swap_a & ~0x7ff) | (swap_b & 0x7ff)); 7650 data |= 0x18; /* p3 */ 7651 ocp_reg_write(tp, 0xd068, data); 7652 ocp_reg_write(tp, 0xd06a, 7653 (swap_b & ~0x7ff) | (swap_a & 0x7ff)); 7654 data &= ~0x18; 7655 data |= 0x08; /* p1 */ 7656 ocp_reg_write(tp, 0xd068, data); 7657 swap_a = ocp_reg_read(tp, 0xd06a); 7658 data &= ~0x18; 7659 data |= 0x10; /* p2 */ 7660 ocp_reg_write(tp, 0xd068, data); 7661 swap_b = ocp_reg_read(tp, 0xd06a); 7662 data &= ~0x18; 7663 data |= 0x08; /* p1 */ 7664 ocp_reg_write(tp, 0xd068, data); 7665 ocp_reg_write(tp, 0xd06a, 7666 (swap_a & ~0x7ff) | (swap_b & 0x7ff)); 7667 data &= ~0x18; 7668 data |= 0x10; /* p2 */ 7669 ocp_reg_write(tp, 0xd068, data); 7670 ocp_reg_write(tp, 0xd06a, 7671 (swap_b & ~0x7ff) | (swap_a & 0x7ff)); 7672 swap_a = ocp_reg_read(tp, 0xbd5a); 7673 swap_b = ocp_reg_read(tp, 0xbd5c); 7674 ocp_reg_write(tp, 0xbd5a, (swap_a & ~0x1f1f) | 7675 ((swap_b & 0x1f) << 8) | 7676 ((swap_b >> 8) & 0x1f)); 7677 ocp_reg_write(tp, 0xbd5c, (swap_b & ~0x1f1f) | 7678 ((swap_a & 0x1f) << 8) | 7679 ((swap_a >> 8) & 0x1f)); 7680 swap_a = ocp_reg_read(tp, 0xbc18); 7681 swap_b = ocp_reg_read(tp, 0xbc1a); 7682 ocp_reg_write(tp, 0xbc18, (swap_a & ~0x1f1f) | 7683 ((swap_b & 0x1f) << 8) | 7684 ((swap_b >> 8) & 0x1f)); 7685 ocp_reg_write(tp, 0xbc1a, (swap_b & ~0x1f1f) | 7686 ((swap_a & 0x1f) << 8) | 7687 ((swap_a >> 8) & 0x1f)); 7688 } 7689 7690 /* Notify the MAC when the speed is changed to force mode. */ 7691 data = ocp_reg_read(tp, OCP_INTR_EN); 7692 data |= INTR_SPEED_FORCE; 7693 ocp_reg_write(tp, OCP_INTR_EN, data); 7694 break; 7695 default: 7696 break; 7697 } 7698 7699 rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); 7700 7701 data = ocp_reg_read(tp, 0xa428); 7702 data &= ~BIT(9); 7703 ocp_reg_write(tp, 0xa428, data); 7704 data = ocp_reg_read(tp, 0xa5ea); 7705 data &= ~BIT(0); 7706 ocp_reg_write(tp, 0xa5ea, data); 7707 tp->ups_info.lite_mode = 0; 7708 7709 if (tp->eee_en) 7710 rtl_eee_enable(tp, true); 7711 7712 r8153_aldps_en(tp, true); 7713 r8152b_enable_fc(tp); 7714 r8153_u2p3en(tp, true); 7715 7716 set_bit(PHY_RESET, &tp->flags); 7717} 7718 7719static void r8156b_hw_phy_cfg(struct r8152 *tp) 7720{ 7721 u32 ocp_data; 7722 u16 data; 7723 7724 switch (tp->version) { 7725 case RTL_VER_12: 7726 ocp_reg_write(tp, 0xbf86, 0x9000); 7727 data = ocp_reg_read(tp, 0xc402); 7728 data |= BIT(10); 7729 ocp_reg_write(tp, 0xc402, data); 7730 data &= ~BIT(10); 7731 ocp_reg_write(tp, 0xc402, data); 7732 ocp_reg_write(tp, 0xbd86, 0x1010); 7733 ocp_reg_write(tp, 0xbd88, 0x1010); 7734 data = ocp_reg_read(tp, 0xbd4e); 7735 data &= ~(BIT(10) | BIT(11)); 7736 data |= BIT(11); 7737 ocp_reg_write(tp, 0xbd4e, data); 7738 data = ocp_reg_read(tp, 0xbf46); 7739 data &= ~0xf00; 7740 data |= 0x700; 7741 ocp_reg_write(tp, 0xbf46, data); 7742 break; 7743 case RTL_VER_13: 7744 case RTL_VER_15: 7745 r8156b_wait_loading_flash(tp); 7746 break; 7747 default: 7748 break; 7749 } 7750 7751 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_MISC_0); 7752 if (ocp_data & PCUT_STATUS) { 7753 ocp_data &= ~PCUT_STATUS; 7754 ocp_write_word(tp, MCU_TYPE_USB, USB_MISC_0, ocp_data); 7755 } 7756 7757 data = r8153_phy_status(tp, 0); 7758 switch (data) { 7759 case PHY_STAT_EXT_INIT: 7760 rtl8152_apply_firmware(tp, true); 7761 7762 data = ocp_reg_read(tp, 0xa466); 7763 data &= ~BIT(0); 7764 ocp_reg_write(tp, 0xa466, data); 7765 7766 data = ocp_reg_read(tp, 0xa468); 7767 data &= ~(BIT(3) | BIT(1)); 7768 ocp_reg_write(tp, 0xa468, data); 7769 break; 7770 case PHY_STAT_LAN_ON: 7771 case PHY_STAT_PWRDN: 7772 default: 7773 rtl8152_apply_firmware(tp, false); 7774 break; 7775 } 7776 7777 data = r8152_mdio_read(tp, MII_BMCR); 7778 if (data & BMCR_PDOWN) { 7779 data &= ~BMCR_PDOWN; 7780 r8152_mdio_write(tp, MII_BMCR, data); 7781 } 7782 7783 /* disable ALDPS before updating the PHY parameters */ 7784 r8153_aldps_en(tp, false); 7785 7786 /* disable EEE before updating the PHY parameters */ 7787 rtl_eee_enable(tp, false); 7788 7789 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 7790 WARN_ON_ONCE(data != PHY_STAT_LAN_ON); 7791 7792 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR); 7793 ocp_data |= PFM_PWM_SWITCH; 7794 ocp_write_word(tp, MCU_TYPE_PLA, PLA_PHY_PWR, ocp_data); 7795 7796 switch (tp->version) { 7797 case RTL_VER_12: 7798 data = ocp_reg_read(tp, 0xbc08); 7799 data |= BIT(3) | BIT(2); 7800 ocp_reg_write(tp, 0xbc08, data); 7801 7802 data = sram_read(tp, 0x8fff); 7803 data &= ~0xff00; 7804 data |= 0x0400; 7805 sram_write(tp, 0x8fff, data); 7806 7807 data = ocp_reg_read(tp, 0xacda); 7808 data |= 0xff00; 7809 ocp_reg_write(tp, 0xacda, data); 7810 data = ocp_reg_read(tp, 0xacde); 7811 data |= 0xf000; 7812 ocp_reg_write(tp, 0xacde, data); 7813 ocp_reg_write(tp, 0xac8c, 0x0ffc); 7814 ocp_reg_write(tp, 0xac46, 0xb7b4); 7815 ocp_reg_write(tp, 0xac50, 0x0fbc); 7816 ocp_reg_write(tp, 0xac3c, 0x9240); 7817 ocp_reg_write(tp, 0xac4e, 0x0db4); 7818 ocp_reg_write(tp, 0xacc6, 0x0707); 7819 ocp_reg_write(tp, 0xacc8, 0xa0d3); 7820 ocp_reg_write(tp, 0xad08, 0x0007); 7821 7822 ocp_reg_write(tp, 0xb87c, 0x8560); 7823 ocp_reg_write(tp, 0xb87e, 0x19cc); 7824 ocp_reg_write(tp, 0xb87c, 0x8562); 7825 ocp_reg_write(tp, 0xb87e, 0x19cc); 7826 ocp_reg_write(tp, 0xb87c, 0x8564); 7827 ocp_reg_write(tp, 0xb87e, 0x19cc); 7828 ocp_reg_write(tp, 0xb87c, 0x8566); 7829 ocp_reg_write(tp, 0xb87e, 0x147d); 7830 ocp_reg_write(tp, 0xb87c, 0x8568); 7831 ocp_reg_write(tp, 0xb87e, 0x147d); 7832 ocp_reg_write(tp, 0xb87c, 0x856a); 7833 ocp_reg_write(tp, 0xb87e, 0x147d); 7834 ocp_reg_write(tp, 0xb87c, 0x8ffe); 7835 ocp_reg_write(tp, 0xb87e, 0x0907); 7836 ocp_reg_write(tp, 0xb87c, 0x80d6); 7837 ocp_reg_write(tp, 0xb87e, 0x2801); 7838 ocp_reg_write(tp, 0xb87c, 0x80f2); 7839 ocp_reg_write(tp, 0xb87e, 0x2801); 7840 ocp_reg_write(tp, 0xb87c, 0x80f4); 7841 ocp_reg_write(tp, 0xb87e, 0x6077); 7842 ocp_reg_write(tp, 0xb506, 0x01e7); 7843 7844 ocp_reg_write(tp, 0xb87c, 0x8013); 7845 ocp_reg_write(tp, 0xb87e, 0x0700); 7846 ocp_reg_write(tp, 0xb87c, 0x8fb9); 7847 ocp_reg_write(tp, 0xb87e, 0x2801); 7848 ocp_reg_write(tp, 0xb87c, 0x8fba); 7849 ocp_reg_write(tp, 0xb87e, 0x0100); 7850 ocp_reg_write(tp, 0xb87c, 0x8fbc); 7851 ocp_reg_write(tp, 0xb87e, 0x1900); 7852 ocp_reg_write(tp, 0xb87c, 0x8fbe); 7853 ocp_reg_write(tp, 0xb87e, 0xe100); 7854 ocp_reg_write(tp, 0xb87c, 0x8fc0); 7855 ocp_reg_write(tp, 0xb87e, 0x0800); 7856 ocp_reg_write(tp, 0xb87c, 0x8fc2); 7857 ocp_reg_write(tp, 0xb87e, 0xe500); 7858 ocp_reg_write(tp, 0xb87c, 0x8fc4); 7859 ocp_reg_write(tp, 0xb87e, 0x0f00); 7860 ocp_reg_write(tp, 0xb87c, 0x8fc6); 7861 ocp_reg_write(tp, 0xb87e, 0xf100); 7862 ocp_reg_write(tp, 0xb87c, 0x8fc8); 7863 ocp_reg_write(tp, 0xb87e, 0x0400); 7864 ocp_reg_write(tp, 0xb87c, 0x8fca); 7865 ocp_reg_write(tp, 0xb87e, 0xf300); 7866 ocp_reg_write(tp, 0xb87c, 0x8fcc); 7867 ocp_reg_write(tp, 0xb87e, 0xfd00); 7868 ocp_reg_write(tp, 0xb87c, 0x8fce); 7869 ocp_reg_write(tp, 0xb87e, 0xff00); 7870 ocp_reg_write(tp, 0xb87c, 0x8fd0); 7871 ocp_reg_write(tp, 0xb87e, 0xfb00); 7872 ocp_reg_write(tp, 0xb87c, 0x8fd2); 7873 ocp_reg_write(tp, 0xb87e, 0x0100); 7874 ocp_reg_write(tp, 0xb87c, 0x8fd4); 7875 ocp_reg_write(tp, 0xb87e, 0xf400); 7876 ocp_reg_write(tp, 0xb87c, 0x8fd6); 7877 ocp_reg_write(tp, 0xb87e, 0xff00); 7878 ocp_reg_write(tp, 0xb87c, 0x8fd8); 7879 ocp_reg_write(tp, 0xb87e, 0xf600); 7880 7881 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG); 7882 ocp_data |= EN_XG_LIP | EN_G_LIP; 7883 ocp_write_byte(tp, MCU_TYPE_PLA, PLA_USB_CFG, ocp_data); 7884 ocp_reg_write(tp, 0xb87c, 0x813d); 7885 ocp_reg_write(tp, 0xb87e, 0x390e); 7886 ocp_reg_write(tp, 0xb87c, 0x814f); 7887 ocp_reg_write(tp, 0xb87e, 0x790e); 7888 ocp_reg_write(tp, 0xb87c, 0x80b0); 7889 ocp_reg_write(tp, 0xb87e, 0x0f31); 7890 data = ocp_reg_read(tp, 0xbf4c); 7891 data |= BIT(1); 7892 ocp_reg_write(tp, 0xbf4c, data); 7893 data = ocp_reg_read(tp, 0xbcca); 7894 data |= BIT(9) | BIT(8); 7895 ocp_reg_write(tp, 0xbcca, data); 7896 ocp_reg_write(tp, 0xb87c, 0x8141); 7897 ocp_reg_write(tp, 0xb87e, 0x320e); 7898 ocp_reg_write(tp, 0xb87c, 0x8153); 7899 ocp_reg_write(tp, 0xb87e, 0x720e); 7900 ocp_reg_write(tp, 0xb87c, 0x8529); 7901 ocp_reg_write(tp, 0xb87e, 0x050e); 7902 data = ocp_reg_read(tp, OCP_EEE_CFG); 7903 data &= ~CTAP_SHORT_EN; 7904 ocp_reg_write(tp, OCP_EEE_CFG, data); 7905 7906 sram_write(tp, 0x816c, 0xc4a0); 7907 sram_write(tp, 0x8170, 0xc4a0); 7908 sram_write(tp, 0x8174, 0x04a0); 7909 sram_write(tp, 0x8178, 0x04a0); 7910 sram_write(tp, 0x817c, 0x0719); 7911 sram_write(tp, 0x8ff4, 0x0400); 7912 sram_write(tp, 0x8ff1, 0x0404); 7913 7914 ocp_reg_write(tp, 0xbf4a, 0x001b); 7915 ocp_reg_write(tp, 0xb87c, 0x8033); 7916 ocp_reg_write(tp, 0xb87e, 0x7c13); 7917 ocp_reg_write(tp, 0xb87c, 0x8037); 7918 ocp_reg_write(tp, 0xb87e, 0x7c13); 7919 ocp_reg_write(tp, 0xb87c, 0x803b); 7920 ocp_reg_write(tp, 0xb87e, 0xfc32); 7921 ocp_reg_write(tp, 0xb87c, 0x803f); 7922 ocp_reg_write(tp, 0xb87e, 0x7c13); 7923 ocp_reg_write(tp, 0xb87c, 0x8043); 7924 ocp_reg_write(tp, 0xb87e, 0x7c13); 7925 ocp_reg_write(tp, 0xb87c, 0x8047); 7926 ocp_reg_write(tp, 0xb87e, 0x7c13); 7927 7928 ocp_reg_write(tp, 0xb87c, 0x8145); 7929 ocp_reg_write(tp, 0xb87e, 0x370e); 7930 ocp_reg_write(tp, 0xb87c, 0x8157); 7931 ocp_reg_write(tp, 0xb87e, 0x770e); 7932 ocp_reg_write(tp, 0xb87c, 0x8169); 7933 ocp_reg_write(tp, 0xb87e, 0x0d0a); 7934 ocp_reg_write(tp, 0xb87c, 0x817b); 7935 ocp_reg_write(tp, 0xb87e, 0x1d0a); 7936 7937 data = sram_read(tp, 0x8217); 7938 data &= ~0xff00; 7939 data |= 0x5000; 7940 sram_write(tp, 0x8217, data); 7941 data = sram_read(tp, 0x821a); 7942 data &= ~0xff00; 7943 data |= 0x5000; 7944 sram_write(tp, 0x821a, data); 7945 sram_write(tp, 0x80da, 0x0403); 7946 data = sram_read(tp, 0x80dc); 7947 data &= ~0xff00; 7948 data |= 0x1000; 7949 sram_write(tp, 0x80dc, data); 7950 sram_write(tp, 0x80b3, 0x0384); 7951 sram_write(tp, 0x80b7, 0x2007); 7952 data = sram_read(tp, 0x80ba); 7953 data &= ~0xff00; 7954 data |= 0x6c00; 7955 sram_write(tp, 0x80ba, data); 7956 sram_write(tp, 0x80b5, 0xf009); 7957 data = sram_read(tp, 0x80bd); 7958 data &= ~0xff00; 7959 data |= 0x9f00; 7960 sram_write(tp, 0x80bd, data); 7961 sram_write(tp, 0x80c7, 0xf083); 7962 sram_write(tp, 0x80dd, 0x03f0); 7963 data = sram_read(tp, 0x80df); 7964 data &= ~0xff00; 7965 data |= 0x1000; 7966 sram_write(tp, 0x80df, data); 7967 sram_write(tp, 0x80cb, 0x2007); 7968 data = sram_read(tp, 0x80ce); 7969 data &= ~0xff00; 7970 data |= 0x6c00; 7971 sram_write(tp, 0x80ce, data); 7972 sram_write(tp, 0x80c9, 0x8009); 7973 data = sram_read(tp, 0x80d1); 7974 data &= ~0xff00; 7975 data |= 0x8000; 7976 sram_write(tp, 0x80d1, data); 7977 sram_write(tp, 0x80a3, 0x200a); 7978 sram_write(tp, 0x80a5, 0xf0ad); 7979 sram_write(tp, 0x809f, 0x6073); 7980 sram_write(tp, 0x80a1, 0x000b); 7981 data = sram_read(tp, 0x80a9); 7982 data &= ~0xff00; 7983 data |= 0xc000; 7984 sram_write(tp, 0x80a9, data); 7985 7986 if (rtl_phy_patch_request(tp, true, true)) 7987 return; 7988 7989 data = ocp_reg_read(tp, 0xb896); 7990 data &= ~BIT(0); 7991 ocp_reg_write(tp, 0xb896, data); 7992 data = ocp_reg_read(tp, 0xb892); 7993 data &= ~0xff00; 7994 ocp_reg_write(tp, 0xb892, data); 7995 ocp_reg_write(tp, 0xb88e, 0xc23e); 7996 ocp_reg_write(tp, 0xb890, 0x0000); 7997 ocp_reg_write(tp, 0xb88e, 0xc240); 7998 ocp_reg_write(tp, 0xb890, 0x0103); 7999 ocp_reg_write(tp, 0xb88e, 0xc242); 8000 ocp_reg_write(tp, 0xb890, 0x0507); 8001 ocp_reg_write(tp, 0xb88e, 0xc244); 8002 ocp_reg_write(tp, 0xb890, 0x090b); 8003 ocp_reg_write(tp, 0xb88e, 0xc246); 8004 ocp_reg_write(tp, 0xb890, 0x0c0e); 8005 ocp_reg_write(tp, 0xb88e, 0xc248); 8006 ocp_reg_write(tp, 0xb890, 0x1012); 8007 ocp_reg_write(tp, 0xb88e, 0xc24a); 8008 ocp_reg_write(tp, 0xb890, 0x1416); 8009 data = ocp_reg_read(tp, 0xb896); 8010 data |= BIT(0); 8011 ocp_reg_write(tp, 0xb896, data); 8012 8013 rtl_phy_patch_request(tp, false, true); 8014 8015 data = ocp_reg_read(tp, 0xa86a); 8016 data |= BIT(0); 8017 ocp_reg_write(tp, 0xa86a, data); 8018 data = ocp_reg_read(tp, 0xa6f0); 8019 data |= BIT(0); 8020 ocp_reg_write(tp, 0xa6f0, data); 8021 8022 ocp_reg_write(tp, 0xbfa0, 0xd70d); 8023 ocp_reg_write(tp, 0xbfa2, 0x4100); 8024 ocp_reg_write(tp, 0xbfa4, 0xe868); 8025 ocp_reg_write(tp, 0xbfa6, 0xdc59); 8026 ocp_reg_write(tp, 0xb54c, 0x3c18); 8027 data = ocp_reg_read(tp, 0xbfa4); 8028 data &= ~BIT(5); 8029 ocp_reg_write(tp, 0xbfa4, data); 8030 data = sram_read(tp, 0x817d); 8031 data |= BIT(12); 8032 sram_write(tp, 0x817d, data); 8033 break; 8034 case RTL_VER_13: 8035 /* 2.5G INRX */ 8036 data = ocp_reg_read(tp, 0xac46); 8037 data &= ~0x00f0; 8038 data |= 0x0090; 8039 ocp_reg_write(tp, 0xac46, data); 8040 data = ocp_reg_read(tp, 0xad30); 8041 data &= ~0x0003; 8042 data |= 0x0001; 8043 ocp_reg_write(tp, 0xad30, data); 8044 fallthrough; 8045 case RTL_VER_15: 8046 /* EEE parameter */ 8047 ocp_reg_write(tp, 0xb87c, 0x80f5); 8048 ocp_reg_write(tp, 0xb87e, 0x760e); 8049 ocp_reg_write(tp, 0xb87c, 0x8107); 8050 ocp_reg_write(tp, 0xb87e, 0x360e); 8051 ocp_reg_write(tp, 0xb87c, 0x8551); 8052 data = ocp_reg_read(tp, 0xb87e); 8053 data &= ~0xff00; 8054 data |= 0x0800; 8055 ocp_reg_write(tp, 0xb87e, data); 8056 8057 /* ADC_PGA parameter */ 8058 data = ocp_reg_read(tp, 0xbf00); 8059 data &= ~0xe000; 8060 data |= 0xa000; 8061 ocp_reg_write(tp, 0xbf00, data); 8062 data = ocp_reg_read(tp, 0xbf46); 8063 data &= ~0x0f00; 8064 data |= 0x0300; 8065 ocp_reg_write(tp, 0xbf46, data); 8066 8067 /* Green Table-PGA, 1G full viterbi */ 8068 sram_write(tp, 0x8044, 0x2417); 8069 sram_write(tp, 0x804a, 0x2417); 8070 sram_write(tp, 0x8050, 0x2417); 8071 sram_write(tp, 0x8056, 0x2417); 8072 sram_write(tp, 0x805c, 0x2417); 8073 sram_write(tp, 0x8062, 0x2417); 8074 sram_write(tp, 0x8068, 0x2417); 8075 sram_write(tp, 0x806e, 0x2417); 8076 sram_write(tp, 0x8074, 0x2417); 8077 sram_write(tp, 0x807a, 0x2417); 8078 8079 /* XG PLL */ 8080 data = ocp_reg_read(tp, 0xbf84); 8081 data &= ~0xe000; 8082 data |= 0xa000; 8083 ocp_reg_write(tp, 0xbf84, data); 8084 break; 8085 default: 8086 break; 8087 } 8088 8089 /* Notify the MAC when the speed is changed to force mode. */ 8090 data = ocp_reg_read(tp, OCP_INTR_EN); 8091 data |= INTR_SPEED_FORCE; 8092 ocp_reg_write(tp, OCP_INTR_EN, data); 8093 8094 if (rtl_phy_patch_request(tp, true, true)) 8095 return; 8096 8097 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4); 8098 ocp_data |= EEE_SPDWN_EN; 8099 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL4, ocp_data); 8100 8101 data = ocp_reg_read(tp, OCP_DOWN_SPEED); 8102 data &= ~(EN_EEE_100 | EN_EEE_1000); 8103 data |= EN_10M_CLKDIV; 8104 ocp_reg_write(tp, OCP_DOWN_SPEED, data); 8105 tp->ups_info._10m_ckdiv = true; 8106 tp->ups_info.eee_plloff_100 = false; 8107 tp->ups_info.eee_plloff_giga = false; 8108 8109 data = ocp_reg_read(tp, OCP_POWER_CFG); 8110 data &= ~EEE_CLKDIV_EN; 8111 ocp_reg_write(tp, OCP_POWER_CFG, data); 8112 tp->ups_info.eee_ckdiv = false; 8113 8114 rtl_phy_patch_request(tp, false, true); 8115 8116 rtl_green_en(tp, test_bit(GREEN_ETHERNET, &tp->flags)); 8117 8118 data = ocp_reg_read(tp, 0xa428); 8119 data &= ~BIT(9); 8120 ocp_reg_write(tp, 0xa428, data); 8121 data = ocp_reg_read(tp, 0xa5ea); 8122 data &= ~BIT(0); 8123 ocp_reg_write(tp, 0xa5ea, data); 8124 tp->ups_info.lite_mode = 0; 8125 8126 if (tp->eee_en) 8127 rtl_eee_enable(tp, true); 8128 8129 r8153_aldps_en(tp, true); 8130 r8152b_enable_fc(tp); 8131 r8153_u2p3en(tp, true); 8132 8133 set_bit(PHY_RESET, &tp->flags); 8134} 8135 8136static void r8156_init(struct r8152 *tp) 8137{ 8138 u32 ocp_data; 8139 u16 data; 8140 int i; 8141 8142 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 8143 return; 8144 8145 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP); 8146 ocp_data &= ~EN_ALL_SPEED; 8147 ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data); 8148 8149 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0); 8150 8151 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION); 8152 ocp_data |= BYPASS_MAC_RESET; 8153 ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data); 8154 8155 r8153b_u1u2en(tp, false); 8156 8157 for (i = 0; i < 500; i++) { 8158 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 8159 AUTOLOAD_DONE) 8160 break; 8161 8162 msleep(20); 8163 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 8164 return; 8165 } 8166 8167 data = r8153_phy_status(tp, 0); 8168 if (data == PHY_STAT_EXT_INIT) { 8169 data = ocp_reg_read(tp, 0xa468); 8170 data &= ~(BIT(3) | BIT(1)); 8171 ocp_reg_write(tp, 0xa468, data); 8172 } 8173 8174 data = r8152_mdio_read(tp, MII_BMCR); 8175 if (data & BMCR_PDOWN) { 8176 data &= ~BMCR_PDOWN; 8177 r8152_mdio_write(tp, MII_BMCR, data); 8178 } 8179 8180 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 8181 WARN_ON_ONCE(data != PHY_STAT_LAN_ON); 8182 8183 r8153_u2p3en(tp, false); 8184 8185 /* MSC timer = 0xfff * 8ms = 32760 ms */ 8186 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); 8187 8188 /* U1/U2/L1 idle timer. 500 us */ 8189 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); 8190 8191 r8153b_power_cut_en(tp, false); 8192 r8156_ups_en(tp, false); 8193 r8153_queue_wake(tp, false); 8194 rtl_runtime_suspend_enable(tp, false); 8195 8196 if (tp->udev->speed >= USB_SPEED_SUPER) 8197 r8153b_u1u2en(tp, true); 8198 8199 usb_enable_lpm(tp->udev); 8200 8201 r8156_mac_clk_spd(tp, true); 8202 8203 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); 8204 ocp_data &= ~PLA_MCU_SPDWN_EN; 8205 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); 8206 8207 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); 8208 if (rtl8152_get_speed(tp) & LINK_STATUS) 8209 ocp_data |= CUR_LINK_OK; 8210 else 8211 ocp_data &= ~CUR_LINK_OK; 8212 ocp_data |= POLL_LINK_CHG; 8213 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); 8214 8215 set_bit(GREEN_ETHERNET, &tp->flags); 8216 8217 /* rx aggregation */ 8218 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 8219 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 8220 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 8221 8222 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG); 8223 ocp_data |= ACT_ODMA; 8224 ocp_write_byte(tp, MCU_TYPE_USB, USB_BMU_CONFIG, ocp_data); 8225 8226 r8156_mdio_force_mode(tp); 8227 rtl_tally_reset(tp); 8228 8229 tp->coalesce = 15000; /* 15 us */ 8230} 8231 8232static void r8156b_init(struct r8152 *tp) 8233{ 8234 u32 ocp_data; 8235 u16 data; 8236 int i; 8237 8238 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 8239 return; 8240 8241 ocp_data = ocp_read_byte(tp, MCU_TYPE_USB, USB_ECM_OP); 8242 ocp_data &= ~EN_ALL_SPEED; 8243 ocp_write_byte(tp, MCU_TYPE_USB, USB_ECM_OP, ocp_data); 8244 8245 ocp_write_word(tp, MCU_TYPE_USB, USB_SPEED_OPTION, 0); 8246 8247 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_ECM_OPTION); 8248 ocp_data |= BYPASS_MAC_RESET; 8249 ocp_write_word(tp, MCU_TYPE_USB, USB_ECM_OPTION, ocp_data); 8250 8251 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL); 8252 ocp_data |= RX_DETECT8; 8253 ocp_write_word(tp, MCU_TYPE_USB, USB_U2P3_CTRL, ocp_data); 8254 8255 r8153b_u1u2en(tp, false); 8256 8257 switch (tp->version) { 8258 case RTL_VER_13: 8259 case RTL_VER_15: 8260 r8156b_wait_loading_flash(tp); 8261 break; 8262 default: 8263 break; 8264 } 8265 8266 for (i = 0; i < 500; i++) { 8267 if (ocp_read_word(tp, MCU_TYPE_PLA, PLA_BOOT_CTRL) & 8268 AUTOLOAD_DONE) 8269 break; 8270 8271 msleep(20); 8272 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 8273 return; 8274 } 8275 8276 data = r8153_phy_status(tp, 0); 8277 if (data == PHY_STAT_EXT_INIT) { 8278 data = ocp_reg_read(tp, 0xa468); 8279 data &= ~(BIT(3) | BIT(1)); 8280 ocp_reg_write(tp, 0xa468, data); 8281 8282 data = ocp_reg_read(tp, 0xa466); 8283 data &= ~BIT(0); 8284 ocp_reg_write(tp, 0xa466, data); 8285 } 8286 8287 data = r8152_mdio_read(tp, MII_BMCR); 8288 if (data & BMCR_PDOWN) { 8289 data &= ~BMCR_PDOWN; 8290 r8152_mdio_write(tp, MII_BMCR, data); 8291 } 8292 8293 data = r8153_phy_status(tp, PHY_STAT_LAN_ON); 8294 8295 r8153_u2p3en(tp, false); 8296 8297 /* MSC timer = 0xfff * 8ms = 32760 ms */ 8298 ocp_write_word(tp, MCU_TYPE_USB, USB_MSC_TIMER, 0x0fff); 8299 8300 /* U1/U2/L1 idle timer. 500 us */ 8301 ocp_write_word(tp, MCU_TYPE_USB, USB_U1U2_TIMER, 500); 8302 8303 r8153b_power_cut_en(tp, false); 8304 r8156_ups_en(tp, false); 8305 r8153_queue_wake(tp, false); 8306 rtl_runtime_suspend_enable(tp, false); 8307 8308 if (tp->udev->speed >= USB_SPEED_SUPER) 8309 r8153b_u1u2en(tp, true); 8310 8311 usb_enable_lpm(tp->udev); 8312 8313 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_RCR); 8314 ocp_data &= ~SLOT_EN; 8315 ocp_write_word(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 8316 8317 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_CPCR); 8318 ocp_data |= FLOW_CTRL_EN; 8319 ocp_write_word(tp, MCU_TYPE_PLA, PLA_CPCR, ocp_data); 8320 8321 /* enable fc timer and set timer to 600 ms. */ 8322 ocp_write_word(tp, MCU_TYPE_USB, USB_FC_TIMER, 8323 CTRL_TIMER_EN | (600 / 8)); 8324 8325 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_CTRL); 8326 if (!(ocp_read_word(tp, MCU_TYPE_PLA, PLA_POL_GPIO_CTRL) & DACK_DET_EN)) 8327 ocp_data |= FLOW_CTRL_PATCH_2; 8328 ocp_data &= ~AUTO_SPEEDUP; 8329 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_CTRL, ocp_data); 8330 8331 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_FW_TASK); 8332 ocp_data |= FC_PATCH_TASK; 8333 ocp_write_word(tp, MCU_TYPE_USB, USB_FW_TASK, ocp_data); 8334 8335 r8156_mac_clk_spd(tp, true); 8336 8337 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3); 8338 ocp_data &= ~PLA_MCU_SPDWN_EN; 8339 ocp_write_word(tp, MCU_TYPE_PLA, PLA_MAC_PWR_CTRL3, ocp_data); 8340 8341 ocp_data = ocp_read_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS); 8342 if (rtl8152_get_speed(tp) & LINK_STATUS) 8343 ocp_data |= CUR_LINK_OK; 8344 else 8345 ocp_data &= ~CUR_LINK_OK; 8346 ocp_data |= POLL_LINK_CHG; 8347 ocp_write_word(tp, MCU_TYPE_PLA, PLA_EXTRA_STATUS, ocp_data); 8348 8349 set_bit(GREEN_ETHERNET, &tp->flags); 8350 8351 /* rx aggregation */ 8352 ocp_data = ocp_read_word(tp, MCU_TYPE_USB, USB_USB_CTRL); 8353 ocp_data &= ~(RX_AGG_DISABLE | RX_ZERO_EN); 8354 ocp_write_word(tp, MCU_TYPE_USB, USB_USB_CTRL, ocp_data); 8355 8356 r8156_mdio_force_mode(tp); 8357 rtl_tally_reset(tp); 8358 8359 tp->coalesce = 15000; /* 15 us */ 8360} 8361 8362static bool rtl_check_vendor_ok(struct usb_interface *intf) 8363{ 8364 struct usb_host_interface *alt = intf->cur_altsetting; 8365 struct usb_endpoint_descriptor *in, *out, *intr; 8366 8367 if (usb_find_common_endpoints(alt, &in, &out, &intr, NULL) < 0) { 8368 dev_err(&intf->dev, "Expected endpoints are not found\n"); 8369 return false; 8370 } 8371 8372 /* Check Rx endpoint address */ 8373 if (usb_endpoint_num(in) != 1) { 8374 dev_err(&intf->dev, "Invalid Rx endpoint address\n"); 8375 return false; 8376 } 8377 8378 /* Check Tx endpoint address */ 8379 if (usb_endpoint_num(out) != 2) { 8380 dev_err(&intf->dev, "Invalid Tx endpoint address\n"); 8381 return false; 8382 } 8383 8384 /* Check interrupt endpoint address */ 8385 if (usb_endpoint_num(intr) != 3) { 8386 dev_err(&intf->dev, "Invalid interrupt endpoint address\n"); 8387 return false; 8388 } 8389 8390 return true; 8391} 8392 8393static int rtl8152_pre_reset(struct usb_interface *intf) 8394{ 8395 struct r8152 *tp = usb_get_intfdata(intf); 8396 struct net_device *netdev; 8397 8398 rtnl_lock(); 8399 8400 if (!tp || !test_bit(PROBED_WITH_NO_ERRORS, &tp->flags)) 8401 return 0; 8402 8403 netdev = tp->netdev; 8404 if (!netif_running(netdev)) 8405 return 0; 8406 8407 netif_stop_queue(netdev); 8408 tasklet_disable(&tp->tx_tl); 8409 clear_bit(WORK_ENABLE, &tp->flags); 8410 usb_kill_urb(tp->intr_urb); 8411 cancel_delayed_work_sync(&tp->schedule); 8412 napi_disable(&tp->napi); 8413 if (netif_carrier_ok(netdev)) { 8414 mutex_lock(&tp->control); 8415 set_bit(IN_PRE_RESET, &tp->flags); 8416 tp->rtl_ops.disable(tp); 8417 clear_bit(IN_PRE_RESET, &tp->flags); 8418 mutex_unlock(&tp->control); 8419 } 8420 8421 return 0; 8422} 8423 8424static int rtl8152_post_reset(struct usb_interface *intf) 8425{ 8426 struct r8152 *tp = usb_get_intfdata(intf); 8427 struct net_device *netdev; 8428 struct sockaddr_storage ss; 8429 8430 if (!tp || !test_bit(PROBED_WITH_NO_ERRORS, &tp->flags)) 8431 goto exit; 8432 8433 rtl_set_accessible(tp); 8434 8435 /* reset the MAC address in case of policy change */ 8436 if (determine_ethernet_addr(tp, &ss) >= 0) 8437 dev_set_mac_address(tp->netdev, &ss, NULL); 8438 8439 netdev = tp->netdev; 8440 if (!netif_running(netdev)) 8441 goto exit; 8442 8443 set_bit(WORK_ENABLE, &tp->flags); 8444 if (netif_carrier_ok(netdev)) { 8445 mutex_lock(&tp->control); 8446 tp->rtl_ops.enable(tp); 8447 rtl_start_rx(tp); 8448 _rtl8152_set_rx_mode(netdev); 8449 mutex_unlock(&tp->control); 8450 } 8451 8452 napi_enable(&tp->napi); 8453 tasklet_enable(&tp->tx_tl); 8454 netif_wake_queue(netdev); 8455 usb_submit_urb(tp->intr_urb, GFP_KERNEL); 8456 8457 if (!list_empty(&tp->rx_done)) 8458 napi_schedule(&tp->napi); 8459 8460exit: 8461 rtnl_unlock(); 8462 return 0; 8463} 8464 8465static bool delay_autosuspend(struct r8152 *tp) 8466{ 8467 bool sw_linking = !!netif_carrier_ok(tp->netdev); 8468 bool hw_linking = !!(rtl8152_get_speed(tp) & LINK_STATUS); 8469 8470 /* This means a linking change occurs and the driver doesn't detect it, 8471 * yet. If the driver has disabled tx/rx and hw is linking on, the 8472 * device wouldn't wake up by receiving any packet. 8473 */ 8474 if (work_busy(&tp->schedule.work) || sw_linking != hw_linking) 8475 return true; 8476 8477 /* If the linking down is occurred by nway, the device may miss the 8478 * linking change event. And it wouldn't wake when linking on. 8479 */ 8480 if (!sw_linking && tp->rtl_ops.in_nway(tp)) 8481 return true; 8482 else if (!skb_queue_empty(&tp->tx_queue)) 8483 return true; 8484 else 8485 return false; 8486} 8487 8488static int rtl8152_runtime_resume(struct r8152 *tp) 8489{ 8490 struct net_device *netdev = tp->netdev; 8491 8492 if (netif_running(netdev) && netdev->flags & IFF_UP) { 8493 struct napi_struct *napi = &tp->napi; 8494 8495 tp->rtl_ops.autosuspend_en(tp, false); 8496 napi_disable(napi); 8497 set_bit(WORK_ENABLE, &tp->flags); 8498 8499 if (netif_carrier_ok(netdev)) { 8500 if (rtl8152_get_speed(tp) & LINK_STATUS) { 8501 rtl_start_rx(tp); 8502 } else { 8503 netif_carrier_off(netdev); 8504 tp->rtl_ops.disable(tp); 8505 netif_info(tp, link, netdev, "linking down\n"); 8506 } 8507 } 8508 8509 napi_enable(napi); 8510 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 8511 smp_mb__after_atomic(); 8512 8513 if (!list_empty(&tp->rx_done)) 8514 napi_schedule(&tp->napi); 8515 8516 usb_submit_urb(tp->intr_urb, GFP_NOIO); 8517 } else { 8518 if (netdev->flags & IFF_UP) 8519 tp->rtl_ops.autosuspend_en(tp, false); 8520 8521 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 8522 } 8523 8524 return 0; 8525} 8526 8527static int rtl8152_system_resume(struct r8152 *tp) 8528{ 8529 struct net_device *netdev = tp->netdev; 8530 8531 netif_device_attach(netdev); 8532 8533 if (netif_running(netdev) && (netdev->flags & IFF_UP)) { 8534 tp->rtl_ops.up(tp); 8535 netif_carrier_off(netdev); 8536 set_bit(WORK_ENABLE, &tp->flags); 8537 usb_submit_urb(tp->intr_urb, GFP_NOIO); 8538 } 8539 8540 return 0; 8541} 8542 8543static int rtl8152_runtime_suspend(struct r8152 *tp) 8544{ 8545 struct net_device *netdev = tp->netdev; 8546 int ret = 0; 8547 8548 if (!tp->rtl_ops.autosuspend_en) 8549 return -EBUSY; 8550 8551 set_bit(SELECTIVE_SUSPEND, &tp->flags); 8552 smp_mb__after_atomic(); 8553 8554 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 8555 u32 rcr = 0; 8556 8557 if (netif_carrier_ok(netdev)) { 8558 u32 ocp_data; 8559 8560 rcr = ocp_read_dword(tp, MCU_TYPE_PLA, PLA_RCR); 8561 ocp_data = rcr & ~RCR_ACPT_ALL; 8562 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, ocp_data); 8563 rxdy_gated_en(tp, true); 8564 ocp_data = ocp_read_byte(tp, MCU_TYPE_PLA, 8565 PLA_OOB_CTRL); 8566 if (!(ocp_data & RXFIFO_EMPTY)) { 8567 rxdy_gated_en(tp, false); 8568 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); 8569 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 8570 smp_mb__after_atomic(); 8571 ret = -EBUSY; 8572 goto out1; 8573 } 8574 } 8575 8576 clear_bit(WORK_ENABLE, &tp->flags); 8577 usb_kill_urb(tp->intr_urb); 8578 8579 tp->rtl_ops.autosuspend_en(tp, true); 8580 8581 if (netif_carrier_ok(netdev)) { 8582 struct napi_struct *napi = &tp->napi; 8583 8584 napi_disable(napi); 8585 rtl_stop_rx(tp); 8586 rxdy_gated_en(tp, false); 8587 ocp_write_dword(tp, MCU_TYPE_PLA, PLA_RCR, rcr); 8588 napi_enable(napi); 8589 } 8590 8591 if (delay_autosuspend(tp)) { 8592 rtl8152_runtime_resume(tp); 8593 ret = -EBUSY; 8594 } 8595 } 8596 8597out1: 8598 return ret; 8599} 8600 8601static int rtl8152_system_suspend(struct r8152 *tp) 8602{ 8603 struct net_device *netdev = tp->netdev; 8604 8605 netif_device_detach(netdev); 8606 8607 if (netif_running(netdev) && test_bit(WORK_ENABLE, &tp->flags)) { 8608 struct napi_struct *napi = &tp->napi; 8609 8610 clear_bit(WORK_ENABLE, &tp->flags); 8611 usb_kill_urb(tp->intr_urb); 8612 tasklet_disable(&tp->tx_tl); 8613 napi_disable(napi); 8614 cancel_delayed_work_sync(&tp->schedule); 8615 tp->rtl_ops.down(tp); 8616 napi_enable(napi); 8617 tasklet_enable(&tp->tx_tl); 8618 } 8619 8620 /* If we're inaccessible here then some of the work that we did to 8621 * get the adapter ready for suspend didn't work. Queue up a wakeup 8622 * event so we can try again. 8623 */ 8624 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 8625 pm_wakeup_event(&tp->udev->dev, 0); 8626 8627 return 0; 8628} 8629 8630static int rtl8152_suspend(struct usb_interface *intf, pm_message_t message) 8631{ 8632 struct r8152 *tp = usb_get_intfdata(intf); 8633 int ret; 8634 8635 mutex_lock(&tp->control); 8636 8637 if (PMSG_IS_AUTO(message)) 8638 ret = rtl8152_runtime_suspend(tp); 8639 else 8640 ret = rtl8152_system_suspend(tp); 8641 8642 mutex_unlock(&tp->control); 8643 8644 return ret; 8645} 8646 8647static int rtl8152_resume(struct usb_interface *intf) 8648{ 8649 struct r8152 *tp = usb_get_intfdata(intf); 8650 bool runtime_resume = test_bit(SELECTIVE_SUSPEND, &tp->flags); 8651 int ret; 8652 8653 mutex_lock(&tp->control); 8654 8655 rtl_reset_ocp_base(tp); 8656 8657 if (runtime_resume) 8658 ret = rtl8152_runtime_resume(tp); 8659 else 8660 ret = rtl8152_system_resume(tp); 8661 8662 mutex_unlock(&tp->control); 8663 8664 /* If the device is RTL8152_INACCESSIBLE here then we should do a 8665 * reset. This is important because the usb_lock_device_for_reset() 8666 * that happens as a result of usb_queue_reset_device() will silently 8667 * fail if the device was suspended or if too much time passed. 8668 * 8669 * NOTE: The device is locked here so we can directly do the reset. 8670 * We don't need usb_lock_device_for_reset() because that's just a 8671 * wrapper over device_lock() and device_resume() (which calls us) 8672 * does that for us. 8673 */ 8674 if (!runtime_resume && test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 8675 usb_reset_device(tp->udev); 8676 8677 return ret; 8678} 8679 8680static int rtl8152_reset_resume(struct usb_interface *intf) 8681{ 8682 struct r8152 *tp = usb_get_intfdata(intf); 8683 8684 clear_bit(SELECTIVE_SUSPEND, &tp->flags); 8685 rtl_reset_ocp_base(tp); 8686 tp->rtl_ops.init(tp); 8687 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 8688 set_ethernet_addr(tp, true); 8689 return rtl8152_resume(intf); 8690} 8691 8692static void rtl8152_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 8693{ 8694 struct r8152 *tp = netdev_priv(dev); 8695 8696 if (usb_autopm_get_interface(tp->intf) < 0) 8697 return; 8698 8699 if (!rtl_can_wakeup(tp)) { 8700 wol->supported = 0; 8701 wol->wolopts = 0; 8702 } else { 8703 mutex_lock(&tp->control); 8704 wol->supported = WAKE_ANY; 8705 wol->wolopts = __rtl_get_wol(tp); 8706 mutex_unlock(&tp->control); 8707 } 8708 8709 usb_autopm_put_interface(tp->intf); 8710} 8711 8712static int rtl8152_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 8713{ 8714 struct r8152 *tp = netdev_priv(dev); 8715 int ret; 8716 8717 if (!rtl_can_wakeup(tp)) 8718 return -EOPNOTSUPP; 8719 8720 if (wol->wolopts & ~WAKE_ANY) 8721 return -EINVAL; 8722 8723 ret = usb_autopm_get_interface(tp->intf); 8724 if (ret < 0) 8725 goto out_set_wol; 8726 8727 mutex_lock(&tp->control); 8728 8729 __rtl_set_wol(tp, wol->wolopts); 8730 tp->saved_wolopts = wol->wolopts & WAKE_ANY; 8731 8732 mutex_unlock(&tp->control); 8733 8734 usb_autopm_put_interface(tp->intf); 8735 8736out_set_wol: 8737 return ret; 8738} 8739 8740static u32 rtl8152_get_msglevel(struct net_device *dev) 8741{ 8742 struct r8152 *tp = netdev_priv(dev); 8743 8744 return tp->msg_enable; 8745} 8746 8747static void rtl8152_set_msglevel(struct net_device *dev, u32 value) 8748{ 8749 struct r8152 *tp = netdev_priv(dev); 8750 8751 tp->msg_enable = value; 8752} 8753 8754static void rtl8152_get_drvinfo(struct net_device *netdev, 8755 struct ethtool_drvinfo *info) 8756{ 8757 struct r8152 *tp = netdev_priv(netdev); 8758 8759 strscpy(info->driver, MODULENAME, sizeof(info->driver)); 8760 strscpy(info->version, DRIVER_VERSION, sizeof(info->version)); 8761 usb_make_path(tp->udev, info->bus_info, sizeof(info->bus_info)); 8762 if (!IS_ERR_OR_NULL(tp->rtl_fw.fw)) 8763 strscpy(info->fw_version, tp->rtl_fw.version, 8764 sizeof(info->fw_version)); 8765} 8766 8767static 8768int rtl8152_get_link_ksettings(struct net_device *netdev, 8769 struct ethtool_link_ksettings *cmd) 8770{ 8771 struct r8152 *tp = netdev_priv(netdev); 8772 int ret; 8773 8774 if (!tp->mii.mdio_read) 8775 return -EOPNOTSUPP; 8776 8777 ret = usb_autopm_get_interface(tp->intf); 8778 if (ret < 0) 8779 goto out; 8780 8781 mutex_lock(&tp->control); 8782 8783 mii_ethtool_get_link_ksettings(&tp->mii, cmd); 8784 8785 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 8786 cmd->link_modes.supported, tp->support_2500full); 8787 8788 if (tp->support_2500full) { 8789 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 8790 cmd->link_modes.advertising, 8791 ocp_reg_read(tp, OCP_10GBT_CTRL) & MDIO_AN_10GBT_CTRL_ADV2_5G); 8792 8793 linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 8794 cmd->link_modes.lp_advertising, 8795 ocp_reg_read(tp, OCP_10GBT_STAT) & MDIO_AN_10GBT_STAT_LP2_5G); 8796 8797 if (is_speed_2500(rtl8152_get_speed(tp))) 8798 cmd->base.speed = SPEED_2500; 8799 } 8800 8801 mutex_unlock(&tp->control); 8802 8803 usb_autopm_put_interface(tp->intf); 8804 8805out: 8806 return ret; 8807} 8808 8809static int rtl8152_set_link_ksettings(struct net_device *dev, 8810 const struct ethtool_link_ksettings *cmd) 8811{ 8812 struct r8152 *tp = netdev_priv(dev); 8813 u32 advertising = 0; 8814 int ret; 8815 8816 ret = usb_autopm_get_interface(tp->intf); 8817 if (ret < 0) 8818 goto out; 8819 8820 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, 8821 cmd->link_modes.advertising)) 8822 advertising |= RTL_ADVERTISED_10_HALF; 8823 8824 if (test_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, 8825 cmd->link_modes.advertising)) 8826 advertising |= RTL_ADVERTISED_10_FULL; 8827 8828 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, 8829 cmd->link_modes.advertising)) 8830 advertising |= RTL_ADVERTISED_100_HALF; 8831 8832 if (test_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, 8833 cmd->link_modes.advertising)) 8834 advertising |= RTL_ADVERTISED_100_FULL; 8835 8836 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 8837 cmd->link_modes.advertising)) 8838 advertising |= RTL_ADVERTISED_1000_HALF; 8839 8840 if (test_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 8841 cmd->link_modes.advertising)) 8842 advertising |= RTL_ADVERTISED_1000_FULL; 8843 8844 if (test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, 8845 cmd->link_modes.advertising)) 8846 advertising |= RTL_ADVERTISED_2500_FULL; 8847 8848 mutex_lock(&tp->control); 8849 8850 ret = rtl8152_set_speed(tp, cmd->base.autoneg, cmd->base.speed, 8851 cmd->base.duplex, advertising); 8852 if (!ret) { 8853 tp->autoneg = cmd->base.autoneg; 8854 tp->speed = cmd->base.speed; 8855 tp->duplex = cmd->base.duplex; 8856 tp->advertising = advertising; 8857 } 8858 8859 mutex_unlock(&tp->control); 8860 8861 usb_autopm_put_interface(tp->intf); 8862 8863out: 8864 return ret; 8865} 8866 8867static const char rtl8152_gstrings[][ETH_GSTRING_LEN] = { 8868 "tx_packets", 8869 "rx_packets", 8870 "tx_errors", 8871 "rx_errors", 8872 "rx_missed", 8873 "align_errors", 8874 "tx_single_collisions", 8875 "tx_multi_collisions", 8876 "rx_unicast", 8877 "rx_broadcast", 8878 "rx_multicast", 8879 "tx_aborted", 8880 "tx_underrun", 8881}; 8882 8883static int rtl8152_get_sset_count(struct net_device *dev, int sset) 8884{ 8885 switch (sset) { 8886 case ETH_SS_STATS: 8887 return ARRAY_SIZE(rtl8152_gstrings); 8888 default: 8889 return -EOPNOTSUPP; 8890 } 8891} 8892 8893static void rtl8152_get_ethtool_stats(struct net_device *dev, 8894 struct ethtool_stats *stats, u64 *data) 8895{ 8896 struct r8152 *tp = netdev_priv(dev); 8897 struct tally_counter tally; 8898 8899 if (usb_autopm_get_interface(tp->intf) < 0) 8900 return; 8901 8902 generic_ocp_read(tp, PLA_TALLYCNT, sizeof(tally), &tally, MCU_TYPE_PLA); 8903 8904 usb_autopm_put_interface(tp->intf); 8905 8906 data[0] = le64_to_cpu(tally.tx_packets); 8907 data[1] = le64_to_cpu(tally.rx_packets); 8908 data[2] = le64_to_cpu(tally.tx_errors); 8909 data[3] = le32_to_cpu(tally.rx_errors); 8910 data[4] = le16_to_cpu(tally.rx_missed); 8911 data[5] = le16_to_cpu(tally.align_errors); 8912 data[6] = le32_to_cpu(tally.tx_one_collision); 8913 data[7] = le32_to_cpu(tally.tx_multi_collision); 8914 data[8] = le64_to_cpu(tally.rx_unicast); 8915 data[9] = le64_to_cpu(tally.rx_broadcast); 8916 data[10] = le32_to_cpu(tally.rx_multicast); 8917 data[11] = le16_to_cpu(tally.tx_aborted); 8918 data[12] = le16_to_cpu(tally.tx_underrun); 8919} 8920 8921static void rtl8152_get_strings(struct net_device *dev, u32 stringset, u8 *data) 8922{ 8923 switch (stringset) { 8924 case ETH_SS_STATS: 8925 memcpy(data, rtl8152_gstrings, sizeof(rtl8152_gstrings)); 8926 break; 8927 } 8928} 8929 8930static int r8152_get_eee(struct r8152 *tp, struct ethtool_keee *eee) 8931{ 8932 __ETHTOOL_DECLARE_LINK_MODE_MASK(common); 8933 u16 val; 8934 8935 val = r8152_mmd_read(tp, MDIO_MMD_PCS, MDIO_PCS_EEE_ABLE); 8936 mii_eee_cap1_mod_linkmode_t(eee->supported, val); 8937 8938 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_ADV); 8939 mii_eee_cap1_mod_linkmode_t(eee->advertised, val); 8940 8941 val = r8152_mmd_read(tp, MDIO_MMD_AN, MDIO_AN_EEE_LPABLE); 8942 mii_eee_cap1_mod_linkmode_t(eee->lp_advertised, val); 8943 8944 eee->eee_enabled = tp->eee_en; 8945 8946 linkmode_and(common, eee->advertised, eee->lp_advertised); 8947 eee->eee_active = phy_check_valid(tp->speed, tp->duplex, common); 8948 8949 return 0; 8950} 8951 8952static int r8152_set_eee(struct r8152 *tp, struct ethtool_keee *eee) 8953{ 8954 u16 val = linkmode_to_mii_eee_cap1_t(eee->advertised); 8955 8956 tp->eee_en = eee->eee_enabled; 8957 tp->eee_adv = val; 8958 8959 rtl_eee_enable(tp, tp->eee_en); 8960 8961 return 0; 8962} 8963 8964static int r8153_get_eee(struct r8152 *tp, struct ethtool_keee *eee) 8965{ 8966 __ETHTOOL_DECLARE_LINK_MODE_MASK(common); 8967 u16 val; 8968 8969 val = ocp_reg_read(tp, OCP_EEE_ABLE); 8970 mii_eee_cap1_mod_linkmode_t(eee->supported, val); 8971 8972 val = ocp_reg_read(tp, OCP_EEE_ADV); 8973 mii_eee_cap1_mod_linkmode_t(eee->advertised, val); 8974 8975 val = ocp_reg_read(tp, OCP_EEE_LPABLE); 8976 mii_eee_cap1_mod_linkmode_t(eee->lp_advertised, val); 8977 8978 eee->eee_enabled = tp->eee_en; 8979 8980 linkmode_and(common, eee->advertised, eee->lp_advertised); 8981 eee->eee_active = phy_check_valid(tp->speed, tp->duplex, common); 8982 8983 return 0; 8984} 8985 8986static int 8987rtl_ethtool_get_eee(struct net_device *net, struct ethtool_keee *edata) 8988{ 8989 struct r8152 *tp = netdev_priv(net); 8990 int ret; 8991 8992 if (!tp->rtl_ops.eee_get) { 8993 ret = -EOPNOTSUPP; 8994 goto out; 8995 } 8996 8997 ret = usb_autopm_get_interface(tp->intf); 8998 if (ret < 0) 8999 goto out; 9000 9001 mutex_lock(&tp->control); 9002 9003 ret = tp->rtl_ops.eee_get(tp, edata); 9004 9005 mutex_unlock(&tp->control); 9006 9007 usb_autopm_put_interface(tp->intf); 9008 9009out: 9010 return ret; 9011} 9012 9013static int 9014rtl_ethtool_set_eee(struct net_device *net, struct ethtool_keee *edata) 9015{ 9016 struct r8152 *tp = netdev_priv(net); 9017 int ret; 9018 9019 if (!tp->rtl_ops.eee_set) { 9020 ret = -EOPNOTSUPP; 9021 goto out; 9022 } 9023 9024 ret = usb_autopm_get_interface(tp->intf); 9025 if (ret < 0) 9026 goto out; 9027 9028 mutex_lock(&tp->control); 9029 9030 ret = tp->rtl_ops.eee_set(tp, edata); 9031 if (!ret) 9032 ret = mii_nway_restart(&tp->mii); 9033 9034 mutex_unlock(&tp->control); 9035 9036 usb_autopm_put_interface(tp->intf); 9037 9038out: 9039 return ret; 9040} 9041 9042static int rtl8152_nway_reset(struct net_device *dev) 9043{ 9044 struct r8152 *tp = netdev_priv(dev); 9045 int ret; 9046 9047 ret = usb_autopm_get_interface(tp->intf); 9048 if (ret < 0) 9049 goto out; 9050 9051 mutex_lock(&tp->control); 9052 9053 ret = mii_nway_restart(&tp->mii); 9054 9055 mutex_unlock(&tp->control); 9056 9057 usb_autopm_put_interface(tp->intf); 9058 9059out: 9060 return ret; 9061} 9062 9063static int rtl8152_get_coalesce(struct net_device *netdev, 9064 struct ethtool_coalesce *coalesce, 9065 struct kernel_ethtool_coalesce *kernel_coal, 9066 struct netlink_ext_ack *extack) 9067{ 9068 struct r8152 *tp = netdev_priv(netdev); 9069 9070 switch (tp->version) { 9071 case RTL_VER_01: 9072 case RTL_VER_02: 9073 case RTL_VER_07: 9074 return -EOPNOTSUPP; 9075 default: 9076 break; 9077 } 9078 9079 coalesce->rx_coalesce_usecs = tp->coalesce; 9080 9081 return 0; 9082} 9083 9084static int rtl8152_set_coalesce(struct net_device *netdev, 9085 struct ethtool_coalesce *coalesce, 9086 struct kernel_ethtool_coalesce *kernel_coal, 9087 struct netlink_ext_ack *extack) 9088{ 9089 struct r8152 *tp = netdev_priv(netdev); 9090 int ret; 9091 9092 switch (tp->version) { 9093 case RTL_VER_01: 9094 case RTL_VER_02: 9095 case RTL_VER_07: 9096 return -EOPNOTSUPP; 9097 default: 9098 break; 9099 } 9100 9101 if (coalesce->rx_coalesce_usecs > COALESCE_SLOW) 9102 return -EINVAL; 9103 9104 ret = usb_autopm_get_interface(tp->intf); 9105 if (ret < 0) 9106 return ret; 9107 9108 mutex_lock(&tp->control); 9109 9110 if (tp->coalesce != coalesce->rx_coalesce_usecs) { 9111 tp->coalesce = coalesce->rx_coalesce_usecs; 9112 9113 if (netif_running(netdev) && netif_carrier_ok(netdev)) { 9114 netif_stop_queue(netdev); 9115 napi_disable(&tp->napi); 9116 tp->rtl_ops.disable(tp); 9117 tp->rtl_ops.enable(tp); 9118 rtl_start_rx(tp); 9119 clear_bit(RTL8152_SET_RX_MODE, &tp->flags); 9120 _rtl8152_set_rx_mode(netdev); 9121 napi_enable(&tp->napi); 9122 netif_wake_queue(netdev); 9123 } 9124 } 9125 9126 mutex_unlock(&tp->control); 9127 9128 usb_autopm_put_interface(tp->intf); 9129 9130 return ret; 9131} 9132 9133static int rtl8152_get_tunable(struct net_device *netdev, 9134 const struct ethtool_tunable *tunable, void *d) 9135{ 9136 struct r8152 *tp = netdev_priv(netdev); 9137 9138 switch (tunable->id) { 9139 case ETHTOOL_RX_COPYBREAK: 9140 *(u32 *)d = tp->rx_copybreak; 9141 break; 9142 default: 9143 return -EOPNOTSUPP; 9144 } 9145 9146 return 0; 9147} 9148 9149static int rtl8152_set_tunable(struct net_device *netdev, 9150 const struct ethtool_tunable *tunable, 9151 const void *d) 9152{ 9153 struct r8152 *tp = netdev_priv(netdev); 9154 u32 val; 9155 9156 switch (tunable->id) { 9157 case ETHTOOL_RX_COPYBREAK: 9158 val = *(u32 *)d; 9159 if (val < ETH_ZLEN) { 9160 netif_err(tp, rx_err, netdev, 9161 "Invalid rx copy break value\n"); 9162 return -EINVAL; 9163 } 9164 9165 if (tp->rx_copybreak != val) { 9166 if (netdev->flags & IFF_UP) { 9167 mutex_lock(&tp->control); 9168 napi_disable(&tp->napi); 9169 tp->rx_copybreak = val; 9170 napi_enable(&tp->napi); 9171 mutex_unlock(&tp->control); 9172 } else { 9173 tp->rx_copybreak = val; 9174 } 9175 } 9176 break; 9177 default: 9178 return -EOPNOTSUPP; 9179 } 9180 9181 return 0; 9182} 9183 9184static void rtl8152_get_ringparam(struct net_device *netdev, 9185 struct ethtool_ringparam *ring, 9186 struct kernel_ethtool_ringparam *kernel_ring, 9187 struct netlink_ext_ack *extack) 9188{ 9189 struct r8152 *tp = netdev_priv(netdev); 9190 9191 ring->rx_max_pending = RTL8152_RX_MAX_PENDING; 9192 ring->rx_pending = tp->rx_pending; 9193} 9194 9195static int rtl8152_set_ringparam(struct net_device *netdev, 9196 struct ethtool_ringparam *ring, 9197 struct kernel_ethtool_ringparam *kernel_ring, 9198 struct netlink_ext_ack *extack) 9199{ 9200 struct r8152 *tp = netdev_priv(netdev); 9201 9202 if (ring->rx_pending < (RTL8152_MAX_RX * 2)) 9203 return -EINVAL; 9204 9205 if (tp->rx_pending != ring->rx_pending) { 9206 if (netdev->flags & IFF_UP) { 9207 mutex_lock(&tp->control); 9208 napi_disable(&tp->napi); 9209 tp->rx_pending = ring->rx_pending; 9210 napi_enable(&tp->napi); 9211 mutex_unlock(&tp->control); 9212 } else { 9213 tp->rx_pending = ring->rx_pending; 9214 } 9215 } 9216 9217 return 0; 9218} 9219 9220static void rtl8152_get_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause) 9221{ 9222 struct r8152 *tp = netdev_priv(netdev); 9223 u16 bmcr, lcladv, rmtadv; 9224 u8 cap; 9225 9226 if (usb_autopm_get_interface(tp->intf) < 0) 9227 return; 9228 9229 mutex_lock(&tp->control); 9230 9231 bmcr = r8152_mdio_read(tp, MII_BMCR); 9232 lcladv = r8152_mdio_read(tp, MII_ADVERTISE); 9233 rmtadv = r8152_mdio_read(tp, MII_LPA); 9234 9235 mutex_unlock(&tp->control); 9236 9237 usb_autopm_put_interface(tp->intf); 9238 9239 if (!(bmcr & BMCR_ANENABLE)) { 9240 pause->autoneg = 0; 9241 pause->rx_pause = 0; 9242 pause->tx_pause = 0; 9243 return; 9244 } 9245 9246 pause->autoneg = 1; 9247 9248 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv); 9249 9250 if (cap & FLOW_CTRL_RX) 9251 pause->rx_pause = 1; 9252 9253 if (cap & FLOW_CTRL_TX) 9254 pause->tx_pause = 1; 9255} 9256 9257static int rtl8152_set_pauseparam(struct net_device *netdev, struct ethtool_pauseparam *pause) 9258{ 9259 struct r8152 *tp = netdev_priv(netdev); 9260 u16 old, new1; 9261 u8 cap = 0; 9262 int ret; 9263 9264 ret = usb_autopm_get_interface(tp->intf); 9265 if (ret < 0) 9266 return ret; 9267 9268 mutex_lock(&tp->control); 9269 9270 if (pause->autoneg && !(r8152_mdio_read(tp, MII_BMCR) & BMCR_ANENABLE)) { 9271 ret = -EINVAL; 9272 goto out; 9273 } 9274 9275 if (pause->rx_pause) 9276 cap |= FLOW_CTRL_RX; 9277 9278 if (pause->tx_pause) 9279 cap |= FLOW_CTRL_TX; 9280 9281 old = r8152_mdio_read(tp, MII_ADVERTISE); 9282 new1 = (old & ~(ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM)) | mii_advertise_flowctrl(cap); 9283 if (old != new1) 9284 r8152_mdio_write(tp, MII_ADVERTISE, new1); 9285 9286out: 9287 mutex_unlock(&tp->control); 9288 usb_autopm_put_interface(tp->intf); 9289 9290 return ret; 9291} 9292 9293static const struct ethtool_ops ops = { 9294 .supported_coalesce_params = ETHTOOL_COALESCE_USECS, 9295 .get_drvinfo = rtl8152_get_drvinfo, 9296 .get_link = ethtool_op_get_link, 9297 .nway_reset = rtl8152_nway_reset, 9298 .get_msglevel = rtl8152_get_msglevel, 9299 .set_msglevel = rtl8152_set_msglevel, 9300 .get_wol = rtl8152_get_wol, 9301 .set_wol = rtl8152_set_wol, 9302 .get_strings = rtl8152_get_strings, 9303 .get_sset_count = rtl8152_get_sset_count, 9304 .get_ethtool_stats = rtl8152_get_ethtool_stats, 9305 .get_coalesce = rtl8152_get_coalesce, 9306 .set_coalesce = rtl8152_set_coalesce, 9307 .get_eee = rtl_ethtool_get_eee, 9308 .set_eee = rtl_ethtool_set_eee, 9309 .get_link_ksettings = rtl8152_get_link_ksettings, 9310 .set_link_ksettings = rtl8152_set_link_ksettings, 9311 .get_tunable = rtl8152_get_tunable, 9312 .set_tunable = rtl8152_set_tunable, 9313 .get_ringparam = rtl8152_get_ringparam, 9314 .set_ringparam = rtl8152_set_ringparam, 9315 .get_pauseparam = rtl8152_get_pauseparam, 9316 .set_pauseparam = rtl8152_set_pauseparam, 9317 .get_ts_info = ethtool_op_get_ts_info, 9318}; 9319 9320static int rtl8152_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd) 9321{ 9322 struct r8152 *tp = netdev_priv(netdev); 9323 struct mii_ioctl_data *data = if_mii(rq); 9324 int res; 9325 9326 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 9327 return -ENODEV; 9328 9329 res = usb_autopm_get_interface(tp->intf); 9330 if (res < 0) 9331 goto out; 9332 9333 switch (cmd) { 9334 case SIOCGMIIPHY: 9335 data->phy_id = R8152_PHY_ID; /* Internal PHY */ 9336 break; 9337 9338 case SIOCGMIIREG: 9339 mutex_lock(&tp->control); 9340 data->val_out = r8152_mdio_read(tp, data->reg_num); 9341 mutex_unlock(&tp->control); 9342 break; 9343 9344 case SIOCSMIIREG: 9345 if (!capable(CAP_NET_ADMIN)) { 9346 res = -EPERM; 9347 break; 9348 } 9349 mutex_lock(&tp->control); 9350 r8152_mdio_write(tp, data->reg_num, data->val_in); 9351 mutex_unlock(&tp->control); 9352 break; 9353 9354 default: 9355 res = -EOPNOTSUPP; 9356 } 9357 9358 usb_autopm_put_interface(tp->intf); 9359 9360out: 9361 return res; 9362} 9363 9364static int rtl8152_change_mtu(struct net_device *dev, int new_mtu) 9365{ 9366 struct r8152 *tp = netdev_priv(dev); 9367 int ret; 9368 9369 switch (tp->version) { 9370 case RTL_VER_01: 9371 case RTL_VER_02: 9372 case RTL_VER_07: 9373 WRITE_ONCE(dev->mtu, new_mtu); 9374 return 0; 9375 default: 9376 break; 9377 } 9378 9379 ret = usb_autopm_get_interface(tp->intf); 9380 if (ret < 0) 9381 return ret; 9382 9383 mutex_lock(&tp->control); 9384 9385 WRITE_ONCE(dev->mtu, new_mtu); 9386 9387 if (netif_running(dev)) { 9388 if (tp->rtl_ops.change_mtu) 9389 tp->rtl_ops.change_mtu(tp); 9390 9391 if (netif_carrier_ok(dev)) { 9392 netif_stop_queue(dev); 9393 napi_disable(&tp->napi); 9394 tasklet_disable(&tp->tx_tl); 9395 tp->rtl_ops.disable(tp); 9396 tp->rtl_ops.enable(tp); 9397 rtl_start_rx(tp); 9398 tasklet_enable(&tp->tx_tl); 9399 napi_enable(&tp->napi); 9400 rtl8152_set_rx_mode(dev); 9401 netif_wake_queue(dev); 9402 } 9403 } 9404 9405 mutex_unlock(&tp->control); 9406 9407 usb_autopm_put_interface(tp->intf); 9408 9409 return ret; 9410} 9411 9412static const struct net_device_ops rtl8152_netdev_ops = { 9413 .ndo_open = rtl8152_open, 9414 .ndo_stop = rtl8152_close, 9415 .ndo_eth_ioctl = rtl8152_ioctl, 9416 .ndo_start_xmit = rtl8152_start_xmit, 9417 .ndo_tx_timeout = rtl8152_tx_timeout, 9418 .ndo_set_features = rtl8152_set_features, 9419 .ndo_set_rx_mode = rtl8152_set_rx_mode, 9420 .ndo_set_mac_address = rtl8152_set_mac_address, 9421 .ndo_change_mtu = rtl8152_change_mtu, 9422 .ndo_validate_addr = eth_validate_addr, 9423 .ndo_features_check = rtl8152_features_check, 9424}; 9425 9426static void rtl8152_unload(struct r8152 *tp) 9427{ 9428 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 9429 return; 9430 9431 if (tp->version != RTL_VER_01) 9432 r8152_power_cut_en(tp, true); 9433} 9434 9435static void rtl8153_unload(struct r8152 *tp) 9436{ 9437 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 9438 return; 9439 9440 r8153_power_cut_en(tp, false); 9441} 9442 9443static void rtl8153b_unload(struct r8152 *tp) 9444{ 9445 if (test_bit(RTL8152_INACCESSIBLE, &tp->flags)) 9446 return; 9447 9448 r8153b_power_cut_en(tp, false); 9449} 9450 9451static int rtl_ops_init(struct r8152 *tp) 9452{ 9453 struct rtl_ops *ops = &tp->rtl_ops; 9454 int ret = 0; 9455 9456 switch (tp->version) { 9457 case RTL_VER_01: 9458 case RTL_VER_02: 9459 case RTL_VER_07: 9460 ops->init = r8152b_init; 9461 ops->enable = rtl8152_enable; 9462 ops->disable = rtl8152_disable; 9463 ops->up = rtl8152_up; 9464 ops->down = rtl8152_down; 9465 ops->unload = rtl8152_unload; 9466 ops->eee_get = r8152_get_eee; 9467 ops->eee_set = r8152_set_eee; 9468 ops->in_nway = rtl8152_in_nway; 9469 ops->hw_phy_cfg = r8152b_hw_phy_cfg; 9470 ops->autosuspend_en = rtl_runtime_suspend_enable; 9471 tp->rx_buf_sz = 16 * 1024; 9472 tp->eee_en = true; 9473 tp->eee_adv = MDIO_EEE_100TX; 9474 break; 9475 9476 case RTL_VER_03: 9477 case RTL_VER_04: 9478 case RTL_VER_05: 9479 case RTL_VER_06: 9480 ops->init = r8153_init; 9481 ops->enable = rtl8153_enable; 9482 ops->disable = rtl8153_disable; 9483 ops->up = rtl8153_up; 9484 ops->down = rtl8153_down; 9485 ops->unload = rtl8153_unload; 9486 ops->eee_get = r8153_get_eee; 9487 ops->eee_set = r8152_set_eee; 9488 ops->in_nway = rtl8153_in_nway; 9489 ops->hw_phy_cfg = r8153_hw_phy_cfg; 9490 ops->autosuspend_en = rtl8153_runtime_enable; 9491 ops->change_mtu = rtl8153_change_mtu; 9492 if (tp->udev->speed < USB_SPEED_SUPER) 9493 tp->rx_buf_sz = 16 * 1024; 9494 else 9495 tp->rx_buf_sz = 32 * 1024; 9496 tp->eee_en = true; 9497 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; 9498 break; 9499 9500 case RTL_VER_08: 9501 case RTL_VER_09: 9502 ops->init = r8153b_init; 9503 ops->enable = rtl8153_enable; 9504 ops->disable = rtl8153_disable; 9505 ops->up = rtl8153b_up; 9506 ops->down = rtl8153b_down; 9507 ops->unload = rtl8153b_unload; 9508 ops->eee_get = r8153_get_eee; 9509 ops->eee_set = r8152_set_eee; 9510 ops->in_nway = rtl8153_in_nway; 9511 ops->hw_phy_cfg = r8153b_hw_phy_cfg; 9512 ops->autosuspend_en = rtl8153b_runtime_enable; 9513 ops->change_mtu = rtl8153_change_mtu; 9514 tp->rx_buf_sz = 32 * 1024; 9515 tp->eee_en = true; 9516 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; 9517 break; 9518 9519 case RTL_VER_11: 9520 tp->eee_en = true; 9521 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; 9522 fallthrough; 9523 case RTL_VER_10: 9524 ops->init = r8156_init; 9525 ops->enable = rtl8156_enable; 9526 ops->disable = rtl8156_disable; 9527 ops->up = rtl8156_up; 9528 ops->down = rtl8156_down; 9529 ops->unload = rtl8153_unload; 9530 ops->eee_get = r8153_get_eee; 9531 ops->eee_set = r8152_set_eee; 9532 ops->in_nway = rtl8153_in_nway; 9533 ops->hw_phy_cfg = r8156_hw_phy_cfg; 9534 ops->autosuspend_en = rtl8156_runtime_enable; 9535 ops->change_mtu = rtl8156_change_mtu; 9536 tp->rx_buf_sz = 48 * 1024; 9537 tp->support_2500full = 1; 9538 break; 9539 9540 case RTL_VER_12: 9541 case RTL_VER_13: 9542 tp->support_2500full = 1; 9543 fallthrough; 9544 case RTL_VER_15: 9545 tp->eee_en = true; 9546 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; 9547 ops->init = r8156b_init; 9548 ops->enable = rtl8156b_enable; 9549 ops->disable = rtl8153_disable; 9550 ops->up = rtl8156_up; 9551 ops->down = rtl8156_down; 9552 ops->unload = rtl8153_unload; 9553 ops->eee_get = r8153_get_eee; 9554 ops->eee_set = r8152_set_eee; 9555 ops->in_nway = rtl8153_in_nway; 9556 ops->hw_phy_cfg = r8156b_hw_phy_cfg; 9557 ops->autosuspend_en = rtl8156_runtime_enable; 9558 ops->change_mtu = rtl8156_change_mtu; 9559 tp->rx_buf_sz = 48 * 1024; 9560 break; 9561 9562 case RTL_VER_14: 9563 ops->init = r8153c_init; 9564 ops->enable = rtl8153_enable; 9565 ops->disable = rtl8153_disable; 9566 ops->up = rtl8153c_up; 9567 ops->down = rtl8153b_down; 9568 ops->unload = rtl8153_unload; 9569 ops->eee_get = r8153_get_eee; 9570 ops->eee_set = r8152_set_eee; 9571 ops->in_nway = rtl8153_in_nway; 9572 ops->hw_phy_cfg = r8153c_hw_phy_cfg; 9573 ops->autosuspend_en = rtl8153c_runtime_enable; 9574 ops->change_mtu = rtl8153c_change_mtu; 9575 tp->rx_buf_sz = 32 * 1024; 9576 tp->eee_en = true; 9577 tp->eee_adv = MDIO_EEE_1000T | MDIO_EEE_100TX; 9578 break; 9579 9580 default: 9581 ret = -ENODEV; 9582 dev_err(&tp->intf->dev, "Unknown Device\n"); 9583 break; 9584 } 9585 9586 return ret; 9587} 9588 9589#define FIRMWARE_8153A_2 "rtl_nic/rtl8153a-2.fw" 9590#define FIRMWARE_8153A_3 "rtl_nic/rtl8153a-3.fw" 9591#define FIRMWARE_8153A_4 "rtl_nic/rtl8153a-4.fw" 9592#define FIRMWARE_8153B_2 "rtl_nic/rtl8153b-2.fw" 9593#define FIRMWARE_8153C_1 "rtl_nic/rtl8153c-1.fw" 9594#define FIRMWARE_8156A_2 "rtl_nic/rtl8156a-2.fw" 9595#define FIRMWARE_8156B_2 "rtl_nic/rtl8156b-2.fw" 9596 9597MODULE_FIRMWARE(FIRMWARE_8153A_2); 9598MODULE_FIRMWARE(FIRMWARE_8153A_3); 9599MODULE_FIRMWARE(FIRMWARE_8153A_4); 9600MODULE_FIRMWARE(FIRMWARE_8153B_2); 9601MODULE_FIRMWARE(FIRMWARE_8153C_1); 9602MODULE_FIRMWARE(FIRMWARE_8156A_2); 9603MODULE_FIRMWARE(FIRMWARE_8156B_2); 9604 9605static int rtl_fw_init(struct r8152 *tp) 9606{ 9607 struct rtl_fw *rtl_fw = &tp->rtl_fw; 9608 9609 switch (tp->version) { 9610 case RTL_VER_04: 9611 rtl_fw->fw_name = FIRMWARE_8153A_2; 9612 rtl_fw->pre_fw = r8153_pre_firmware_1; 9613 rtl_fw->post_fw = r8153_post_firmware_1; 9614 break; 9615 case RTL_VER_05: 9616 rtl_fw->fw_name = FIRMWARE_8153A_3; 9617 rtl_fw->pre_fw = r8153_pre_firmware_2; 9618 rtl_fw->post_fw = r8153_post_firmware_2; 9619 break; 9620 case RTL_VER_06: 9621 rtl_fw->fw_name = FIRMWARE_8153A_4; 9622 rtl_fw->post_fw = r8153_post_firmware_3; 9623 break; 9624 case RTL_VER_09: 9625 rtl_fw->fw_name = FIRMWARE_8153B_2; 9626 rtl_fw->pre_fw = r8153b_pre_firmware_1; 9627 rtl_fw->post_fw = r8153b_post_firmware_1; 9628 break; 9629 case RTL_VER_11: 9630 rtl_fw->fw_name = FIRMWARE_8156A_2; 9631 rtl_fw->post_fw = r8156a_post_firmware_1; 9632 break; 9633 case RTL_VER_13: 9634 case RTL_VER_15: 9635 rtl_fw->fw_name = FIRMWARE_8156B_2; 9636 break; 9637 case RTL_VER_14: 9638 rtl_fw->fw_name = FIRMWARE_8153C_1; 9639 rtl_fw->pre_fw = r8153b_pre_firmware_1; 9640 rtl_fw->post_fw = r8153c_post_firmware_1; 9641 break; 9642 default: 9643 break; 9644 } 9645 9646 return 0; 9647} 9648 9649static u8 __rtl_get_hw_ver(struct usb_device *udev) 9650{ 9651 u32 ocp_data = 0; 9652 __le32 *tmp; 9653 u8 version; 9654 int ret; 9655 int i; 9656 9657 tmp = kmalloc(sizeof(*tmp), GFP_KERNEL); 9658 if (!tmp) 9659 return 0; 9660 9661 /* Retry up to 3 times in case there is a transitory error. We do this 9662 * since retrying a read of the version is always safe and this 9663 * function doesn't take advantage of r8152_control_msg(). 9664 */ 9665 for (i = 0; i < 3; i++) { 9666 ret = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0), 9667 RTL8152_REQ_GET_REGS, RTL8152_REQT_READ, 9668 PLA_TCR0, MCU_TYPE_PLA, tmp, sizeof(*tmp), 9669 USB_CTRL_GET_TIMEOUT); 9670 if (ret > 0) { 9671 ocp_data = (__le32_to_cpu(*tmp) >> 16) & VERSION_MASK; 9672 break; 9673 } 9674 } 9675 9676 if (i != 0 && ret > 0) 9677 dev_warn(&udev->dev, "Needed %d retries to read version\n", i); 9678 9679 kfree(tmp); 9680 9681 switch (ocp_data) { 9682 case 0x4c00: 9683 version = RTL_VER_01; 9684 break; 9685 case 0x4c10: 9686 version = RTL_VER_02; 9687 break; 9688 case 0x5c00: 9689 version = RTL_VER_03; 9690 break; 9691 case 0x5c10: 9692 version = RTL_VER_04; 9693 break; 9694 case 0x5c20: 9695 version = RTL_VER_05; 9696 break; 9697 case 0x5c30: 9698 version = RTL_VER_06; 9699 break; 9700 case 0x4800: 9701 version = RTL_VER_07; 9702 break; 9703 case 0x6000: 9704 version = RTL_VER_08; 9705 break; 9706 case 0x6010: 9707 version = RTL_VER_09; 9708 break; 9709 case 0x7010: 9710 version = RTL_TEST_01; 9711 break; 9712 case 0x7020: 9713 version = RTL_VER_10; 9714 break; 9715 case 0x7030: 9716 version = RTL_VER_11; 9717 break; 9718 case 0x7400: 9719 version = RTL_VER_12; 9720 break; 9721 case 0x7410: 9722 version = RTL_VER_13; 9723 break; 9724 case 0x6400: 9725 version = RTL_VER_14; 9726 break; 9727 case 0x7420: 9728 version = RTL_VER_15; 9729 break; 9730 default: 9731 version = RTL_VER_UNKNOWN; 9732 dev_info(&udev->dev, "Unknown version 0x%04x\n", ocp_data); 9733 break; 9734 } 9735 9736 return version; 9737} 9738 9739u8 rtl8152_get_version(struct usb_interface *intf) 9740{ 9741 u8 version; 9742 9743 version = __rtl_get_hw_ver(interface_to_usbdev(intf)); 9744 9745 dev_dbg(&intf->dev, "Detected version 0x%04x\n", version); 9746 9747 return version; 9748} 9749EXPORT_SYMBOL_GPL(rtl8152_get_version); 9750 9751static bool rtl8152_supports_lenovo_macpassthru(struct usb_device *udev) 9752{ 9753 int parent_vendor_id = le16_to_cpu(udev->parent->descriptor.idVendor); 9754 int product_id = le16_to_cpu(udev->descriptor.idProduct); 9755 int vendor_id = le16_to_cpu(udev->descriptor.idVendor); 9756 9757 if (vendor_id == VENDOR_ID_LENOVO) { 9758 switch (product_id) { 9759 case DEVICE_ID_LENOVO_USB_C_TRAVEL_HUB: 9760 case DEVICE_ID_THINKPAD_ONELINK_PLUS_DOCK: 9761 case DEVICE_ID_THINKPAD_THUNDERBOLT3_DOCK_GEN2: 9762 case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN2: 9763 case DEVICE_ID_THINKPAD_USB_C_DOCK_GEN3: 9764 case DEVICE_ID_THINKPAD_USB_C_DONGLE: 9765 case DEVICE_ID_THINKPAD_HYBRID_USB_C_DOCK: 9766 return 1; 9767 } 9768 } else if (vendor_id == VENDOR_ID_REALTEK && parent_vendor_id == VENDOR_ID_LENOVO) { 9769 switch (product_id) { 9770 case 0x8153: 9771 return 1; 9772 } 9773 } 9774 return 0; 9775} 9776 9777static int rtl8152_probe_once(struct usb_interface *intf, 9778 const struct usb_device_id *id, u8 version) 9779{ 9780 struct usb_device *udev = interface_to_usbdev(intf); 9781 struct r8152 *tp; 9782 struct net_device *netdev; 9783 int ret; 9784 9785 usb_reset_device(udev); 9786 netdev = alloc_etherdev(sizeof(struct r8152)); 9787 if (!netdev) { 9788 dev_err(&intf->dev, "Out of memory\n"); 9789 return -ENOMEM; 9790 } 9791 9792 SET_NETDEV_DEV(netdev, &intf->dev); 9793 tp = netdev_priv(netdev); 9794 tp->msg_enable = 0x7FFF; 9795 9796 tp->udev = udev; 9797 tp->netdev = netdev; 9798 tp->intf = intf; 9799 tp->version = version; 9800 9801 tp->pipe_ctrl_in = usb_rcvctrlpipe(udev, 0); 9802 tp->pipe_ctrl_out = usb_sndctrlpipe(udev, 0); 9803 tp->pipe_in = usb_rcvbulkpipe(udev, 1); 9804 tp->pipe_out = usb_sndbulkpipe(udev, 2); 9805 tp->pipe_intr = usb_rcvintpipe(udev, 3); 9806 9807 switch (version) { 9808 case RTL_VER_01: 9809 case RTL_VER_02: 9810 case RTL_VER_07: 9811 tp->mii.supports_gmii = 0; 9812 break; 9813 default: 9814 tp->mii.supports_gmii = 1; 9815 break; 9816 } 9817 9818 ret = rtl_ops_init(tp); 9819 if (ret) 9820 goto out; 9821 9822 rtl_fw_init(tp); 9823 9824 mutex_init(&tp->control); 9825 INIT_DELAYED_WORK(&tp->schedule, rtl_work_func_t); 9826 INIT_DELAYED_WORK(&tp->hw_phy_work, rtl_hw_phy_work_func_t); 9827 tasklet_setup(&tp->tx_tl, bottom_half); 9828 tasklet_disable(&tp->tx_tl); 9829 9830 netdev->netdev_ops = &rtl8152_netdev_ops; 9831 netdev->watchdog_timeo = RTL8152_TX_TIMEOUT; 9832 9833 netdev->features |= NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 9834 NETIF_F_TSO | NETIF_F_FRAGLIST | NETIF_F_IPV6_CSUM | 9835 NETIF_F_TSO6 | NETIF_F_HW_VLAN_CTAG_RX | 9836 NETIF_F_HW_VLAN_CTAG_TX; 9837 netdev->hw_features = NETIF_F_RXCSUM | NETIF_F_IP_CSUM | NETIF_F_SG | 9838 NETIF_F_TSO | NETIF_F_FRAGLIST | 9839 NETIF_F_IPV6_CSUM | NETIF_F_TSO6 | 9840 NETIF_F_HW_VLAN_CTAG_RX | NETIF_F_HW_VLAN_CTAG_TX; 9841 netdev->vlan_features = NETIF_F_SG | NETIF_F_IP_CSUM | NETIF_F_TSO | 9842 NETIF_F_HIGHDMA | NETIF_F_FRAGLIST | 9843 NETIF_F_IPV6_CSUM | NETIF_F_TSO6; 9844 9845 if (tp->version == RTL_VER_01) { 9846 netdev->features &= ~NETIF_F_RXCSUM; 9847 netdev->hw_features &= ~NETIF_F_RXCSUM; 9848 } 9849 9850 tp->lenovo_macpassthru = rtl8152_supports_lenovo_macpassthru(udev); 9851 9852 if (le16_to_cpu(udev->descriptor.bcdDevice) == 0x3011 && udev->serial && 9853 (!strcmp(udev->serial, "000001000000") || 9854 !strcmp(udev->serial, "000002000000"))) { 9855 dev_info(&udev->dev, "Dell TB16 Dock, disable RX aggregation"); 9856 tp->dell_tb_rx_agg_bug = 1; 9857 } 9858 9859 netdev->ethtool_ops = &ops; 9860 netif_set_tso_max_size(netdev, RTL_LIMITED_TSO_SIZE); 9861 9862 /* MTU range: 68 - 1500 or 9194 */ 9863 netdev->min_mtu = ETH_MIN_MTU; 9864 switch (tp->version) { 9865 case RTL_VER_03: 9866 case RTL_VER_04: 9867 case RTL_VER_05: 9868 case RTL_VER_06: 9869 case RTL_VER_08: 9870 case RTL_VER_09: 9871 case RTL_VER_14: 9872 netdev->max_mtu = size_to_mtu(9 * 1024); 9873 break; 9874 case RTL_VER_10: 9875 case RTL_VER_11: 9876 netdev->max_mtu = size_to_mtu(15 * 1024); 9877 break; 9878 case RTL_VER_12: 9879 case RTL_VER_13: 9880 case RTL_VER_15: 9881 netdev->max_mtu = size_to_mtu(16 * 1024); 9882 break; 9883 case RTL_VER_01: 9884 case RTL_VER_02: 9885 case RTL_VER_07: 9886 default: 9887 netdev->max_mtu = ETH_DATA_LEN; 9888 break; 9889 } 9890 9891 tp->mii.dev = netdev; 9892 tp->mii.mdio_read = read_mii_word; 9893 tp->mii.mdio_write = write_mii_word; 9894 tp->mii.phy_id_mask = 0x3f; 9895 tp->mii.reg_num_mask = 0x1f; 9896 tp->mii.phy_id = R8152_PHY_ID; 9897 9898 tp->autoneg = AUTONEG_ENABLE; 9899 tp->speed = SPEED_100; 9900 tp->advertising = RTL_ADVERTISED_10_HALF | RTL_ADVERTISED_10_FULL | 9901 RTL_ADVERTISED_100_HALF | RTL_ADVERTISED_100_FULL; 9902 if (tp->mii.supports_gmii) { 9903 if (tp->support_2500full && 9904 tp->udev->speed >= USB_SPEED_SUPER) { 9905 tp->speed = SPEED_2500; 9906 tp->advertising |= RTL_ADVERTISED_2500_FULL; 9907 } else { 9908 tp->speed = SPEED_1000; 9909 } 9910 tp->advertising |= RTL_ADVERTISED_1000_FULL; 9911 } 9912 tp->duplex = DUPLEX_FULL; 9913 9914 tp->rx_copybreak = RTL8152_RXFG_HEADSZ; 9915 tp->rx_pending = 10 * RTL8152_MAX_RX; 9916 9917 intf->needs_remote_wakeup = 1; 9918 9919 if (!rtl_can_wakeup(tp)) 9920 __rtl_set_wol(tp, 0); 9921 else 9922 tp->saved_wolopts = __rtl_get_wol(tp); 9923 9924 tp->rtl_ops.init(tp); 9925#if IS_BUILTIN(CONFIG_USB_RTL8152) 9926 /* Retry in case request_firmware() is not ready yet. */ 9927 tp->rtl_fw.retry = true; 9928#endif 9929 queue_delayed_work(system_long_wq, &tp->hw_phy_work, 0); 9930 set_ethernet_addr(tp, false); 9931 9932 usb_set_intfdata(intf, tp); 9933 9934 netif_napi_add(netdev, &tp->napi, r8152_poll); 9935 9936 ret = register_netdev(netdev); 9937 if (ret != 0) { 9938 dev_err(&intf->dev, "couldn't register the device\n"); 9939 goto out1; 9940 } 9941 9942 if (tp->saved_wolopts) 9943 device_set_wakeup_enable(&udev->dev, true); 9944 else 9945 device_set_wakeup_enable(&udev->dev, false); 9946 9947 /* If we saw a control transfer error while probing then we may 9948 * want to try probe() again. Consider this an error. 9949 */ 9950 if (test_bit(PROBE_SHOULD_RETRY, &tp->flags)) 9951 goto out2; 9952 9953 set_bit(PROBED_WITH_NO_ERRORS, &tp->flags); 9954 netif_info(tp, probe, netdev, "%s\n", DRIVER_VERSION); 9955 9956 return 0; 9957 9958out2: 9959 unregister_netdev(netdev); 9960 9961out1: 9962 tasklet_kill(&tp->tx_tl); 9963 cancel_delayed_work_sync(&tp->hw_phy_work); 9964 if (tp->rtl_ops.unload) 9965 tp->rtl_ops.unload(tp); 9966 rtl8152_release_firmware(tp); 9967 usb_set_intfdata(intf, NULL); 9968out: 9969 if (test_bit(PROBE_SHOULD_RETRY, &tp->flags)) 9970 ret = -EAGAIN; 9971 9972 free_netdev(netdev); 9973 return ret; 9974} 9975 9976#define RTL8152_PROBE_TRIES 3 9977 9978static int rtl8152_probe(struct usb_interface *intf, 9979 const struct usb_device_id *id) 9980{ 9981 u8 version; 9982 int ret; 9983 int i; 9984 9985 if (intf->cur_altsetting->desc.bInterfaceClass != USB_CLASS_VENDOR_SPEC) 9986 return -ENODEV; 9987 9988 if (!rtl_check_vendor_ok(intf)) 9989 return -ENODEV; 9990 9991 version = rtl8152_get_version(intf); 9992 if (version == RTL_VER_UNKNOWN) 9993 return -ENODEV; 9994 9995 for (i = 0; i < RTL8152_PROBE_TRIES; i++) { 9996 ret = rtl8152_probe_once(intf, id, version); 9997 if (ret != -EAGAIN) 9998 break; 9999 } 10000 if (ret == -EAGAIN) { 10001 dev_err(&intf->dev, 10002 "r8152 failed probe after %d tries; giving up\n", i); 10003 return -ENODEV; 10004 } 10005 10006 return ret; 10007} 10008 10009static void rtl8152_disconnect(struct usb_interface *intf) 10010{ 10011 struct r8152 *tp = usb_get_intfdata(intf); 10012 10013 usb_set_intfdata(intf, NULL); 10014 if (tp) { 10015 rtl_set_unplug(tp); 10016 10017 unregister_netdev(tp->netdev); 10018 tasklet_kill(&tp->tx_tl); 10019 cancel_delayed_work_sync(&tp->hw_phy_work); 10020 if (tp->rtl_ops.unload) 10021 tp->rtl_ops.unload(tp); 10022 rtl8152_release_firmware(tp); 10023 free_netdev(tp->netdev); 10024 } 10025} 10026 10027/* table of devices that work with this driver */ 10028static const struct usb_device_id rtl8152_table[] = { 10029 /* Realtek */ 10030 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8050) }, 10031 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8053) }, 10032 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8152) }, 10033 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8153) }, 10034 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8155) }, 10035 { USB_DEVICE(VENDOR_ID_REALTEK, 0x8156) }, 10036 10037 /* Microsoft */ 10038 { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07ab) }, 10039 { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x07c6) }, 10040 { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0927) }, 10041 { USB_DEVICE(VENDOR_ID_MICROSOFT, 0x0c5e) }, 10042 { USB_DEVICE(VENDOR_ID_SAMSUNG, 0xa101) }, 10043 10044 /* Lenovo */ 10045 { USB_DEVICE(VENDOR_ID_LENOVO, 0x304f) }, 10046 { USB_DEVICE(VENDOR_ID_LENOVO, 0x3054) }, 10047 { USB_DEVICE(VENDOR_ID_LENOVO, 0x3062) }, 10048 { USB_DEVICE(VENDOR_ID_LENOVO, 0x3069) }, 10049 { USB_DEVICE(VENDOR_ID_LENOVO, 0x3082) }, 10050 { USB_DEVICE(VENDOR_ID_LENOVO, 0x3098) }, 10051 { USB_DEVICE(VENDOR_ID_LENOVO, 0x7205) }, 10052 { USB_DEVICE(VENDOR_ID_LENOVO, 0x720c) }, 10053 { USB_DEVICE(VENDOR_ID_LENOVO, 0x7214) }, 10054 { USB_DEVICE(VENDOR_ID_LENOVO, 0x721e) }, 10055 { USB_DEVICE(VENDOR_ID_LENOVO, 0xa359) }, 10056 { USB_DEVICE(VENDOR_ID_LENOVO, 0xa387) }, 10057 10058 { USB_DEVICE(VENDOR_ID_LINKSYS, 0x0041) }, 10059 { USB_DEVICE(VENDOR_ID_NVIDIA, 0x09ff) }, 10060 { USB_DEVICE(VENDOR_ID_TPLINK, 0x0601) }, 10061 { USB_DEVICE(VENDOR_ID_TPLINK, 0x0602) }, 10062 { USB_DEVICE(VENDOR_ID_DLINK, 0xb301) }, 10063 { USB_DEVICE(VENDOR_ID_DELL, 0xb097) }, 10064 { USB_DEVICE(VENDOR_ID_ASUS, 0x1976) }, 10065 { USB_DEVICE(VENDOR_ID_TRENDNET, 0xe02b) }, 10066 {} 10067}; 10068 10069MODULE_DEVICE_TABLE(usb, rtl8152_table); 10070 10071static struct usb_driver rtl8152_driver = { 10072 .name = MODULENAME, 10073 .id_table = rtl8152_table, 10074 .probe = rtl8152_probe, 10075 .disconnect = rtl8152_disconnect, 10076 .suspend = rtl8152_suspend, 10077 .resume = rtl8152_resume, 10078 .reset_resume = rtl8152_reset_resume, 10079 .pre_reset = rtl8152_pre_reset, 10080 .post_reset = rtl8152_post_reset, 10081 .supports_autosuspend = 1, 10082 .disable_hub_initiated_lpm = 1, 10083}; 10084 10085static int rtl8152_cfgselector_choose_configuration(struct usb_device *udev) 10086{ 10087 struct usb_host_config *c; 10088 int i, num_configs; 10089 10090 /* Switch the device to vendor mode, if and only if the vendor mode 10091 * driver supports it. 10092 */ 10093 if (__rtl_get_hw_ver(udev) == RTL_VER_UNKNOWN) 10094 return -ENODEV; 10095 10096 /* The vendor mode is not always config #1, so to find it out. */ 10097 c = udev->config; 10098 num_configs = udev->descriptor.bNumConfigurations; 10099 for (i = 0; i < num_configs; (i++, c++)) { 10100 struct usb_interface_descriptor *desc = NULL; 10101 10102 if (!c->desc.bNumInterfaces) 10103 continue; 10104 desc = &c->intf_cache[0]->altsetting->desc; 10105 if (desc->bInterfaceClass == USB_CLASS_VENDOR_SPEC) 10106 break; 10107 } 10108 10109 if (i == num_configs) 10110 return -ENODEV; 10111 10112 return c->desc.bConfigurationValue; 10113} 10114 10115static struct usb_device_driver rtl8152_cfgselector_driver = { 10116 .name = MODULENAME "-cfgselector", 10117 .choose_configuration = rtl8152_cfgselector_choose_configuration, 10118 .id_table = rtl8152_table, 10119 .generic_subclass = 1, 10120 .supports_autosuspend = 1, 10121}; 10122 10123static int __init rtl8152_driver_init(void) 10124{ 10125 int ret; 10126 10127 ret = usb_register_device_driver(&rtl8152_cfgselector_driver, THIS_MODULE); 10128 if (ret) 10129 return ret; 10130 10131 ret = usb_register(&rtl8152_driver); 10132 if (ret) 10133 usb_deregister_device_driver(&rtl8152_cfgselector_driver); 10134 10135 return ret; 10136} 10137 10138static void __exit rtl8152_driver_exit(void) 10139{ 10140 usb_deregister(&rtl8152_driver); 10141 usb_deregister_device_driver(&rtl8152_cfgselector_driver); 10142} 10143 10144module_init(rtl8152_driver_init); 10145module_exit(rtl8152_driver_exit); 10146 10147MODULE_AUTHOR(DRIVER_AUTHOR); 10148MODULE_DESCRIPTION(DRIVER_DESC); 10149MODULE_LICENSE("GPL"); 10150MODULE_VERSION(DRIVER_VERSION);
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