pd692x0.c

   1// SPDX-License-Identifier: GPL-2.0-only
   2/*
   3 * Driver for the Microchip PD692X0 PoE PSE Controller driver (I2C bus)
   4 *
   5 * Copyright (c) 2023 Bootlin, Kory Maincent <kory.maincent@bootlin.com>
   6 */
   7
   8#include <linux/delay.h>
   9#include <linux/firmware.h>
  10#include <linux/i2c.h>
  11#include <linux/module.h>
  12#include <linux/of.h>
  13#include <linux/platform_device.h>
  14#include <linux/pse-pd/pse.h>
  15#include <linux/regulator/driver.h>
  16#include <linux/regulator/machine.h>
  17
  18#define PD692X0_PSE_NAME "pd692x0_pse"
  19
  20#define PD692X0_MAX_PIS	48
  21#define PD692X0_MAX_MANAGERS		12
  22#define PD692X0_MAX_MANAGER_PORTS	8
  23#define PD692X0_MAX_HW_PORTS	(PD692X0_MAX_MANAGERS * PD692X0_MAX_MANAGER_PORTS)
  24
  25#define PD69200_BT_PROD_VER	24
  26#define PD69210_BT_PROD_VER	26
  27#define PD69220_BT_PROD_VER	29
  28
  29#define PD692X0_FW_MAJ_VER	3
  30#define PD692X0_FW_MIN_VER	5
  31#define PD692X0_FW_PATCH_VER	5
  32
  33#define PD692X0_USER_BYTE	42
  34
  35enum pd692x0_fw_state {
  36	PD692X0_FW_UNKNOWN,
  37	PD692X0_FW_OK,
  38	PD692X0_FW_BROKEN,
  39	PD692X0_FW_NEED_UPDATE,
  40	PD692X0_FW_PREPARE,
  41	PD692X0_FW_WRITE,
  42	PD692X0_FW_COMPLETE,
  43};
  44
  45struct pd692x0_msg {
  46	u8 key;
  47	u8 echo;
  48	u8 sub[3];
  49	u8 data[8];
  50	__be16 chksum;
  51} __packed;
  52
  53struct pd692x0_msg_ver {
  54	u8 prod;
  55	u8 maj_sw_ver;
  56	u8 min_sw_ver;
  57	u8 pa_sw_ver;
  58	u8 param;
  59	u8 build;
  60};
  61
  62enum {
  63	PD692X0_KEY_CMD,
  64	PD692X0_KEY_PRG,
  65	PD692X0_KEY_REQ,
  66	PD692X0_KEY_TLM,
  67	PD692X0_KEY_TEST,
  68	PD692X0_KEY_REPORT = 0x52
  69};
  70
  71enum {
  72	PD692X0_MSG_RESET,
  73	PD692X0_MSG_GET_SYS_STATUS,
  74	PD692X0_MSG_GET_SW_VER,
  75	PD692X0_MSG_SET_TMP_PORT_MATRIX,
  76	PD692X0_MSG_PRG_PORT_MATRIX,
  77	PD692X0_MSG_SET_PORT_PARAM,
  78	PD692X0_MSG_GET_PORT_STATUS,
  79	PD692X0_MSG_DOWNLOAD_CMD,
  80	PD692X0_MSG_GET_PORT_CLASS,
  81	PD692X0_MSG_GET_PORT_MEAS,
  82	PD692X0_MSG_GET_PORT_PARAM,
  83	PD692X0_MSG_GET_POWER_BANK,
  84	PD692X0_MSG_SET_POWER_BANK,
  85	PD692X0_MSG_SET_USER_BYTE,
  86
  87	/* add new message above here */
  88	PD692X0_MSG_CNT
  89};
  90
  91struct pd692x0_matrix {
  92	u8 hw_port_a;
  93	u8 hw_port_b;
  94};
  95
  96struct pd692x0_priv {
  97	struct i2c_client *client;
  98	struct pse_controller_dev pcdev;
  99	struct device_node *np;
 100
 101	enum pd692x0_fw_state fw_state;
 102	struct fw_upload *fwl;
 103	bool cancel_request;
 104
 105	u8 msg_id;
 106	bool last_cmd_key;
 107	unsigned long last_cmd_key_time;
 108
 109	bool cfg_saved;
 110	enum ethtool_c33_pse_admin_state admin_state[PD692X0_MAX_PIS];
 111	struct regulator_dev *manager_reg[PD692X0_MAX_MANAGERS];
 112	int manager_pw_budget[PD692X0_MAX_MANAGERS];
 113	int nmanagers;
 114	struct pd692x0_matrix *port_matrix;
 115};
 116
 117/* Template list of communication messages. The non-null bytes defined here
 118 * constitute the fixed portion of the messages. The remaining bytes will
 119 * be configured later within the functions. Refer to the "PD692x0 BT Serial
 120 * Communication Protocol User Guide" for comprehensive details on messages
 121 * content.
 122 */
 123static const struct pd692x0_msg pd692x0_msg_template_list[PD692X0_MSG_CNT] = {
 124	[PD692X0_MSG_RESET] = {
 125		.key = PD692X0_KEY_CMD,
 126		.sub = {0x07, 0x55, 0x00},
 127		.data = {0x55, 0x00, 0x55, 0x4e,
 128			 0x4e, 0x4e, 0x4e, 0x4e},
 129	},
 130	[PD692X0_MSG_GET_SYS_STATUS] = {
 131		.key = PD692X0_KEY_REQ,
 132		.sub = {0x07, 0xd0, 0x4e},
 133		.data = {0x4e, 0x4e, 0x4e, 0x4e,
 134			 0x4e, 0x4e, 0x4e, 0x4e},
 135	},
 136	[PD692X0_MSG_GET_SW_VER] = {
 137		.key = PD692X0_KEY_REQ,
 138		.sub = {0x07, 0x1e, 0x21},
 139		.data = {0x4e, 0x4e, 0x4e, 0x4e,
 140			 0x4e, 0x4e, 0x4e, 0x4e},
 141	},
 142	[PD692X0_MSG_SET_TMP_PORT_MATRIX] = {
 143		.key = PD692X0_KEY_CMD,
 144		.sub	 = {0x05, 0x43},
 145		.data = {   0, 0x4e, 0x4e, 0x4e,
 146			 0x4e, 0x4e, 0x4e, 0x4e},
 147	},
 148	[PD692X0_MSG_PRG_PORT_MATRIX] = {
 149		.key = PD692X0_KEY_CMD,
 150		.sub = {0x07, 0x43, 0x4e},
 151		.data = {0x4e, 0x4e, 0x4e, 0x4e,
 152			 0x4e, 0x4e, 0x4e, 0x4e},
 153	},
 154	[PD692X0_MSG_SET_PORT_PARAM] = {
 155		.key = PD692X0_KEY_CMD,
 156		.sub = {0x05, 0xc0},
 157		.data = { 0xf, 0xff, 0xff, 0xff,
 158			 0x4e, 0x4e, 0x4e, 0x4e},
 159	},
 160	[PD692X0_MSG_GET_PORT_STATUS] = {
 161		.key = PD692X0_KEY_REQ,
 162		.sub = {0x05, 0xc1},
 163		.data = {0x4e, 0x4e, 0x4e, 0x4e,
 164			 0x4e, 0x4e, 0x4e, 0x4e},
 165	},
 166	[PD692X0_MSG_DOWNLOAD_CMD] = {
 167		.key = PD692X0_KEY_PRG,
 168		.sub = {0xff, 0x99, 0x15},
 169		.data = {0x16, 0x16, 0x99, 0x4e,
 170			 0x4e, 0x4e, 0x4e, 0x4e},
 171	},
 172	[PD692X0_MSG_GET_PORT_CLASS] = {
 173		.key = PD692X0_KEY_REQ,
 174		.sub = {0x05, 0xc4},
 175		.data = {0x4e, 0x4e, 0x4e, 0x4e,
 176			 0x4e, 0x4e, 0x4e, 0x4e},
 177	},
 178	[PD692X0_MSG_GET_PORT_MEAS] = {
 179		.key = PD692X0_KEY_REQ,
 180		.sub = {0x05, 0xc5},
 181		.data = {0x4e, 0x4e, 0x4e, 0x4e,
 182			 0x4e, 0x4e, 0x4e, 0x4e},
 183	},
 184	[PD692X0_MSG_GET_PORT_PARAM] = {
 185		.key = PD692X0_KEY_REQ,
 186		.sub = {0x05, 0xc0},
 187		.data = {0x4e, 0x4e, 0x4e, 0x4e,
 188			 0x4e, 0x4e, 0x4e, 0x4e},
 189	},
 190	[PD692X0_MSG_GET_POWER_BANK] = {
 191		.key = PD692X0_KEY_REQ,
 192		.sub = {0x07, 0x0b, 0x57},
 193		.data = {   0, 0x4e, 0x4e, 0x4e,
 194			 0x4e, 0x4e, 0x4e, 0x4e},
 195	},
 196	[PD692X0_MSG_SET_POWER_BANK] = {
 197		.key = PD692X0_KEY_CMD,
 198		.sub = {0x07, 0x0b, 0x57},
 199	},
 200	[PD692X0_MSG_SET_USER_BYTE] = {
 201		.key = PD692X0_KEY_PRG,
 202		.sub = {0x41, PD692X0_USER_BYTE},
 203		.data = {0x4e, 0x4e, 0x4e, 0x4e,
 204			 0x4e, 0x4e, 0x4e, 0x4e},
 205	},
 206};
 207
 208static u8 pd692x0_build_msg(struct pd692x0_msg *msg, u8 echo)
 209{
 210	u8 *data = (u8 *)msg;
 211	u16 chksum = 0;
 212	int i;
 213
 214	msg->echo = echo++;
 215	if (echo == 0xff)
 216		echo = 0;
 217
 218	for (i = 0; i < sizeof(*msg) - sizeof(msg->chksum); i++)
 219		chksum += data[i];
 220
 221	msg->chksum = cpu_to_be16(chksum);
 222
 223	return echo;
 224}
 225
 226static int pd692x0_send_msg(struct pd692x0_priv *priv, struct pd692x0_msg *msg)
 227{
 228	const struct i2c_client *client = priv->client;
 229	int ret;
 230
 231	if (msg->key == PD692X0_KEY_CMD && priv->last_cmd_key) {
 232		int cmd_msleep;
 233
 234		cmd_msleep = 30 - jiffies_to_msecs(jiffies - priv->last_cmd_key_time);
 235		if (cmd_msleep > 0)
 236			msleep(cmd_msleep);
 237	}
 238
 239	/* Add echo and checksum bytes to the message */
 240	priv->msg_id = pd692x0_build_msg(msg, priv->msg_id);
 241
 242	ret = i2c_master_send(client, (u8 *)msg, sizeof(*msg));
 243	if (ret != sizeof(*msg))
 244		return -EIO;
 245
 246	return 0;
 247}
 248
 249static int pd692x0_reset(struct pd692x0_priv *priv)
 250{
 251	const struct i2c_client *client = priv->client;
 252	struct pd692x0_msg msg, buf = {0};
 253	int ret;
 254
 255	msg = pd692x0_msg_template_list[PD692X0_MSG_RESET];
 256	ret = pd692x0_send_msg(priv, &msg);
 257	if (ret) {
 258		dev_err(&client->dev,
 259			"Failed to reset the controller (%pe)\n", ERR_PTR(ret));
 260		return ret;
 261	}
 262
 263	msleep(30);
 264
 265	ret = i2c_master_recv(client, (u8 *)&buf, sizeof(buf));
 266	if (ret != sizeof(buf))
 267		return ret < 0 ? ret : -EIO;
 268
 269	/* Is the reply a successful report message */
 270	if (buf.key != PD692X0_KEY_REPORT || buf.sub[0] || buf.sub[1])
 271		return -EIO;
 272
 273	msleep(300);
 274
 275	ret = i2c_master_recv(client, (u8 *)&buf, sizeof(buf));
 276	if (ret != sizeof(buf))
 277		return ret < 0 ? ret : -EIO;
 278
 279	/* Is the boot status without error */
 280	if (buf.key != 0x03 || buf.echo != 0xff || buf.sub[0] & 0x1) {
 281		dev_err(&client->dev, "PSE controller error\n");
 282		return -EIO;
 283	}
 284
 285	return 0;
 286}
 287
 288static bool pd692x0_try_recv_msg(const struct i2c_client *client,
 289				 struct pd692x0_msg *msg,
 290				 struct pd692x0_msg *buf)
 291{
 292	/* Wait 30ms before readback as mandated by the protocol */
 293	msleep(30);
 294
 295	memset(buf, 0, sizeof(*buf));
 296	i2c_master_recv(client, (u8 *)buf, sizeof(*buf));
 297	if (buf->key)
 298		return 0;
 299
 300	msleep(100);
 301
 302	memset(buf, 0, sizeof(*buf));
 303	i2c_master_recv(client, (u8 *)buf, sizeof(*buf));
 304	if (buf->key)
 305		return 0;
 306
 307	return 1;
 308}
 309
 310/* Implementation of I2C communication, specifically addressing scenarios
 311 * involving communication loss. Refer to the "Synchronization During
 312 * Communication Loss" section in the Communication Protocol document for
 313 * further details.
 314 */
 315static int pd692x0_recv_msg(struct pd692x0_priv *priv,
 316			    struct pd692x0_msg *msg,
 317			    struct pd692x0_msg *buf)
 318{
 319	const struct i2c_client *client = priv->client;
 320	int ret;
 321
 322	ret = pd692x0_try_recv_msg(client, msg, buf);
 323	if (!ret)
 324		goto out_success;
 325
 326	dev_warn(&client->dev,
 327		 "Communication lost, rtnl is locked until communication is back!");
 328
 329	ret = pd692x0_send_msg(priv, msg);
 330	if (ret)
 331		return ret;
 332
 333	ret = pd692x0_try_recv_msg(client, msg, buf);
 334	if (!ret)
 335		goto out_success2;
 336
 337	msleep(10000);
 338
 339	ret = pd692x0_send_msg(priv, msg);
 340	if (ret)
 341		return ret;
 342
 343	ret = pd692x0_try_recv_msg(client, msg, buf);
 344	if (!ret)
 345		goto out_success2;
 346
 347	return pd692x0_reset(priv);
 348
 349out_success2:
 350	dev_warn(&client->dev, "Communication is back, rtnl is unlocked!");
 351out_success:
 352	if (msg->key == PD692X0_KEY_CMD) {
 353		priv->last_cmd_key = true;
 354		priv->last_cmd_key_time = jiffies;
 355	} else {
 356		priv->last_cmd_key = false;
 357	}
 358
 359	return 0;
 360}
 361
 362static int pd692x0_sendrecv_msg(struct pd692x0_priv *priv,
 363				struct pd692x0_msg *msg,
 364				struct pd692x0_msg *buf)
 365{
 366	struct device *dev = &priv->client->dev;
 367	int ret;
 368
 369	ret = pd692x0_send_msg(priv, msg);
 370	if (ret)
 371		return ret;
 372
 373	ret = pd692x0_recv_msg(priv, msg, buf);
 374	if (ret)
 375		return ret;
 376
 377	if (msg->echo != buf->echo) {
 378		dev_err(dev,
 379			"Wrong match in message ID, expect %d received %d.\n",
 380			msg->echo, buf->echo);
 381		return -EIO;
 382	}
 383
 384	/* If the reply is a report message is it successful */
 385	if (buf->key == PD692X0_KEY_REPORT &&
 386	    (buf->sub[0] || buf->sub[1])) {
 387		return -EIO;
 388	}
 389
 390	return 0;
 391}
 392
 393static struct pd692x0_priv *to_pd692x0_priv(struct pse_controller_dev *pcdev)
 394{
 395	return container_of(pcdev, struct pd692x0_priv, pcdev);
 396}
 397
 398static int pd692x0_fw_unavailable(struct pd692x0_priv *priv)
 399{
 400	switch (priv->fw_state) {
 401	case PD692X0_FW_OK:
 402		return 0;
 403	case PD692X0_FW_PREPARE:
 404	case PD692X0_FW_WRITE:
 405	case PD692X0_FW_COMPLETE:
 406		dev_err(&priv->client->dev, "Firmware update in progress!\n");
 407		return -EBUSY;
 408	case PD692X0_FW_BROKEN:
 409	case PD692X0_FW_NEED_UPDATE:
 410	default:
 411		dev_err(&priv->client->dev,
 412			"Firmware issue. Please update it!\n");
 413		return -EOPNOTSUPP;
 414	}
 415}
 416
 417static int pd692x0_pi_enable(struct pse_controller_dev *pcdev, int id)
 418{
 419	struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
 420	struct pd692x0_msg msg, buf = {0};
 421	int ret;
 422
 423	ret = pd692x0_fw_unavailable(priv);
 424	if (ret)
 425		return ret;
 426
 427	if (priv->admin_state[id] == ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED)
 428		return 0;
 429
 430	msg = pd692x0_msg_template_list[PD692X0_MSG_SET_PORT_PARAM];
 431	msg.data[0] = 0x1;
 432	msg.sub[2] = id;
 433	ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
 434	if (ret < 0)
 435		return ret;
 436
 437	priv->admin_state[id] = ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED;
 438
 439	return 0;
 440}
 441
 442static int pd692x0_pi_disable(struct pse_controller_dev *pcdev, int id)
 443{
 444	struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
 445	struct pd692x0_msg msg, buf = {0};
 446	int ret;
 447
 448	ret = pd692x0_fw_unavailable(priv);
 449	if (ret)
 450		return ret;
 451
 452	if (priv->admin_state[id] == ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED)
 453		return 0;
 454
 455	msg = pd692x0_msg_template_list[PD692X0_MSG_SET_PORT_PARAM];
 456	msg.data[0] = 0x0;
 457	msg.sub[2] = id;
 458	ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
 459	if (ret < 0)
 460		return ret;
 461
 462	priv->admin_state[id] = ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED;
 463
 464	return 0;
 465}
 466
 467struct pd692x0_pse_ext_state_mapping {
 468	u32 status_code;
 469	enum ethtool_c33_pse_ext_state pse_ext_state;
 470	u32 pse_ext_substate;
 471};
 472
 473static const struct pd692x0_pse_ext_state_mapping
 474pd692x0_pse_ext_state_map[] = {
 475	{0x06, ETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM,
 476		ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_HIGH_VOLTAGE},
 477	{0x07, ETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM,
 478		ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_LOW_VOLTAGE},
 479	{0x08, ETHTOOL_C33_PSE_EXT_STATE_MR_PSE_ENABLE,
 480		ETHTOOL_C33_PSE_EXT_SUBSTATE_MR_PSE_ENABLE_DISABLE_PIN_ACTIVE},
 481	{0x0C, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION,
 482		ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_NON_EXISTING_PORT},
 483	{0x11, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION,
 484		ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNDEFINED_PORT},
 485	{0x12, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION,
 486		ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_INTERNAL_HW_FAULT},
 487	{0x1B, ETHTOOL_C33_PSE_EXT_STATE_OPTION_DETECT_TED,
 488		ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_DET_IN_PROCESS},
 489	{0x1C, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION,
 490		ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS},
 491	{0x1E, ETHTOOL_C33_PSE_EXT_STATE_MR_MPS_VALID,
 492		ETHTOOL_C33_PSE_EXT_SUBSTATE_MR_MPS_VALID_DETECTED_UNDERLOAD},
 493	{0x1F, ETHTOOL_C33_PSE_EXT_STATE_OVLD_DETECTED,
 494		ETHTOOL_C33_PSE_EXT_SUBSTATE_OVLD_DETECTED_OVERLOAD},
 495	{0x20, ETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE,
 496		ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_BUDGET_EXCEEDED},
 497	{0x21, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION,
 498		ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_INTERNAL_HW_FAULT},
 499	{0x22, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION,
 500		ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_CONFIG_CHANGE},
 501	{0x24, ETHTOOL_C33_PSE_EXT_STATE_OPTION_VPORT_LIM,
 502		ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_VPORT_LIM_VOLTAGE_INJECTION},
 503	{0x25, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION,
 504		ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS},
 505	{0x34, ETHTOOL_C33_PSE_EXT_STATE_SHORT_DETECTED,
 506		ETHTOOL_C33_PSE_EXT_SUBSTATE_SHORT_DETECTED_SHORT_CONDITION},
 507	{0x35, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION,
 508		ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_DETECTED_OVER_TEMP},
 509	{0x36, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION,
 510		ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_DETECTED_OVER_TEMP},
 511	{0x37, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION,
 512		ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS},
 513	{0x3C, ETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE,
 514		ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PORT_PW_LIMIT_EXCEEDS_CONTROLLER_BUDGET},
 515	{0x3D, ETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE,
 516		ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_PD_REQUEST_EXCEEDS_PORT_LIMIT},
 517	{0x41, ETHTOOL_C33_PSE_EXT_STATE_POWER_NOT_AVAILABLE,
 518		ETHTOOL_C33_PSE_EXT_SUBSTATE_POWER_NOT_AVAILABLE_HW_PW_LIMIT},
 519	{0x43, ETHTOOL_C33_PSE_EXT_STATE_ERROR_CONDITION,
 520		ETHTOOL_C33_PSE_EXT_SUBSTATE_ERROR_CONDITION_UNKNOWN_PORT_STATUS},
 521	{0xA7, ETHTOOL_C33_PSE_EXT_STATE_OPTION_DETECT_TED,
 522		ETHTOOL_C33_PSE_EXT_SUBSTATE_OPTION_DETECT_TED_CONNECTION_CHECK_ERROR},
 523	{0xA8, ETHTOOL_C33_PSE_EXT_STATE_MR_MPS_VALID,
 524		ETHTOOL_C33_PSE_EXT_SUBSTATE_MR_MPS_VALID_CONNECTION_OPEN},
 525	{ /* sentinel */ }
 526};
 527
 528static int
 529pd692x0_pi_get_ext_state(struct pse_controller_dev *pcdev, int id,
 530			 struct pse_ext_state_info *ext_state_info)
 531{
 532	struct ethtool_c33_pse_ext_state_info *c33_ext_state_info;
 533	const struct pd692x0_pse_ext_state_mapping *ext_state_map;
 534	struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
 535	struct pd692x0_msg msg, buf = {0};
 536	int ret;
 537
 538	ret = pd692x0_fw_unavailable(priv);
 539	if (ret)
 540		return ret;
 541
 542	msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS];
 543	msg.sub[2] = id;
 544	ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
 545	if (ret < 0)
 546		return ret;
 547
 548	c33_ext_state_info = &ext_state_info->c33_ext_state_info;
 549	ext_state_map = pd692x0_pse_ext_state_map;
 550	while (ext_state_map->status_code) {
 551		if (ext_state_map->status_code == buf.sub[0]) {
 552			c33_ext_state_info->c33_pse_ext_state = ext_state_map->pse_ext_state;
 553			c33_ext_state_info->__c33_pse_ext_substate = ext_state_map->pse_ext_substate;
 554			return  0;
 555		}
 556		ext_state_map++;
 557	}
 558
 559	return 0;
 560}
 561
 562struct pd692x0_class_pw {
 563	int class;
 564	int class_cfg_value;
 565	int class_pw;
 566	int max_added_class_pw;
 567};
 568
 569#define PD692X0_CLASS_PW_TABLE_SIZE 4
 570/* 4/2 pairs class configuration power table in compliance mode.
 571 * Need to be arranged in ascending order of power support.
 572 */
 573static const struct pd692x0_class_pw
 574pd692x0_class_pw_table[PD692X0_CLASS_PW_TABLE_SIZE] = {
 575	{.class = 3, .class_cfg_value = 0x3, .class_pw = 15000, .max_added_class_pw = 3100},
 576	{.class = 4, .class_cfg_value = 0x2, .class_pw = 30000, .max_added_class_pw = 8000},
 577	{.class = 6, .class_cfg_value = 0x1, .class_pw = 60000, .max_added_class_pw = 5000},
 578	{.class = 8, .class_cfg_value = 0x0, .class_pw = 90000, .max_added_class_pw = 7500},
 579};
 580
 581static int pd692x0_pi_get_pw_from_table(int op_mode, int added_pw)
 582{
 583	const struct pd692x0_class_pw *pw_table;
 584	int i;
 585
 586	pw_table = pd692x0_class_pw_table;
 587	for (i = 0; i < PD692X0_CLASS_PW_TABLE_SIZE; i++, pw_table++) {
 588		if (pw_table->class_cfg_value == op_mode)
 589			return pw_table->class_pw + added_pw * 100;
 590	}
 591
 592	return -ERANGE;
 593}
 594
 595static int pd692x0_pi_set_pw_from_table(struct device *dev,
 596					struct pd692x0_msg *msg, int pw)
 597{
 598	const struct pd692x0_class_pw *pw_table;
 599	int i;
 600
 601	pw_table = pd692x0_class_pw_table;
 602	if (pw < pw_table->class_pw) {
 603		dev_err(dev,
 604			"Power limit %dmW not supported. Ranges minimal available: [%d-%d]\n",
 605			pw,
 606			pw_table->class_pw,
 607			pw_table->class_pw + pw_table->max_added_class_pw);
 608		return -ERANGE;
 609	}
 610
 611	for (i = 0; i < PD692X0_CLASS_PW_TABLE_SIZE; i++, pw_table++) {
 612		if (pw > (pw_table->class_pw + pw_table->max_added_class_pw))
 613			continue;
 614
 615		if (pw < pw_table->class_pw) {
 616			dev_err(dev,
 617				"Power limit %dmW not supported. Ranges available: [%d-%d] or [%d-%d]\n",
 618				pw,
 619				(pw_table - 1)->class_pw,
 620				(pw_table - 1)->class_pw + (pw_table - 1)->max_added_class_pw,
 621				pw_table->class_pw,
 622				pw_table->class_pw + pw_table->max_added_class_pw);
 623			return -ERANGE;
 624		}
 625
 626		msg->data[2] = pw_table->class_cfg_value;
 627		msg->data[3] = (pw - pw_table->class_pw) / 100;
 628		return 0;
 629	}
 630
 631	pw_table--;
 632	dev_warn(dev,
 633		 "Power limit %dmW not supported. Set to highest power limit %dmW\n",
 634		 pw, pw_table->class_pw + pw_table->max_added_class_pw);
 635	msg->data[2] = pw_table->class_cfg_value;
 636	msg->data[3] = pw_table->max_added_class_pw / 100;
 637	return 0;
 638}
 639
 640static int
 641pd692x0_pi_get_pw_limit_ranges(struct pse_controller_dev *pcdev, int id,
 642			       struct pse_pw_limit_ranges *pw_limit_ranges)
 643{
 644	struct ethtool_c33_pse_pw_limit_range *c33_pw_limit_ranges;
 645	const struct pd692x0_class_pw *pw_table;
 646	int i;
 647
 648	pw_table = pd692x0_class_pw_table;
 649	c33_pw_limit_ranges = kcalloc(PD692X0_CLASS_PW_TABLE_SIZE,
 650				      sizeof(*c33_pw_limit_ranges),
 651				      GFP_KERNEL);
 652	if (!c33_pw_limit_ranges)
 653		return -ENOMEM;
 654
 655	for (i = 0; i < PD692X0_CLASS_PW_TABLE_SIZE; i++, pw_table++) {
 656		c33_pw_limit_ranges[i].min = pw_table->class_pw;
 657		c33_pw_limit_ranges[i].max = pw_table->class_pw +
 658					     pw_table->max_added_class_pw;
 659	}
 660
 661	pw_limit_ranges->c33_pw_limit_ranges = c33_pw_limit_ranges;
 662	return i;
 663}
 664
 665static int
 666pd692x0_pi_get_admin_state(struct pse_controller_dev *pcdev, int id,
 667			   struct pse_admin_state *admin_state)
 668{
 669	struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
 670	struct pd692x0_msg msg, buf = {0};
 671	int ret;
 672
 673	ret = pd692x0_fw_unavailable(priv);
 674	if (ret)
 675		return ret;
 676
 677	msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS];
 678	msg.sub[2] = id;
 679	ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
 680	if (ret < 0)
 681		return ret;
 682
 683	if (buf.sub[1])
 684		admin_state->c33_admin_state =
 685			ETHTOOL_C33_PSE_ADMIN_STATE_ENABLED;
 686	else
 687		admin_state->c33_admin_state =
 688			ETHTOOL_C33_PSE_ADMIN_STATE_DISABLED;
 689
 690	priv->admin_state[id] = admin_state->c33_admin_state;
 691
 692	return 0;
 693}
 694
 695static int
 696pd692x0_pi_get_pw_status(struct pse_controller_dev *pcdev, int id,
 697			 struct pse_pw_status *pw_status)
 698{
 699	struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
 700	struct pd692x0_msg msg, buf = {0};
 701	int ret;
 702
 703	ret = pd692x0_fw_unavailable(priv);
 704	if (ret)
 705		return ret;
 706
 707	msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS];
 708	msg.sub[2] = id;
 709	ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
 710	if (ret < 0)
 711		return ret;
 712
 713	/* Compare Port Status (Communication Protocol Document par. 7.1) */
 714	if ((buf.sub[0] & 0xf0) == 0x80 || (buf.sub[0] & 0xf0) == 0x90)
 715		pw_status->c33_pw_status =
 716			ETHTOOL_C33_PSE_PW_D_STATUS_DELIVERING;
 717	else if (buf.sub[0] == 0x1b || buf.sub[0] == 0x22)
 718		pw_status->c33_pw_status =
 719			ETHTOOL_C33_PSE_PW_D_STATUS_SEARCHING;
 720	else if (buf.sub[0] == 0x12)
 721		pw_status->c33_pw_status =
 722			ETHTOOL_C33_PSE_PW_D_STATUS_FAULT;
 723	else
 724		pw_status->c33_pw_status =
 725			ETHTOOL_C33_PSE_PW_D_STATUS_DISABLED;
 726
 727	return 0;
 728}
 729
 730static int
 731pd692x0_pi_get_pw_class(struct pse_controller_dev *pcdev, int id)
 732{
 733	struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
 734	struct pd692x0_msg msg, buf = {0};
 735	u32 class;
 736	int ret;
 737
 738	ret = pd692x0_fw_unavailable(priv);
 739	if (ret)
 740		return ret;
 741
 742	msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_CLASS];
 743	msg.sub[2] = id;
 744	ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
 745	if (ret < 0)
 746		return ret;
 747
 748	class = buf.data[3] >> 4;
 749	if (class <= 8)
 750		return class;
 751
 752	return 0;
 753}
 754
 755static int
 756pd692x0_pi_get_actual_pw(struct pse_controller_dev *pcdev, int id)
 757{
 758	struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
 759	struct pd692x0_msg msg, buf = {0};
 760	int ret;
 761
 762	ret = pd692x0_fw_unavailable(priv);
 763	if (ret)
 764		return ret;
 765
 766	msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_STATUS];
 767	msg.sub[2] = id;
 768	ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
 769	if (ret < 0)
 770		return ret;
 771
 772	return (buf.data[0] << 4 | buf.data[1]) * 100;
 773}
 774
 775static int
 776pd692x0_pi_get_prio(struct pse_controller_dev *pcdev, int id)
 777{
 778	struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
 779	struct pd692x0_msg msg, buf = {0};
 780	int ret;
 781
 782	ret = pd692x0_fw_unavailable(priv);
 783	if (ret)
 784		return ret;
 785
 786	msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_PARAM];
 787	msg.sub[2] = id;
 788	ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
 789	if (ret < 0)
 790		return ret;
 791	if (!buf.data[2] || buf.data[2] > pcdev->pis_prio_max + 1)
 792		return -ERANGE;
 793
 794	/* PSE core priority start at 0 */
 795	return buf.data[2] - 1;
 796}
 797
 798static struct pd692x0_msg_ver pd692x0_get_sw_version(struct pd692x0_priv *priv)
 799{
 800	struct device *dev = &priv->client->dev;
 801	struct pd692x0_msg msg, buf = {0};
 802	struct pd692x0_msg_ver ver = {0};
 803	int ret;
 804
 805	msg = pd692x0_msg_template_list[PD692X0_MSG_GET_SW_VER];
 806	ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
 807	if (ret < 0) {
 808		dev_err(dev, "Failed to get PSE version (%pe)\n", ERR_PTR(ret));
 809		return ver;
 810	}
 811
 812	/* Extract version from the message */
 813	ver.prod = buf.sub[2];
 814	ver.maj_sw_ver = (buf.data[0] << 8 | buf.data[1]) / 100;
 815	ver.min_sw_ver = ((buf.data[0] << 8 | buf.data[1]) / 10) % 10;
 816	ver.pa_sw_ver = (buf.data[0] << 8 | buf.data[1]) % 10;
 817	ver.param = buf.data[2];
 818	ver.build = buf.data[3];
 819
 820	return ver;
 821}
 822
 823struct pd692x0_manager {
 824	struct device_node *port_node[PD692X0_MAX_MANAGER_PORTS];
 825	struct device_node *node;
 826	int nports;
 827};
 828
 829static int
 830pd692x0_of_get_ports_manager(struct pd692x0_priv *priv,
 831			     struct pd692x0_manager *manager,
 832			     struct device_node *np)
 833{
 834	struct device_node *node;
 835	int ret, nports, i;
 836
 837	nports = 0;
 838	for_each_child_of_node(np, node) {
 839		u32 port;
 840
 841		if (!of_node_name_eq(node, "port"))
 842			continue;
 843
 844		ret = of_property_read_u32(node, "reg", &port);
 845		if (ret)
 846			goto out;
 847
 848		if (port >= PD692X0_MAX_MANAGER_PORTS || port != nports) {
 849			dev_err(&priv->client->dev,
 850				"wrong number or order of manager ports (%d)\n",
 851				port);
 852			ret = -EINVAL;
 853			goto out;
 854		}
 855
 856		of_node_get(node);
 857		manager->port_node[port] = node;
 858		nports++;
 859	}
 860
 861	manager->nports = nports;
 862	return 0;
 863
 864out:
 865	for (i = 0; i < nports; i++) {
 866		of_node_put(manager->port_node[i]);
 867		manager->port_node[i] = NULL;
 868	}
 869	of_node_put(node);
 870	return ret;
 871}
 872
 873static int
 874pd692x0_of_get_managers(struct pd692x0_priv *priv,
 875			struct pd692x0_manager *manager)
 876{
 877	struct device_node *managers_node, *node;
 878	int ret, nmanagers, i, j;
 879
 880	if (!priv->np)
 881		return -EINVAL;
 882
 883	nmanagers = 0;
 884	managers_node = of_get_child_by_name(priv->np, "managers");
 885	if (!managers_node)
 886		return -EINVAL;
 887
 888	for_each_child_of_node(managers_node, node) {
 889		u32 manager_id;
 890
 891		if (!of_node_name_eq(node, "manager"))
 892			continue;
 893
 894		ret = of_property_read_u32(node, "reg", &manager_id);
 895		if (ret)
 896			goto out;
 897
 898		if (manager_id >= PD692X0_MAX_MANAGERS ||
 899		    manager_id != nmanagers) {
 900			dev_err(&priv->client->dev,
 901				"wrong number or order of managers (%d)\n",
 902				manager_id);
 903			ret = -EINVAL;
 904			goto out;
 905		}
 906
 907		ret = pd692x0_of_get_ports_manager(priv, &manager[manager_id],
 908						   node);
 909		if (ret)
 910			goto out;
 911
 912		of_node_get(node);
 913		manager[manager_id].node = node;
 914		nmanagers++;
 915	}
 916
 917	of_node_put(managers_node);
 918	priv->nmanagers = nmanagers;
 919	return 0;
 920
 921out:
 922	for (i = 0; i < nmanagers; i++) {
 923		for (j = 0; j < manager[i].nports; j++) {
 924			of_node_put(manager[i].port_node[j]);
 925			manager[i].port_node[j] = NULL;
 926		}
 927		of_node_put(manager[i].node);
 928		manager[i].node = NULL;
 929	}
 930
 931	of_node_put(node);
 932	of_node_put(managers_node);
 933	return ret;
 934}
 935
 936static const struct regulator_ops dummy_ops;
 937
 938static struct regulator_dev *
 939pd692x0_register_manager_regulator(struct device *dev, char *reg_name,
 940				   struct device_node *node)
 941{
 942	struct regulator_init_data *rinit_data;
 943	struct regulator_config rconfig = {0};
 944	struct regulator_desc *rdesc;
 945	struct regulator_dev *rdev;
 946
 947	rinit_data = devm_kzalloc(dev, sizeof(*rinit_data),
 948				  GFP_KERNEL);
 949	if (!rinit_data)
 950		return ERR_PTR(-ENOMEM);
 951
 952	rdesc = devm_kzalloc(dev, sizeof(*rdesc), GFP_KERNEL);
 953	if (!rdesc)
 954		return ERR_PTR(-ENOMEM);
 955
 956	rdesc->name = reg_name;
 957	rdesc->type = REGULATOR_VOLTAGE;
 958	rdesc->ops = &dummy_ops;
 959	rdesc->owner = THIS_MODULE;
 960
 961	rinit_data->supply_regulator = "vmain";
 962
 963	rconfig.dev = dev;
 964	rconfig.init_data = rinit_data;
 965	rconfig.of_node = node;
 966
 967	rdev = devm_regulator_register(dev, rdesc, &rconfig);
 968	if (IS_ERR(rdev)) {
 969		dev_err_probe(dev, PTR_ERR(rdev),
 970			      "Failed to register regulator\n");
 971		return rdev;
 972	}
 973
 974	return rdev;
 975}
 976
 977static int
 978pd692x0_register_managers_regulator(struct pd692x0_priv *priv,
 979				    const struct pd692x0_manager *manager)
 980{
 981	struct device *dev = &priv->client->dev;
 982	size_t reg_name_len;
 983	int i;
 984
 985	/* Each regulator name len is dev name + 12 char +
 986	 * int max digit number (10) + 1
 987	 */
 988	reg_name_len = strlen(dev_name(dev)) + 23;
 989
 990	for (i = 0; i < priv->nmanagers; i++) {
 991		static const char * const regulators[] = { "vaux5", "vaux3p3" };
 992		struct regulator_dev *rdev;
 993		char *reg_name;
 994		int ret;
 995
 996		reg_name = devm_kzalloc(dev, reg_name_len, GFP_KERNEL);
 997		if (!reg_name)
 998			return -ENOMEM;
 999		snprintf(reg_name, 26, "pse-%s-manager%d", dev_name(dev), i);
1000		rdev = pd692x0_register_manager_regulator(dev, reg_name,
1001							  manager[i].node);
1002		if (IS_ERR(rdev))
1003			return PTR_ERR(rdev);
1004
1005		/* VMAIN is described as main supply for the manager.
1006		 * Add other VAUX power supplies and link them to the
1007		 * virtual device rdev->dev.
1008		 */
1009		ret = devm_regulator_bulk_get_enable(&rdev->dev,
1010						     ARRAY_SIZE(regulators),
1011						     regulators);
1012		if (ret)
1013			return dev_err_probe(&rdev->dev, ret,
1014					     "Failed to enable regulators\n");
1015
1016		priv->manager_reg[i] = rdev;
1017	}
1018
1019	return 0;
1020}
1021
1022static int
1023pd692x0_conf_manager_power_budget(struct pd692x0_priv *priv, int id)
1024{
1025	struct pd692x0_msg msg, buf;
1026	int ret, pw_mW;
1027
1028	pw_mW = priv->manager_pw_budget[id] / 1000;
1029	if (!pw_mW)
1030		return 0;
1031
1032	msg = pd692x0_msg_template_list[PD692X0_MSG_GET_POWER_BANK];
1033	msg.data[0] = id;
1034	ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
1035	if (ret < 0)
1036		return ret;
1037
1038	msg = pd692x0_msg_template_list[PD692X0_MSG_SET_POWER_BANK];
1039	msg.data[0] = id;
1040	msg.data[1] = pw_mW >> 8;
1041	msg.data[2] = pw_mW & 0xff;
1042	msg.data[3] = buf.sub[2];
1043	msg.data[4] = buf.data[0];
1044	msg.data[5] = buf.data[1];
1045	msg.data[6] = buf.data[2];
1046	msg.data[7] = buf.data[3];
1047	return pd692x0_sendrecv_msg(priv, &msg, &buf);
1048}
1049
1050static int
1051pd692x0_req_managers_pw_budget(struct pd692x0_priv *priv)
1052{
1053	int i, ret;
1054
1055	for (i = 0; i < priv->nmanagers; i++) {
1056		struct regulator *supply = priv->manager_reg[i]->supply;
1057		int pw_budget;
1058
1059		pw_budget = regulator_get_unclaimed_power_budget(supply);
1060		if (!pw_budget)
1061			/* Do nothing if no power budget */
1062			continue;
1063
1064		/* Max power budget per manager */
1065		if (pw_budget > 6000000)
1066			pw_budget = 6000000;
1067		ret = regulator_request_power_budget(supply, pw_budget);
1068		if (ret < 0)
1069			return ret;
1070
1071		priv->manager_pw_budget[i] = pw_budget;
1072	}
1073
1074	return 0;
1075}
1076
1077static int
1078pd692x0_configure_managers(struct pd692x0_priv *priv)
1079{
1080	int i, ret;
1081
1082	for (i = 0; i < priv->nmanagers; i++) {
1083		ret = pd692x0_conf_manager_power_budget(priv, i);
1084		if (ret < 0)
1085			return ret;
1086	}
1087
1088	return 0;
1089}
1090
1091static int
1092pd692x0_set_port_matrix(const struct pse_pi_pairset *pairset,
1093			const struct pd692x0_manager *manager,
1094			int nmanagers, struct pd692x0_matrix *port_matrix)
1095{
1096	int i, j, port_cnt;
1097	bool found = false;
1098
1099	if (!pairset->np)
1100		return 0;
1101
1102	/* Look on every managers */
1103	port_cnt = 0;
1104	for (i = 0; i < nmanagers; i++) {
1105		/* Look on every ports of the manager */
1106		for (j = 0; j < manager[i].nports; j++) {
1107			if (pairset->np == manager[i].port_node[j]) {
1108				found = true;
1109				break;
1110			}
1111		}
1112		port_cnt += j;
1113
1114		if (found)
1115			break;
1116	}
1117
1118	if (!found)
1119		return -ENODEV;
1120
1121	if (pairset->pinout == ALTERNATIVE_A)
1122		port_matrix->hw_port_a = port_cnt;
1123	else if (pairset->pinout == ALTERNATIVE_B)
1124		port_matrix->hw_port_b = port_cnt;
1125
1126	return 0;
1127}
1128
1129static int
1130pd692x0_set_ports_matrix(struct pd692x0_priv *priv,
1131			 const struct pd692x0_manager *manager)
1132{
1133	struct pd692x0_matrix *port_matrix = priv->port_matrix;
1134	struct pse_controller_dev *pcdev = &priv->pcdev;
1135	int i, ret;
1136
1137	/* Init Matrix */
1138	for (i = 0; i < PD692X0_MAX_PIS; i++) {
1139		port_matrix[i].hw_port_a = 0xff;
1140		port_matrix[i].hw_port_b = 0xff;
1141	}
1142
1143	/* Update with values for every PSE PIs */
1144	for (i = 0; i < pcdev->nr_lines; i++) {
1145		ret = pd692x0_set_port_matrix(&pcdev->pi[i].pairset[0],
1146					      manager, priv->nmanagers,
1147					      &port_matrix[i]);
1148		if (ret) {
1149			dev_err(&priv->client->dev,
1150				"unable to configure pi %d pairset 0", i);
1151			return ret;
1152		}
1153
1154		ret = pd692x0_set_port_matrix(&pcdev->pi[i].pairset[1],
1155					      manager, priv->nmanagers,
1156					      &port_matrix[i]);
1157		if (ret) {
1158			dev_err(&priv->client->dev,
1159				"unable to configure pi %d pairset 1", i);
1160			return ret;
1161		}
1162	}
1163
1164	return 0;
1165}
1166
1167static int
1168pd692x0_write_ports_matrix(struct pd692x0_priv *priv)
1169{
1170	struct pd692x0_matrix *port_matrix = priv->port_matrix;
1171	struct pd692x0_msg msg, buf;
1172	int ret, i;
1173
1174	/* Write temporary Matrix */
1175	msg = pd692x0_msg_template_list[PD692X0_MSG_SET_TMP_PORT_MATRIX];
1176	for (i = 0; i < PD692X0_MAX_PIS; i++) {
1177		msg.sub[2] = i;
1178		msg.data[0] = port_matrix[i].hw_port_b;
1179		msg.data[1] = port_matrix[i].hw_port_a;
1180
1181		ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
1182		if (ret < 0)
1183			return ret;
1184	}
1185
1186	/* Program Matrix */
1187	msg = pd692x0_msg_template_list[PD692X0_MSG_PRG_PORT_MATRIX];
1188	ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
1189	if (ret < 0)
1190		return ret;
1191
1192	return 0;
1193}
1194
1195static int pd692x0_hw_conf_init(struct pd692x0_priv *priv)
1196{
1197	int ret;
1198
1199	/* Is PD692x0 ready to be configured? */
1200	if (priv->fw_state != PD692X0_FW_OK &&
1201	    priv->fw_state != PD692X0_FW_COMPLETE)
1202		return 0;
1203
1204	ret = pd692x0_configure_managers(priv);
1205	if (ret)
1206		return ret;
1207
1208	ret = pd692x0_write_ports_matrix(priv);
1209	if (ret)
1210		return ret;
1211
1212	return 0;
1213}
1214
1215static void pd692x0_of_put_managers(struct pd692x0_priv *priv,
1216				    struct pd692x0_manager *manager)
1217{
1218	int i, j;
1219
1220	for (i = 0; i < priv->nmanagers; i++) {
1221		for (j = 0; j < manager[i].nports; j++)
1222			of_node_put(manager[i].port_node[j]);
1223		of_node_put(manager[i].node);
1224	}
1225}
1226
1227static void pd692x0_managers_free_pw_budget(struct pd692x0_priv *priv)
1228{
1229	int i;
1230
1231	for (i = 0; i < PD692X0_MAX_MANAGERS; i++) {
1232		struct regulator *supply;
1233
1234		if (!priv->manager_reg[i] || !priv->manager_pw_budget[i])
1235			continue;
1236
1237		supply = priv->manager_reg[i]->supply;
1238		if (!supply)
1239			continue;
1240
1241		regulator_free_power_budget(supply,
1242					    priv->manager_pw_budget[i]);
1243	}
1244}
1245
1246static int
1247pd692x0_save_user_byte(struct pd692x0_priv *priv)
1248{
1249	struct pd692x0_msg msg, buf;
1250
1251	msg = pd692x0_msg_template_list[PD692X0_MSG_SET_USER_BYTE];
1252	return pd692x0_sendrecv_msg(priv, &msg, &buf);
1253}
1254
1255static int pd692x0_setup_pi_matrix(struct pse_controller_dev *pcdev)
1256{
1257	struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
1258	struct pd692x0_matrix *port_matrix;
1259	struct pd692x0_manager *manager;
1260	int ret;
1261
1262	manager = kcalloc(PD692X0_MAX_MANAGERS, sizeof(*manager), GFP_KERNEL);
1263	if (!manager)
1264		return -ENOMEM;
1265
1266	port_matrix = devm_kcalloc(&priv->client->dev, PD692X0_MAX_PIS,
1267				   sizeof(*port_matrix), GFP_KERNEL);
1268	if (!port_matrix) {
1269		ret = -ENOMEM;
1270		goto err_free_manager;
1271	}
1272	priv->port_matrix = port_matrix;
1273
1274	ret = pd692x0_of_get_managers(priv, manager);
1275	if (ret < 0)
1276		goto err_free_manager;
1277
1278	ret = pd692x0_register_managers_regulator(priv, manager);
1279	if (ret)
1280		goto err_of_managers;
1281
1282	ret = pd692x0_req_managers_pw_budget(priv);
1283	if (ret)
1284		goto err_of_managers;
1285
1286	ret = pd692x0_set_ports_matrix(priv, manager);
1287	if (ret)
1288		goto err_managers_req_pw;
1289
1290	/* Do not init the conf if it is already saved */
1291	if (!priv->cfg_saved) {
1292		ret = pd692x0_hw_conf_init(priv);
1293		if (ret)
1294			goto err_managers_req_pw;
1295
1296		ret = pd692x0_save_user_byte(priv);
1297		if (ret)
1298			goto err_managers_req_pw;
1299	}
1300
1301	pd692x0_of_put_managers(priv, manager);
1302	kfree(manager);
1303	return 0;
1304
1305err_managers_req_pw:
1306	pd692x0_managers_free_pw_budget(priv);
1307err_of_managers:
1308	pd692x0_of_put_managers(priv, manager);
1309err_free_manager:
1310	kfree(manager);
1311	return ret;
1312}
1313
1314static int pd692x0_pi_get_voltage(struct pse_controller_dev *pcdev, int id)
1315{
1316	struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
1317	struct pd692x0_msg msg, buf = {0};
1318	int ret;
1319
1320	ret = pd692x0_fw_unavailable(priv);
1321	if (ret)
1322		return ret;
1323
1324	msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_MEAS];
1325	msg.sub[2] = id;
1326	ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
1327	if (ret < 0)
1328		return ret;
1329
1330	/* Convert 0.1V unit to uV */
1331	return (buf.sub[0] << 8 | buf.sub[1]) * 100000;
1332}
1333
1334static int pd692x0_pi_get_pw_limit(struct pse_controller_dev *pcdev,
1335				   int id)
1336{
1337	struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
1338	struct pd692x0_msg msg, buf = {0};
1339	int ret;
1340
1341	msg = pd692x0_msg_template_list[PD692X0_MSG_GET_PORT_PARAM];
1342	msg.sub[2] = id;
1343	ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
1344	if (ret < 0)
1345		return ret;
1346
1347	return pd692x0_pi_get_pw_from_table(buf.data[0], buf.data[1]);
1348}
1349
1350static int pd692x0_pi_set_pw_limit(struct pse_controller_dev *pcdev,
1351				   int id, int max_mW)
1352{
1353	struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
1354	struct device *dev = &priv->client->dev;
1355	struct pd692x0_msg msg, buf = {0};
1356	int ret;
1357
1358	ret = pd692x0_fw_unavailable(priv);
1359	if (ret)
1360		return ret;
1361
1362	msg = pd692x0_msg_template_list[PD692X0_MSG_SET_PORT_PARAM];
1363	msg.sub[2] = id;
1364	ret = pd692x0_pi_set_pw_from_table(dev, &msg, max_mW);
1365	if (ret)
1366		return ret;
1367
1368	return pd692x0_sendrecv_msg(priv, &msg, &buf);
1369}
1370
1371static int pd692x0_pi_set_prio(struct pse_controller_dev *pcdev, int id,
1372			       unsigned int prio)
1373{
1374	struct pd692x0_priv *priv = to_pd692x0_priv(pcdev);
1375	struct pd692x0_msg msg, buf = {0};
1376	int ret;
1377
1378	ret = pd692x0_fw_unavailable(priv);
1379	if (ret)
1380		return ret;
1381
1382	msg = pd692x0_msg_template_list[PD692X0_MSG_SET_PORT_PARAM];
1383	msg.sub[2] = id;
1384	/* Controller priority from 1 to 3 */
1385	msg.data[4] = prio + 1;
1386
1387	return pd692x0_sendrecv_msg(priv, &msg, &buf);
1388}
1389
1390static const struct pse_controller_ops pd692x0_ops = {
1391	.setup_pi_matrix = pd692x0_setup_pi_matrix,
1392	.pi_get_admin_state = pd692x0_pi_get_admin_state,
1393	.pi_get_pw_status = pd692x0_pi_get_pw_status,
1394	.pi_get_ext_state = pd692x0_pi_get_ext_state,
1395	.pi_get_pw_class = pd692x0_pi_get_pw_class,
1396	.pi_get_actual_pw = pd692x0_pi_get_actual_pw,
1397	.pi_enable = pd692x0_pi_enable,
1398	.pi_disable = pd692x0_pi_disable,
1399	.pi_get_voltage = pd692x0_pi_get_voltage,
1400	.pi_get_pw_limit = pd692x0_pi_get_pw_limit,
1401	.pi_set_pw_limit = pd692x0_pi_set_pw_limit,
1402	.pi_get_pw_limit_ranges = pd692x0_pi_get_pw_limit_ranges,
1403	.pi_get_prio = pd692x0_pi_get_prio,
1404	.pi_set_prio = pd692x0_pi_set_prio,
1405};
1406
1407#define PD692X0_FW_LINE_MAX_SZ 0xff
1408static int pd692x0_fw_get_next_line(const u8 *data,
1409				    char *line, size_t size)
1410{
1411	size_t line_size;
1412	int i;
1413
1414	line_size = min_t(size_t, size, PD692X0_FW_LINE_MAX_SZ);
1415
1416	memset(line, 0, PD692X0_FW_LINE_MAX_SZ);
1417	for (i = 0; i < line_size - 1; i++) {
1418		if (*data == '\r' && *(data + 1) == '\n') {
1419			line[i] = '\r';
1420			line[i + 1] = '\n';
1421			return i + 2;
1422		}
1423		line[i] = *data;
1424		data++;
1425	}
1426
1427	return -EIO;
1428}
1429
1430static enum fw_upload_err
1431pd692x0_fw_recv_resp(const struct i2c_client *client, unsigned long ms_timeout,
1432		     const char *msg_ok, unsigned int msg_size)
1433{
1434	/* Maximum controller response size */
1435	char fw_msg_buf[5] = {0};
1436	unsigned long timeout;
1437	int ret;
1438
1439	if (msg_size > sizeof(fw_msg_buf))
1440		return FW_UPLOAD_ERR_RW_ERROR;
1441
1442	/* Read until we get something */
1443	timeout = msecs_to_jiffies(ms_timeout) + jiffies;
1444	while (true) {
1445		if (time_is_before_jiffies(timeout))
1446			return FW_UPLOAD_ERR_TIMEOUT;
1447
1448		ret = i2c_master_recv(client, fw_msg_buf, 1);
1449		if (ret < 0 || *fw_msg_buf == 0) {
1450			usleep_range(1000, 2000);
1451			continue;
1452		} else {
1453			break;
1454		}
1455	}
1456
1457	/* Read remaining characters */
1458	ret = i2c_master_recv(client, fw_msg_buf + 1, msg_size - 1);
1459	if (strncmp(fw_msg_buf, msg_ok, msg_size)) {
1460		dev_err(&client->dev,
1461			"Wrong FW download process answer (%*pE)\n",
1462			msg_size, fw_msg_buf);
1463		return FW_UPLOAD_ERR_HW_ERROR;
1464	}
1465
1466	return FW_UPLOAD_ERR_NONE;
1467}
1468
1469static int pd692x0_fw_write_line(const struct i2c_client *client,
1470				 const char line[PD692X0_FW_LINE_MAX_SZ],
1471				 const bool last_line)
1472{
1473	int ret;
1474
1475	while (*line != 0) {
1476		ret = i2c_master_send(client, line, 1);
1477		if (ret < 0)
1478			return FW_UPLOAD_ERR_RW_ERROR;
1479		line++;
1480	}
1481
1482	if (last_line) {
1483		ret = pd692x0_fw_recv_resp(client, 100, "TP\r\n",
1484					   sizeof("TP\r\n") - 1);
1485		if (ret)
1486			return ret;
1487	} else {
1488		ret = pd692x0_fw_recv_resp(client, 100, "T*\r\n",
1489					   sizeof("T*\r\n") - 1);
1490		if (ret)
1491			return ret;
1492	}
1493
1494	return FW_UPLOAD_ERR_NONE;
1495}
1496
1497static enum fw_upload_err pd692x0_fw_reset(const struct i2c_client *client)
1498{
1499	const struct pd692x0_msg zero = {0};
1500	struct pd692x0_msg buf = {0};
1501	unsigned long timeout;
1502	char cmd[] = "RST";
1503	int ret;
1504
1505	ret = i2c_master_send(client, cmd, strlen(cmd));
1506	if (ret < 0) {
1507		dev_err(&client->dev,
1508			"Failed to reset the controller (%pe)\n",
1509			ERR_PTR(ret));
1510		return ret;
1511	}
1512
1513	timeout = msecs_to_jiffies(10000) + jiffies;
1514	while (true) {
1515		if (time_is_before_jiffies(timeout))
1516			return FW_UPLOAD_ERR_TIMEOUT;
1517
1518		ret = i2c_master_recv(client, (u8 *)&buf, sizeof(buf));
1519		if (ret < 0 ||
1520		    !memcmp(&buf, &zero, sizeof(buf)))
1521			usleep_range(1000, 2000);
1522		else
1523			break;
1524	}
1525
1526	/* Is the reply a successful report message */
1527	if (buf.key != PD692X0_KEY_TLM || buf.echo != 0xff ||
1528	    buf.sub[0] & 0x01) {
1529		dev_err(&client->dev, "PSE controller error\n");
1530		return FW_UPLOAD_ERR_HW_ERROR;
1531	}
1532
1533	/* Is the firmware operational */
1534	if (buf.sub[0] & 0x02) {
1535		dev_err(&client->dev,
1536			"PSE firmware error. Please update it.\n");
1537		return FW_UPLOAD_ERR_HW_ERROR;
1538	}
1539
1540	return FW_UPLOAD_ERR_NONE;
1541}
1542
1543static enum fw_upload_err pd692x0_fw_prepare(struct fw_upload *fwl,
1544					     const u8 *data, u32 size)
1545{
1546	struct pd692x0_priv *priv = fwl->dd_handle;
1547	const struct i2c_client *client = priv->client;
1548	enum pd692x0_fw_state last_fw_state;
1549	int ret;
1550
1551	priv->cancel_request = false;
1552	last_fw_state = priv->fw_state;
1553
1554	priv->fw_state = PD692X0_FW_PREPARE;
1555
1556	/* Enter program mode */
1557	if (last_fw_state == PD692X0_FW_BROKEN) {
1558		const char *msg = "ENTR";
1559		const char *c;
1560
1561		c = msg;
1562		do {
1563			ret = i2c_master_send(client, c, 1);
1564			if (ret < 0)
1565				return FW_UPLOAD_ERR_RW_ERROR;
1566			if (*(c + 1))
1567				usleep_range(10000, 20000);
1568		} while (*(++c));
1569	} else {
1570		struct pd692x0_msg msg, buf;
1571
1572		msg = pd692x0_msg_template_list[PD692X0_MSG_DOWNLOAD_CMD];
1573		ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
1574		if (ret < 0) {
1575			dev_err(&client->dev,
1576				"Failed to enter programming mode (%pe)\n",
1577				ERR_PTR(ret));
1578			return FW_UPLOAD_ERR_RW_ERROR;
1579		}
1580	}
1581
1582	ret = pd692x0_fw_recv_resp(client, 100, "TPE\r\n", sizeof("TPE\r\n") - 1);
1583	if (ret)
1584		goto err_out;
1585
1586	if (priv->cancel_request) {
1587		ret = FW_UPLOAD_ERR_CANCELED;
1588		goto err_out;
1589	}
1590
1591	return FW_UPLOAD_ERR_NONE;
1592
1593err_out:
1594	pd692x0_fw_reset(priv->client);
1595	priv->fw_state = last_fw_state;
1596	return ret;
1597}
1598
1599static enum fw_upload_err pd692x0_fw_write(struct fw_upload *fwl,
1600					   const u8 *data, u32 offset,
1601					   u32 size, u32 *written)
1602{
1603	struct pd692x0_priv *priv = fwl->dd_handle;
1604	char line[PD692X0_FW_LINE_MAX_SZ];
1605	const struct i2c_client *client;
1606	int ret, i;
1607	char cmd;
1608
1609	client = priv->client;
1610	priv->fw_state = PD692X0_FW_WRITE;
1611
1612	/* Erase */
1613	cmd = 'E';
1614	ret = i2c_master_send(client, &cmd, 1);
1615	if (ret < 0) {
1616		dev_err(&client->dev,
1617			"Failed to boot programming mode (%pe)\n",
1618			ERR_PTR(ret));
1619		return FW_UPLOAD_ERR_RW_ERROR;
1620	}
1621
1622	ret = pd692x0_fw_recv_resp(client, 100, "TOE\r\n", sizeof("TOE\r\n") - 1);
1623	if (ret)
1624		return ret;
1625
1626	ret = pd692x0_fw_recv_resp(client, 5000, "TE\r\n", sizeof("TE\r\n") - 1);
1627	if (ret)
1628		dev_warn(&client->dev,
1629			 "Failed to erase internal memory, however still try to write Firmware\n");
1630
1631	ret = pd692x0_fw_recv_resp(client, 100, "TPE\r\n", sizeof("TPE\r\n") - 1);
1632	if (ret)
1633		dev_warn(&client->dev,
1634			 "Failed to erase internal memory, however still try to write Firmware\n");
1635
1636	if (priv->cancel_request)
1637		return FW_UPLOAD_ERR_CANCELED;
1638
1639	/* Program */
1640	cmd = 'P';
1641	ret = i2c_master_send(client, &cmd, sizeof(char));
1642	if (ret < 0) {
1643		dev_err(&client->dev,
1644			"Failed to boot programming mode (%pe)\n",
1645			ERR_PTR(ret));
1646		return ret;
1647	}
1648
1649	ret = pd692x0_fw_recv_resp(client, 100, "TOP\r\n", sizeof("TOP\r\n") - 1);
1650	if (ret)
1651		return ret;
1652
1653	i = 0;
1654	while (i < size) {
1655		ret = pd692x0_fw_get_next_line(data, line, size - i);
1656		if (ret < 0) {
1657			ret = FW_UPLOAD_ERR_FW_INVALID;
1658			goto err;
1659		}
1660
1661		i += ret;
1662		data += ret;
1663		if (line[0] == 'S' && line[1] == '0') {
1664			continue;
1665		} else if (line[0] == 'S' && line[1] == '7') {
1666			ret = pd692x0_fw_write_line(client, line, true);
1667			if (ret)
1668				goto err;
1669		} else {
1670			ret = pd692x0_fw_write_line(client, line, false);
1671			if (ret)
1672				goto err;
1673		}
1674
1675		if (priv->cancel_request) {
1676			ret = FW_UPLOAD_ERR_CANCELED;
1677			goto err;
1678		}
1679	}
1680	*written = i;
1681
1682	msleep(400);
1683
1684	return FW_UPLOAD_ERR_NONE;
1685
1686err:
1687	strscpy_pad(line, "S7\r\n", sizeof(line));
1688	pd692x0_fw_write_line(client, line, true);
1689	return ret;
1690}
1691
1692static enum fw_upload_err pd692x0_fw_poll_complete(struct fw_upload *fwl)
1693{
1694	struct pd692x0_priv *priv = fwl->dd_handle;
1695	const struct i2c_client *client = priv->client;
1696	struct pd692x0_msg_ver ver;
1697	int ret;
1698
1699	priv->fw_state = PD692X0_FW_COMPLETE;
1700
1701	ret = pd692x0_fw_reset(client);
1702	if (ret)
1703		return ret;
1704
1705	ver = pd692x0_get_sw_version(priv);
1706	if (ver.maj_sw_ver < PD692X0_FW_MAJ_VER) {
1707		dev_err(&client->dev,
1708			"Too old firmware version. Please update it\n");
1709		priv->fw_state = PD692X0_FW_NEED_UPDATE;
1710		return FW_UPLOAD_ERR_FW_INVALID;
1711	}
1712
1713	ret = pd692x0_hw_conf_init(priv);
1714	if (ret < 0) {
1715		dev_err(&client->dev, "Error configuring ports matrix (%pe)\n",
1716			ERR_PTR(ret));
1717		priv->fw_state = PD692X0_FW_NEED_UPDATE;
1718		return FW_UPLOAD_ERR_HW_ERROR;
1719	}
1720
1721	priv->fw_state = PD692X0_FW_OK;
1722	return FW_UPLOAD_ERR_NONE;
1723}
1724
1725static void pd692x0_fw_cancel(struct fw_upload *fwl)
1726{
1727	struct pd692x0_priv *priv = fwl->dd_handle;
1728
1729	priv->cancel_request = true;
1730}
1731
1732static void pd692x0_fw_cleanup(struct fw_upload *fwl)
1733{
1734	struct pd692x0_priv *priv = fwl->dd_handle;
1735
1736	switch (priv->fw_state) {
1737	case PD692X0_FW_WRITE:
1738		pd692x0_fw_reset(priv->client);
1739		fallthrough;
1740	case PD692X0_FW_COMPLETE:
1741		priv->fw_state = PD692X0_FW_BROKEN;
1742		break;
1743	default:
1744		break;
1745	}
1746}
1747
1748static const struct fw_upload_ops pd692x0_fw_ops = {
1749	.prepare = pd692x0_fw_prepare,
1750	.write = pd692x0_fw_write,
1751	.poll_complete = pd692x0_fw_poll_complete,
1752	.cancel = pd692x0_fw_cancel,
1753	.cleanup = pd692x0_fw_cleanup,
1754};
1755
1756static int pd692x0_i2c_probe(struct i2c_client *client)
1757{
1758	static const char * const regulators[] = { "vdd", "vdda" };
1759	struct pd692x0_msg msg, buf = {0}, zero = {0};
1760	struct device *dev = &client->dev;
1761	struct pd692x0_msg_ver ver;
1762	struct pd692x0_priv *priv;
1763	struct fw_upload *fwl;
1764	int ret;
1765
1766	ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(regulators),
1767					     regulators);
1768	if (ret)
1769		return dev_err_probe(dev, ret,
1770				     "Failed to enable regulators\n");
1771
1772	if (!i2c_check_functionality(client->adapter, I2C_FUNC_I2C)) {
1773		dev_err(dev, "i2c check functionality failed\n");
1774		return -ENXIO;
1775	}
1776
1777	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1778	if (!priv)
1779		return -ENOMEM;
1780
1781	priv->client = client;
1782	i2c_set_clientdata(client, priv);
1783
1784	ret = i2c_master_recv(client, (u8 *)&buf, sizeof(buf));
1785	if (ret != sizeof(buf)) {
1786		dev_err(dev, "Failed to get device status\n");
1787		return -EIO;
1788	}
1789
1790	/* Probe has been already run and the status dumped */
1791	if (!memcmp(&buf, &zero, sizeof(buf))) {
1792		/* Ask again the controller status */
1793		msg = pd692x0_msg_template_list[PD692X0_MSG_GET_SYS_STATUS];
1794		ret = pd692x0_sendrecv_msg(priv, &msg, &buf);
1795		if (ret < 0) {
1796			dev_err(dev, "Failed to get device status\n");
1797			return ret;
1798		}
1799	}
1800
1801	if (buf.key != 0x03 || buf.sub[0] & 0x01) {
1802		dev_err(dev, "PSE controller error\n");
1803		return -EIO;
1804	}
1805	if (buf.sub[0] & 0x02) {
1806		dev_err(dev, "PSE firmware error. Please update it.\n");
1807		priv->fw_state = PD692X0_FW_BROKEN;
1808	} else {
1809		ver = pd692x0_get_sw_version(priv);
1810		dev_info(&client->dev, "Software version %d.%02d.%d.%d\n",
1811			 ver.prod, ver.maj_sw_ver, ver.min_sw_ver,
1812			 ver.pa_sw_ver);
1813
1814		if (ver.maj_sw_ver < PD692X0_FW_MAJ_VER) {
1815			dev_err(dev, "Too old firmware version. Please update it\n");
1816			priv->fw_state = PD692X0_FW_NEED_UPDATE;
1817		} else {
1818			priv->fw_state = PD692X0_FW_OK;
1819		}
1820	}
1821
1822	if (buf.data[2] == PD692X0_USER_BYTE)
1823		priv->cfg_saved = true;
1824
1825	priv->np = dev->of_node;
1826	priv->pcdev.nr_lines = PD692X0_MAX_PIS;
1827	priv->pcdev.owner = THIS_MODULE;
1828	priv->pcdev.ops = &pd692x0_ops;
1829	priv->pcdev.dev = dev;
1830	priv->pcdev.types = ETHTOOL_PSE_C33;
1831	priv->pcdev.supp_budget_eval_strategies = PSE_BUDGET_EVAL_STRAT_DYNAMIC;
1832	priv->pcdev.pis_prio_max = 2;
1833	ret = devm_pse_controller_register(dev, &priv->pcdev);
1834	if (ret)
1835		return dev_err_probe(dev, ret,
1836				     "failed to register PSE controller\n");
1837
1838	fwl = firmware_upload_register(THIS_MODULE, dev, dev_name(dev),
1839				       &pd692x0_fw_ops, priv);
1840	if (IS_ERR(fwl))
1841		return dev_err_probe(dev, PTR_ERR(fwl),
1842				     "failed to register to the Firmware Upload API\n");
1843	priv->fwl = fwl;
1844
1845	return 0;
1846}
1847
1848static void pd692x0_i2c_remove(struct i2c_client *client)
1849{
1850	struct pd692x0_priv *priv = i2c_get_clientdata(client);
1851
1852	pd692x0_managers_free_pw_budget(priv);
1853	firmware_upload_unregister(priv->fwl);
1854}
1855
1856static const struct i2c_device_id pd692x0_id[] = {
1857	{ PD692X0_PSE_NAME },
1858	{ }
1859};
1860MODULE_DEVICE_TABLE(i2c, pd692x0_id);
1861
1862static const struct of_device_id pd692x0_of_match[] = {
1863	{ .compatible = "microchip,pd69200", },
1864	{ .compatible = "microchip,pd69210", },
1865	{ .compatible = "microchip,pd69220", },
1866	{ },
1867};
1868MODULE_DEVICE_TABLE(of, pd692x0_of_match);
1869
1870static struct i2c_driver pd692x0_driver = {
1871	.probe		= pd692x0_i2c_probe,
1872	.remove		= pd692x0_i2c_remove,
1873	.id_table	= pd692x0_id,
1874	.driver		= {
1875		.name		= PD692X0_PSE_NAME,
1876		.of_match_table = pd692x0_of_match,
1877	},
1878};
1879module_i2c_driver(pd692x0_driver);
1880
1881MODULE_AUTHOR("Kory Maincent <kory.maincent@bootlin.com>");
1882MODULE_DESCRIPTION("Microchip PD692x0 PoE PSE Controller driver");
1883MODULE_LICENSE("GPL");