qca808x.c

  1// SPDX-License-Identifier: GPL-2.0+
  2
  3#include <linux/phy.h>
  4#include <linux/module.h>
  5
  6#include "qcom.h"
  7
  8/* ADC threshold */
  9#define QCA808X_PHY_DEBUG_ADC_THRESHOLD		0x2c80
 10#define QCA808X_ADC_THRESHOLD_MASK		GENMASK(7, 0)
 11#define QCA808X_ADC_THRESHOLD_80MV		0
 12#define QCA808X_ADC_THRESHOLD_100MV		0xf0
 13#define QCA808X_ADC_THRESHOLD_200MV		0x0f
 14#define QCA808X_ADC_THRESHOLD_300MV		0xff
 15
 16/* CLD control */
 17#define QCA808X_PHY_MMD3_ADDR_CLD_CTRL7		0x8007
 18#define QCA808X_8023AZ_AFE_CTRL_MASK		GENMASK(8, 4)
 19#define QCA808X_8023AZ_AFE_EN			0x90
 20
 21/* AZ control */
 22#define QCA808X_PHY_MMD3_AZ_TRAINING_CTRL	0x8008
 23#define QCA808X_MMD3_AZ_TRAINING_VAL		0x1c32
 24
 25#define QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB	0x8014
 26#define QCA808X_MSE_THRESHOLD_20DB_VALUE	0x529
 27
 28#define QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB	0x800E
 29#define QCA808X_MSE_THRESHOLD_17DB_VALUE	0x341
 30
 31#define QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB	0x801E
 32#define QCA808X_MSE_THRESHOLD_27DB_VALUE	0x419
 33
 34#define QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB	0x8020
 35#define QCA808X_MSE_THRESHOLD_28DB_VALUE	0x341
 36
 37#define QCA808X_PHY_MMD7_TOP_OPTION1		0x901c
 38#define QCA808X_TOP_OPTION1_DATA		0x0
 39
 40#define QCA808X_PHY_MMD3_DEBUG_1		0xa100
 41#define QCA808X_MMD3_DEBUG_1_VALUE		0x9203
 42#define QCA808X_PHY_MMD3_DEBUG_2		0xa101
 43#define QCA808X_MMD3_DEBUG_2_VALUE		0x48ad
 44#define QCA808X_PHY_MMD3_DEBUG_3		0xa103
 45#define QCA808X_MMD3_DEBUG_3_VALUE		0x1698
 46#define QCA808X_PHY_MMD3_DEBUG_4		0xa105
 47#define QCA808X_MMD3_DEBUG_4_VALUE		0x8001
 48#define QCA808X_PHY_MMD3_DEBUG_5		0xa106
 49#define QCA808X_MMD3_DEBUG_5_VALUE		0x1111
 50#define QCA808X_PHY_MMD3_DEBUG_6		0xa011
 51#define QCA808X_MMD3_DEBUG_6_VALUE		0x5f85
 52
 53/* master/slave seed config */
 54#define QCA808X_PHY_DEBUG_LOCAL_SEED		9
 55#define QCA808X_MASTER_SLAVE_SEED_ENABLE	BIT(1)
 56#define QCA808X_MASTER_SLAVE_SEED_CFG		GENMASK(12, 2)
 57#define QCA808X_MASTER_SLAVE_SEED_RANGE		0x32
 58
 59/* Hibernation yields lower power consumpiton in contrast with normal operation mode.
 60 * when the copper cable is unplugged, the PHY enters into hibernation mode in about 10s.
 61 */
 62#define QCA808X_DBG_AN_TEST			0xb
 63#define QCA808X_HIBERNATION_EN			BIT(15)
 64
 65#define QCA808X_MMD7_LED2_CTRL			0x8074
 66#define QCA808X_MMD7_LED2_FORCE_CTRL		0x8075
 67#define QCA808X_MMD7_LED1_CTRL			0x8076
 68#define QCA808X_MMD7_LED1_FORCE_CTRL		0x8077
 69#define QCA808X_MMD7_LED0_CTRL			0x8078
 70#define QCA808X_MMD7_LED_CTRL(x)		(0x8078 - ((x) * 2))
 71
 72#define QCA808X_MMD7_LED0_FORCE_CTRL		0x8079
 73#define QCA808X_MMD7_LED_FORCE_CTRL(x)		(0x8079 - ((x) * 2))
 74
 75#define QCA808X_MMD7_LED_POLARITY_CTRL		0x901a
 76/* QSDK sets by default 0x46 to this reg that sets BIT 6 for
 77 * LED to active high. It's not clear what BIT 3 and BIT 4 does.
 78 */
 79#define QCA808X_LED_ACTIVE_HIGH			BIT(6)
 80
 81/* QCA808X 1G chip type */
 82#define QCA808X_PHY_MMD7_CHIP_TYPE		0x901d
 83#define QCA808X_PHY_CHIP_TYPE_1G		BIT(0)
 84
 85#define QCA8081_PHY_SERDES_MMD1_FIFO_CTRL	0x9072
 86#define QCA8081_PHY_FIFO_RSTN			BIT(11)
 87
 88#define QCA8081_PHY_ID				0x004dd101
 89
 90MODULE_DESCRIPTION("Qualcomm Atheros QCA808X PHY driver");
 91MODULE_AUTHOR("Matus Ujhelyi");
 92MODULE_LICENSE("GPL");
 93
 94struct qca808x_priv {
 95	int led_polarity_mode;
 96	struct qcom_phy_hw_stats hw_stats;
 97};
 98
 99static int qca808x_phy_fast_retrain_config(struct phy_device *phydev)
100{
101	int ret;
102
103	/* Enable fast retrain */
104	ret = genphy_c45_fast_retrain(phydev, true);
105	if (ret)
106		return ret;
107
108	phy_write_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_TOP_OPTION1,
109		      QCA808X_TOP_OPTION1_DATA);
110	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_20DB,
111		      QCA808X_MSE_THRESHOLD_20DB_VALUE);
112	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_17DB,
113		      QCA808X_MSE_THRESHOLD_17DB_VALUE);
114	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_27DB,
115		      QCA808X_MSE_THRESHOLD_27DB_VALUE);
116	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, QCA808X_PHY_MMD1_MSE_THRESHOLD_28DB,
117		      QCA808X_MSE_THRESHOLD_28DB_VALUE);
118	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_1,
119		      QCA808X_MMD3_DEBUG_1_VALUE);
120	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_4,
121		      QCA808X_MMD3_DEBUG_4_VALUE);
122	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_5,
123		      QCA808X_MMD3_DEBUG_5_VALUE);
124	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_3,
125		      QCA808X_MMD3_DEBUG_3_VALUE);
126	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_6,
127		      QCA808X_MMD3_DEBUG_6_VALUE);
128	phy_write_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_DEBUG_2,
129		      QCA808X_MMD3_DEBUG_2_VALUE);
130
131	return 0;
132}
133
134static int qca808x_phy_ms_seed_enable(struct phy_device *phydev, bool enable)
135{
136	u16 seed_value;
137
138	if (!enable)
139		return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
140				QCA808X_MASTER_SLAVE_SEED_ENABLE, 0);
141
142	seed_value = get_random_u32_below(QCA808X_MASTER_SLAVE_SEED_RANGE);
143	return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_LOCAL_SEED,
144			QCA808X_MASTER_SLAVE_SEED_CFG | QCA808X_MASTER_SLAVE_SEED_ENABLE,
145			FIELD_PREP(QCA808X_MASTER_SLAVE_SEED_CFG, seed_value) |
146			QCA808X_MASTER_SLAVE_SEED_ENABLE);
147}
148
149static bool qca808x_is_prefer_master(struct phy_device *phydev)
150{
151	return (phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_FORCE) ||
152		(phydev->master_slave_get == MASTER_SLAVE_CFG_MASTER_PREFERRED);
153}
154
155static bool qca808x_has_fast_retrain_or_slave_seed(struct phy_device *phydev)
156{
157	return linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
158}
159
160static bool qca808x_is_1g_only(struct phy_device *phydev)
161{
162	int ret;
163
164	ret = phy_read_mmd(phydev, MDIO_MMD_AN, QCA808X_PHY_MMD7_CHIP_TYPE);
165	if (ret < 0)
166		return true;
167
168	return !!(QCA808X_PHY_CHIP_TYPE_1G & ret);
169}
170
171static void qca808x_fill_possible_interfaces(struct phy_device *phydev)
172{
173	unsigned long *possible = phydev->possible_interfaces;
174
175	__set_bit(PHY_INTERFACE_MODE_SGMII, possible);
176
177	if (!qca808x_is_1g_only(phydev))
178		__set_bit(PHY_INTERFACE_MODE_2500BASEX, possible);
179}
180
181static int qca808x_probe(struct phy_device *phydev)
182{
183	struct device *dev = &phydev->mdio.dev;
184	struct qca808x_priv *priv;
185
186	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
187	if (!priv)
188		return -ENOMEM;
189
190	/* Init LED polarity mode to -1 */
191	priv->led_polarity_mode = -1;
192
193	phydev->priv = priv;
194
195	return 0;
196}
197
198static int qca808x_config_init(struct phy_device *phydev)
199{
200	struct qca808x_priv *priv = phydev->priv;
201	int ret;
202
203	/* Default to LED Active High if active-low not in DT */
204	if (priv->led_polarity_mode == -1) {
205		ret = phy_set_bits_mmd(phydev, MDIO_MMD_AN,
206				       QCA808X_MMD7_LED_POLARITY_CTRL,
207				       QCA808X_LED_ACTIVE_HIGH);
208		if (ret)
209			return ret;
210	}
211
212	/* Active adc&vga on 802.3az for the link 1000M and 100M */
213	ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, QCA808X_PHY_MMD3_ADDR_CLD_CTRL7,
214			     QCA808X_8023AZ_AFE_CTRL_MASK, QCA808X_8023AZ_AFE_EN);
215	if (ret)
216		return ret;
217
218	/* Adjust the threshold on 802.3az for the link 1000M */
219	ret = phy_write_mmd(phydev, MDIO_MMD_PCS,
220			    QCA808X_PHY_MMD3_AZ_TRAINING_CTRL,
221			    QCA808X_MMD3_AZ_TRAINING_VAL);
222	if (ret)
223		return ret;
224
225	if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
226		/* Config the fast retrain for the link 2500M */
227		ret = qca808x_phy_fast_retrain_config(phydev);
228		if (ret)
229			return ret;
230
231		ret = genphy_read_master_slave(phydev);
232		if (ret < 0)
233			return ret;
234
235		if (!qca808x_is_prefer_master(phydev)) {
236			/* Enable seed and configure lower ramdom seed to make phy
237			 * linked as slave mode.
238			 */
239			ret = qca808x_phy_ms_seed_enable(phydev, true);
240			if (ret)
241				return ret;
242		}
243	}
244
245	qca808x_fill_possible_interfaces(phydev);
246
247	ret = qcom_phy_counter_config(phydev);
248	if (ret)
249		return ret;
250
251	/* Configure adc threshold as 100mv for the link 10M */
252	return at803x_debug_reg_mask(phydev, QCA808X_PHY_DEBUG_ADC_THRESHOLD,
253				     QCA808X_ADC_THRESHOLD_MASK,
254				     QCA808X_ADC_THRESHOLD_100MV);
255}
256
257static int qca808x_read_status(struct phy_device *phydev)
258{
259	struct at803x_ss_mask ss_mask = { 0 };
260	int ret;
261
262	ret = phy_read_mmd(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_STAT);
263	if (ret < 0)
264		return ret;
265
266	linkmode_mod_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->lp_advertising,
267			 ret & MDIO_AN_10GBT_STAT_LP2_5G);
268
269	ret = genphy_read_status(phydev);
270	if (ret)
271		return ret;
272
273	/* qca8081 takes the different bits for speed value from at803x */
274	ss_mask.speed_mask = QCA808X_SS_SPEED_MASK;
275	ss_mask.speed_shift = __bf_shf(QCA808X_SS_SPEED_MASK);
276	ret = at803x_read_specific_status(phydev, ss_mask);
277	if (ret < 0)
278		return ret;
279
280	if (phydev->link) {
281		if (phydev->speed == SPEED_2500)
282			phydev->interface = PHY_INTERFACE_MODE_2500BASEX;
283		else
284			phydev->interface = PHY_INTERFACE_MODE_SGMII;
285	} else {
286		/* generate seed as a lower random value to make PHY linked as SLAVE easily,
287		 * except for master/slave configuration fault detected or the master mode
288		 * preferred.
289		 *
290		 * the reason for not putting this code into the function link_change_notify is
291		 * the corner case where the link partner is also the qca8081 PHY and the seed
292		 * value is configured as the same value, the link can't be up and no link change
293		 * occurs.
294		 */
295		if (qca808x_has_fast_retrain_or_slave_seed(phydev)) {
296			if (phydev->master_slave_state == MASTER_SLAVE_STATE_ERR ||
297			    qca808x_is_prefer_master(phydev)) {
298				qca808x_phy_ms_seed_enable(phydev, false);
299			} else {
300				qca808x_phy_ms_seed_enable(phydev, true);
301			}
302		}
303	}
304
305	return 0;
306}
307
308static int qca808x_soft_reset(struct phy_device *phydev)
309{
310	int ret;
311
312	ret = genphy_soft_reset(phydev);
313	if (ret < 0)
314		return ret;
315
316	if (qca808x_has_fast_retrain_or_slave_seed(phydev))
317		ret = qca808x_phy_ms_seed_enable(phydev, true);
318
319	return ret;
320}
321
322static int qca808x_cable_test_start(struct phy_device *phydev)
323{
324	int ret;
325
326	/* perform CDT with the following configs:
327	 * 1. disable hibernation.
328	 * 2. force PHY working in MDI mode.
329	 * 3. for PHY working in 1000BaseT.
330	 * 4. configure the threshold.
331	 */
332
333	ret = at803x_debug_reg_mask(phydev, QCA808X_DBG_AN_TEST, QCA808X_HIBERNATION_EN, 0);
334	if (ret < 0)
335		return ret;
336
337	ret = at803x_config_mdix(phydev, ETH_TP_MDI);
338	if (ret < 0)
339		return ret;
340
341	/* Force 1000base-T needs to configure PMA/PMD and MII_BMCR */
342	phydev->duplex = DUPLEX_FULL;
343	phydev->speed = SPEED_1000;
344	ret = genphy_c45_pma_setup_forced(phydev);
345	if (ret < 0)
346		return ret;
347
348	ret = genphy_setup_forced(phydev);
349	if (ret < 0)
350		return ret;
351
352	/* configure the thresholds for open, short, pair ok test */
353	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8074, 0xc040);
354	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8076, 0xc040);
355	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8077, 0xa060);
356	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8078, 0xc050);
357	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807a, 0xc060);
358	phy_write_mmd(phydev, MDIO_MMD_PCS, 0x807e, 0xb060);
359
360	return 0;
361}
362
363static int qca808x_get_features(struct phy_device *phydev)
364{
365	int ret;
366
367	ret = genphy_c45_pma_read_abilities(phydev);
368	if (ret)
369		return ret;
370
371	/* The autoneg ability is not existed in bit3 of MMD7.1,
372	 * but it is supported by qca808x PHY, so we add it here
373	 * manually.
374	 */
375	linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported);
376
377	/* As for the qca8081 1G version chip, the 2500baseT ability is also
378	 * existed in the bit0 of MMD1.21, we need to remove it manually if
379	 * it is the qca8081 1G chip according to the bit0 of MMD7.0x901d.
380	 */
381	if (qca808x_is_1g_only(phydev))
382		linkmode_clear_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported);
383
384	return 0;
385}
386
387static int qca808x_config_aneg(struct phy_device *phydev)
388{
389	int phy_ctrl = 0;
390	int ret;
391
392	ret = at803x_prepare_config_aneg(phydev);
393	if (ret)
394		return ret;
395
396	/* The reg MII_BMCR also needs to be configured for force mode, the
397	 * genphy_config_aneg is also needed.
398	 */
399	if (phydev->autoneg == AUTONEG_DISABLE)
400		genphy_c45_pma_setup_forced(phydev);
401
402	if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->advertising))
403		phy_ctrl = MDIO_AN_10GBT_CTRL_ADV2_5G;
404
405	ret = phy_modify_mmd_changed(phydev, MDIO_MMD_AN, MDIO_AN_10GBT_CTRL,
406				     MDIO_AN_10GBT_CTRL_ADV2_5G, phy_ctrl);
407	if (ret < 0)
408		return ret;
409
410	return __genphy_config_aneg(phydev, ret);
411}
412
413static void qca808x_link_change_notify(struct phy_device *phydev)
414{
415	/* Assert interface sgmii fifo on link down, deassert it on link up,
416	 * the interface device address is always phy address added by 1.
417	 */
418	mdiobus_c45_modify_changed(phydev->mdio.bus, phydev->mdio.addr + 1,
419				   MDIO_MMD_PMAPMD, QCA8081_PHY_SERDES_MMD1_FIFO_CTRL,
420				   QCA8081_PHY_FIFO_RSTN,
421				   phydev->link ? QCA8081_PHY_FIFO_RSTN : 0);
422}
423
424static int qca808x_led_parse_netdev(struct phy_device *phydev, unsigned long rules,
425				    u16 *offload_trigger)
426{
427	/* Parsing specific to netdev trigger */
428	if (test_bit(TRIGGER_NETDEV_TX, &rules))
429		*offload_trigger |= QCA808X_LED_TX_BLINK;
430	if (test_bit(TRIGGER_NETDEV_RX, &rules))
431		*offload_trigger |= QCA808X_LED_RX_BLINK;
432	if (test_bit(TRIGGER_NETDEV_LINK_10, &rules))
433		*offload_trigger |= QCA808X_LED_SPEED10_ON;
434	if (test_bit(TRIGGER_NETDEV_LINK_100, &rules))
435		*offload_trigger |= QCA808X_LED_SPEED100_ON;
436	if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules))
437		*offload_trigger |= QCA808X_LED_SPEED1000_ON;
438	if (test_bit(TRIGGER_NETDEV_LINK_2500, &rules))
439		*offload_trigger |= QCA808X_LED_SPEED2500_ON;
440	if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules))
441		*offload_trigger |= QCA808X_LED_HALF_DUPLEX_ON;
442	if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules))
443		*offload_trigger |= QCA808X_LED_FULL_DUPLEX_ON;
444
445	if (rules && !*offload_trigger)
446		return -EOPNOTSUPP;
447
448	/* Enable BLINK_CHECK_BYPASS by default to make the LED
449	 * blink even with duplex or speed mode not enabled.
450	 */
451	*offload_trigger |= QCA808X_LED_BLINK_CHECK_BYPASS;
452
453	return 0;
454}
455
456static int qca808x_led_hw_control_enable(struct phy_device *phydev, u8 index)
457{
458	u16 reg;
459
460	if (index > 2)
461		return -EINVAL;
462
463	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
464	return qca808x_led_reg_hw_control_enable(phydev, reg);
465}
466
467static int qca808x_led_hw_is_supported(struct phy_device *phydev, u8 index,
468				       unsigned long rules)
469{
470	u16 offload_trigger = 0;
471
472	if (index > 2)
473		return -EINVAL;
474
475	return qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
476}
477
478static int qca808x_led_hw_control_set(struct phy_device *phydev, u8 index,
479				      unsigned long rules)
480{
481	u16 reg, offload_trigger = 0;
482	int ret;
483
484	if (index > 2)
485		return -EINVAL;
486
487	reg = QCA808X_MMD7_LED_CTRL(index);
488
489	ret = qca808x_led_parse_netdev(phydev, rules, &offload_trigger);
490	if (ret)
491		return ret;
492
493	ret = qca808x_led_hw_control_enable(phydev, index);
494	if (ret)
495		return ret;
496
497	return phy_modify_mmd(phydev, MDIO_MMD_AN, reg,
498			      QCA808X_LED_PATTERN_MASK,
499			      offload_trigger);
500}
501
502static bool qca808x_led_hw_control_status(struct phy_device *phydev, u8 index)
503{
504	u16 reg;
505
506	if (index > 2)
507		return false;
508
509	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
510	return qca808x_led_reg_hw_control_status(phydev, reg);
511}
512
513static int qca808x_led_hw_control_get(struct phy_device *phydev, u8 index,
514				      unsigned long *rules)
515{
516	u16 reg;
517	int val;
518
519	if (index > 2)
520		return -EINVAL;
521
522	/* Check if we have hw control enabled */
523	if (qca808x_led_hw_control_status(phydev, index))
524		return -EINVAL;
525
526	reg = QCA808X_MMD7_LED_CTRL(index);
527
528	val = phy_read_mmd(phydev, MDIO_MMD_AN, reg);
529	if (val & QCA808X_LED_TX_BLINK)
530		set_bit(TRIGGER_NETDEV_TX, rules);
531	if (val & QCA808X_LED_RX_BLINK)
532		set_bit(TRIGGER_NETDEV_RX, rules);
533	if (val & QCA808X_LED_SPEED10_ON)
534		set_bit(TRIGGER_NETDEV_LINK_10, rules);
535	if (val & QCA808X_LED_SPEED100_ON)
536		set_bit(TRIGGER_NETDEV_LINK_100, rules);
537	if (val & QCA808X_LED_SPEED1000_ON)
538		set_bit(TRIGGER_NETDEV_LINK_1000, rules);
539	if (val & QCA808X_LED_SPEED2500_ON)
540		set_bit(TRIGGER_NETDEV_LINK_2500, rules);
541	if (val & QCA808X_LED_HALF_DUPLEX_ON)
542		set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules);
543	if (val & QCA808X_LED_FULL_DUPLEX_ON)
544		set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules);
545
546	return 0;
547}
548
549static int qca808x_led_hw_control_reset(struct phy_device *phydev, u8 index)
550{
551	u16 reg;
552
553	if (index > 2)
554		return -EINVAL;
555
556	reg = QCA808X_MMD7_LED_CTRL(index);
557
558	return phy_clear_bits_mmd(phydev, MDIO_MMD_AN, reg,
559				  QCA808X_LED_PATTERN_MASK);
560}
561
562static int qca808x_led_brightness_set(struct phy_device *phydev,
563				      u8 index, enum led_brightness value)
564{
565	u16 reg;
566	int ret;
567
568	if (index > 2)
569		return -EINVAL;
570
571	if (!value) {
572		ret = qca808x_led_hw_control_reset(phydev, index);
573		if (ret)
574			return ret;
575	}
576
577	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
578	return qca808x_led_reg_brightness_set(phydev, reg, value);
579}
580
581static int qca808x_led_blink_set(struct phy_device *phydev, u8 index,
582				 unsigned long *delay_on,
583				 unsigned long *delay_off)
584{
585	u16 reg;
586
587	if (index > 2)
588		return -EINVAL;
589
590	reg = QCA808X_MMD7_LED_FORCE_CTRL(index);
591	return qca808x_led_reg_blink_set(phydev, reg, delay_on, delay_off);
592}
593
594static int qca808x_led_polarity_set(struct phy_device *phydev, int index,
595				    unsigned long modes)
596{
597	struct qca808x_priv *priv = phydev->priv;
598	bool active_low = false;
599	u32 mode;
600
601	for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) {
602		switch (mode) {
603		case PHY_LED_ACTIVE_LOW:
604			active_low = true;
605			break;
606		default:
607			return -EINVAL;
608		}
609	}
610
611	/* PHY polarity is global and can't be set per LED.
612	 * To detect this, check if last requested polarity mode
613	 * match the new one.
614	 */
615	if (priv->led_polarity_mode >= 0 &&
616	    priv->led_polarity_mode != active_low) {
617		phydev_err(phydev, "PHY polarity is global. Mismatched polarity on different LED\n");
618		return -EINVAL;
619	}
620
621	/* Save the last PHY polarity mode */
622	priv->led_polarity_mode = active_low;
623
624	return phy_modify_mmd(phydev, MDIO_MMD_AN,
625			      QCA808X_MMD7_LED_POLARITY_CTRL,
626			      QCA808X_LED_ACTIVE_HIGH,
627			      active_low ? 0 : QCA808X_LED_ACTIVE_HIGH);
628}
629
630static int qca808x_update_stats(struct phy_device *phydev)
631{
632	struct qca808x_priv *priv = phydev->priv;
633
634	return qcom_phy_update_stats(phydev, &priv->hw_stats);
635}
636
637static void qca808x_get_phy_stats(struct phy_device *phydev,
638				  struct ethtool_eth_phy_stats *eth_stats,
639				  struct ethtool_phy_stats *stats)
640{
641	struct qca808x_priv *priv = phydev->priv;
642
643	qcom_phy_get_stats(stats, priv->hw_stats);
644}
645
646static struct phy_driver qca808x_driver[] = {
647{
648	/* Qualcomm QCA8081 */
649	PHY_ID_MATCH_EXACT(QCA8081_PHY_ID),
650	.name			= "Qualcomm QCA8081",
651	.flags			= PHY_POLL_CABLE_TEST,
652	.probe			= qca808x_probe,
653	.config_intr		= at803x_config_intr,
654	.handle_interrupt	= at803x_handle_interrupt,
655	.get_tunable		= at803x_get_tunable,
656	.set_tunable		= at803x_set_tunable,
657	.set_wol		= at8031_set_wol,
658	.get_wol		= at803x_get_wol,
659	.get_features		= qca808x_get_features,
660	.config_aneg		= qca808x_config_aneg,
661	.suspend		= genphy_suspend,
662	.resume			= genphy_resume,
663	.read_status		= qca808x_read_status,
664	.config_init		= qca808x_config_init,
665	.soft_reset		= qca808x_soft_reset,
666	.cable_test_start	= qca808x_cable_test_start,
667	.cable_test_get_status	= qca808x_cable_test_get_status,
668	.link_change_notify	= qca808x_link_change_notify,
669	.led_brightness_set	= qca808x_led_brightness_set,
670	.led_blink_set		= qca808x_led_blink_set,
671	.led_hw_is_supported	= qca808x_led_hw_is_supported,
672	.led_hw_control_set	= qca808x_led_hw_control_set,
673	.led_hw_control_get	= qca808x_led_hw_control_get,
674	.led_polarity_set	= qca808x_led_polarity_set,
675	.update_stats		= qca808x_update_stats,
676	.get_phy_stats		= qca808x_get_phy_stats,
677}, };
678
679module_phy_driver(qca808x_driver);
680
681static const struct mdio_device_id __maybe_unused qca808x_tbl[] = {
682	{ PHY_ID_MATCH_EXACT(QCA8081_PHY_ID) },
683	{ }
684};
685
686MODULE_DEVICE_TABLE(mdio, qca808x_tbl);