at803x.c

   1// SPDX-License-Identifier: GPL-2.0+
   2/*
   3 * drivers/net/phy/at803x.c
   4 *
   5 * Driver for Qualcomm Atheros AR803x PHY
   6 *
   7 * Author: Matus Ujhelyi <ujhelyi.m@gmail.com>
   8 */
   9
  10#include <linux/phy.h>
  11#include <linux/module.h>
  12#include <linux/string.h>
  13#include <linux/netdevice.h>
  14#include <linux/etherdevice.h>
  15#include <linux/ethtool_netlink.h>
  16#include <linux/bitfield.h>
  17#include <linux/regulator/of_regulator.h>
  18#include <linux/regulator/driver.h>
  19#include <linux/regulator/consumer.h>
  20#include <linux/of.h>
  21#include <linux/phylink.h>
  22#include <linux/reset.h>
  23#include <linux/sfp.h>
  24#include <dt-bindings/net/qca-ar803x.h>
  25
  26#include "qcom.h"
  27
  28#define AT803X_LED_CONTROL			0x18
  29
  30#define AT803X_REG_CHIP_CONFIG			0x1f
  31#define AT803X_BT_BX_REG_SEL			0x8000
  32
  33#define AT803X_MODE_CFG_MASK			0x0F
  34#define AT803X_MODE_CFG_BASET_RGMII		0x00
  35#define AT803X_MODE_CFG_BASET_SGMII		0x01
  36#define AT803X_MODE_CFG_BX1000_RGMII_50OHM	0x02
  37#define AT803X_MODE_CFG_BX1000_RGMII_75OHM	0x03
  38#define AT803X_MODE_CFG_BX1000_CONV_50OHM	0x04
  39#define AT803X_MODE_CFG_BX1000_CONV_75OHM	0x05
  40#define AT803X_MODE_CFG_FX100_RGMII_50OHM	0x06
  41#define AT803X_MODE_CFG_FX100_CONV_50OHM	0x07
  42#define AT803X_MODE_CFG_RGMII_AUTO_MDET		0x0B
  43#define AT803X_MODE_CFG_FX100_RGMII_75OHM	0x0E
  44#define AT803X_MODE_CFG_FX100_CONV_75OHM	0x0F
  45
  46#define AT803X_PSSR				0x11	/*PHY-Specific Status Register*/
  47#define AT803X_PSSR_MR_AN_COMPLETE		0x0200
  48
  49#define AT803X_DEBUG_REG_1F			0x1F
  50#define AT803X_DEBUG_PLL_ON			BIT(2)
  51#define AT803X_DEBUG_RGMII_1V8			BIT(3)
  52
  53/* AT803x supports either the XTAL input pad, an internal PLL or the
  54 * DSP as clock reference for the clock output pad. The XTAL reference
  55 * is only used for 25 MHz output, all other frequencies need the PLL.
  56 * The DSP as a clock reference is used in synchronous ethernet
  57 * applications.
  58 *
  59 * By default the PLL is only enabled if there is a link. Otherwise
  60 * the PHY will go into low power state and disabled the PLL. You can
  61 * set the PLL_ON bit (see debug register 0x1f) to keep the PLL always
  62 * enabled.
  63 */
  64#define AT803X_MMD7_CLK25M			0x8016
  65#define AT803X_CLK_OUT_MASK			GENMASK(4, 2)
  66#define AT803X_CLK_OUT_25MHZ_XTAL		0
  67#define AT803X_CLK_OUT_25MHZ_DSP		1
  68#define AT803X_CLK_OUT_50MHZ_PLL		2
  69#define AT803X_CLK_OUT_50MHZ_DSP		3
  70#define AT803X_CLK_OUT_62_5MHZ_PLL		4
  71#define AT803X_CLK_OUT_62_5MHZ_DSP		5
  72#define AT803X_CLK_OUT_125MHZ_PLL		6
  73#define AT803X_CLK_OUT_125MHZ_DSP		7
  74
  75/* The AR8035 has another mask which is compatible with the AR8031/AR8033 mask
  76 * but doesn't support choosing between XTAL/PLL and DSP.
  77 */
  78#define AT8035_CLK_OUT_MASK			GENMASK(4, 3)
  79
  80#define AT803X_CLK_OUT_STRENGTH_MASK		GENMASK(8, 7)
  81#define AT803X_CLK_OUT_STRENGTH_FULL		0
  82#define AT803X_CLK_OUT_STRENGTH_HALF		1
  83#define AT803X_CLK_OUT_STRENGTH_QUARTER		2
  84
  85#define AT803X_MMD3_SMARTEEE_CTL1		0x805b
  86#define AT803X_MMD3_SMARTEEE_CTL2		0x805c
  87#define AT803X_MMD3_SMARTEEE_CTL3		0x805d
  88#define AT803X_MMD3_SMARTEEE_CTL3_LPI_EN	BIT(8)
  89
  90#define ATH9331_PHY_ID				0x004dd041
  91#define ATH8030_PHY_ID				0x004dd076
  92#define ATH8031_PHY_ID				0x004dd074
  93#define ATH8032_PHY_ID				0x004dd023
  94#define ATH8035_PHY_ID				0x004dd072
  95#define AT8030_PHY_ID_MASK			0xffffffef
  96
  97#define IPQ5018_PHY_ID				0x004dd0c0
  98
  99#define QCA9561_PHY_ID				0x004dd042
 100
 101#define AT803X_PAGE_FIBER			0
 102#define AT803X_PAGE_COPPER			1
 103
 104/* don't turn off internal PLL */
 105#define AT803X_KEEP_PLL_ENABLED			BIT(0)
 106#define AT803X_DISABLE_SMARTEEE			BIT(1)
 107
 108/* disable hibernation mode */
 109#define AT803X_DISABLE_HIBERNATION_MODE		BIT(2)
 110
 111#define IPQ5018_PHY_FIFO_CONTROL		0x19
 112#define IPQ5018_PHY_FIFO_RESET			GENMASK(1, 0)
 113
 114#define IPQ5018_PHY_DEBUG_EDAC			0x4380
 115#define IPQ5018_PHY_MMD1_MDAC			0x8100
 116#define IPQ5018_PHY_DAC_MASK			GENMASK(15, 8)
 117
 118/* MDAC and EDAC values for short cable length */
 119#define IPQ5018_PHY_DEBUG_EDAC_VAL		0x10
 120#define IPQ5018_PHY_MMD1_MDAC_VAL		0x10
 121
 122#define IPQ5018_PHY_MMD1_MSE_THRESH1		0x1000
 123#define IPQ5018_PHY_MMD1_MSE_THRESH2		0x1001
 124#define IPQ5018_PHY_PCS_EEE_TX_TIMER		0x8008
 125#define IPQ5018_PHY_PCS_EEE_RX_TIMER		0x8009
 126#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL3	0x8074
 127#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL4	0x8075
 128#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL5	0x8076
 129#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL6	0x8077
 130#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL7	0x8078
 131#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL9	0x807a
 132#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL13	0x807e
 133#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL14	0x807f
 134
 135#define IPQ5018_PHY_MMD1_MSE_THRESH1_VAL	0xf1
 136#define IPQ5018_PHY_MMD1_MSE_THRESH2_VAL	0x1f6
 137#define IPQ5018_PHY_PCS_EEE_TX_TIMER_VAL	0x7880
 138#define IPQ5018_PHY_PCS_EEE_RX_TIMER_VAL	0xc8
 139#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL3_VAL	0xc040
 140#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL4_VAL	0xa060
 141#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL5_VAL	0xc040
 142#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL6_VAL	0xa060
 143#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL7_VAL	0xc24c
 144#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL9_VAL	0xc060
 145#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL13_VAL	0xb060
 146#define IPQ5018_PHY_PCS_NEAR_ECHO_THRESH_VAL	0x90b0
 147
 148#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE		0x1
 149#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK	GENMASK(7, 4)
 150#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT	0x50
 151#define IPQ5018_PHY_DEBUG_ANA_DAC_FILTER	0xa080
 152
 153MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver");
 154MODULE_AUTHOR("Matus Ujhelyi");
 155MODULE_LICENSE("GPL");
 156
 157struct at803x_priv {
 158	int flags;
 159	u16 clk_25m_reg;
 160	u16 clk_25m_mask;
 161	u8 smarteee_lpi_tw_1g;
 162	u8 smarteee_lpi_tw_100m;
 163	bool is_fiber;
 164	bool is_1000basex;
 165	struct regulator_dev *vddio_rdev;
 166	struct regulator_dev *vddh_rdev;
 167};
 168
 169struct at803x_context {
 170	u16 bmcr;
 171	u16 advertise;
 172	u16 control1000;
 173	u16 int_enable;
 174	u16 smart_speed;
 175	u16 led_control;
 176};
 177
 178struct ipq5018_priv {
 179	struct reset_control *rst;
 180	bool set_short_cable_dac;
 181};
 182
 183static int at803x_write_page(struct phy_device *phydev, int page)
 184{
 185	int mask;
 186	int set;
 187
 188	if (page == AT803X_PAGE_COPPER) {
 189		set = AT803X_BT_BX_REG_SEL;
 190		mask = 0;
 191	} else {
 192		set = 0;
 193		mask = AT803X_BT_BX_REG_SEL;
 194	}
 195
 196	return __phy_modify(phydev, AT803X_REG_CHIP_CONFIG, mask, set);
 197}
 198
 199static int at803x_read_page(struct phy_device *phydev)
 200{
 201	int ccr = __phy_read(phydev, AT803X_REG_CHIP_CONFIG);
 202
 203	if (ccr < 0)
 204		return ccr;
 205
 206	if (ccr & AT803X_BT_BX_REG_SEL)
 207		return AT803X_PAGE_COPPER;
 208
 209	return AT803X_PAGE_FIBER;
 210}
 211
 212static int at803x_enable_rx_delay(struct phy_device *phydev)
 213{
 214	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL, 0,
 215				     AT803X_DEBUG_RX_CLK_DLY_EN);
 216}
 217
 218static int at803x_enable_tx_delay(struct phy_device *phydev)
 219{
 220	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE, 0,
 221				     AT803X_DEBUG_TX_CLK_DLY_EN);
 222}
 223
 224static int at803x_disable_rx_delay(struct phy_device *phydev)
 225{
 226	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_ANALOG_TEST_CTRL,
 227				     AT803X_DEBUG_RX_CLK_DLY_EN, 0);
 228}
 229
 230static int at803x_disable_tx_delay(struct phy_device *phydev)
 231{
 232	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_SYSTEM_CTRL_MODE,
 233				     AT803X_DEBUG_TX_CLK_DLY_EN, 0);
 234}
 235
 236/* save relevant PHY registers to private copy */
 237static void at803x_context_save(struct phy_device *phydev,
 238				struct at803x_context *context)
 239{
 240	context->bmcr = phy_read(phydev, MII_BMCR);
 241	context->advertise = phy_read(phydev, MII_ADVERTISE);
 242	context->control1000 = phy_read(phydev, MII_CTRL1000);
 243	context->int_enable = phy_read(phydev, AT803X_INTR_ENABLE);
 244	context->smart_speed = phy_read(phydev, AT803X_SMART_SPEED);
 245	context->led_control = phy_read(phydev, AT803X_LED_CONTROL);
 246}
 247
 248/* restore relevant PHY registers from private copy */
 249static void at803x_context_restore(struct phy_device *phydev,
 250				   const struct at803x_context *context)
 251{
 252	phy_write(phydev, MII_BMCR, context->bmcr);
 253	phy_write(phydev, MII_ADVERTISE, context->advertise);
 254	phy_write(phydev, MII_CTRL1000, context->control1000);
 255	phy_write(phydev, AT803X_INTR_ENABLE, context->int_enable);
 256	phy_write(phydev, AT803X_SMART_SPEED, context->smart_speed);
 257	phy_write(phydev, AT803X_LED_CONTROL, context->led_control);
 258}
 259
 260static int at803x_suspend(struct phy_device *phydev)
 261{
 262	int value;
 263	int wol_enabled;
 264
 265	value = phy_read(phydev, AT803X_INTR_ENABLE);
 266	wol_enabled = value & AT803X_INTR_ENABLE_WOL;
 267
 268	if (wol_enabled)
 269		value = BMCR_ISOLATE;
 270	else
 271		value = BMCR_PDOWN;
 272
 273	phy_modify(phydev, MII_BMCR, 0, value);
 274
 275	return 0;
 276}
 277
 278static int at803x_resume(struct phy_device *phydev)
 279{
 280	return phy_modify(phydev, MII_BMCR, BMCR_PDOWN | BMCR_ISOLATE, 0);
 281}
 282
 283static int at803x_parse_dt(struct phy_device *phydev)
 284{
 285	struct device_node *node = phydev->mdio.dev.of_node;
 286	struct at803x_priv *priv = phydev->priv;
 287	u32 freq, strength, tw;
 288	unsigned int sel;
 289	int ret;
 290
 291	if (!IS_ENABLED(CONFIG_OF_MDIO))
 292		return 0;
 293
 294	if (of_property_read_bool(node, "qca,disable-smarteee"))
 295		priv->flags |= AT803X_DISABLE_SMARTEEE;
 296
 297	if (of_property_read_bool(node, "qca,disable-hibernation-mode"))
 298		priv->flags |= AT803X_DISABLE_HIBERNATION_MODE;
 299
 300	if (!of_property_read_u32(node, "qca,smarteee-tw-us-1g", &tw)) {
 301		if (!tw || tw > 255) {
 302			phydev_err(phydev, "invalid qca,smarteee-tw-us-1g\n");
 303			return -EINVAL;
 304		}
 305		priv->smarteee_lpi_tw_1g = tw;
 306	}
 307
 308	if (!of_property_read_u32(node, "qca,smarteee-tw-us-100m", &tw)) {
 309		if (!tw || tw > 255) {
 310			phydev_err(phydev, "invalid qca,smarteee-tw-us-100m\n");
 311			return -EINVAL;
 312		}
 313		priv->smarteee_lpi_tw_100m = tw;
 314	}
 315
 316	ret = of_property_read_u32(node, "qca,clk-out-frequency", &freq);
 317	if (!ret) {
 318		switch (freq) {
 319		case 25000000:
 320			sel = AT803X_CLK_OUT_25MHZ_XTAL;
 321			break;
 322		case 50000000:
 323			sel = AT803X_CLK_OUT_50MHZ_PLL;
 324			break;
 325		case 62500000:
 326			sel = AT803X_CLK_OUT_62_5MHZ_PLL;
 327			break;
 328		case 125000000:
 329			sel = AT803X_CLK_OUT_125MHZ_PLL;
 330			break;
 331		default:
 332			phydev_err(phydev, "invalid qca,clk-out-frequency\n");
 333			return -EINVAL;
 334		}
 335
 336		priv->clk_25m_reg |= FIELD_PREP(AT803X_CLK_OUT_MASK, sel);
 337		priv->clk_25m_mask |= AT803X_CLK_OUT_MASK;
 338	}
 339
 340	ret = of_property_read_u32(node, "qca,clk-out-strength", &strength);
 341	if (!ret) {
 342		priv->clk_25m_mask |= AT803X_CLK_OUT_STRENGTH_MASK;
 343		switch (strength) {
 344		case AR803X_STRENGTH_FULL:
 345			priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_FULL;
 346			break;
 347		case AR803X_STRENGTH_HALF:
 348			priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_HALF;
 349			break;
 350		case AR803X_STRENGTH_QUARTER:
 351			priv->clk_25m_reg |= AT803X_CLK_OUT_STRENGTH_QUARTER;
 352			break;
 353		default:
 354			phydev_err(phydev, "invalid qca,clk-out-strength\n");
 355			return -EINVAL;
 356		}
 357	}
 358
 359	return 0;
 360}
 361
 362static int at803x_probe(struct phy_device *phydev)
 363{
 364	struct device *dev = &phydev->mdio.dev;
 365	struct at803x_priv *priv;
 366	int ret;
 367
 368	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 369	if (!priv)
 370		return -ENOMEM;
 371
 372	phydev->priv = priv;
 373
 374	ret = at803x_parse_dt(phydev);
 375	if (ret)
 376		return ret;
 377
 378	return 0;
 379}
 380
 381static int at803x_get_features(struct phy_device *phydev)
 382{
 383	struct at803x_priv *priv = phydev->priv;
 384	int err;
 385
 386	err = genphy_read_abilities(phydev);
 387	if (err)
 388		return err;
 389
 390	if (phydev->drv->phy_id != ATH8031_PHY_ID)
 391		return 0;
 392
 393	/* AR8031/AR8033 have different status registers
 394	 * for copper and fiber operation. However, the
 395	 * extended status register is the same for both
 396	 * operation modes.
 397	 *
 398	 * As a result of that, ESTATUS_1000_XFULL is set
 399	 * to 1 even when operating in copper TP mode.
 400	 *
 401	 * Remove this mode from the supported link modes
 402	 * when not operating in 1000BaseX mode.
 403	 */
 404	if (!priv->is_1000basex)
 405		linkmode_clear_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT,
 406				   phydev->supported);
 407
 408	return 0;
 409}
 410
 411static int at803x_smarteee_config(struct phy_device *phydev)
 412{
 413	struct at803x_priv *priv = phydev->priv;
 414	u16 mask = 0, val = 0;
 415	int ret;
 416
 417	if (priv->flags & AT803X_DISABLE_SMARTEEE)
 418		return phy_modify_mmd(phydev, MDIO_MMD_PCS,
 419				      AT803X_MMD3_SMARTEEE_CTL3,
 420				      AT803X_MMD3_SMARTEEE_CTL3_LPI_EN, 0);
 421
 422	if (priv->smarteee_lpi_tw_1g) {
 423		mask |= 0xff00;
 424		val |= priv->smarteee_lpi_tw_1g << 8;
 425	}
 426	if (priv->smarteee_lpi_tw_100m) {
 427		mask |= 0x00ff;
 428		val |= priv->smarteee_lpi_tw_100m;
 429	}
 430	if (!mask)
 431		return 0;
 432
 433	ret = phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL1,
 434			     mask, val);
 435	if (ret)
 436		return ret;
 437
 438	return phy_modify_mmd(phydev, MDIO_MMD_PCS, AT803X_MMD3_SMARTEEE_CTL3,
 439			      AT803X_MMD3_SMARTEEE_CTL3_LPI_EN,
 440			      AT803X_MMD3_SMARTEEE_CTL3_LPI_EN);
 441}
 442
 443static int at803x_clk_out_config(struct phy_device *phydev)
 444{
 445	struct at803x_priv *priv = phydev->priv;
 446
 447	if (!priv->clk_25m_mask)
 448		return 0;
 449
 450	return phy_modify_mmd(phydev, MDIO_MMD_AN, AT803X_MMD7_CLK25M,
 451			      priv->clk_25m_mask, priv->clk_25m_reg);
 452}
 453
 454static int at8031_pll_config(struct phy_device *phydev)
 455{
 456	struct at803x_priv *priv = phydev->priv;
 457
 458	/* The default after hardware reset is PLL OFF. After a soft reset, the
 459	 * values are retained.
 460	 */
 461	if (priv->flags & AT803X_KEEP_PLL_ENABLED)
 462		return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
 463					     0, AT803X_DEBUG_PLL_ON);
 464	else
 465		return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
 466					     AT803X_DEBUG_PLL_ON, 0);
 467}
 468
 469static int at803x_hibernation_mode_config(struct phy_device *phydev)
 470{
 471	struct at803x_priv *priv = phydev->priv;
 472
 473	/* The default after hardware reset is hibernation mode enabled. After
 474	 * software reset, the value is retained.
 475	 */
 476	if (!(priv->flags & AT803X_DISABLE_HIBERNATION_MODE) &&
 477	    !(phydev->dev_flags & PHY_F_RXC_ALWAYS_ON))
 478		return 0;
 479
 480	return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_HIB_CTRL,
 481					 AT803X_DEBUG_HIB_CTRL_PS_HIB_EN, 0);
 482}
 483
 484static int at803x_config_init(struct phy_device *phydev)
 485{
 486	int ret;
 487
 488	/* The RX and TX delay default is:
 489	 *   after HW reset: RX delay enabled and TX delay disabled
 490	 *   after SW reset: RX delay enabled, while TX delay retains the
 491	 *   value before reset.
 492	 */
 493	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 494	    phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID)
 495		ret = at803x_enable_rx_delay(phydev);
 496	else
 497		ret = at803x_disable_rx_delay(phydev);
 498	if (ret < 0)
 499		return ret;
 500
 501	if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID ||
 502	    phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID)
 503		ret = at803x_enable_tx_delay(phydev);
 504	else
 505		ret = at803x_disable_tx_delay(phydev);
 506	if (ret < 0)
 507		return ret;
 508
 509	ret = at803x_smarteee_config(phydev);
 510	if (ret < 0)
 511		return ret;
 512
 513	ret = at803x_clk_out_config(phydev);
 514	if (ret < 0)
 515		return ret;
 516
 517	ret = at803x_hibernation_mode_config(phydev);
 518	if (ret < 0)
 519		return ret;
 520
 521	/* Ar803x extended next page bit is enabled by default. Cisco
 522	 * multigig switches read this bit and attempt to negotiate 10Gbps
 523	 * rates even if the next page bit is disabled. This is incorrect
 524	 * behaviour but we still need to accommodate it. XNP is only needed
 525	 * for 10Gbps support, so disable XNP.
 526	 */
 527	return phy_modify(phydev, MII_ADVERTISE, MDIO_AN_CTRL1_XNP, 0);
 528}
 529
 530static void at803x_link_change_notify(struct phy_device *phydev)
 531{
 532	/*
 533	 * Conduct a hardware reset for AT8030 every time a link loss is
 534	 * signalled. This is necessary to circumvent a hardware bug that
 535	 * occurs when the cable is unplugged while TX packets are pending
 536	 * in the FIFO. In such cases, the FIFO enters an error mode it
 537	 * cannot recover from by software.
 538	 */
 539	if (phydev->state == PHY_NOLINK && phydev->mdio.reset_gpio) {
 540		struct at803x_context context;
 541
 542		at803x_context_save(phydev, &context);
 543
 544		phy_device_reset(phydev, 1);
 545		usleep_range(1000, 2000);
 546		phy_device_reset(phydev, 0);
 547		usleep_range(1000, 2000);
 548
 549		at803x_context_restore(phydev, &context);
 550
 551		phydev_dbg(phydev, "%s(): phy was reset\n", __func__);
 552	}
 553}
 554
 555static int at803x_config_aneg(struct phy_device *phydev)
 556{
 557	struct at803x_priv *priv = phydev->priv;
 558	int ret;
 559
 560	ret = at803x_prepare_config_aneg(phydev);
 561	if (ret)
 562		return ret;
 563
 564	if (priv->is_1000basex)
 565		return genphy_c37_config_aneg(phydev);
 566
 567	return genphy_config_aneg(phydev);
 568}
 569
 570static int at803x_cable_test_result_trans(u16 status)
 571{
 572	switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
 573	case AT803X_CDT_STATUS_STAT_NORMAL:
 574		return ETHTOOL_A_CABLE_RESULT_CODE_OK;
 575	case AT803X_CDT_STATUS_STAT_SHORT:
 576		return ETHTOOL_A_CABLE_RESULT_CODE_SAME_SHORT;
 577	case AT803X_CDT_STATUS_STAT_OPEN:
 578		return ETHTOOL_A_CABLE_RESULT_CODE_OPEN;
 579	case AT803X_CDT_STATUS_STAT_FAIL:
 580	default:
 581		return ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
 582	}
 583}
 584
 585static bool at803x_cdt_test_failed(u16 status)
 586{
 587	return FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status) ==
 588		AT803X_CDT_STATUS_STAT_FAIL;
 589}
 590
 591static bool at803x_cdt_fault_length_valid(u16 status)
 592{
 593	switch (FIELD_GET(AT803X_CDT_STATUS_STAT_MASK, status)) {
 594	case AT803X_CDT_STATUS_STAT_OPEN:
 595	case AT803X_CDT_STATUS_STAT_SHORT:
 596		return true;
 597	}
 598	return false;
 599}
 600
 601static int at803x_cable_test_one_pair(struct phy_device *phydev, int pair)
 602{
 603	static const int ethtool_pair[] = {
 604		ETHTOOL_A_CABLE_PAIR_A,
 605		ETHTOOL_A_CABLE_PAIR_B,
 606		ETHTOOL_A_CABLE_PAIR_C,
 607		ETHTOOL_A_CABLE_PAIR_D,
 608	};
 609	int ret, val;
 610
 611	val = FIELD_PREP(AT803X_CDT_MDI_PAIR_MASK, pair) |
 612	      AT803X_CDT_ENABLE_TEST;
 613	ret = at803x_cdt_start(phydev, val);
 614	if (ret)
 615		return ret;
 616
 617	ret = at803x_cdt_wait_for_completion(phydev, AT803X_CDT_ENABLE_TEST);
 618	if (ret)
 619		return ret;
 620
 621	val = phy_read(phydev, AT803X_CDT_STATUS);
 622	if (val < 0)
 623		return val;
 624
 625	if (at803x_cdt_test_failed(val))
 626		return 0;
 627
 628	ethnl_cable_test_result(phydev, ethtool_pair[pair],
 629				at803x_cable_test_result_trans(val));
 630
 631	if (at803x_cdt_fault_length_valid(val)) {
 632		val = FIELD_GET(AT803X_CDT_STATUS_DELTA_TIME_MASK, val);
 633		ethnl_cable_test_fault_length(phydev, ethtool_pair[pair],
 634					      at803x_cdt_fault_length(val));
 635	}
 636
 637	return 1;
 638}
 639
 640static int at803x_cable_test_get_status(struct phy_device *phydev,
 641					bool *finished, unsigned long pair_mask)
 642{
 643	int retries = 20;
 644	int pair, ret;
 645
 646	*finished = false;
 647
 648	/* According to the datasheet the CDT can be performed when
 649	 * there is no link partner or when the link partner is
 650	 * auto-negotiating. Starting the test will restart the AN
 651	 * automatically. It seems that doing this repeatedly we will
 652	 * get a slot where our link partner won't disturb our
 653	 * measurement.
 654	 */
 655	while (pair_mask && retries--) {
 656		for_each_set_bit(pair, &pair_mask, 4) {
 657			ret = at803x_cable_test_one_pair(phydev, pair);
 658			if (ret < 0)
 659				return ret;
 660			if (ret)
 661				clear_bit(pair, &pair_mask);
 662		}
 663		if (pair_mask)
 664			msleep(250);
 665	}
 666
 667	*finished = true;
 668
 669	return 0;
 670}
 671
 672static void at803x_cable_test_autoneg(struct phy_device *phydev)
 673{
 674	/* Enable auto-negotiation, but advertise no capabilities, no link
 675	 * will be established. A restart of the auto-negotiation is not
 676	 * required, because the cable test will automatically break the link.
 677	 */
 678	phy_write(phydev, MII_BMCR, BMCR_ANENABLE);
 679	phy_write(phydev, MII_ADVERTISE, ADVERTISE_CSMA);
 680}
 681
 682static int at803x_cable_test_start(struct phy_device *phydev)
 683{
 684	at803x_cable_test_autoneg(phydev);
 685	/* we do all the (time consuming) work later */
 686	return 0;
 687}
 688
 689static int at8031_rgmii_reg_set_voltage_sel(struct regulator_dev *rdev,
 690					    unsigned int selector)
 691{
 692	struct phy_device *phydev = rdev_get_drvdata(rdev);
 693
 694	if (selector)
 695		return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
 696					     0, AT803X_DEBUG_RGMII_1V8);
 697	else
 698		return at803x_debug_reg_mask(phydev, AT803X_DEBUG_REG_1F,
 699					     AT803X_DEBUG_RGMII_1V8, 0);
 700}
 701
 702static int at8031_rgmii_reg_get_voltage_sel(struct regulator_dev *rdev)
 703{
 704	struct phy_device *phydev = rdev_get_drvdata(rdev);
 705	int val;
 706
 707	val = at803x_debug_reg_read(phydev, AT803X_DEBUG_REG_1F);
 708	if (val < 0)
 709		return val;
 710
 711	return (val & AT803X_DEBUG_RGMII_1V8) ? 1 : 0;
 712}
 713
 714static const struct regulator_ops vddio_regulator_ops = {
 715	.list_voltage = regulator_list_voltage_table,
 716	.set_voltage_sel = at8031_rgmii_reg_set_voltage_sel,
 717	.get_voltage_sel = at8031_rgmii_reg_get_voltage_sel,
 718};
 719
 720static const unsigned int vddio_voltage_table[] = {
 721	1500000,
 722	1800000,
 723};
 724
 725static const struct regulator_desc vddio_desc = {
 726	.name = "vddio",
 727	.of_match = of_match_ptr("vddio-regulator"),
 728	.n_voltages = ARRAY_SIZE(vddio_voltage_table),
 729	.volt_table = vddio_voltage_table,
 730	.ops = &vddio_regulator_ops,
 731	.type = REGULATOR_VOLTAGE,
 732	.owner = THIS_MODULE,
 733};
 734
 735static const struct regulator_ops vddh_regulator_ops = {
 736};
 737
 738static const struct regulator_desc vddh_desc = {
 739	.name = "vddh",
 740	.of_match = of_match_ptr("vddh-regulator"),
 741	.n_voltages = 1,
 742	.fixed_uV = 2500000,
 743	.ops = &vddh_regulator_ops,
 744	.type = REGULATOR_VOLTAGE,
 745	.owner = THIS_MODULE,
 746};
 747
 748static int at8031_register_regulators(struct phy_device *phydev)
 749{
 750	struct at803x_priv *priv = phydev->priv;
 751	struct device *dev = &phydev->mdio.dev;
 752	struct regulator_config config = { };
 753
 754	config.dev = dev;
 755	config.driver_data = phydev;
 756
 757	priv->vddio_rdev = devm_regulator_register(dev, &vddio_desc, &config);
 758	if (IS_ERR(priv->vddio_rdev)) {
 759		phydev_err(phydev, "failed to register VDDIO regulator\n");
 760		return PTR_ERR(priv->vddio_rdev);
 761	}
 762
 763	priv->vddh_rdev = devm_regulator_register(dev, &vddh_desc, &config);
 764	if (IS_ERR(priv->vddh_rdev)) {
 765		phydev_err(phydev, "failed to register VDDH regulator\n");
 766		return PTR_ERR(priv->vddh_rdev);
 767	}
 768
 769	return 0;
 770}
 771
 772static int at8031_sfp_insert(void *upstream, const struct sfp_eeprom_id *id)
 773{
 774	__ETHTOOL_DECLARE_LINK_MODE_MASK(phy_support);
 775	__ETHTOOL_DECLARE_LINK_MODE_MASK(sfp_support);
 776	struct phy_device *phydev = upstream;
 777	const struct sfp_module_caps *caps;
 778	phy_interface_t iface;
 779
 780	linkmode_zero(phy_support);
 781	phylink_set(phy_support, 1000baseX_Full);
 782	phylink_set(phy_support, 1000baseT_Full);
 783	phylink_set(phy_support, Autoneg);
 784	phylink_set(phy_support, Pause);
 785	phylink_set(phy_support, Asym_Pause);
 786
 787	caps = sfp_get_module_caps(phydev->sfp_bus);
 788	/* Some modules support 10G modes as well as others we support.
 789	 * Mask out non-supported modes so the correct interface is picked.
 790	 */
 791	linkmode_and(sfp_support, phy_support, caps->link_modes);
 792
 793	if (linkmode_empty(sfp_support)) {
 794		dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n");
 795		return -EINVAL;
 796	}
 797
 798	iface = sfp_select_interface(phydev->sfp_bus, sfp_support);
 799
 800	/* Only 1000Base-X is supported by AR8031/8033 as the downstream SerDes
 801	 * interface for use with SFP modules.
 802	 * However, some copper modules detected as having a preferred SGMII
 803	 * interface do default to and function in 1000Base-X mode, so just
 804	 * print a warning and allow such modules, as they may have some chance
 805	 * of working.
 806	 */
 807	if (iface == PHY_INTERFACE_MODE_SGMII)
 808		dev_warn(&phydev->mdio.dev, "module may not function if 1000Base-X not supported\n");
 809	else if (iface != PHY_INTERFACE_MODE_1000BASEX)
 810		return -EINVAL;
 811
 812	return 0;
 813}
 814
 815static const struct sfp_upstream_ops at8031_sfp_ops = {
 816	.attach = phy_sfp_attach,
 817	.detach = phy_sfp_detach,
 818	.module_insert = at8031_sfp_insert,
 819	.connect_phy = phy_sfp_connect_phy,
 820	.disconnect_phy = phy_sfp_disconnect_phy,
 821};
 822
 823static int at8031_parse_dt(struct phy_device *phydev)
 824{
 825	struct device_node *node = phydev->mdio.dev.of_node;
 826	struct at803x_priv *priv = phydev->priv;
 827	int ret;
 828
 829	if (of_property_read_bool(node, "qca,keep-pll-enabled"))
 830		priv->flags |= AT803X_KEEP_PLL_ENABLED;
 831
 832	ret = at8031_register_regulators(phydev);
 833	if (ret < 0)
 834		return ret;
 835
 836	ret = devm_regulator_get_enable_optional(&phydev->mdio.dev,
 837						 "vddio");
 838	if (ret) {
 839		phydev_err(phydev, "failed to get VDDIO regulator\n");
 840		return ret;
 841	}
 842
 843	/* Only AR8031/8033 support 1000Base-X for SFP modules */
 844	return phy_sfp_probe(phydev, &at8031_sfp_ops);
 845}
 846
 847static int at8031_probe(struct phy_device *phydev)
 848{
 849	struct at803x_priv *priv;
 850	int mode_cfg;
 851	int ccr;
 852	int ret;
 853
 854	ret = at803x_probe(phydev);
 855	if (ret)
 856		return ret;
 857
 858	priv = phydev->priv;
 859
 860	/* Only supported on AR8031/AR8033, the AR8030/AR8035 use strapping
 861	 * options.
 862	 */
 863	ret = at8031_parse_dt(phydev);
 864	if (ret)
 865		return ret;
 866
 867	ccr = phy_read(phydev, AT803X_REG_CHIP_CONFIG);
 868	if (ccr < 0)
 869		return ccr;
 870	mode_cfg = ccr & AT803X_MODE_CFG_MASK;
 871
 872	switch (mode_cfg) {
 873	case AT803X_MODE_CFG_BX1000_RGMII_50OHM:
 874	case AT803X_MODE_CFG_BX1000_RGMII_75OHM:
 875		priv->is_1000basex = true;
 876		fallthrough;
 877	case AT803X_MODE_CFG_FX100_RGMII_50OHM:
 878	case AT803X_MODE_CFG_FX100_RGMII_75OHM:
 879		priv->is_fiber = true;
 880		break;
 881	}
 882
 883	/* Disable WoL in 1588 register which is enabled
 884	 * by default
 885	 */
 886	return phy_modify_mmd(phydev, MDIO_MMD_PCS,
 887			      AT803X_PHY_MMD3_WOL_CTRL,
 888			      AT803X_WOL_EN, 0);
 889}
 890
 891static int at8031_config_init(struct phy_device *phydev)
 892{
 893	struct at803x_priv *priv = phydev->priv;
 894	int ret;
 895
 896	/* Some bootloaders leave the fiber page selected.
 897	 * Switch to the appropriate page (fiber or copper), as otherwise we
 898	 * read the PHY capabilities from the wrong page.
 899	 */
 900	phy_lock_mdio_bus(phydev);
 901	ret = at803x_write_page(phydev,
 902				priv->is_fiber ? AT803X_PAGE_FIBER :
 903						 AT803X_PAGE_COPPER);
 904	phy_unlock_mdio_bus(phydev);
 905	if (ret)
 906		return ret;
 907
 908	ret = at8031_pll_config(phydev);
 909	if (ret < 0)
 910		return ret;
 911
 912	return at803x_config_init(phydev);
 913}
 914
 915static int at8031_config_intr(struct phy_device *phydev)
 916{
 917	struct at803x_priv *priv = phydev->priv;
 918	int err, value = 0;
 919
 920	if (phydev->interrupts == PHY_INTERRUPT_ENABLED &&
 921	    priv->is_fiber) {
 922		/* Clear any pending interrupts */
 923		err = at803x_ack_interrupt(phydev);
 924		if (err)
 925			return err;
 926
 927		value |= AT803X_INTR_ENABLE_LINK_FAIL_BX;
 928		value |= AT803X_INTR_ENABLE_LINK_SUCCESS_BX;
 929
 930		err = phy_set_bits(phydev, AT803X_INTR_ENABLE, value);
 931		if (err)
 932			return err;
 933	}
 934
 935	return at803x_config_intr(phydev);
 936}
 937
 938/* AR8031 and AR8033 share the same read status logic */
 939static int at8031_read_status(struct phy_device *phydev)
 940{
 941	struct at803x_priv *priv = phydev->priv;
 942	bool changed;
 943
 944	if (priv->is_1000basex)
 945		return genphy_c37_read_status(phydev, &changed);
 946
 947	return at803x_read_status(phydev);
 948}
 949
 950/* AR8031 and AR8035 share the same cable test get status reg */
 951static int at8031_cable_test_get_status(struct phy_device *phydev,
 952					bool *finished)
 953{
 954	return at803x_cable_test_get_status(phydev, finished, 0xf);
 955}
 956
 957/* AR8031 and AR8035 share the same cable test start logic */
 958static int at8031_cable_test_start(struct phy_device *phydev)
 959{
 960	at803x_cable_test_autoneg(phydev);
 961	phy_write(phydev, MII_CTRL1000, 0);
 962	/* we do all the (time consuming) work later */
 963	return 0;
 964}
 965
 966/* AR8032, AR9331 and QCA9561 share the same cable test get status reg */
 967static int at8032_cable_test_get_status(struct phy_device *phydev,
 968					bool *finished)
 969{
 970	return at803x_cable_test_get_status(phydev, finished, 0x3);
 971}
 972
 973static int at8035_parse_dt(struct phy_device *phydev)
 974{
 975	struct at803x_priv *priv = phydev->priv;
 976
 977	/* Mask is set by the generic at803x_parse_dt
 978	 * if property is set. Assume property is set
 979	 * with the mask not zero.
 980	 */
 981	if (priv->clk_25m_mask) {
 982		/* Fixup for the AR8030/AR8035. This chip has another mask and
 983		 * doesn't support the DSP reference. Eg. the lowest bit of the
 984		 * mask. The upper two bits select the same frequencies. Mask
 985		 * the lowest bit here.
 986		 *
 987		 * Warning:
 988		 *   There was no datasheet for the AR8030 available so this is
 989		 *   just a guess. But the AR8035 is listed as pin compatible
 990		 *   to the AR8030 so there might be a good chance it works on
 991		 *   the AR8030 too.
 992		 */
 993		priv->clk_25m_reg &= AT8035_CLK_OUT_MASK;
 994		priv->clk_25m_mask &= AT8035_CLK_OUT_MASK;
 995	}
 996
 997	return 0;
 998}
 999
1000/* AR8030 and AR8035 shared the same special mask for clk_25m */
1001static int at8035_probe(struct phy_device *phydev)
1002{
1003	int ret;
1004
1005	ret = at803x_probe(phydev);
1006	if (ret)
1007		return ret;
1008
1009	return at8035_parse_dt(phydev);
1010}
1011
1012static int ipq5018_cable_test_start(struct phy_device *phydev)
1013{
1014	phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL3,
1015		      IPQ5018_PHY_PCS_CDT_THRESH_CTRL3_VAL);
1016	phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL4,
1017		      IPQ5018_PHY_PCS_CDT_THRESH_CTRL4_VAL);
1018	phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL5,
1019		      IPQ5018_PHY_PCS_CDT_THRESH_CTRL5_VAL);
1020	phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL6,
1021		      IPQ5018_PHY_PCS_CDT_THRESH_CTRL6_VAL);
1022	phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL7,
1023		      IPQ5018_PHY_PCS_CDT_THRESH_CTRL7_VAL);
1024	phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL9,
1025		      IPQ5018_PHY_PCS_CDT_THRESH_CTRL9_VAL);
1026	phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL13,
1027		      IPQ5018_PHY_PCS_CDT_THRESH_CTRL13_VAL);
1028	phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL3,
1029		      IPQ5018_PHY_PCS_NEAR_ECHO_THRESH_VAL);
1030
1031	/* we do all the (time consuming) work later */
1032	return 0;
1033}
1034
1035static int ipq5018_config_init(struct phy_device *phydev)
1036{
1037	struct ipq5018_priv *priv = phydev->priv;
1038	u16 val;
1039
1040	/*
1041	 * set LDO efuse: first temporarily store ANA_DAC_FILTER value from
1042	 * debug register as it will be reset once the ANA_LDO_EFUSE register
1043	 * is written to
1044	 */
1045	val = at803x_debug_reg_read(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER);
1046	at803x_debug_reg_mask(phydev, IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE,
1047			      IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK,
1048			      IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT);
1049	at803x_debug_reg_write(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER, val);
1050
1051	/* set 8023AZ EEE TX and RX timer values */
1052	phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_EEE_TX_TIMER,
1053		      IPQ5018_PHY_PCS_EEE_TX_TIMER_VAL);
1054	phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_EEE_RX_TIMER,
1055		      IPQ5018_PHY_PCS_EEE_RX_TIMER_VAL);
1056
1057	/* set MSE threshold values */
1058	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MSE_THRESH1,
1059		      IPQ5018_PHY_MMD1_MSE_THRESH1_VAL);
1060	phy_write_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MSE_THRESH2,
1061		      IPQ5018_PHY_MMD1_MSE_THRESH2_VAL);
1062
1063	/* PHY DAC values are optional and only set in a PHY to PHY link architecture */
1064	if (priv->set_short_cable_dac) {
1065		/* setting MDAC (Multi-level Digital-to-Analog Converter) in MMD1 */
1066		phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MDAC,
1067			       IPQ5018_PHY_DAC_MASK, IPQ5018_PHY_MMD1_MDAC_VAL);
1068
1069		/* setting EDAC (Error-detection and Correction) in debug register */
1070		at803x_debug_reg_mask(phydev, IPQ5018_PHY_DEBUG_EDAC,
1071				      IPQ5018_PHY_DAC_MASK, IPQ5018_PHY_DEBUG_EDAC_VAL);
1072	}
1073
1074	return 0;
1075}
1076
1077static void ipq5018_link_change_notify(struct phy_device *phydev)
1078{
1079	/*
1080	 * Reset the FIFO buffer upon link disconnects to clear any residual data
1081	 * which may cause issues with the FIFO which it cannot recover from.
1082	 */
1083	mdiobus_modify_changed(phydev->mdio.bus, phydev->mdio.addr,
1084			       IPQ5018_PHY_FIFO_CONTROL, IPQ5018_PHY_FIFO_RESET,
1085			       phydev->link ? IPQ5018_PHY_FIFO_RESET : 0);
1086}
1087
1088static int ipq5018_probe(struct phy_device *phydev)
1089{
1090	struct device *dev = &phydev->mdio.dev;
1091	struct ipq5018_priv *priv;
1092	int ret;
1093
1094	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
1095	if (!priv)
1096		return -ENOMEM;
1097
1098	priv->set_short_cable_dac = of_property_read_bool(dev->of_node,
1099							  "qcom,dac-preset-short-cable");
1100
1101	priv->rst = devm_reset_control_array_get_exclusive(dev);
1102	if (IS_ERR(priv->rst))
1103		return dev_err_probe(dev, PTR_ERR(priv->rst),
1104				     "failed to acquire reset\n");
1105
1106	ret = reset_control_reset(priv->rst);
1107	if (ret)
1108		return dev_err_probe(dev, ret, "failed to reset\n");
1109
1110	phydev->priv = priv;
1111
1112	return 0;
1113}
1114
1115static struct phy_driver at803x_driver[] = {
1116{
1117	/* Qualcomm Atheros AR8035 */
1118	PHY_ID_MATCH_EXACT(ATH8035_PHY_ID),
1119	.name			= "Qualcomm Atheros AR8035",
1120	.flags			= PHY_POLL_CABLE_TEST,
1121	.probe			= at8035_probe,
1122	.config_aneg		= at803x_config_aneg,
1123	.config_init		= at803x_config_init,
1124	.soft_reset		= genphy_soft_reset,
1125	.set_wol		= at803x_set_wol,
1126	.get_wol		= at803x_get_wol,
1127	.suspend		= at803x_suspend,
1128	.resume			= at803x_resume,
1129	/* PHY_GBIT_FEATURES */
1130	.read_status		= at803x_read_status,
1131	.config_intr		= at803x_config_intr,
1132	.handle_interrupt	= at803x_handle_interrupt,
1133	.get_tunable		= at803x_get_tunable,
1134	.set_tunable		= at803x_set_tunable,
1135	.cable_test_start	= at8031_cable_test_start,
1136	.cable_test_get_status	= at8031_cable_test_get_status,
1137}, {
1138	/* Qualcomm Atheros AR8030 */
1139	.phy_id			= ATH8030_PHY_ID,
1140	.name			= "Qualcomm Atheros AR8030",
1141	.phy_id_mask		= AT8030_PHY_ID_MASK,
1142	.probe			= at8035_probe,
1143	.config_init		= at803x_config_init,
1144	.link_change_notify	= at803x_link_change_notify,
1145	.set_wol		= at803x_set_wol,
1146	.get_wol		= at803x_get_wol,
1147	.suspend		= at803x_suspend,
1148	.resume			= at803x_resume,
1149	/* PHY_BASIC_FEATURES */
1150	.config_intr		= at803x_config_intr,
1151	.handle_interrupt	= at803x_handle_interrupt,
1152}, {
1153	/* Qualcomm Atheros AR8031/AR8033 */
1154	PHY_ID_MATCH_EXACT(ATH8031_PHY_ID),
1155	.name			= "Qualcomm Atheros AR8031/AR8033",
1156	.flags			= PHY_POLL_CABLE_TEST,
1157	.probe			= at8031_probe,
1158	.config_init		= at8031_config_init,
1159	.config_aneg		= at803x_config_aneg,
1160	.soft_reset		= genphy_soft_reset,
1161	.set_wol		= at8031_set_wol,
1162	.get_wol		= at803x_get_wol,
1163	.suspend		= at803x_suspend,
1164	.resume			= at803x_resume,
1165	.read_page		= at803x_read_page,
1166	.write_page		= at803x_write_page,
1167	.get_features		= at803x_get_features,
1168	.read_status		= at8031_read_status,
1169	.config_intr		= at8031_config_intr,
1170	.handle_interrupt	= at803x_handle_interrupt,
1171	.get_tunable		= at803x_get_tunable,
1172	.set_tunable		= at803x_set_tunable,
1173	.cable_test_start	= at8031_cable_test_start,
1174	.cable_test_get_status	= at8031_cable_test_get_status,
1175}, {
1176	/* Qualcomm Atheros AR8032 */
1177	PHY_ID_MATCH_EXACT(ATH8032_PHY_ID),
1178	.name			= "Qualcomm Atheros AR8032",
1179	.probe			= at803x_probe,
1180	.flags			= PHY_POLL_CABLE_TEST,
1181	.config_init		= at803x_config_init,
1182	.link_change_notify	= at803x_link_change_notify,
1183	.suspend		= at803x_suspend,
1184	.resume			= at803x_resume,
1185	/* PHY_BASIC_FEATURES */
1186	.config_intr		= at803x_config_intr,
1187	.handle_interrupt	= at803x_handle_interrupt,
1188	.cable_test_start	= at803x_cable_test_start,
1189	.cable_test_get_status	= at8032_cable_test_get_status,
1190}, {
1191	/* ATHEROS AR9331 */
1192	PHY_ID_MATCH_EXACT(ATH9331_PHY_ID),
1193	.name			= "Qualcomm Atheros AR9331 built-in PHY",
1194	.probe			= at803x_probe,
1195	.suspend		= at803x_suspend,
1196	.resume			= at803x_resume,
1197	.flags			= PHY_POLL_CABLE_TEST,
1198	/* PHY_BASIC_FEATURES */
1199	.config_intr		= at803x_config_intr,
1200	.handle_interrupt	= at803x_handle_interrupt,
1201	.cable_test_start	= at803x_cable_test_start,
1202	.cable_test_get_status	= at8032_cable_test_get_status,
1203	.read_status		= at803x_read_status,
1204	.soft_reset		= genphy_soft_reset,
1205	.config_aneg		= at803x_config_aneg,
1206}, {
1207	PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID),
1208	.name			= "Qualcomm Atheros IPQ5018 internal PHY",
1209	.flags			= PHY_IS_INTERNAL | PHY_POLL_CABLE_TEST,
1210	.probe			= ipq5018_probe,
1211	.config_init		= ipq5018_config_init,
1212	.link_change_notify	= ipq5018_link_change_notify,
1213	.read_status		= at803x_read_status,
1214	.config_intr		= at803x_config_intr,
1215	.handle_interrupt	= at803x_handle_interrupt,
1216	.cable_test_start	= ipq5018_cable_test_start,
1217	.cable_test_get_status	= qca808x_cable_test_get_status,
1218	.soft_reset		= genphy_soft_reset,
1219}, {
1220	/* Qualcomm Atheros QCA9561 */
1221	PHY_ID_MATCH_EXACT(QCA9561_PHY_ID),
1222	.name			= "Qualcomm Atheros QCA9561 built-in PHY",
1223	.probe			= at803x_probe,
1224	.suspend		= at803x_suspend,
1225	.resume			= at803x_resume,
1226	.flags			= PHY_POLL_CABLE_TEST,
1227	/* PHY_BASIC_FEATURES */
1228	.config_intr		= at803x_config_intr,
1229	.handle_interrupt	= at803x_handle_interrupt,
1230	.cable_test_start	= at803x_cable_test_start,
1231	.cable_test_get_status	= at8032_cable_test_get_status,
1232	.read_status		= at803x_read_status,
1233	.soft_reset		= genphy_soft_reset,
1234	.config_aneg		= at803x_config_aneg,
1235}, };
1236
1237module_phy_driver(at803x_driver);
1238
1239static const struct mdio_device_id __maybe_unused atheros_tbl[] = {
1240	{ ATH8030_PHY_ID, AT8030_PHY_ID_MASK },
1241	{ PHY_ID_MATCH_EXACT(ATH8031_PHY_ID) },
1242	{ PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) },
1243	{ PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) },
1244	{ PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) },
1245	{ PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID) },
1246	{ PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) },
1247	{ }
1248};
1249
1250MODULE_DEVICE_TABLE(mdio, atheros_tbl);