mscc_ptp.h

  1/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
  2/*
  3 * Driver for Microsemi VSC85xx PHYs
  4 *
  5 * Copyright (c) 2020 Microsemi Corporation
  6 */
  7
  8#ifndef _MSCC_PHY_PTP_H_
  9#define _MSCC_PHY_PTP_H_
 10
 11/* 1588 page Registers */
 12#define MSCC_PHY_TS_BIU_ADDR_CNTL	  16
 13#define BIU_ADDR_EXE			  0x8000
 14#define BIU_ADDR_READ			  0x4000
 15#define BIU_ADDR_WRITE			  0x0000
 16#define BIU_BLK_ID(x)			  ((x) << 11)
 17#define BIU_CSR_ADDR(x)			  (x)
 18#define BIU_ADDR_CNT_MAX		  8
 19
 20#define MSCC_PHY_TS_CSR_DATA_LSB	  17
 21#define MSCC_PHY_TS_CSR_DATA_MSB	  18
 22
 23#define MSCC_PHY_1588_INGR_VSC85XX_INT_STATUS  0x002d
 24#define MSCC_PHY_1588_VSC85XX_INT_STATUS  0x004d
 25#define VSC85XX_1588_INT_FIFO_ADD	  0x0004
 26#define VSC85XX_1588_INT_FIFO_OVERFLOW	  0x0001
 27
 28#define MSCC_PHY_1588_INGR_VSC85XX_INT_MASK	  0x002e
 29#define MSCC_PHY_1588_VSC85XX_INT_MASK	  0x004e
 30#define VSC85XX_1588_INT_MASK_MASK	  (VSC85XX_1588_INT_FIFO_ADD | \
 31					   VSC85XX_1588_INT_FIFO_OVERFLOW)
 32
 33/* TS CSR addresses */
 34#define MSCC_PHY_ANA_ETH1_NTX_PROT	  0x0000
 35#define ANA_ETH1_NTX_PROT_SIG_OFF_MASK	  GENMASK(20, 16)
 36#define ANA_ETH1_NTX_PROT_SIG_OFF(x)	  (((x) << 16) & ANA_ETH1_NTX_PROT_SIG_OFF_MASK)
 37#define ANA_ETH1_NTX_PROT_COMPARATOR_MASK GENMASK(2, 0)
 38#define ANA_ETH1_NTX_PROT_PTP_OAM	  0x0005
 39#define ANA_ETH1_NTX_PROT_MPLS		  0x0004
 40#define ANA_ETH1_NTX_PROT_IP_UDP_ACH_2	  0x0003
 41#define ANA_ETH1_NTX_PROT_IP_UDP_ACH_1	  0x0002
 42#define ANA_ETH1_NTX_PROT_ETH2		  0x0001
 43
 44#define MSCC_PHY_PTP_IFACE_CTRL		  0x0000
 45#define PTP_IFACE_CTRL_CLK_ENA		  0x0040
 46#define PTP_IFACE_CTRL_INGR_BYPASS	  0x0008
 47#define PTP_IFACE_CTRL_EGR_BYPASS	  0x0004
 48#define PTP_IFACE_CTRL_MII_PROT		  0x0003
 49#define PTP_IFACE_CTRL_GMII_PROT	  0x0002
 50#define PTP_IFACE_CTRL_XGMII_64_PROT	  0x0000
 51
 52#define MSCC_PHY_ANA_ETH1_NTX_PROT_VLAN_TPID	0x0001
 53#define ANA_ETH1_NTX_PROT_VLAN_TPID_MASK  GENMASK(31, 16)
 54#define ANA_ETH1_NTX_PROT_VLAN_TPID(x)	  (((x) << 16) & ANA_ETH1_NTX_PROT_VLAN_TPID_MASK)
 55
 56#define MSCC_PHY_PTP_ANALYZER_MODE	  0x0001
 57#define PTP_ANA_SPLIT_ENCAP_FLOW	  0x1000000
 58#define PTP_ANA_EGR_ENCAP_FLOW_MODE_MASK  GENMASK(22, 20)
 59#define PTP_ANA_EGR_ENCAP_FLOW_MODE(x)	  (((x) << 20) & PTP_ANA_EGR_ENCAP_FLOW_MODE_MASK)
 60#define PTP_ANA_INGR_ENCAP_FLOW_MODE_MASK GENMASK(18, 16)
 61#define PTP_ANA_INGR_ENCAP_FLOW_MODE(x)	  (((x) << 16) & PTP_ANA_INGR_ENCAP_FLOW_MODE_MASK)
 62#define PTP_ANALYZER_MODE_EGR_ENA_MASK	  GENMASK(6, 4)
 63#define PTP_ANALYZER_MODE_EGR_ENA(x)	  (((x) << 4) & PTP_ANALYZER_MODE_EGR_ENA_MASK)
 64#define PTP_ANALYZER_MODE_INGR_ENA_MASK	  GENMASK(2, 0)
 65#define PTP_ANALYZER_MODE_INGR_ENA(x)	  ((x) & PTP_ANALYZER_MODE_INGR_ENA_MASK)
 66
 67#define MSCC_PHY_ANA_ETH1_NXT_PROT_TAG	  0x0002
 68#define ANA_ETH1_NXT_PROT_TAG_ENA	  0x0001
 69
 70#define MSCC_PHY_PTP_MODE_CTRL		  0x0002
 71#define PTP_MODE_CTRL_MODE_MASK		  GENMASK(2, 0)
 72#define PTP_MODE_CTRL_PKT_MODE		  0x0004
 73
 74#define MSCC_PHY_ANA_ETH1_NXT_PROT_ETYPE_MATCH	0x0003
 75#define ANA_ETH1_NXT_PROT_ETYPE_MATCH_ENA 0x10000
 76#define ANA_ETH1_NXT_PROT_ETYPE_MATCH_MASK	GENMASK(15, 0)
 77#define ANA_ETH1_NXT_PROT_ETYPE_MATCH(x)  ((x) & ANA_ETH1_NXT_PROT_ETYPE_MATCH_MASK)
 78
 79#define MSCC_PHY_PTP_VERSION_CODE	  0x0003
 80#define PTP_IP_VERSION_MASK		  GENMASK(7, 0)
 81#define PTP_IP_VERSION_2_1		  0x0021
 82
 83#define MSCC_ANA_ETH1_FLOW_ENA(x)	  (0x0010 + ((x) << 4))
 84#define ETH1_FLOW_ENA_CHANNEL_MASK_MASK	  GENMASK(9, 8)
 85#define ETH1_FLOW_ENA_CHANNEL_MASK(x)	  (((x) << 8) & ETH1_FLOW_ENA_CHANNEL_MASK_MASK)
 86#define ETH1_FLOW_VALID_CH1	  ETH1_FLOW_ENA_CHANNEL_MASK(2)
 87#define ETH1_FLOW_VALID_CH0	  ETH1_FLOW_ENA_CHANNEL_MASK(1)
 88#define ETH1_FLOW_ENA			  0x0001
 89
 90#define MSCC_ANA_ETH1_FLOW_MATCH_MODE(x)  (MSCC_ANA_ETH1_FLOW_ENA(x) + 1)
 91#define ANA_ETH1_FLOW_MATCH_VLAN_TAG_MASK GENMASK(7, 6)
 92#define ANA_ETH1_FLOW_MATCH_VLAN_TAG(x)	  (((x) << 6) & ANA_ETH1_FLOW_MATCH_VLAN_TAG_MASK)
 93#define ANA_ETH1_FLOW_MATCH_VLAN_TAG2	  0x0200
 94#define ANA_ETH1_FLOW_MATCH_VLAN_VERIFY	  0x0010
 95
 96#define MSCC_ANA_ETH1_FLOW_ADDR_MATCH1(x) (MSCC_ANA_ETH1_FLOW_ENA(x) + 2)
 97
 98#define MSCC_ANA_ETH1_FLOW_ADDR_MATCH2(x) (MSCC_ANA_ETH1_FLOW_ENA(x) + 3)
 99#define ANA_ETH1_FLOW_ADDR_MATCH2_MASK_MASK	GENMASK(22, 20)
100#define ANA_ETH1_FLOW_ADDR_MATCH2_ANY_MULTICAST	0x400000
101#define ANA_ETH1_FLOW_ADDR_MATCH2_ANY_UNICAST	0x200000
102#define ANA_ETH1_FLOW_ADDR_MATCH2_FULL_ADDR	0x100000
103#define ANA_ETH1_FLOW_ADDR_MATCH2_SRC_DEST_MASK	GENMASK(17, 16)
104#define ANA_ETH1_FLOW_ADDR_MATCH2_SRC_DEST	0x020000
105#define ANA_ETH1_FLOW_ADDR_MATCH2_SRC	  0x010000
106#define ANA_ETH1_FLOW_ADDR_MATCH2_DEST	  0x000000
107
108#define MSCC_ANA_ETH1_FLOW_VLAN_RANGE_I_TAG(x)	(MSCC_ANA_ETH1_FLOW_ENA(x) + 4)
109#define MSCC_ANA_ETH1_FLOW_VLAN_TAG1(x)	  (MSCC_ANA_ETH1_FLOW_ENA(x) + 5)
110#define MSCC_ANA_ETH1_FLOW_VLAN_TAG2_I_TAG(x)	(MSCC_ANA_ETH1_FLOW_ENA(x) + 6)
111
112#define MSCC_PHY_PTP_LTC_CTRL		  0x0010
113#define PTP_LTC_CTRL_CLK_SEL_MASK	  GENMASK(14, 12)
114#define PTP_LTC_CTRL_CLK_SEL(x)		  (((x) << 12) & PTP_LTC_CTRL_CLK_SEL_MASK)
115#define PTP_LTC_CTRL_CLK_SEL_INTERNAL_250 PTP_LTC_CTRL_CLK_SEL(5)
116#define PTP_LTC_CTRL_AUTO_ADJ_UPDATE	  0x0010
117#define PTP_LTC_CTRL_ADD_SUB_1NS_REQ	  0x0008
118#define PTP_LTC_CTRL_ADD_1NS		  0x0004
119#define PTP_LTC_CTRL_SAVE_ENA		  0x0002
120#define PTP_LTC_CTRL_LOAD_ENA		  0x0001
121
122#define MSCC_PHY_PTP_LTC_LOAD_SEC_MSB	  0x0011
123#define PTP_LTC_LOAD_SEC_MSB(x)		  (((x) & GENMASK_ULL(47, 32)) >> 32)
124
125#define MSCC_PHY_PTP_LTC_LOAD_SEC_LSB	  0x0012
126#define PTP_LTC_LOAD_SEC_LSB(x)		  ((x) & GENMASK(31, 0))
127
128#define MSCC_PHY_PTP_LTC_LOAD_NS	  0x0013
129#define PTP_LTC_LOAD_NS(x)		  ((x) & GENMASK(31, 0))
130
131#define MSCC_PHY_PTP_LTC_SAVED_SEC_MSB	  0x0014
132#define MSCC_PHY_PTP_LTC_SAVED_SEC_LSB	  0x0015
133#define MSCC_PHY_PTP_LTC_SAVED_NS	  0x0016
134
135#define MSCC_PHY_PTP_LTC_SEQUENCE	  0x0017
136#define PTP_LTC_SEQUENCE_A_MASK		  GENMASK(3, 0)
137#define PTP_LTC_SEQUENCE_A(x)		  ((x) & PTP_LTC_SEQUENCE_A_MASK)
138
139#define MSCC_PHY_PTP_LTC_SEQ		  0x0018
140#define PTP_LTC_SEQ_ADD_SUB		  0x80000
141#define PTP_LTC_SEQ_ERR_MASK		  GENMASK(18, 0)
142#define PTP_LTC_SEQ_ERR(x)		  ((x) & PTP_LTC_SEQ_ERR_MASK)
143
144#define MSCC_PHY_PTP_LTC_AUTO_ADJ	  0x001a
145#define PTP_AUTO_ADJ_NS_ROLLOVER(x)	  ((x) & GENMASK(29, 0))
146#define PTP_AUTO_ADJ_ADD_SUB_1NS_MASK	  GENMASK(31, 30)
147#define PTP_AUTO_ADJ_SUB_1NS		  0x80000000
148#define PTP_AUTO_ADJ_ADD_1NS		  0x40000000
149
150#define MSCC_PHY_PTP_LTC_1PPS_WIDTH_ADJ	  0x001b
151#define PTP_LTC_1PPS_WIDTH_ADJ_MASK	  GENMASK(29, 0)
152
153#define MSCC_PHY_PTP_TSTAMP_FIFO_SI	  0x0020
154#define PTP_TSTAMP_FIFO_SI_EN		  0x0001
155
156#define MSCC_PHY_PTP_INGR_PREDICTOR	  0x0022
157#define PTP_INGR_PREDICTOR_EN		  0x0001
158
159#define MSCC_PHY_PTP_EGR_PREDICTOR	  0x0026
160#define PTP_EGR_PREDICTOR_EN		  0x0001
161
162#define MSCC_PHY_PTP_INGR_TSP_CTRL	  0x0035
163#define PHY_PTP_INGR_TSP_CTRL_FRACT_NS	  0x0004
164#define PHY_PTP_INGR_TSP_CTRL_LOAD_DELAYS 0x0001
165
166#define MSCC_PHY_PTP_INGR_LOCAL_LATENCY	  0x0037
167#define PTP_INGR_LOCAL_LATENCY_MASK	  GENMASK(22, 0)
168#define PTP_INGR_LOCAL_LATENCY(x)	  ((x) & PTP_INGR_LOCAL_LATENCY_MASK)
169
170#define MSCC_PHY_PTP_INGR_DELAY_FIFO	  0x003a
171#define PTP_INGR_DELAY_FIFO_DEPTH_MACSEC  0x0013
172#define PTP_INGR_DELAY_FIFO_DEPTH_DEFAULT 0x000f
173
174#define MSCC_PHY_PTP_INGR_TS_FIFO(x)	  (0x005c + (x))
175#define PTP_INGR_TS_FIFO_EMPTY		  0x80000000
176
177#define MSCC_PHY_PTP_INGR_REWRITER_CTRL	  0x0044
178#define PTP_INGR_REWRITER_REDUCE_PREAMBLE 0x0010
179#define PTP_INGR_REWRITER_FLAG_VAL	  0x0008
180#define PTP_INGR_REWRITER_FLAG_BIT_OFF_M  GENMASK(2, 0)
181#define PTP_INGR_REWRITER_FLAG_BIT_OFF(x) ((x) & PTP_INGR_REWRITER_FLAG_BIT_OFF_M)
182
183#define MSCC_PHY_PTP_EGR_STALL_LATENCY	  0x004f
184
185#define MSCC_PHY_PTP_EGR_TSP_CTRL	  0x0055
186#define PHY_PTP_EGR_TSP_CTRL_FRACT_NS	  0x0004
187#define PHY_PTP_EGR_TSP_CTRL_LOAD_DELAYS  0x0001
188
189#define MSCC_PHY_PTP_EGR_LOCAL_LATENCY	  0x0057
190#define PTP_EGR_LOCAL_LATENCY_MASK	  GENMASK(22, 0)
191#define PTP_EGR_LOCAL_LATENCY(x)	  ((x) & PTP_EGR_LOCAL_LATENCY_MASK)
192
193#define MSCC_PHY_PTP_EGR_DELAY_FIFO	  0x005a
194#define PTP_EGR_DELAY_FIFO_DEPTH_MACSEC	  0x0013
195#define PTP_EGR_DELAY_FIFO_DEPTH_DEFAULT  0x000f
196
197#define MSCC_PHY_PTP_EGR_TS_FIFO_CTRL	  0x005b
198#define PTP_EGR_TS_FIFO_RESET		  0x10000
199#define PTP_EGR_FIFO_LEVEL_LAST_READ_MASK GENMASK(15, 12)
200#define PTP_EGR_FIFO_LEVEL_LAST_READ(x)	  (((x) & PTP_EGR_FIFO_LEVEL_LAST_READ_MASK) >> 12)
201#define PTP_EGR_TS_FIFO_THRESH_MASK	  GENMASK(11, 8)
202#define PTP_EGR_TS_FIFO_THRESH(x)	  (((x) << 8) & PTP_EGR_TS_FIFO_THRESH_MASK)
203#define PTP_EGR_TS_FIFO_SIG_BYTES_MASK	  GENMASK(4, 0)
204#define PTP_EGR_TS_FIFO_SIG_BYTES(x)	  ((x) & PTP_EGR_TS_FIFO_SIG_BYTES_MASK)
205
206#define MSCC_PHY_PTP_EGR_TS_FIFO(x)	  (0x005c + (x))
207#define PTP_EGR_TS_FIFO_EMPTY		  0x80000000
208#define PTP_EGR_TS_FIFO_0_MASK		  GENMASK(15, 0)
209
210#define MSCC_PHY_PTP_EGR_REWRITER_CTRL	  0x0064
211#define PTP_EGR_REWRITER_REDUCE_PREAMBLE  0x0010
212#define PTP_EGR_REWRITER_FLAG_VAL	  0x0008
213#define PTP_EGR_REWRITER_FLAG_BIT_OFF_M   GENMASK(2, 0)
214#define PTP_EGR_REWRITER_FLAG_BIT_OFF(x)  ((x) & PTP_EGR_REWRITER_FLAG_BIT_OFF_M)
215
216#define MSCC_PHY_PTP_SERIAL_TOD_IFACE	  0x006e
217#define PTP_SERIAL_TOD_IFACE_LS_AUTO_CLR  0x0004
218
219#define MSCC_PHY_PTP_LTC_OFFSET		  0x0070
220#define PTP_LTC_OFFSET_ADJ		  BIT(31)
221#define PTP_LTC_OFFSET_ADD		  BIT(30)
222#define PTP_LTC_OFFSET_VAL(x)		  (x)
223
224#define MSCC_PHY_PTP_ACCUR_CFG_STATUS	  0x0074
225#define PTP_ACCUR_PPS_OUT_CALIB_ERR	  0x20000
226#define PTP_ACCUR_PPS_OUT_CALIB_DONE	  0x10000
227#define PTP_ACCUR_PPS_IN_CALIB_ERR	  0x4000
228#define PTP_ACCUR_PPS_IN_CALIB_DONE	  0x2000
229#define PTP_ACCUR_EGR_SOF_CALIB_ERR	  0x1000
230#define PTP_ACCUR_EGR_SOF_CALIB_DONE	  0x0800
231#define PTP_ACCUR_INGR_SOF_CALIB_ERR	  0x0400
232#define PTP_ACCUR_INGR_SOF_CALIB_DONE	  0x0200
233#define PTP_ACCUR_LOAD_SAVE_CALIB_ERR	  0x0100
234#define PTP_ACCUR_LOAD_SAVE_CALIB_DONE	  0x0080
235#define PTP_ACCUR_CALIB_TRIGG		  0x0040
236#define PTP_ACCUR_PPS_OUT_BYPASS	  0x0010
237#define PTP_ACCUR_PPS_IN_BYPASS		  0x0008
238#define PTP_ACCUR_EGR_SOF_BYPASS	  0x0004
239#define PTP_ACCUR_INGR_SOF_BYPASS	  0x0002
240#define PTP_ACCUR_LOAD_SAVE_BYPASS	  0x0001
241
242#define MSCC_PHY_ANA_ETH2_NTX_PROT	  0x0090
243#define ANA_ETH2_NTX_PROT_COMPARATOR_MASK GENMASK(2, 0)
244#define ANA_ETH2_NTX_PROT_PTP_OAM	  0x0005
245#define ANA_ETH2_NTX_PROT_MPLS		  0x0004
246#define ANA_ETH2_NTX_PROT_IP_UDP_ACH_2	  0x0003
247#define ANA_ETH2_NTX_PROT_IP_UDP_ACH_1	  0x0002
248#define ANA_ETH2_NTX_PROT_ETH2		  0x0001
249
250#define MSCC_PHY_ANA_ETH2_NXT_PROT_ETYPE_MATCH	0x0003
251#define ANA_ETH2_NXT_PROT_ETYPE_MATCH_ENA 0x10000
252#define ANA_ETH2_NXT_PROT_ETYPE_MATCH_MASK	GENMASK(15, 0)
253#define ANA_ETH2_NXT_PROT_ETYPE_MATCH(x)  ((x) & ANA_ETH2_NXT_PROT_ETYPE_MATCH_MASK)
254
255#define MSCC_ANA_ETH2_FLOW_ENA(x)	  (0x00a0 + ((x) << 4))
256#define ETH2_FLOW_ENA_CHANNEL_MASK_MASK	  GENMASK(9, 8)
257#define ETH2_FLOW_ENA_CHANNEL_MASK(x)	  (((x) << 8) & ETH2_FLOW_ENA_CHANNEL_MASK_MASK)
258#define ETH2_FLOW_VALID_CH1	  ETH2_FLOW_ENA_CHANNEL_MASK(2)
259#define ETH2_FLOW_VALID_CH0	  ETH2_FLOW_ENA_CHANNEL_MASK(1)
260
261#define MSCC_PHY_ANA_MPLS_COMP_NXT_COMP	  0x0120
262#define ANA_MPLS_NTX_PROT_COMPARATOR_MASK GENMASK(2, 0)
263#define ANA_MPLS_NTX_PROT_PTP_OAM	  0x0005
264#define ANA_MPLS_NTX_PROT_MPLS		  0x0004
265#define ANA_MPLS_NTX_PROT_IP_UDP_ACH_2	  0x0003
266#define ANA_MPLS_NTX_PROT_IP_UDP_ACH_1	  0x0002
267#define ANA_MPLS_NTX_PROT_ETH2		  0x0001
268
269#define MSCC_ANA_MPLS_FLOW_CTRL(x)	  (0x0130 + ((x) << 4))
270#define MPLS_FLOW_CTRL_CHANNEL_MASK_MASK  GENMASK(25, 24)
271#define MPLS_FLOW_CTRL_CHANNEL_MASK(x)	  (((x) << 24) & MPLS_FLOW_CTRL_CHANNEL_MASK_MASK)
272#define MPLS_FLOW_VALID_CH1		  MPLS_FLOW_CTRL_CHANNEL_MASK(2)
273#define MPLS_FLOW_VALID_CH0		  MPLS_FLOW_CTRL_CHANNEL_MASK(1)
274
275#define MSCC_ANA_IP1_NXT_PROT_NXT_COMP	  0x01b0
276#define ANA_IP1_NXT_PROT_NXT_COMP_BYTES_HDR_MASK	GENMASK(15, 8)
277#define ANA_IP1_NXT_PROT_NXT_COMP_BYTES_HDR(x)	(((x) << 8) & ANA_IP1_NXT_PROT_NXT_COMP_BYTES_HDR_MASK)
278#define ANA_IP1_NXT_PROT_NXT_COMP_PTP_OAM	0x0005
279#define ANA_IP1_NXT_PROT_NXT_COMP_IP_UDP_ACH2	0x0003
280
281#define MSCC_ANA_IP1_NXT_PROT_IP1_MODE	  0x01b1
282#define ANA_IP1_NXT_PROT_FLOW_OFFSET_IPV4 0x0c00
283#define ANA_IP1_NXT_PROT_FLOW_OFFSET_IPV6 0x0800
284#define ANA_IP1_NXT_PROT_IPV6		  0x0001
285#define ANA_IP1_NXT_PROT_IPV4		  0x0000
286
287#define MSCC_ANA_IP1_NXT_PROT_IP_MATCH1	  0x01b2
288#define ANA_IP1_NXT_PROT_IP_MATCH1_PROT_OFF_MASK	GENMASK(20, 16)
289#define ANA_IP1_NXT_PROT_IP_MATCH1_PROT_OFF(x)	(((x) << 16) & ANA_IP1_NXT_PROT_IP_MATCH1_PROT_OFF_MASK)
290#define ANA_IP1_NXT_PROT_IP_MATCH1_PROT_MASK_MASK	GENMASK(15, 8)
291#define ANA_IP1_NXT_PROT_IP_MATCH1_PROT_MASK(x)	(((x) << 15) & ANA_IP1_NXT_PROT_IP_MATCH1_PROT_MASK_MASK)
292#define ANA_IP1_NXT_PROT_IP_MATCH1_PROT_MATCH_MASK	GENMASK(7, 0)
293#define ANA_IP1_NXT_PROT_IP_MATCH1_PROT_MATCH(x)	((x) & ANA_IP1_NXT_PROT_IP_MATCH1_PROT_MATCH_MASK)
294
295#define MSCC_ANA_IP1_NXT_PROT_MATCH2_UPPER	0x01b3
296#define MSCC_ANA_IP1_NXT_PROT_MATCH2_LOWER	0x01b4
297#define MSCC_ANA_IP1_NXT_PROT_MASK2_UPPER	0x01b5
298#define MSCC_ANA_IP1_NXT_PROT_MASK2_LOWER	0x01b6
299
300#define MSCC_ANA_IP1_NXT_PROT_OFFSET2	  0x01b7
301#define ANA_IP1_NXT_PROT_OFFSET2_MASK	  GENMASK(6, 0)
302#define ANA_IP1_NXT_PROT_OFFSET2(x)	  ((x) & ANA_IP1_NXT_PROT_OFFSET2_MASK)
303
304#define MSCC_ANA_IP1_NXT_PROT_UDP_CHKSUM  0x01b8
305#define IP1_NXT_PROT_UDP_CHKSUM_OFF_MASK  GENMASK(15, 8)
306#define IP1_NXT_PROT_UDP_CHKSUM_OFF(x)	  (((x) << 8) & IP1_NXT_PROT_UDP_CHKSUM_OFF_MASK)
307#define IP1_NXT_PROT_UDP_CHKSUM_WIDTH_MASK	GENMASK(5, 4)
308#define IP1_NXT_PROT_UDP_CHKSUM_WIDTH(x)  (((x) << 4) & IP1_NXT_PROT_UDP_CHKSUM_WIDTH_MASK)
309#define IP1_NXT_PROT_UDP_CHKSUM_UPDATE	  0x0002
310#define IP1_NXT_PROT_UDP_CHKSUM_CLEAR	  0x0001
311
312#define MSCC_ANA_IP1_FLOW_ENA(x)	  (0x01c0 + ((x) << 4))
313#define IP1_FLOW_MATCH_ADDR_MASK	  GENMASK(9, 8)
314#define IP1_FLOW_MATCH_DEST_SRC_ADDR	  0x0200
315#define IP1_FLOW_MATCH_DEST_ADDR	  0x0100
316#define IP1_FLOW_MATCH_SRC_ADDR		  0x0000
317#define IP1_FLOW_ENA_CHANNEL_MASK_MASK	  GENMASK(5, 4)
318#define IP1_FLOW_ENA_CHANNEL_MASK(x)	  (((x) << 4) & IP1_FLOW_ENA_CHANNEL_MASK_MASK)
319#define IP1_FLOW_VALID_CH1		  IP1_FLOW_ENA_CHANNEL_MASK(2)
320#define IP1_FLOW_VALID_CH0		  IP1_FLOW_ENA_CHANNEL_MASK(1)
321#define IP1_FLOW_ENA			  0x0001
322
323#define MSCC_ANA_OAM_PTP_FLOW_ENA(x)	  (0x1e0 + ((x) << 4))
324#define MSCC_ANA_OAM_PTP_FLOW_MATCH_LOWER(x)	(MSCC_ANA_OAM_PTP_FLOW_ENA(x) + 2)
325#define MSCC_ANA_OAM_PTP_FLOW_MASK_LOWER(x)	(MSCC_ANA_OAM_PTP_FLOW_ENA(x) + 4)
326
327#define MSCC_ANA_OAM_PTP_FLOW_PTP_0_FIELD(x)	(MSCC_ANA_OAM_PTP_FLOW_ENA(x) + 8)
328
329#define MSCC_ANA_IP1_FLOW_MATCH_UPPER(x)  (MSCC_ANA_IP1_FLOW_ENA(x) + 1)
330#define MSCC_ANA_IP1_FLOW_MATCH_UPPER_MID(x)  (MSCC_ANA_IP1_FLOW_ENA(x) + 2)
331#define MSCC_ANA_IP1_FLOW_MATCH_LOWER_MID(x)  (MSCC_ANA_IP1_FLOW_ENA(x) + 3)
332#define MSCC_ANA_IP1_FLOW_MATCH_LOWER(x)  (MSCC_ANA_IP1_FLOW_ENA(x) + 4)
333#define MSCC_ANA_IP1_FLOW_MASK_UPPER(x)	  (MSCC_ANA_IP1_FLOW_ENA(x) + 5)
334#define MSCC_ANA_IP1_FLOW_MASK_UPPER_MID(x)	  (MSCC_ANA_IP1_FLOW_ENA(x) + 6)
335#define MSCC_ANA_IP1_FLOW_MASK_LOWER_MID(x)	  (MSCC_ANA_IP1_FLOW_ENA(x) + 7)
336#define MSCC_ANA_IP1_FLOW_MASK_LOWER(x)	  (MSCC_ANA_IP1_FLOW_ENA(x) + 8)
337
338#define MSCC_ANA_IP2_NXT_PROT_NXT_COMP	  0x0240
339#define ANA_IP2_NXT_PROT_NXT_COMP_BYTES_HDR_MASK	GENMASK(15, 8)
340#define ANA_IP2_NXT_PROT_NXT_COMP_BYTES_HDR(x)	(((x) << 8) & ANA_IP2_NXT_PROT_NXT_COMP_BYTES_HDR_MASK)
341#define ANA_IP2_NXT_PROT_NXT_COMP_PTP_OAM	0x0005
342#define ANA_IP2_NXT_PROT_NXT_COMP_IP_UDP_ACH2	0x0003
343
344#define MSCC_ANA_IP2_NXT_PROT_UDP_CHKSUM  0x0248
345#define IP2_NXT_PROT_UDP_CHKSUM_OFF_MASK  GENMASK(15, 8)
346#define IP2_NXT_PROT_UDP_CHKSUM_OFF(x)	  (((x) << 8) & IP2_NXT_PROT_UDP_CHKSUM_OFF_MASK)
347#define IP2_NXT_PROT_UDP_CHKSUM_WIDTH_MASK  GENMASK(5, 4)
348#define IP2_NXT_PROT_UDP_CHKSUM_WIDTH(x)  (((x) << 4) & IP2_NXT_PROT_UDP_CHKSUM_WIDTH_MASK)
349
350#define MSCC_ANA_IP2_FLOW_ENA(x)	  (0x0250 + ((x) << 4))
351#define IP2_FLOW_ENA_CHANNEL_MASK_MASK	  GENMASK(5, 4)
352#define IP2_FLOW_ENA_CHANNEL_MASK(x)	  (((x) << 4) & IP2_FLOW_ENA_CHANNEL_MASK_MASK)
353#define IP2_FLOW_VALID_CH1	  IP2_FLOW_ENA_CHANNEL_MASK(2)
354#define IP2_FLOW_VALID_CH0	  IP2_FLOW_ENA_CHANNEL_MASK(1)
355
356#define MSCC_ANA_PTP_FLOW_ENA(x)	  (0x02d0 + ((x) << 4))
357#define PTP_FLOW_ENA_CHANNEL_MASK_MASK	  GENMASK(5, 4)
358#define PTP_FLOW_ENA_CHANNEL_MASK(x)	  (((x) << 4) & PTP_FLOW_ENA_CHANNEL_MASK_MASK)
359#define PTP_FLOW_VALID_CH1	  PTP_FLOW_ENA_CHANNEL_MASK(2)
360#define PTP_FLOW_VALID_CH0	  PTP_FLOW_ENA_CHANNEL_MASK(1)
361#define PTP_FLOW_ENA			  0x0001
362
363#define MSCC_ANA_PTP_FLOW_MATCH_UPPER(x)  (MSCC_ANA_PTP_FLOW_ENA(x) + 1)
364#define PTP_FLOW_MSG_TYPE_MASK		  0x0F000000
365#define PTP_FLOW_MSG_PDELAY_RESP	  0x04000000
366#define PTP_FLOW_MSG_PDELAY_REQ		  0x02000000
367#define PTP_FLOW_MSG_DELAY_REQ		  0x01000000
368#define PTP_FLOW_MSG_SYNC		  0x00000000
369
370#define MSCC_ANA_PTP_FLOW_MATCH_LOWER(x)  (MSCC_ANA_PTP_FLOW_ENA(x) + 2)
371#define MSCC_ANA_PTP_FLOW_MASK_UPPER(x)	  (MSCC_ANA_PTP_FLOW_ENA(x) + 3)
372#define MSCC_ANA_PTP_FLOW_MASK_LOWER(x)	  (MSCC_ANA_PTP_FLOW_ENA(x) + 4)
373
374#define MSCC_ANA_PTP_FLOW_DOMAIN_RANGE(x) (MSCC_ANA_PTP_FLOW_ENA(x) + 5)
375#define PTP_FLOW_DOMAIN_RANGE_ENA	   0x0001
376
377#define MSCC_ANA_PTP_FLOW_PTP_ACTION(x)	  (MSCC_ANA_PTP_FLOW_ENA(x) + 6)
378#define PTP_FLOW_PTP_ACTION_MOD_FRAME_STATUS_UPDATE	0x10000000
379#define PTP_FLOW_PTP_ACTION_MOD_FRAME_STATUS_BYTE_OFFSET_MASK	GENMASK(26, 24)
380#define PTP_FLOW_PTP_ACTION_MOD_FRAME_STATUS_BYTE_OFFSET(x)	(((x) << 24) & PTP_FLOW_PTP_ACTION_MOD_FRAME_STATUS_BYTE_OFFSET_MASK)
381#define PTP_FLOW_PTP_ACTION_PTP_CMD_MASK  GENMASK(3, 0)
382#define PTP_FLOW_PTP_ACTION_PTP_CMD(x)	  ((x) & PTP_FLOW_PTP_ACTION_PTP_CMD_MASK)
383#define PTP_FLOW_PTP_ACTION_SUB_DELAY_ASYM	0x00200000
384#define PTP_FLOW_PTP_ACTION_ADD_DELAY_ASYM	0x00100000
385#define PTP_FLOW_PTP_ACTION_TIME_OFFSET_MASK	GENMASK(15, 10)
386#define PTP_FLOW_PTP_ACTION_TIME_OFFSET(x)	(((x) << 10) & PTP_FLOW_PTP_ACTION_TIME_OFFSET_MASK)
387#define PTP_FLOW_PTP_ACTION_CORR_OFFSET_MASK	GENMASK(9, 5)
388#define PTP_FLOW_PTP_ACTION_CORR_OFFSET(x)	(((x) << 5) & PTP_FLOW_PTP_ACTION_CORR_OFFSET_MASK)
389#define PTP_FLOW_PTP_ACTION_SAVE_LOCAL_TIME 0x00000010
390
391#define MSCC_ANA_PTP_FLOW_PTP_ACTION2(x)  (MSCC_ANA_PTP_FLOW_ENA(x) + 7)
392#define PTP_FLOW_PTP_ACTION2_REWRITE_OFFSET_MASK	GENMASK(15, 8)
393#define PTP_FLOW_PTP_ACTION2_REWRITE_OFFSET(x)	(((x) << 8) & PTP_FLOW_PTP_ACTION2_REWRITE_OFFSET_MASK)
394#define PTP_FLOW_PTP_ACTION2_REWRITE_BYTES_MASK	GENMASK(3, 0)
395#define PTP_FLOW_PTP_ACTION2_REWRITE_BYTES(x)	((x) & PTP_FLOW_PTP_ACTION2_REWRITE_BYTES_MASK)
396
397#define MSCC_ANA_PTP_FLOW_PTP_0_FIELD(x)  (MSCC_ANA_PTP_FLOW_ENA(x) + 8)
398#define PTP_FLOW_PTP_0_FIELD_PTP_FRAME	  0x8000
399#define PTP_FLOW_PTP_0_FIELD_RSVRD_CHECK  0x4000
400#define PTP_FLOW_PTP_0_FIELD_OFFSET_MASK  GENMASK(13, 8)
401#define PTP_FLOW_PTP_0_FIELD_OFFSET(x)	  (((x) << 8) & PTP_FLOW_PTP_0_FIELD_OFFSET_MASK)
402#define PTP_FLOW_PTP_0_FIELD_BYTES_MASK	  GENMASK(3, 0)
403#define PTP_FLOW_PTP_0_FIELD_BYTES(x)	  ((x) & PTP_FLOW_PTP_0_FIELD_BYTES_MASK)
404
405#define MSCC_ANA_PTP_IP_CHKSUM_SEL	  0x0330
406#define ANA_PTP_IP_CHKSUM_SEL_IP_COMP_2   0x0001
407#define ANA_PTP_IP_CHKSUM_SEL_IP_COMP_1	  0x0000
408
409#define MSCC_PHY_ANA_FSB_CFG		  0x331
410#define ANA_FSB_ADDR_FROM_BLOCK_SEL_MASK  GENMASK(1, 0)
411#define ANA_FSB_ADDR_FROM_IP2		  0x0003
412#define ANA_FSB_ADDR_FROM_IP1		  0x0002
413#define ANA_FSB_ADDR_FROM_ETH2		  0x0001
414#define ANA_FSB_ADDR_FROM_ETH1		  0x0000
415
416#define MSCC_PHY_ANA_FSB_REG(x)		  (0x332 + (x))
417
418#define COMP_MAX_FLOWS			  8
419#define PTP_COMP_MAX_FLOWS		  6
420
421#define PPS_WIDTH_ADJ			  0x1dcd6500
422#define STALL_EGR_LATENCY(x)		  (1536000 / (x))
423
424/* PHC clock available frequencies. */
425enum {
426	PHC_CLK_125MHZ,
427	PHC_CLK_156_25MHZ,
428	PHC_CLK_200MHZ,
429	PHC_CLK_250MHZ,
430	PHC_CLK_500MHZ,
431};
432
433enum ptp_cmd {
434	PTP_NOP = 0,
435	PTP_WRITE_1588 = 5,
436	PTP_WRITE_NS = 7,
437	PTP_SAVE_IN_TS_FIFO = 11, /* invalid when writing in reg */
438};
439
440struct vsc85xx_ptphdr {
441	u8 tsmt; /* transportSpecific | messageType */
442	u8 ver;  /* reserved0 | versionPTP */
443	__be16 msglen;
444	u8 domain;
445	u8 rsrvd1;
446	__be16 flags;
447	__be64 correction;
448	__be32 rsrvd2;
449	__be64 clk_identity;
450	__be16 src_port_id;
451	__be16 seq_id;
452	u8 ctrl;
453	u8 log_interval;
454} __attribute__((__packed__));
455
456/* Represents an entry in the timestamping FIFO */
457struct vsc85xx_ts_fifo {
458	u32 ns;
459	u64 secs:48;
460	u8 sig[16];
461} __attribute__((__packed__));
462
463struct vsc85xx_ptp {
464	struct phy_device *phydev;
465	struct ptp_clock *ptp_clock;
466	struct ptp_clock_info caps;
467	struct sk_buff_head tx_queue;
468	enum hwtstamp_tx_types tx_type;
469	enum hwtstamp_rx_filters rx_filter;
470	u8 configured:1;
471};
472
473#endif /* _MSCC_PHY_PTP_H_ */