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motorcomm.c
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linux-6.19.14/drivers/net/phy/motorcomm.c
1// SPDX-License-Identifier: GPL-2.0+ 2/* 3 * Motorcomm 8511/8521/8531/8531S/8821 PHY driver. 4 * 5 * Author: Peter Geis <pgwipeout@gmail.com> 6 * Author: Frank <Frank.Sae@motor-comm.com> 7 */ 8 9#include <linux/etherdevice.h> 10#include <linux/kernel.h> 11#include <linux/module.h> 12#include <linux/phy.h> 13#include <linux/of.h> 14 15#define PHY_ID_YT8511 0x0000010a 16#define PHY_ID_YT8521 0x0000011a 17#define PHY_ID_YT8531 0x4f51e91b 18#define PHY_ID_YT8531S 0x4f51e91a 19#define PHY_ID_YT8821 0x4f51ea19 20/* YT8521/YT8531S/YT8821 Register Overview 21 * UTP Register space | FIBER Register space 22 * ------------------------------------------------------------ 23 * | UTP MII | FIBER MII | 24 * | UTP MMD | | 25 * | UTP Extended | FIBER Extended | 26 * ------------------------------------------------------------ 27 * | Common Extended | 28 * ------------------------------------------------------------ 29 */ 30 31/* 0x10 ~ 0x15 , 0x1E and 0x1F are common MII registers of yt phy */ 32 33/* Specific Function Control Register */ 34#define YTPHY_SPECIFIC_FUNCTION_CONTROL_REG 0x10 35 36/* 2b00 Manual MDI configuration 37 * 2b01 Manual MDIX configuration 38 * 2b10 Reserved 39 * 2b11 Enable automatic crossover for all modes *default* 40 */ 41#define YTPHY_SFCR_MDI_CROSSOVER_MODE_MASK (BIT(6) | BIT(5)) 42#define YTPHY_SFCR_CROSSOVER_EN BIT(3) 43#define YTPHY_SFCR_SQE_TEST_EN BIT(2) 44#define YTPHY_SFCR_POLARITY_REVERSAL_EN BIT(1) 45#define YTPHY_SFCR_JABBER_DIS BIT(0) 46 47/* Specific Status Register */ 48#define YTPHY_SPECIFIC_STATUS_REG 0x11 49#define YTPHY_SSR_SPEED_MASK ((0x3 << 14) | BIT(9)) 50#define YTPHY_SSR_SPEED_10M ((0x0 << 14)) 51#define YTPHY_SSR_SPEED_100M ((0x1 << 14)) 52#define YTPHY_SSR_SPEED_1000M ((0x2 << 14)) 53#define YTPHY_SSR_SPEED_10G ((0x3 << 14)) 54#define YTPHY_SSR_SPEED_2500M ((0x0 << 14) | BIT(9)) 55#define YTPHY_SSR_DUPLEX_OFFSET 13 56#define YTPHY_SSR_DUPLEX BIT(13) 57#define YTPHY_SSR_PAGE_RECEIVED BIT(12) 58#define YTPHY_SSR_SPEED_DUPLEX_RESOLVED BIT(11) 59#define YTPHY_SSR_LINK BIT(10) 60#define YTPHY_SSR_MDIX_CROSSOVER BIT(6) 61#define YTPHY_SSR_DOWNGRADE BIT(5) 62#define YTPHY_SSR_TRANSMIT_PAUSE BIT(3) 63#define YTPHY_SSR_RECEIVE_PAUSE BIT(2) 64#define YTPHY_SSR_POLARITY BIT(1) 65#define YTPHY_SSR_JABBER BIT(0) 66 67/* Interrupt enable Register */ 68#define YTPHY_INTERRUPT_ENABLE_REG 0x12 69#define YTPHY_IER_WOL BIT(6) 70 71/* Interrupt Status Register */ 72#define YTPHY_INTERRUPT_STATUS_REG 0x13 73#define YTPHY_ISR_AUTONEG_ERR BIT(15) 74#define YTPHY_ISR_SPEED_CHANGED BIT(14) 75#define YTPHY_ISR_DUPLEX_CHANGED BIT(13) 76#define YTPHY_ISR_PAGE_RECEIVED BIT(12) 77#define YTPHY_ISR_LINK_FAILED BIT(11) 78#define YTPHY_ISR_LINK_SUCCESSED BIT(10) 79#define YTPHY_ISR_WOL BIT(6) 80#define YTPHY_ISR_WIRESPEED_DOWNGRADE BIT(5) 81#define YTPHY_ISR_SERDES_LINK_FAILED BIT(3) 82#define YTPHY_ISR_SERDES_LINK_SUCCESSED BIT(2) 83#define YTPHY_ISR_POLARITY_CHANGED BIT(1) 84#define YTPHY_ISR_JABBER_HAPPENED BIT(0) 85 86/* Speed Auto Downgrade Control Register */ 87#define YTPHY_SPEED_AUTO_DOWNGRADE_CONTROL_REG 0x14 88#define YTPHY_SADCR_SPEED_DOWNGRADE_EN BIT(5) 89 90/* If these bits are set to 3, the PHY attempts five times ( 3(set value) + 91 * additional 2) before downgrading, default 0x3 92 */ 93#define YTPHY_SADCR_SPEED_RETRY_LIMIT (0x3 << 2) 94 95/* Rx Error Counter Register */ 96#define YTPHY_RX_ERROR_COUNTER_REG 0x15 97 98/* Extended Register's Address Offset Register */ 99#define YTPHY_PAGE_SELECT 0x1E 100 101/* Extended Register's Data Register */ 102#define YTPHY_PAGE_DATA 0x1F 103 104/* FIBER Auto-Negotiation link partner ability */ 105#define YTPHY_FLPA_PAUSE (0x3 << 7) 106#define YTPHY_FLPA_ASYM_PAUSE (0x2 << 7) 107 108#define YT8511_PAGE_SELECT 0x1e 109#define YT8511_PAGE 0x1f 110#define YT8511_EXT_CLK_GATE 0x0c 111#define YT8511_EXT_DELAY_DRIVE 0x0d 112#define YT8511_EXT_SLEEP_CTRL 0x27 113 114/* 2b00 25m from pll 115 * 2b01 25m from xtl *default* 116 * 2b10 62.m from pll 117 * 2b11 125m from pll 118 */ 119#define YT8511_CLK_125M (BIT(2) | BIT(1)) 120#define YT8511_PLLON_SLP BIT(14) 121 122/* RX Delay enabled = 1.8ns 1000T, 8ns 10/100T */ 123#define YT8511_DELAY_RX BIT(0) 124 125/* TX Gig-E Delay is bits 7:4, default 0x5 126 * TX Fast-E Delay is bits 15:12, default 0xf 127 * Delay = 150ps * N - 250ps 128 * On = 2000ps, off = 50ps 129 */ 130#define YT8511_DELAY_GE_TX_EN (0xf << 4) 131#define YT8511_DELAY_GE_TX_DIS (0x2 << 4) 132#define YT8511_DELAY_FE_TX_EN (0xf << 12) 133#define YT8511_DELAY_FE_TX_DIS (0x2 << 12) 134 135/* Extended register is different from MMD Register and MII Register. 136 * We can use ytphy_read_ext/ytphy_write_ext/ytphy_modify_ext function to 137 * operate extended register. 138 * Extended Register start 139 */ 140 141/* Phy gmii clock gating Register */ 142#define YT8521_CLOCK_GATING_REG 0xC 143#define YT8521_CGR_RX_CLK_EN BIT(12) 144 145#define YT8521_EXTREG_SLEEP_CONTROL1_REG 0x27 146#define YT8521_ESC1R_SLEEP_SW BIT(15) 147#define YT8521_ESC1R_PLLON_SLP BIT(14) 148 149/* Phy fiber Link timer cfg2 Register */ 150#define YT8521_LINK_TIMER_CFG2_REG 0xA5 151#define YT8521_LTCR_EN_AUTOSEN BIT(15) 152 153/* 0xA000, 0xA001, 0xA003, 0xA006 ~ 0xA00A and 0xA012 are common ext registers 154 * of yt8521 phy. There is no need to switch reg space when operating these 155 * registers. 156 */ 157 158#define YT8521_REG_SPACE_SELECT_REG 0xA000 159#define YT8521_RSSR_SPACE_MASK BIT(1) 160#define YT8521_RSSR_FIBER_SPACE (0x1 << 1) 161#define YT8521_RSSR_UTP_SPACE (0x0 << 1) 162#define YT8521_RSSR_TO_BE_ARBITRATED (0xFF) 163 164#define YT8521_CHIP_CONFIG_REG 0xA001 165#define YT8521_CCR_SW_RST BIT(15) 166#define YT8531_RGMII_LDO_VOL_MASK GENMASK(5, 4) 167#define YT8531_LDO_VOL_3V3 0x0 168#define YT8531_LDO_VOL_1V8 0x2 169 170/* 1b0 disable 1.9ns rxc clock delay *default* 171 * 1b1 enable 1.9ns rxc clock delay 172 */ 173#define YT8521_CCR_RXC_DLY_EN BIT(8) 174#define YT8521_CCR_RXC_DLY_1_900_NS 1900 175 176#define YT8521_CCR_MODE_SEL_MASK (BIT(2) | BIT(1) | BIT(0)) 177#define YT8521_CCR_MODE_UTP_TO_RGMII 0 178#define YT8521_CCR_MODE_FIBER_TO_RGMII 1 179#define YT8521_CCR_MODE_UTP_FIBER_TO_RGMII 2 180#define YT8521_CCR_MODE_UTP_TO_SGMII 3 181#define YT8521_CCR_MODE_SGPHY_TO_RGMAC 4 182#define YT8521_CCR_MODE_SGMAC_TO_RGPHY 5 183#define YT8521_CCR_MODE_UTP_TO_FIBER_AUTO 6 184#define YT8521_CCR_MODE_UTP_TO_FIBER_FORCE 7 185 186/* 3 phy polling modes,poll mode combines utp and fiber mode*/ 187#define YT8521_MODE_FIBER 0x1 188#define YT8521_MODE_UTP 0x2 189#define YT8521_MODE_POLL 0x3 190 191#define YT8521_RGMII_CONFIG1_REG 0xA003 192/* 1b0 use original tx_clk_rgmii *default* 193 * 1b1 use inverted tx_clk_rgmii. 194 */ 195#define YT8521_RC1R_TX_CLK_SEL_INVERTED BIT(14) 196#define YT8521_RC1R_RX_DELAY_MASK GENMASK(13, 10) 197#define YT8521_RC1R_FE_TX_DELAY_MASK GENMASK(7, 4) 198#define YT8521_RC1R_GE_TX_DELAY_MASK GENMASK(3, 0) 199#define YT8521_RC1R_RGMII_0_000_NS 0 200#define YT8521_RC1R_RGMII_0_150_NS 1 201#define YT8521_RC1R_RGMII_0_300_NS 2 202#define YT8521_RC1R_RGMII_0_450_NS 3 203#define YT8521_RC1R_RGMII_0_600_NS 4 204#define YT8521_RC1R_RGMII_0_750_NS 5 205#define YT8521_RC1R_RGMII_0_900_NS 6 206#define YT8521_RC1R_RGMII_1_050_NS 7 207#define YT8521_RC1R_RGMII_1_200_NS 8 208#define YT8521_RC1R_RGMII_1_350_NS 9 209#define YT8521_RC1R_RGMII_1_500_NS 10 210#define YT8521_RC1R_RGMII_1_650_NS 11 211#define YT8521_RC1R_RGMII_1_800_NS 12 212#define YT8521_RC1R_RGMII_1_950_NS 13 213#define YT8521_RC1R_RGMII_2_100_NS 14 214#define YT8521_RC1R_RGMII_2_250_NS 15 215 216/* LED CONFIG */ 217#define YT8521_MAX_LEDS 3 218#define YT8521_LED0_CFG_REG 0xA00C 219#define YT8521_LED1_CFG_REG 0xA00D 220#define YT8521_LED2_CFG_REG 0xA00E 221#define YT8521_LED_ACT_BLK_IND BIT(13) 222#define YT8521_LED_FDX_ON_EN BIT(12) 223#define YT8521_LED_HDX_ON_EN BIT(11) 224#define YT8521_LED_TXACT_BLK_EN BIT(10) 225#define YT8521_LED_RXACT_BLK_EN BIT(9) 226#define YT8521_LED_1000_ON_EN BIT(6) 227#define YT8521_LED_100_ON_EN BIT(5) 228#define YT8521_LED_10_ON_EN BIT(4) 229 230#define YTPHY_MISC_CONFIG_REG 0xA006 231#define YTPHY_MCR_FIBER_SPEED_MASK BIT(0) 232#define YTPHY_MCR_FIBER_1000BX (0x1 << 0) 233#define YTPHY_MCR_FIBER_100FX (0x0 << 0) 234 235/* WOL MAC ADDR: MACADDR2(highest), MACADDR1(middle), MACADDR0(lowest) */ 236#define YTPHY_WOL_MACADDR2_REG 0xA007 237#define YTPHY_WOL_MACADDR1_REG 0xA008 238#define YTPHY_WOL_MACADDR0_REG 0xA009 239 240#define YTPHY_WOL_CONFIG_REG 0xA00A 241#define YTPHY_WCR_INTR_SEL BIT(6) 242#define YTPHY_WCR_ENABLE BIT(3) 243 244/* 2b00 84ms 245 * 2b01 168ms *default* 246 * 2b10 336ms 247 * 2b11 672ms 248 */ 249#define YTPHY_WCR_PULSE_WIDTH_MASK (BIT(2) | BIT(1)) 250#define YTPHY_WCR_PULSE_WIDTH_672MS (BIT(2) | BIT(1)) 251 252/* 1b0 Interrupt and WOL events is level triggered and active LOW *default* 253 * 1b1 Interrupt and WOL events is pulse triggered and active LOW 254 */ 255#define YTPHY_WCR_TYPE_PULSE BIT(0) 256 257#define YTPHY_PAD_DRIVE_STRENGTH_REG 0xA010 258#define YT8531_RGMII_RXC_DS_MASK GENMASK(15, 13) 259#define YT8531_RGMII_RXD_DS_HI_MASK BIT(12) /* Bit 2 of rxd_ds */ 260#define YT8531_RGMII_RXD_DS_LOW_MASK GENMASK(5, 4) /* Bit 1/0 of rxd_ds */ 261#define YT8531_RGMII_RX_DS_DEFAULT 0x3 262 263#define YTPHY_SYNCE_CFG_REG 0xA012 264#define YT8521_SCR_SYNCE_ENABLE BIT(5) 265/* 1b0 output 25m clock 266 * 1b1 output 125m clock *default* 267 */ 268#define YT8521_SCR_CLK_FRE_SEL_125M BIT(3) 269#define YT8521_SCR_CLK_SRC_MASK GENMASK(2, 1) 270#define YT8521_SCR_CLK_SRC_PLL_125M 0 271#define YT8521_SCR_CLK_SRC_UTP_RX 1 272#define YT8521_SCR_CLK_SRC_SDS_RX 2 273#define YT8521_SCR_CLK_SRC_REF_25M 3 274#define YT8531_SCR_SYNCE_ENABLE BIT(6) 275/* 1b0 output 25m clock *default* 276 * 1b1 output 125m clock 277 */ 278#define YT8531_SCR_CLK_FRE_SEL_125M BIT(4) 279#define YT8531_SCR_CLK_SRC_MASK GENMASK(3, 1) 280#define YT8531_SCR_CLK_SRC_PLL_125M 0 281#define YT8531_SCR_CLK_SRC_UTP_RX 1 282#define YT8531_SCR_CLK_SRC_SDS_RX 2 283#define YT8531_SCR_CLK_SRC_CLOCK_FROM_DIGITAL 3 284#define YT8531_SCR_CLK_SRC_REF_25M 4 285#define YT8531_SCR_CLK_SRC_SSC_25M 5 286 287#define YT8821_SDS_EXT_CSR_CTRL_REG 0x23 288#define YT8821_SDS_EXT_CSR_VCO_LDO_EN BIT(15) 289#define YT8821_SDS_EXT_CSR_VCO_BIAS_LPF_EN BIT(8) 290 291#define YT8821_UTP_EXT_PI_CTRL_REG 0x56 292#define YT8821_UTP_EXT_PI_RST_N_FIFO BIT(5) 293#define YT8821_UTP_EXT_PI_TX_CLK_SEL_AFE BIT(4) 294#define YT8821_UTP_EXT_PI_RX_CLK_3_SEL_AFE BIT(3) 295#define YT8821_UTP_EXT_PI_RX_CLK_2_SEL_AFE BIT(2) 296#define YT8821_UTP_EXT_PI_RX_CLK_1_SEL_AFE BIT(1) 297#define YT8821_UTP_EXT_PI_RX_CLK_0_SEL_AFE BIT(0) 298 299#define YT8821_UTP_EXT_VCT_CFG6_CTRL_REG 0x97 300#define YT8821_UTP_EXT_FECHO_AMP_TH_HUGE GENMASK(15, 8) 301 302#define YT8821_UTP_EXT_ECHO_CTRL_REG 0x336 303#define YT8821_UTP_EXT_TRACE_LNG_GAIN_THR_1000 GENMASK(14, 8) 304 305#define YT8821_UTP_EXT_GAIN_CTRL_REG 0x340 306#define YT8821_UTP_EXT_TRACE_MED_GAIN_THR_1000 GENMASK(6, 0) 307 308#define YT8821_UTP_EXT_RPDN_CTRL_REG 0x34E 309#define YT8821_UTP_EXT_RPDN_BP_FFE_LNG_2500 BIT(15) 310#define YT8821_UTP_EXT_RPDN_BP_FFE_SHT_2500 BIT(7) 311#define YT8821_UTP_EXT_RPDN_IPR_SHT_2500 GENMASK(6, 0) 312 313#define YT8821_UTP_EXT_TH_20DB_2500_CTRL_REG 0x36A 314#define YT8821_UTP_EXT_TH_20DB_2500 GENMASK(15, 0) 315 316#define YT8821_UTP_EXT_TRACE_CTRL_REG 0x372 317#define YT8821_UTP_EXT_TRACE_LNG_GAIN_THE_2500 GENMASK(14, 8) 318#define YT8821_UTP_EXT_TRACE_MED_GAIN_THE_2500 GENMASK(6, 0) 319 320#define YT8821_UTP_EXT_ALPHA_IPR_CTRL_REG 0x374 321#define YT8821_UTP_EXT_ALPHA_SHT_2500 GENMASK(14, 8) 322#define YT8821_UTP_EXT_IPR_LNG_2500 GENMASK(6, 0) 323 324#define YT8821_UTP_EXT_PLL_CTRL_REG 0x450 325#define YT8821_UTP_EXT_PLL_SPARE_CFG GENMASK(7, 0) 326 327#define YT8821_UTP_EXT_DAC_IMID_CH_2_3_CTRL_REG 0x466 328#define YT8821_UTP_EXT_DAC_IMID_CH_3_10_ORG GENMASK(14, 8) 329#define YT8821_UTP_EXT_DAC_IMID_CH_2_10_ORG GENMASK(6, 0) 330 331#define YT8821_UTP_EXT_DAC_IMID_CH_0_1_CTRL_REG 0x467 332#define YT8821_UTP_EXT_DAC_IMID_CH_1_10_ORG GENMASK(14, 8) 333#define YT8821_UTP_EXT_DAC_IMID_CH_0_10_ORG GENMASK(6, 0) 334 335#define YT8821_UTP_EXT_DAC_IMSB_CH_2_3_CTRL_REG 0x468 336#define YT8821_UTP_EXT_DAC_IMSB_CH_3_10_ORG GENMASK(14, 8) 337#define YT8821_UTP_EXT_DAC_IMSB_CH_2_10_ORG GENMASK(6, 0) 338 339#define YT8821_UTP_EXT_DAC_IMSB_CH_0_1_CTRL_REG 0x469 340#define YT8821_UTP_EXT_DAC_IMSB_CH_1_10_ORG GENMASK(14, 8) 341#define YT8821_UTP_EXT_DAC_IMSB_CH_0_10_ORG GENMASK(6, 0) 342 343#define YT8821_UTP_EXT_MU_COARSE_FR_CTRL_REG 0x4B3 344#define YT8821_UTP_EXT_MU_COARSE_FR_F_FFE GENMASK(14, 12) 345#define YT8821_UTP_EXT_MU_COARSE_FR_F_FBE GENMASK(10, 8) 346 347#define YT8821_UTP_EXT_MU_FINE_FR_CTRL_REG 0x4B5 348#define YT8821_UTP_EXT_MU_FINE_FR_F_FFE GENMASK(14, 12) 349#define YT8821_UTP_EXT_MU_FINE_FR_F_FBE GENMASK(10, 8) 350 351#define YT8821_UTP_EXT_VGA_LPF1_CAP_CTRL_REG 0x4D2 352#define YT8821_UTP_EXT_VGA_LPF1_CAP_OTHER GENMASK(7, 4) 353#define YT8821_UTP_EXT_VGA_LPF1_CAP_2500 GENMASK(3, 0) 354 355#define YT8821_UTP_EXT_VGA_LPF2_CAP_CTRL_REG 0x4D3 356#define YT8821_UTP_EXT_VGA_LPF2_CAP_OTHER GENMASK(7, 4) 357#define YT8821_UTP_EXT_VGA_LPF2_CAP_2500 GENMASK(3, 0) 358 359#define YT8821_UTP_EXT_TXGE_NFR_FR_THP_CTRL_REG 0x660 360#define YT8821_UTP_EXT_NFR_TX_ABILITY BIT(3) 361/* Extended Register end */ 362 363#define YTPHY_DTS_OUTPUT_CLK_DIS 0 364#define YTPHY_DTS_OUTPUT_CLK_25M 25000000 365#define YTPHY_DTS_OUTPUT_CLK_125M 125000000 366 367#define YT8821_CHIP_MODE_AUTO_BX2500_SGMII 0 368#define YT8821_CHIP_MODE_FORCE_BX2500 1 369 370struct yt8521_priv { 371 /* combo_advertising is used for case of YT8521 in combo mode, 372 * this means that yt8521 may work in utp or fiber mode which depends 373 * on which media is connected (YT8521_RSSR_TO_BE_ARBITRATED). 374 */ 375 __ETHTOOL_DECLARE_LINK_MODE_MASK(combo_advertising); 376 377 /* YT8521_MODE_FIBER / YT8521_MODE_UTP / YT8521_MODE_POLL*/ 378 u8 polling_mode; 379 u8 strap_mode; /* 8 working modes */ 380 /* current reg page of yt8521 phy: 381 * YT8521_RSSR_UTP_SPACE 382 * YT8521_RSSR_FIBER_SPACE 383 * YT8521_RSSR_TO_BE_ARBITRATED 384 */ 385 u8 reg_page; 386}; 387 388/** 389 * ytphy_read_ext() - read a PHY's extended register 390 * @phydev: a pointer to a &struct phy_device 391 * @regnum: register number to read 392 * 393 * NOTE:The caller must have taken the MDIO bus lock. 394 * 395 * returns the value of regnum reg or negative error code 396 */ 397static int ytphy_read_ext(struct phy_device *phydev, u16 regnum) 398{ 399 int ret; 400 401 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum); 402 if (ret < 0) 403 return ret; 404 405 return __phy_read(phydev, YTPHY_PAGE_DATA); 406} 407 408/** 409 * ytphy_read_ext_with_lock() - read a PHY's extended register 410 * @phydev: a pointer to a &struct phy_device 411 * @regnum: register number to read 412 * 413 * returns the value of regnum reg or negative error code 414 */ 415static int ytphy_read_ext_with_lock(struct phy_device *phydev, u16 regnum) 416{ 417 int ret; 418 419 phy_lock_mdio_bus(phydev); 420 ret = ytphy_read_ext(phydev, regnum); 421 phy_unlock_mdio_bus(phydev); 422 423 return ret; 424} 425 426/** 427 * ytphy_write_ext() - write a PHY's extended register 428 * @phydev: a pointer to a &struct phy_device 429 * @regnum: register number to write 430 * @val: value to write to @regnum 431 * 432 * NOTE:The caller must have taken the MDIO bus lock. 433 * 434 * returns 0 or negative error code 435 */ 436static int ytphy_write_ext(struct phy_device *phydev, u16 regnum, u16 val) 437{ 438 int ret; 439 440 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum); 441 if (ret < 0) 442 return ret; 443 444 return __phy_write(phydev, YTPHY_PAGE_DATA, val); 445} 446 447/** 448 * ytphy_write_ext_with_lock() - write a PHY's extended register 449 * @phydev: a pointer to a &struct phy_device 450 * @regnum: register number to write 451 * @val: value to write to @regnum 452 * 453 * returns 0 or negative error code 454 */ 455static int ytphy_write_ext_with_lock(struct phy_device *phydev, u16 regnum, 456 u16 val) 457{ 458 int ret; 459 460 phy_lock_mdio_bus(phydev); 461 ret = ytphy_write_ext(phydev, regnum, val); 462 phy_unlock_mdio_bus(phydev); 463 464 return ret; 465} 466 467/** 468 * ytphy_modify_ext() - bits modify a PHY's extended register 469 * @phydev: a pointer to a &struct phy_device 470 * @regnum: register number to write 471 * @mask: bit mask of bits to clear 472 * @set: bit mask of bits to set 473 * 474 * NOTE: Convenience function which allows a PHY's extended register to be 475 * modified as new register value = (old register value & ~mask) | set. 476 * The caller must have taken the MDIO bus lock. 477 * 478 * returns 0 or negative error code 479 */ 480static int ytphy_modify_ext(struct phy_device *phydev, u16 regnum, u16 mask, 481 u16 set) 482{ 483 int ret; 484 485 ret = __phy_write(phydev, YTPHY_PAGE_SELECT, regnum); 486 if (ret < 0) 487 return ret; 488 489 return __phy_modify(phydev, YTPHY_PAGE_DATA, mask, set); 490} 491 492/** 493 * ytphy_modify_ext_with_lock() - bits modify a PHY's extended register 494 * @phydev: a pointer to a &struct phy_device 495 * @regnum: register number to write 496 * @mask: bit mask of bits to clear 497 * @set: bit mask of bits to set 498 * 499 * NOTE: Convenience function which allows a PHY's extended register to be 500 * modified as new register value = (old register value & ~mask) | set. 501 * 502 * returns 0 or negative error code 503 */ 504static int ytphy_modify_ext_with_lock(struct phy_device *phydev, u16 regnum, 505 u16 mask, u16 set) 506{ 507 int ret; 508 509 phy_lock_mdio_bus(phydev); 510 ret = ytphy_modify_ext(phydev, regnum, mask, set); 511 phy_unlock_mdio_bus(phydev); 512 513 return ret; 514} 515 516/** 517 * ytphy_get_wol() - report whether wake-on-lan is enabled 518 * @phydev: a pointer to a &struct phy_device 519 * @wol: a pointer to a &struct ethtool_wolinfo 520 * 521 * NOTE: YTPHY_WOL_CONFIG_REG is common ext reg. 522 */ 523static void ytphy_get_wol(struct phy_device *phydev, 524 struct ethtool_wolinfo *wol) 525{ 526 int wol_config; 527 528 wol->supported = WAKE_MAGIC; 529 wol->wolopts = 0; 530 531 wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG); 532 if (wol_config < 0) 533 return; 534 535 if (wol_config & YTPHY_WCR_ENABLE) 536 wol->wolopts |= WAKE_MAGIC; 537} 538 539/** 540 * ytphy_set_wol() - turn wake-on-lan on or off 541 * @phydev: a pointer to a &struct phy_device 542 * @wol: a pointer to a &struct ethtool_wolinfo 543 * 544 * NOTE: YTPHY_WOL_CONFIG_REG, YTPHY_WOL_MACADDR2_REG, YTPHY_WOL_MACADDR1_REG 545 * and YTPHY_WOL_MACADDR0_REG are common ext reg. The 546 * YTPHY_INTERRUPT_ENABLE_REG of UTP is special, fiber also use this register. 547 * 548 * returns 0 or negative errno code 549 */ 550static int ytphy_set_wol(struct phy_device *phydev, struct ethtool_wolinfo *wol) 551{ 552 struct net_device *p_attached_dev; 553 const u16 mac_addr_reg[] = { 554 YTPHY_WOL_MACADDR2_REG, 555 YTPHY_WOL_MACADDR1_REG, 556 YTPHY_WOL_MACADDR0_REG, 557 }; 558 const u8 *mac_addr; 559 int old_page; 560 int ret = 0; 561 u16 mask; 562 u16 val; 563 u8 i; 564 565 if (wol->wolopts & WAKE_MAGIC) { 566 p_attached_dev = phydev->attached_dev; 567 if (!p_attached_dev) 568 return -ENODEV; 569 570 mac_addr = (const u8 *)p_attached_dev->dev_addr; 571 if (!is_valid_ether_addr(mac_addr)) 572 return -EINVAL; 573 574 /* lock mdio bus then switch to utp reg space */ 575 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE); 576 if (old_page < 0) 577 goto err_restore_page; 578 579 /* Store the device address for the magic packet */ 580 for (i = 0; i < 3; i++) { 581 ret = ytphy_write_ext(phydev, mac_addr_reg[i], 582 ((mac_addr[i * 2] << 8)) | 583 (mac_addr[i * 2 + 1])); 584 if (ret < 0) 585 goto err_restore_page; 586 } 587 588 /* Enable WOL feature */ 589 mask = YTPHY_WCR_PULSE_WIDTH_MASK | YTPHY_WCR_INTR_SEL; 590 val = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL; 591 val |= YTPHY_WCR_TYPE_PULSE | YTPHY_WCR_PULSE_WIDTH_672MS; 592 ret = ytphy_modify_ext(phydev, YTPHY_WOL_CONFIG_REG, mask, val); 593 if (ret < 0) 594 goto err_restore_page; 595 596 /* Enable WOL interrupt */ 597 ret = __phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 0, 598 YTPHY_IER_WOL); 599 if (ret < 0) 600 goto err_restore_page; 601 602 } else { 603 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE); 604 if (old_page < 0) 605 goto err_restore_page; 606 607 /* Disable WOL feature */ 608 mask = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL; 609 ret = ytphy_modify_ext(phydev, YTPHY_WOL_CONFIG_REG, mask, 0); 610 611 /* Disable WOL interrupt */ 612 ret = __phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 613 YTPHY_IER_WOL, 0); 614 if (ret < 0) 615 goto err_restore_page; 616 } 617 618err_restore_page: 619 return phy_restore_page(phydev, old_page, ret); 620} 621 622static int yt8531_set_wol(struct phy_device *phydev, 623 struct ethtool_wolinfo *wol) 624{ 625 const u16 mac_addr_reg[] = { 626 YTPHY_WOL_MACADDR2_REG, 627 YTPHY_WOL_MACADDR1_REG, 628 YTPHY_WOL_MACADDR0_REG, 629 }; 630 const u8 *mac_addr; 631 u16 mask, val; 632 int ret; 633 u8 i; 634 635 if (wol->wolopts & WAKE_MAGIC) { 636 mac_addr = phydev->attached_dev->dev_addr; 637 638 /* Store the device address for the magic packet */ 639 for (i = 0; i < 3; i++) { 640 ret = ytphy_write_ext_with_lock(phydev, mac_addr_reg[i], 641 ((mac_addr[i * 2] << 8)) | 642 (mac_addr[i * 2 + 1])); 643 if (ret < 0) 644 return ret; 645 } 646 647 /* Enable WOL feature */ 648 mask = YTPHY_WCR_PULSE_WIDTH_MASK | YTPHY_WCR_INTR_SEL; 649 val = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL; 650 val |= YTPHY_WCR_TYPE_PULSE | YTPHY_WCR_PULSE_WIDTH_672MS; 651 ret = ytphy_modify_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG, 652 mask, val); 653 if (ret < 0) 654 return ret; 655 656 /* Enable WOL interrupt */ 657 ret = phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 0, 658 YTPHY_IER_WOL); 659 if (ret < 0) 660 return ret; 661 } else { 662 /* Disable WOL feature */ 663 mask = YTPHY_WCR_ENABLE | YTPHY_WCR_INTR_SEL; 664 ret = ytphy_modify_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG, 665 mask, 0); 666 667 /* Disable WOL interrupt */ 668 ret = phy_modify(phydev, YTPHY_INTERRUPT_ENABLE_REG, 669 YTPHY_IER_WOL, 0); 670 if (ret < 0) 671 return ret; 672 } 673 674 return 0; 675} 676 677static int yt8511_read_page(struct phy_device *phydev) 678{ 679 return __phy_read(phydev, YT8511_PAGE_SELECT); 680}; 681 682static int yt8511_write_page(struct phy_device *phydev, int page) 683{ 684 return __phy_write(phydev, YT8511_PAGE_SELECT, page); 685}; 686 687static int yt8511_config_init(struct phy_device *phydev) 688{ 689 int oldpage, ret = 0; 690 unsigned int ge, fe; 691 692 oldpage = phy_select_page(phydev, YT8511_EXT_CLK_GATE); 693 if (oldpage < 0) 694 goto err_restore_page; 695 696 /* set rgmii delay mode */ 697 switch (phydev->interface) { 698 case PHY_INTERFACE_MODE_RGMII: 699 ge = YT8511_DELAY_GE_TX_DIS; 700 fe = YT8511_DELAY_FE_TX_DIS; 701 break; 702 case PHY_INTERFACE_MODE_RGMII_RXID: 703 ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_DIS; 704 fe = YT8511_DELAY_FE_TX_DIS; 705 break; 706 case PHY_INTERFACE_MODE_RGMII_TXID: 707 ge = YT8511_DELAY_GE_TX_EN; 708 fe = YT8511_DELAY_FE_TX_EN; 709 break; 710 case PHY_INTERFACE_MODE_RGMII_ID: 711 ge = YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN; 712 fe = YT8511_DELAY_FE_TX_EN; 713 break; 714 default: /* do not support other modes */ 715 ret = -EOPNOTSUPP; 716 goto err_restore_page; 717 } 718 719 ret = __phy_modify(phydev, YT8511_PAGE, (YT8511_DELAY_RX | YT8511_DELAY_GE_TX_EN), ge); 720 if (ret < 0) 721 goto err_restore_page; 722 723 /* set clock mode to 125mhz */ 724 ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_CLK_125M); 725 if (ret < 0) 726 goto err_restore_page; 727 728 /* fast ethernet delay is in a separate page */ 729 ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_DELAY_DRIVE); 730 if (ret < 0) 731 goto err_restore_page; 732 733 ret = __phy_modify(phydev, YT8511_PAGE, YT8511_DELAY_FE_TX_EN, fe); 734 if (ret < 0) 735 goto err_restore_page; 736 737 /* leave pll enabled in sleep */ 738 ret = __phy_write(phydev, YT8511_PAGE_SELECT, YT8511_EXT_SLEEP_CTRL); 739 if (ret < 0) 740 goto err_restore_page; 741 742 ret = __phy_modify(phydev, YT8511_PAGE, 0, YT8511_PLLON_SLP); 743 if (ret < 0) 744 goto err_restore_page; 745 746err_restore_page: 747 return phy_restore_page(phydev, oldpage, ret); 748} 749 750/** 751 * yt8521_read_page() - read reg page 752 * @phydev: a pointer to a &struct phy_device 753 * 754 * returns current reg space of yt8521 (YT8521_RSSR_FIBER_SPACE/ 755 * YT8521_RSSR_UTP_SPACE) or negative errno code 756 */ 757static int yt8521_read_page(struct phy_device *phydev) 758{ 759 int old_page; 760 761 old_page = ytphy_read_ext(phydev, YT8521_REG_SPACE_SELECT_REG); 762 if (old_page < 0) 763 return old_page; 764 765 if ((old_page & YT8521_RSSR_SPACE_MASK) == YT8521_RSSR_FIBER_SPACE) 766 return YT8521_RSSR_FIBER_SPACE; 767 768 return YT8521_RSSR_UTP_SPACE; 769}; 770 771/** 772 * yt8521_write_page() - write reg page 773 * @phydev: a pointer to a &struct phy_device 774 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to write. 775 * 776 * returns 0 or negative errno code 777 */ 778static int yt8521_write_page(struct phy_device *phydev, int page) 779{ 780 int mask = YT8521_RSSR_SPACE_MASK; 781 int set; 782 783 if ((page & YT8521_RSSR_SPACE_MASK) == YT8521_RSSR_FIBER_SPACE) 784 set = YT8521_RSSR_FIBER_SPACE; 785 else 786 set = YT8521_RSSR_UTP_SPACE; 787 788 return ytphy_modify_ext(phydev, YT8521_REG_SPACE_SELECT_REG, mask, set); 789}; 790 791/** 792 * struct ytphy_cfg_reg_map - map a config value to a register value 793 * @cfg: value in device configuration 794 * @reg: value in the register 795 */ 796struct ytphy_cfg_reg_map { 797 u32 cfg; 798 u32 reg; 799}; 800 801static const struct ytphy_cfg_reg_map ytphy_rgmii_delays[] = { 802 /* for tx delay / rx delay with YT8521_CCR_RXC_DLY_EN is not set. */ 803 { 0, YT8521_RC1R_RGMII_0_000_NS }, 804 { 150, YT8521_RC1R_RGMII_0_150_NS }, 805 { 300, YT8521_RC1R_RGMII_0_300_NS }, 806 { 450, YT8521_RC1R_RGMII_0_450_NS }, 807 { 600, YT8521_RC1R_RGMII_0_600_NS }, 808 { 750, YT8521_RC1R_RGMII_0_750_NS }, 809 { 900, YT8521_RC1R_RGMII_0_900_NS }, 810 { 1050, YT8521_RC1R_RGMII_1_050_NS }, 811 { 1200, YT8521_RC1R_RGMII_1_200_NS }, 812 { 1350, YT8521_RC1R_RGMII_1_350_NS }, 813 { 1500, YT8521_RC1R_RGMII_1_500_NS }, 814 { 1650, YT8521_RC1R_RGMII_1_650_NS }, 815 { 1800, YT8521_RC1R_RGMII_1_800_NS }, 816 { 1950, YT8521_RC1R_RGMII_1_950_NS }, /* default tx/rx delay */ 817 { 2100, YT8521_RC1R_RGMII_2_100_NS }, 818 { 2250, YT8521_RC1R_RGMII_2_250_NS }, 819 820 /* only for rx delay with YT8521_CCR_RXC_DLY_EN is set. */ 821 { 0 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_000_NS }, 822 { 150 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_150_NS }, 823 { 300 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_300_NS }, 824 { 450 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_450_NS }, 825 { 600 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_600_NS }, 826 { 750 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_750_NS }, 827 { 900 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_0_900_NS }, 828 { 1050 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_050_NS }, 829 { 1200 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_200_NS }, 830 { 1350 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_350_NS }, 831 { 1500 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_500_NS }, 832 { 1650 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_650_NS }, 833 { 1800 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_800_NS }, 834 { 1950 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_1_950_NS }, 835 { 2100 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_2_100_NS }, 836 { 2250 + YT8521_CCR_RXC_DLY_1_900_NS, YT8521_RC1R_RGMII_2_250_NS } 837}; 838 839static u32 ytphy_get_delay_reg_value(struct phy_device *phydev, 840 const char *prop_name, 841 const struct ytphy_cfg_reg_map *tbl, 842 int tb_size, 843 u16 *rxc_dly_en, 844 u32 dflt) 845{ 846 struct device_node *node = phydev->mdio.dev.of_node; 847 int tb_size_half = tb_size / 2; 848 u32 val; 849 int i; 850 851 if (of_property_read_u32(node, prop_name, &val)) 852 goto err_dts_val; 853 854 /* when rxc_dly_en is NULL, it is get the delay for tx, only half of 855 * tb_size is valid. 856 */ 857 if (!rxc_dly_en) 858 tb_size = tb_size_half; 859 860 for (i = 0; i < tb_size; i++) { 861 if (tbl[i].cfg == val) { 862 if (rxc_dly_en && i < tb_size_half) 863 *rxc_dly_en = 0; 864 return tbl[i].reg; 865 } 866 } 867 868 phydev_warn(phydev, "Unsupported value %d for %s using default (%u)\n", 869 val, prop_name, dflt); 870 871err_dts_val: 872 /* when rxc_dly_en is not NULL, it is get the delay for rx. 873 * The rx default in dts and ytphy_rgmii_clk_delay_config is 1950 ps, 874 * so YT8521_CCR_RXC_DLY_EN should not be set. 875 */ 876 if (rxc_dly_en) 877 *rxc_dly_en = 0; 878 879 return dflt; 880} 881 882static int ytphy_rgmii_clk_delay_config(struct phy_device *phydev) 883{ 884 int tb_size = ARRAY_SIZE(ytphy_rgmii_delays); 885 u16 rxc_dly_en = YT8521_CCR_RXC_DLY_EN; 886 u32 rx_reg, tx_reg; 887 u16 mask, val = 0; 888 int ret; 889 890 rx_reg = ytphy_get_delay_reg_value(phydev, "rx-internal-delay-ps", 891 ytphy_rgmii_delays, tb_size, 892 &rxc_dly_en, 893 YT8521_RC1R_RGMII_1_950_NS); 894 tx_reg = ytphy_get_delay_reg_value(phydev, "tx-internal-delay-ps", 895 ytphy_rgmii_delays, tb_size, NULL, 896 YT8521_RC1R_RGMII_1_950_NS); 897 898 switch (phydev->interface) { 899 case PHY_INTERFACE_MODE_RGMII: 900 rxc_dly_en = 0; 901 break; 902 case PHY_INTERFACE_MODE_RGMII_RXID: 903 val |= FIELD_PREP(YT8521_RC1R_RX_DELAY_MASK, rx_reg); 904 break; 905 case PHY_INTERFACE_MODE_RGMII_TXID: 906 rxc_dly_en = 0; 907 val |= FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg); 908 break; 909 case PHY_INTERFACE_MODE_RGMII_ID: 910 val |= FIELD_PREP(YT8521_RC1R_RX_DELAY_MASK, rx_reg) | 911 FIELD_PREP(YT8521_RC1R_GE_TX_DELAY_MASK, tx_reg); 912 break; 913 default: /* do not support other modes */ 914 return -EOPNOTSUPP; 915 } 916 917 ret = ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG, 918 YT8521_CCR_RXC_DLY_EN, rxc_dly_en); 919 if (ret < 0) 920 return ret; 921 922 /* Generally, it is not necessary to adjust YT8521_RC1R_FE_TX_DELAY */ 923 mask = YT8521_RC1R_RX_DELAY_MASK | YT8521_RC1R_GE_TX_DELAY_MASK; 924 return ytphy_modify_ext(phydev, YT8521_RGMII_CONFIG1_REG, mask, val); 925} 926 927static int ytphy_rgmii_clk_delay_config_with_lock(struct phy_device *phydev) 928{ 929 int ret; 930 931 phy_lock_mdio_bus(phydev); 932 ret = ytphy_rgmii_clk_delay_config(phydev); 933 phy_unlock_mdio_bus(phydev); 934 935 return ret; 936} 937 938/** 939 * struct ytphy_ldo_vol_map - map a current value to a register value 940 * @vol: ldo voltage 941 * @ds: value in the register 942 * @cur: value in device configuration 943 */ 944struct ytphy_ldo_vol_map { 945 u32 vol; 946 u32 ds; 947 u32 cur; 948}; 949 950static const struct ytphy_ldo_vol_map yt8531_ldo_vol[] = { 951 {.vol = YT8531_LDO_VOL_1V8, .ds = 0, .cur = 1200}, 952 {.vol = YT8531_LDO_VOL_1V8, .ds = 1, .cur = 2100}, 953 {.vol = YT8531_LDO_VOL_1V8, .ds = 2, .cur = 2700}, 954 {.vol = YT8531_LDO_VOL_1V8, .ds = 3, .cur = 2910}, 955 {.vol = YT8531_LDO_VOL_1V8, .ds = 4, .cur = 3110}, 956 {.vol = YT8531_LDO_VOL_1V8, .ds = 5, .cur = 3600}, 957 {.vol = YT8531_LDO_VOL_1V8, .ds = 6, .cur = 3970}, 958 {.vol = YT8531_LDO_VOL_1V8, .ds = 7, .cur = 4350}, 959 {.vol = YT8531_LDO_VOL_3V3, .ds = 0, .cur = 3070}, 960 {.vol = YT8531_LDO_VOL_3V3, .ds = 1, .cur = 4080}, 961 {.vol = YT8531_LDO_VOL_3V3, .ds = 2, .cur = 4370}, 962 {.vol = YT8531_LDO_VOL_3V3, .ds = 3, .cur = 4680}, 963 {.vol = YT8531_LDO_VOL_3V3, .ds = 4, .cur = 5020}, 964 {.vol = YT8531_LDO_VOL_3V3, .ds = 5, .cur = 5450}, 965 {.vol = YT8531_LDO_VOL_3V3, .ds = 6, .cur = 5740}, 966 {.vol = YT8531_LDO_VOL_3V3, .ds = 7, .cur = 6140}, 967}; 968 969static u32 yt8531_get_ldo_vol(struct phy_device *phydev) 970{ 971 u32 val; 972 973 val = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG); 974 val = FIELD_GET(YT8531_RGMII_LDO_VOL_MASK, val); 975 976 return val <= YT8531_LDO_VOL_1V8 ? val : YT8531_LDO_VOL_1V8; 977} 978 979static int yt8531_get_ds_map(struct phy_device *phydev, u32 cur) 980{ 981 u32 vol; 982 int i; 983 984 vol = yt8531_get_ldo_vol(phydev); 985 for (i = 0; i < ARRAY_SIZE(yt8531_ldo_vol); i++) { 986 if (yt8531_ldo_vol[i].vol == vol && yt8531_ldo_vol[i].cur == cur) 987 return yt8531_ldo_vol[i].ds; 988 } 989 990 return -EINVAL; 991} 992 993static int yt8531_set_ds(struct phy_device *phydev) 994{ 995 struct device_node *node = phydev->mdio.dev.of_node; 996 u32 ds_field_low, ds_field_hi, val; 997 int ret, ds; 998 999 /* set rgmii rx clk driver strength */ 1000 if (!of_property_read_u32(node, "motorcomm,rx-clk-drv-microamp", &val)) { 1001 ds = yt8531_get_ds_map(phydev, val); 1002 if (ds < 0) 1003 return dev_err_probe(&phydev->mdio.dev, ds, 1004 "No matching current value was found.\n"); 1005 } else { 1006 ds = YT8531_RGMII_RX_DS_DEFAULT; 1007 } 1008 1009 ret = ytphy_modify_ext_with_lock(phydev, 1010 YTPHY_PAD_DRIVE_STRENGTH_REG, 1011 YT8531_RGMII_RXC_DS_MASK, 1012 FIELD_PREP(YT8531_RGMII_RXC_DS_MASK, ds)); 1013 if (ret < 0) 1014 return ret; 1015 1016 /* set rgmii rx data driver strength */ 1017 if (!of_property_read_u32(node, "motorcomm,rx-data-drv-microamp", &val)) { 1018 ds = yt8531_get_ds_map(phydev, val); 1019 if (ds < 0) 1020 return dev_err_probe(&phydev->mdio.dev, ds, 1021 "No matching current value was found.\n"); 1022 } else { 1023 ds = YT8531_RGMII_RX_DS_DEFAULT; 1024 } 1025 1026 ds_field_hi = FIELD_GET(BIT(2), ds); 1027 ds_field_hi = FIELD_PREP(YT8531_RGMII_RXD_DS_HI_MASK, ds_field_hi); 1028 1029 ds_field_low = FIELD_GET(GENMASK(1, 0), ds); 1030 ds_field_low = FIELD_PREP(YT8531_RGMII_RXD_DS_LOW_MASK, ds_field_low); 1031 1032 ret = ytphy_modify_ext_with_lock(phydev, 1033 YTPHY_PAD_DRIVE_STRENGTH_REG, 1034 YT8531_RGMII_RXD_DS_LOW_MASK | YT8531_RGMII_RXD_DS_HI_MASK, 1035 ds_field_low | ds_field_hi); 1036 if (ret < 0) 1037 return ret; 1038 1039 return 0; 1040} 1041 1042/** 1043 * yt8521_probe() - read chip config then set suitable polling_mode 1044 * @phydev: a pointer to a &struct phy_device 1045 * 1046 * returns 0 or negative errno code 1047 */ 1048static int yt8521_probe(struct phy_device *phydev) 1049{ 1050 struct device_node *node = phydev->mdio.dev.of_node; 1051 struct device *dev = &phydev->mdio.dev; 1052 struct yt8521_priv *priv; 1053 int chip_config; 1054 u16 mask, val; 1055 u32 freq; 1056 int ret; 1057 1058 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 1059 if (!priv) 1060 return -ENOMEM; 1061 1062 phydev->priv = priv; 1063 1064 chip_config = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG); 1065 if (chip_config < 0) 1066 return chip_config; 1067 1068 priv->strap_mode = chip_config & YT8521_CCR_MODE_SEL_MASK; 1069 switch (priv->strap_mode) { 1070 case YT8521_CCR_MODE_FIBER_TO_RGMII: 1071 case YT8521_CCR_MODE_SGPHY_TO_RGMAC: 1072 case YT8521_CCR_MODE_SGMAC_TO_RGPHY: 1073 priv->polling_mode = YT8521_MODE_FIBER; 1074 priv->reg_page = YT8521_RSSR_FIBER_SPACE; 1075 phydev->port = PORT_FIBRE; 1076 break; 1077 case YT8521_CCR_MODE_UTP_FIBER_TO_RGMII: 1078 case YT8521_CCR_MODE_UTP_TO_FIBER_AUTO: 1079 case YT8521_CCR_MODE_UTP_TO_FIBER_FORCE: 1080 priv->polling_mode = YT8521_MODE_POLL; 1081 priv->reg_page = YT8521_RSSR_TO_BE_ARBITRATED; 1082 phydev->port = PORT_NONE; 1083 break; 1084 case YT8521_CCR_MODE_UTP_TO_SGMII: 1085 case YT8521_CCR_MODE_UTP_TO_RGMII: 1086 priv->polling_mode = YT8521_MODE_UTP; 1087 priv->reg_page = YT8521_RSSR_UTP_SPACE; 1088 phydev->port = PORT_TP; 1089 break; 1090 } 1091 /* set default reg space */ 1092 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 1093 ret = ytphy_write_ext_with_lock(phydev, 1094 YT8521_REG_SPACE_SELECT_REG, 1095 priv->reg_page); 1096 if (ret < 0) 1097 return ret; 1098 } 1099 1100 if (of_property_read_u32(node, "motorcomm,clk-out-frequency-hz", &freq)) 1101 freq = YTPHY_DTS_OUTPUT_CLK_DIS; 1102 1103 if (phydev->drv->phy_id == PHY_ID_YT8521) { 1104 switch (freq) { 1105 case YTPHY_DTS_OUTPUT_CLK_DIS: 1106 mask = YT8521_SCR_SYNCE_ENABLE; 1107 val = 0; 1108 break; 1109 case YTPHY_DTS_OUTPUT_CLK_25M: 1110 mask = YT8521_SCR_SYNCE_ENABLE | 1111 YT8521_SCR_CLK_SRC_MASK | 1112 YT8521_SCR_CLK_FRE_SEL_125M; 1113 val = YT8521_SCR_SYNCE_ENABLE | 1114 FIELD_PREP(YT8521_SCR_CLK_SRC_MASK, 1115 YT8521_SCR_CLK_SRC_REF_25M); 1116 break; 1117 case YTPHY_DTS_OUTPUT_CLK_125M: 1118 mask = YT8521_SCR_SYNCE_ENABLE | 1119 YT8521_SCR_CLK_SRC_MASK | 1120 YT8521_SCR_CLK_FRE_SEL_125M; 1121 val = YT8521_SCR_SYNCE_ENABLE | 1122 YT8521_SCR_CLK_FRE_SEL_125M | 1123 FIELD_PREP(YT8521_SCR_CLK_SRC_MASK, 1124 YT8521_SCR_CLK_SRC_PLL_125M); 1125 break; 1126 default: 1127 phydev_warn(phydev, "Freq err:%u\n", freq); 1128 return -EINVAL; 1129 } 1130 } else if (phydev->drv->phy_id == PHY_ID_YT8531S) { 1131 switch (freq) { 1132 case YTPHY_DTS_OUTPUT_CLK_DIS: 1133 mask = YT8531_SCR_SYNCE_ENABLE; 1134 val = 0; 1135 break; 1136 case YTPHY_DTS_OUTPUT_CLK_25M: 1137 mask = YT8531_SCR_SYNCE_ENABLE | 1138 YT8531_SCR_CLK_SRC_MASK | 1139 YT8531_SCR_CLK_FRE_SEL_125M; 1140 val = YT8531_SCR_SYNCE_ENABLE | 1141 FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, 1142 YT8531_SCR_CLK_SRC_REF_25M); 1143 break; 1144 case YTPHY_DTS_OUTPUT_CLK_125M: 1145 mask = YT8531_SCR_SYNCE_ENABLE | 1146 YT8531_SCR_CLK_SRC_MASK | 1147 YT8531_SCR_CLK_FRE_SEL_125M; 1148 val = YT8531_SCR_SYNCE_ENABLE | 1149 YT8531_SCR_CLK_FRE_SEL_125M | 1150 FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, 1151 YT8531_SCR_CLK_SRC_PLL_125M); 1152 break; 1153 default: 1154 phydev_warn(phydev, "Freq err:%u\n", freq); 1155 return -EINVAL; 1156 } 1157 } else { 1158 phydev_warn(phydev, "PHY id err\n"); 1159 return -EINVAL; 1160 } 1161 1162 return ytphy_modify_ext_with_lock(phydev, YTPHY_SYNCE_CFG_REG, mask, 1163 val); 1164} 1165 1166static int yt8531_probe(struct phy_device *phydev) 1167{ 1168 struct device_node *node = phydev->mdio.dev.of_node; 1169 u16 mask, val; 1170 u32 freq; 1171 1172 if (of_property_read_u32(node, "motorcomm,clk-out-frequency-hz", &freq)) 1173 freq = YTPHY_DTS_OUTPUT_CLK_DIS; 1174 1175 switch (freq) { 1176 case YTPHY_DTS_OUTPUT_CLK_DIS: 1177 mask = YT8531_SCR_SYNCE_ENABLE; 1178 val = 0; 1179 break; 1180 case YTPHY_DTS_OUTPUT_CLK_25M: 1181 mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK | 1182 YT8531_SCR_CLK_FRE_SEL_125M; 1183 val = YT8531_SCR_SYNCE_ENABLE | 1184 FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, 1185 YT8531_SCR_CLK_SRC_REF_25M); 1186 break; 1187 case YTPHY_DTS_OUTPUT_CLK_125M: 1188 mask = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_SRC_MASK | 1189 YT8531_SCR_CLK_FRE_SEL_125M; 1190 val = YT8531_SCR_SYNCE_ENABLE | YT8531_SCR_CLK_FRE_SEL_125M | 1191 FIELD_PREP(YT8531_SCR_CLK_SRC_MASK, 1192 YT8531_SCR_CLK_SRC_PLL_125M); 1193 break; 1194 default: 1195 phydev_warn(phydev, "Freq err:%u\n", freq); 1196 return -EINVAL; 1197 } 1198 1199 return ytphy_modify_ext_with_lock(phydev, YTPHY_SYNCE_CFG_REG, mask, 1200 val); 1201} 1202 1203/** 1204 * ytphy_utp_read_lpa() - read LPA then setup lp_advertising for utp 1205 * @phydev: a pointer to a &struct phy_device 1206 * 1207 * NOTE:The caller must have taken the MDIO bus lock. 1208 * 1209 * returns 0 or negative errno code 1210 */ 1211static int ytphy_utp_read_lpa(struct phy_device *phydev) 1212{ 1213 int lpa, lpagb; 1214 1215 if (phydev->autoneg == AUTONEG_ENABLE) { 1216 if (!phydev->autoneg_complete) { 1217 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, 1218 0); 1219 mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, 0); 1220 return 0; 1221 } 1222 1223 if (phydev->is_gigabit_capable) { 1224 lpagb = __phy_read(phydev, MII_STAT1000); 1225 if (lpagb < 0) 1226 return lpagb; 1227 1228 if (lpagb & LPA_1000MSFAIL) { 1229 int adv = __phy_read(phydev, MII_CTRL1000); 1230 1231 if (adv < 0) 1232 return adv; 1233 1234 if (adv & CTL1000_ENABLE_MASTER) 1235 phydev_err(phydev, "Master/Slave resolution failed, maybe conflicting manual settings?\n"); 1236 else 1237 phydev_err(phydev, "Master/Slave resolution failed\n"); 1238 return -ENOLINK; 1239 } 1240 1241 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, 1242 lpagb); 1243 } 1244 1245 lpa = __phy_read(phydev, MII_LPA); 1246 if (lpa < 0) 1247 return lpa; 1248 1249 mii_lpa_mod_linkmode_lpa_t(phydev->lp_advertising, lpa); 1250 } else { 1251 linkmode_zero(phydev->lp_advertising); 1252 } 1253 1254 return 0; 1255} 1256 1257/** 1258 * yt8521_adjust_status() - update speed and duplex to phydev. when in fiber 1259 * mode, adjust speed and duplex. 1260 * @phydev: a pointer to a &struct phy_device 1261 * @status: yt8521 status read from YTPHY_SPECIFIC_STATUS_REG 1262 * @is_utp: false(yt8521 work in fiber mode) or true(yt8521 work in utp mode) 1263 * 1264 * NOTE:The caller must have taken the MDIO bus lock. 1265 * 1266 * returns 0 1267 */ 1268static int yt8521_adjust_status(struct phy_device *phydev, int status, 1269 bool is_utp) 1270{ 1271 int speed_mode, duplex; 1272 int speed; 1273 int err; 1274 int lpa; 1275 1276 if (is_utp) 1277 duplex = (status & YTPHY_SSR_DUPLEX) >> YTPHY_SSR_DUPLEX_OFFSET; 1278 else 1279 duplex = DUPLEX_FULL; /* for fiber, it always DUPLEX_FULL */ 1280 1281 speed_mode = status & YTPHY_SSR_SPEED_MASK; 1282 1283 switch (speed_mode) { 1284 case YTPHY_SSR_SPEED_10M: 1285 if (is_utp) 1286 speed = SPEED_10; 1287 else 1288 /* for fiber, it will never run here, default to 1289 * SPEED_UNKNOWN 1290 */ 1291 speed = SPEED_UNKNOWN; 1292 break; 1293 case YTPHY_SSR_SPEED_100M: 1294 speed = SPEED_100; 1295 break; 1296 case YTPHY_SSR_SPEED_1000M: 1297 speed = SPEED_1000; 1298 break; 1299 default: 1300 speed = SPEED_UNKNOWN; 1301 break; 1302 } 1303 1304 phydev->speed = speed; 1305 phydev->duplex = duplex; 1306 1307 if (is_utp) { 1308 err = ytphy_utp_read_lpa(phydev); 1309 if (err < 0) 1310 return err; 1311 1312 phy_resolve_aneg_pause(phydev); 1313 } else { 1314 lpa = __phy_read(phydev, MII_LPA); 1315 if (lpa < 0) 1316 return lpa; 1317 1318 /* only support 1000baseX Full */ 1319 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 1320 phydev->lp_advertising, lpa & LPA_1000XFULL); 1321 1322 if (!(lpa & YTPHY_FLPA_PAUSE)) { 1323 phydev->pause = 0; 1324 phydev->asym_pause = 0; 1325 } else if ((lpa & YTPHY_FLPA_ASYM_PAUSE)) { 1326 phydev->pause = 1; 1327 phydev->asym_pause = 1; 1328 } else { 1329 phydev->pause = 1; 1330 phydev->asym_pause = 0; 1331 } 1332 } 1333 1334 return 0; 1335} 1336 1337/** 1338 * yt8521_read_status_paged() - determines the speed and duplex of one page 1339 * @phydev: a pointer to a &struct phy_device 1340 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to 1341 * operate. 1342 * 1343 * returns 1 (utp or fiber link),0 (no link) or negative errno code 1344 */ 1345static int yt8521_read_status_paged(struct phy_device *phydev, int page) 1346{ 1347 int fiber_latch_val; 1348 int fiber_curr_val; 1349 int old_page; 1350 int ret = 0; 1351 int status; 1352 int link; 1353 1354 linkmode_zero(phydev->lp_advertising); 1355 phydev->duplex = DUPLEX_UNKNOWN; 1356 phydev->speed = SPEED_UNKNOWN; 1357 phydev->asym_pause = 0; 1358 phydev->pause = 0; 1359 1360 /* YT8521 has two reg space (utp/fiber) for linkup with utp/fiber 1361 * respectively. but for utp/fiber combo mode, reg space should be 1362 * arbitrated based on media priority. by default, utp takes 1363 * priority. reg space should be properly set before read 1364 * YTPHY_SPECIFIC_STATUS_REG. 1365 */ 1366 1367 page &= YT8521_RSSR_SPACE_MASK; 1368 old_page = phy_select_page(phydev, page); 1369 if (old_page < 0) 1370 goto err_restore_page; 1371 1372 /* Read YTPHY_SPECIFIC_STATUS_REG, which indicates the speed and duplex 1373 * of the PHY is actually using. 1374 */ 1375 ret = __phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG); 1376 if (ret < 0) 1377 goto err_restore_page; 1378 1379 status = ret; 1380 link = !!(status & YTPHY_SSR_LINK); 1381 1382 /* When PHY is in fiber mode, speed transferred from 1000Mbps to 1383 * 100Mbps,there is not link down from YTPHY_SPECIFIC_STATUS_REG, so 1384 * we need check MII_BMSR to identify such case. 1385 */ 1386 if (page == YT8521_RSSR_FIBER_SPACE) { 1387 ret = __phy_read(phydev, MII_BMSR); 1388 if (ret < 0) 1389 goto err_restore_page; 1390 1391 fiber_latch_val = ret; 1392 ret = __phy_read(phydev, MII_BMSR); 1393 if (ret < 0) 1394 goto err_restore_page; 1395 1396 fiber_curr_val = ret; 1397 if (link && fiber_latch_val != fiber_curr_val) { 1398 link = 0; 1399 phydev_info(phydev, 1400 "%s, fiber link down detect, latch = %04x, curr = %04x\n", 1401 __func__, fiber_latch_val, fiber_curr_val); 1402 } 1403 } else { 1404 /* Read autonegotiation status */ 1405 ret = __phy_read(phydev, MII_BMSR); 1406 if (ret < 0) 1407 goto err_restore_page; 1408 1409 phydev->autoneg_complete = ret & BMSR_ANEGCOMPLETE ? 1 : 0; 1410 } 1411 1412 if (link) { 1413 if (page == YT8521_RSSR_UTP_SPACE) 1414 yt8521_adjust_status(phydev, status, true); 1415 else 1416 yt8521_adjust_status(phydev, status, false); 1417 } 1418 return phy_restore_page(phydev, old_page, link); 1419 1420err_restore_page: 1421 return phy_restore_page(phydev, old_page, ret); 1422} 1423 1424/** 1425 * yt8521_read_status() - determines the negotiated speed and duplex 1426 * @phydev: a pointer to a &struct phy_device 1427 * 1428 * returns 0 or negative errno code 1429 */ 1430static int yt8521_read_status(struct phy_device *phydev) 1431{ 1432 struct yt8521_priv *priv = phydev->priv; 1433 int link_fiber = 0; 1434 int link_utp; 1435 int link; 1436 int ret; 1437 1438 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 1439 link = yt8521_read_status_paged(phydev, priv->reg_page); 1440 if (link < 0) 1441 return link; 1442 } else { 1443 /* when page is YT8521_RSSR_TO_BE_ARBITRATED, arbitration is 1444 * needed. by default, utp is higher priority. 1445 */ 1446 1447 link_utp = yt8521_read_status_paged(phydev, 1448 YT8521_RSSR_UTP_SPACE); 1449 if (link_utp < 0) 1450 return link_utp; 1451 1452 if (!link_utp) { 1453 link_fiber = yt8521_read_status_paged(phydev, 1454 YT8521_RSSR_FIBER_SPACE); 1455 if (link_fiber < 0) 1456 return link_fiber; 1457 } 1458 1459 link = link_utp || link_fiber; 1460 } 1461 1462 if (link) { 1463 if (phydev->link == 0) { 1464 /* arbitrate reg space based on linkup media type. */ 1465 if (priv->polling_mode == YT8521_MODE_POLL && 1466 priv->reg_page == YT8521_RSSR_TO_BE_ARBITRATED) { 1467 if (link_fiber) 1468 priv->reg_page = 1469 YT8521_RSSR_FIBER_SPACE; 1470 else 1471 priv->reg_page = YT8521_RSSR_UTP_SPACE; 1472 1473 ret = ytphy_write_ext_with_lock(phydev, 1474 YT8521_REG_SPACE_SELECT_REG, 1475 priv->reg_page); 1476 if (ret < 0) 1477 return ret; 1478 1479 phydev->port = link_fiber ? PORT_FIBRE : PORT_TP; 1480 1481 phydev_info(phydev, "%s, link up, media: %s\n", 1482 __func__, 1483 (phydev->port == PORT_TP) ? 1484 "UTP" : "Fiber"); 1485 } 1486 } 1487 phydev->link = 1; 1488 } else { 1489 if (phydev->link == 1) { 1490 phydev_info(phydev, "%s, link down, media: %s\n", 1491 __func__, (phydev->port == PORT_TP) ? 1492 "UTP" : "Fiber"); 1493 1494 /* When in YT8521_MODE_POLL mode, need prepare for next 1495 * arbitration. 1496 */ 1497 if (priv->polling_mode == YT8521_MODE_POLL) { 1498 priv->reg_page = YT8521_RSSR_TO_BE_ARBITRATED; 1499 phydev->port = PORT_NONE; 1500 } 1501 } 1502 1503 phydev->link = 0; 1504 } 1505 1506 return 0; 1507} 1508 1509/** 1510 * yt8521_modify_bmcr_paged - bits modify a PHY's BMCR register of one page 1511 * @phydev: the phy_device struct 1512 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to operate 1513 * @mask: bit mask of bits to clear 1514 * @set: bit mask of bits to set 1515 * 1516 * NOTE: Convenience function which allows a PHY's BMCR register to be 1517 * modified as new register value = (old register value & ~mask) | set. 1518 * YT8521 has two space (utp/fiber) and three mode (utp/fiber/poll), each space 1519 * has MII_BMCR. poll mode combines utp and faber,so need do both. 1520 * If it is reset, it will wait for completion. 1521 * 1522 * returns 0 or negative errno code 1523 */ 1524static int yt8521_modify_bmcr_paged(struct phy_device *phydev, int page, 1525 u16 mask, u16 set) 1526{ 1527 int max_cnt = 500; /* the max wait time of reset ~ 500 ms */ 1528 int old_page; 1529 int ret = 0; 1530 1531 old_page = phy_select_page(phydev, page & YT8521_RSSR_SPACE_MASK); 1532 if (old_page < 0) 1533 goto err_restore_page; 1534 1535 ret = __phy_modify(phydev, MII_BMCR, mask, set); 1536 if (ret < 0) 1537 goto err_restore_page; 1538 1539 /* If it is reset, need to wait for the reset to complete */ 1540 if (set == BMCR_RESET) { 1541 while (max_cnt--) { 1542 usleep_range(1000, 1100); 1543 ret = __phy_read(phydev, MII_BMCR); 1544 if (ret < 0) 1545 goto err_restore_page; 1546 1547 if (!(ret & BMCR_RESET)) 1548 return phy_restore_page(phydev, old_page, 0); 1549 } 1550 } 1551 1552err_restore_page: 1553 return phy_restore_page(phydev, old_page, ret); 1554} 1555 1556/** 1557 * yt8521_modify_utp_fiber_bmcr - bits modify a PHY's BMCR register 1558 * @phydev: the phy_device struct 1559 * @mask: bit mask of bits to clear 1560 * @set: bit mask of bits to set 1561 * 1562 * NOTE: Convenience function which allows a PHY's BMCR register to be 1563 * modified as new register value = (old register value & ~mask) | set. 1564 * YT8521 has two space (utp/fiber) and three mode (utp/fiber/poll), each space 1565 * has MII_BMCR. poll mode combines utp and faber,so need do both. 1566 * 1567 * returns 0 or negative errno code 1568 */ 1569static int yt8521_modify_utp_fiber_bmcr(struct phy_device *phydev, u16 mask, 1570 u16 set) 1571{ 1572 struct yt8521_priv *priv = phydev->priv; 1573 int ret; 1574 1575 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 1576 ret = yt8521_modify_bmcr_paged(phydev, priv->reg_page, mask, 1577 set); 1578 if (ret < 0) 1579 return ret; 1580 } else { 1581 ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_UTP_SPACE, 1582 mask, set); 1583 if (ret < 0) 1584 return ret; 1585 1586 ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_FIBER_SPACE, 1587 mask, set); 1588 if (ret < 0) 1589 return ret; 1590 } 1591 return 0; 1592} 1593 1594/** 1595 * yt8521_soft_reset() - called to issue a PHY software reset 1596 * @phydev: a pointer to a &struct phy_device 1597 * 1598 * returns 0 or negative errno code 1599 */ 1600static int yt8521_soft_reset(struct phy_device *phydev) 1601{ 1602 return yt8521_modify_utp_fiber_bmcr(phydev, 0, BMCR_RESET); 1603} 1604 1605/** 1606 * yt8521_suspend() - suspend the hardware 1607 * @phydev: a pointer to a &struct phy_device 1608 * 1609 * returns 0 or negative errno code 1610 */ 1611static int yt8521_suspend(struct phy_device *phydev) 1612{ 1613 int wol_config; 1614 1615 /* YTPHY_WOL_CONFIG_REG is common ext reg */ 1616 wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG); 1617 if (wol_config < 0) 1618 return wol_config; 1619 1620 /* if wol enable, do nothing */ 1621 if (wol_config & YTPHY_WCR_ENABLE) 1622 return 0; 1623 1624 return yt8521_modify_utp_fiber_bmcr(phydev, 0, BMCR_PDOWN); 1625} 1626 1627/** 1628 * yt8521_resume() - resume the hardware 1629 * @phydev: a pointer to a &struct phy_device 1630 * 1631 * returns 0 or negative errno code 1632 */ 1633static int yt8521_resume(struct phy_device *phydev) 1634{ 1635 int ret; 1636 int wol_config; 1637 1638 /* disable auto sleep */ 1639 ret = ytphy_modify_ext_with_lock(phydev, 1640 YT8521_EXTREG_SLEEP_CONTROL1_REG, 1641 YT8521_ESC1R_SLEEP_SW, 0); 1642 if (ret < 0) 1643 return ret; 1644 1645 wol_config = ytphy_read_ext_with_lock(phydev, YTPHY_WOL_CONFIG_REG); 1646 if (wol_config < 0) 1647 return wol_config; 1648 1649 /* if wol enable, do nothing */ 1650 if (wol_config & YTPHY_WCR_ENABLE) 1651 return 0; 1652 1653 return yt8521_modify_utp_fiber_bmcr(phydev, BMCR_PDOWN, 0); 1654} 1655 1656/** 1657 * yt8521_config_init() - called to initialize the PHY 1658 * @phydev: a pointer to a &struct phy_device 1659 * 1660 * returns 0 or negative errno code 1661 */ 1662static int yt8521_config_init(struct phy_device *phydev) 1663{ 1664 struct device_node *node = phydev->mdio.dev.of_node; 1665 int old_page; 1666 int ret = 0; 1667 1668 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE); 1669 if (old_page < 0) 1670 goto err_restore_page; 1671 1672 /* set rgmii delay mode */ 1673 if (phydev->interface != PHY_INTERFACE_MODE_SGMII) { 1674 ret = ytphy_rgmii_clk_delay_config(phydev); 1675 if (ret < 0) 1676 goto err_restore_page; 1677 } 1678 1679 if (of_property_read_bool(node, "motorcomm,auto-sleep-disabled")) { 1680 /* disable auto sleep */ 1681 ret = ytphy_modify_ext(phydev, YT8521_EXTREG_SLEEP_CONTROL1_REG, 1682 YT8521_ESC1R_SLEEP_SW, 0); 1683 if (ret < 0) 1684 goto err_restore_page; 1685 } 1686 1687 if (of_property_read_bool(node, "motorcomm,keep-pll-enabled")) { 1688 /* enable RXC clock when no wire plug */ 1689 ret = ytphy_modify_ext(phydev, YT8521_CLOCK_GATING_REG, 1690 YT8521_CGR_RX_CLK_EN, 0); 1691 if (ret < 0) 1692 goto err_restore_page; 1693 } 1694err_restore_page: 1695 return phy_restore_page(phydev, old_page, ret); 1696} 1697 1698static const unsigned long supported_trgs = (BIT(TRIGGER_NETDEV_FULL_DUPLEX) | 1699 BIT(TRIGGER_NETDEV_HALF_DUPLEX) | 1700 BIT(TRIGGER_NETDEV_LINK) | 1701 BIT(TRIGGER_NETDEV_LINK_10) | 1702 BIT(TRIGGER_NETDEV_LINK_100) | 1703 BIT(TRIGGER_NETDEV_LINK_1000) | 1704 BIT(TRIGGER_NETDEV_RX) | 1705 BIT(TRIGGER_NETDEV_TX)); 1706 1707static int yt8521_led_hw_is_supported(struct phy_device *phydev, u8 index, 1708 unsigned long rules) 1709{ 1710 if (index >= YT8521_MAX_LEDS) 1711 return -EINVAL; 1712 1713 /* All combinations of the supported triggers are allowed */ 1714 if (rules & ~supported_trgs) 1715 return -EOPNOTSUPP; 1716 1717 return 0; 1718} 1719 1720static int yt8521_led_hw_control_set(struct phy_device *phydev, u8 index, 1721 unsigned long rules) 1722{ 1723 u16 val = 0; 1724 1725 if (index >= YT8521_MAX_LEDS) 1726 return -EINVAL; 1727 1728 if (test_bit(TRIGGER_NETDEV_LINK, &rules)) { 1729 val |= YT8521_LED_10_ON_EN; 1730 val |= YT8521_LED_100_ON_EN; 1731 val |= YT8521_LED_1000_ON_EN; 1732 } 1733 1734 if (test_bit(TRIGGER_NETDEV_LINK_10, &rules)) 1735 val |= YT8521_LED_10_ON_EN; 1736 1737 if (test_bit(TRIGGER_NETDEV_LINK_100, &rules)) 1738 val |= YT8521_LED_100_ON_EN; 1739 1740 if (test_bit(TRIGGER_NETDEV_LINK_1000, &rules)) 1741 val |= YT8521_LED_1000_ON_EN; 1742 1743 if (test_bit(TRIGGER_NETDEV_FULL_DUPLEX, &rules)) 1744 val |= YT8521_LED_FDX_ON_EN; 1745 1746 if (test_bit(TRIGGER_NETDEV_HALF_DUPLEX, &rules)) 1747 val |= YT8521_LED_HDX_ON_EN; 1748 1749 if (test_bit(TRIGGER_NETDEV_TX, &rules) || 1750 test_bit(TRIGGER_NETDEV_RX, &rules)) 1751 val |= YT8521_LED_ACT_BLK_IND; 1752 1753 if (test_bit(TRIGGER_NETDEV_TX, &rules)) 1754 val |= YT8521_LED_TXACT_BLK_EN; 1755 1756 if (test_bit(TRIGGER_NETDEV_RX, &rules)) 1757 val |= YT8521_LED_RXACT_BLK_EN; 1758 1759 return ytphy_write_ext(phydev, YT8521_LED0_CFG_REG + index, val); 1760} 1761 1762static int yt8521_led_hw_control_get(struct phy_device *phydev, u8 index, 1763 unsigned long *rules) 1764{ 1765 int val; 1766 1767 if (index >= YT8521_MAX_LEDS) 1768 return -EINVAL; 1769 1770 val = ytphy_read_ext(phydev, YT8521_LED0_CFG_REG + index); 1771 if (val < 0) 1772 return val; 1773 1774 if (val & YT8521_LED_TXACT_BLK_EN || val & YT8521_LED_ACT_BLK_IND) 1775 __set_bit(TRIGGER_NETDEV_TX, rules); 1776 1777 if (val & YT8521_LED_RXACT_BLK_EN || val & YT8521_LED_ACT_BLK_IND) 1778 __set_bit(TRIGGER_NETDEV_RX, rules); 1779 1780 if (val & YT8521_LED_FDX_ON_EN) 1781 __set_bit(TRIGGER_NETDEV_FULL_DUPLEX, rules); 1782 1783 if (val & YT8521_LED_HDX_ON_EN) 1784 __set_bit(TRIGGER_NETDEV_HALF_DUPLEX, rules); 1785 1786 if (val & YT8521_LED_1000_ON_EN) 1787 __set_bit(TRIGGER_NETDEV_LINK_1000, rules); 1788 1789 if (val & YT8521_LED_100_ON_EN) 1790 __set_bit(TRIGGER_NETDEV_LINK_100, rules); 1791 1792 if (val & YT8521_LED_10_ON_EN) 1793 __set_bit(TRIGGER_NETDEV_LINK_10, rules); 1794 1795 return 0; 1796} 1797 1798static int yt8531_config_init(struct phy_device *phydev) 1799{ 1800 struct device_node *node = phydev->mdio.dev.of_node; 1801 int ret; 1802 1803 ret = ytphy_rgmii_clk_delay_config_with_lock(phydev); 1804 if (ret < 0) 1805 return ret; 1806 1807 if (of_property_read_bool(node, "motorcomm,auto-sleep-disabled")) { 1808 /* disable auto sleep */ 1809 ret = ytphy_modify_ext_with_lock(phydev, 1810 YT8521_EXTREG_SLEEP_CONTROL1_REG, 1811 YT8521_ESC1R_SLEEP_SW, 0); 1812 if (ret < 0) 1813 return ret; 1814 } 1815 1816 if (of_property_read_bool(node, "motorcomm,keep-pll-enabled")) { 1817 /* enable RXC clock when no wire plug */ 1818 ret = ytphy_modify_ext_with_lock(phydev, 1819 YT8521_CLOCK_GATING_REG, 1820 YT8521_CGR_RX_CLK_EN, 0); 1821 if (ret < 0) 1822 return ret; 1823 } 1824 1825 ret = yt8531_set_ds(phydev); 1826 if (ret < 0) 1827 return ret; 1828 1829 return 0; 1830} 1831 1832/** 1833 * yt8531_link_change_notify() - Adjust the tx clock direction according to 1834 * the current speed and dts config. 1835 * @phydev: a pointer to a &struct phy_device 1836 * 1837 * NOTE: This function is only used to adapt to VF2 with JH7110 SoC. Please 1838 * keep "motorcomm,tx-clk-adj-enabled" not exist in dts when the soc is not 1839 * JH7110. 1840 */ 1841static void yt8531_link_change_notify(struct phy_device *phydev) 1842{ 1843 struct device_node *node = phydev->mdio.dev.of_node; 1844 bool tx_clk_1000_inverted = false; 1845 bool tx_clk_100_inverted = false; 1846 bool tx_clk_10_inverted = false; 1847 bool tx_clk_adj_enabled = false; 1848 u16 val = 0; 1849 int ret; 1850 1851 if (of_property_read_bool(node, "motorcomm,tx-clk-adj-enabled")) 1852 tx_clk_adj_enabled = true; 1853 1854 if (!tx_clk_adj_enabled) 1855 return; 1856 1857 if (of_property_read_bool(node, "motorcomm,tx-clk-10-inverted")) 1858 tx_clk_10_inverted = true; 1859 if (of_property_read_bool(node, "motorcomm,tx-clk-100-inverted")) 1860 tx_clk_100_inverted = true; 1861 if (of_property_read_bool(node, "motorcomm,tx-clk-1000-inverted")) 1862 tx_clk_1000_inverted = true; 1863 1864 if (phydev->speed < 0) 1865 return; 1866 1867 switch (phydev->speed) { 1868 case SPEED_1000: 1869 if (tx_clk_1000_inverted) 1870 val = YT8521_RC1R_TX_CLK_SEL_INVERTED; 1871 break; 1872 case SPEED_100: 1873 if (tx_clk_100_inverted) 1874 val = YT8521_RC1R_TX_CLK_SEL_INVERTED; 1875 break; 1876 case SPEED_10: 1877 if (tx_clk_10_inverted) 1878 val = YT8521_RC1R_TX_CLK_SEL_INVERTED; 1879 break; 1880 default: 1881 return; 1882 } 1883 1884 ret = ytphy_modify_ext_with_lock(phydev, YT8521_RGMII_CONFIG1_REG, 1885 YT8521_RC1R_TX_CLK_SEL_INVERTED, val); 1886 if (ret < 0) 1887 phydev_warn(phydev, "Modify TX_CLK_SEL err:%d\n", ret); 1888} 1889 1890/** 1891 * yt8521_prepare_fiber_features() - A small helper function that setup 1892 * fiber's features. 1893 * @phydev: a pointer to a &struct phy_device 1894 * @dst: a pointer to store fiber's features 1895 */ 1896static void yt8521_prepare_fiber_features(struct phy_device *phydev, 1897 unsigned long *dst) 1898{ 1899 linkmode_set_bit(ETHTOOL_LINK_MODE_100baseFX_Full_BIT, dst); 1900 linkmode_set_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, dst); 1901 linkmode_set_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, dst); 1902 linkmode_set_bit(ETHTOOL_LINK_MODE_FIBRE_BIT, dst); 1903} 1904 1905/** 1906 * yt8521_fiber_setup_forced - configures/forces speed from @phydev 1907 * @phydev: target phy_device struct 1908 * 1909 * NOTE:The caller must have taken the MDIO bus lock. 1910 * 1911 * returns 0 or negative errno code 1912 */ 1913static int yt8521_fiber_setup_forced(struct phy_device *phydev) 1914{ 1915 u16 val; 1916 int ret; 1917 1918 if (phydev->speed == SPEED_1000) 1919 val = YTPHY_MCR_FIBER_1000BX; 1920 else if (phydev->speed == SPEED_100) 1921 val = YTPHY_MCR_FIBER_100FX; 1922 else 1923 return -EINVAL; 1924 1925 ret = __phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); 1926 if (ret < 0) 1927 return ret; 1928 1929 /* disable Fiber auto sensing */ 1930 ret = ytphy_modify_ext(phydev, YT8521_LINK_TIMER_CFG2_REG, 1931 YT8521_LTCR_EN_AUTOSEN, 0); 1932 if (ret < 0) 1933 return ret; 1934 1935 ret = ytphy_modify_ext(phydev, YTPHY_MISC_CONFIG_REG, 1936 YTPHY_MCR_FIBER_SPEED_MASK, val); 1937 if (ret < 0) 1938 return ret; 1939 1940 return ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG, 1941 YT8521_CCR_SW_RST, 0); 1942} 1943 1944/** 1945 * ytphy_check_and_restart_aneg - Enable and restart auto-negotiation 1946 * @phydev: target phy_device struct 1947 * @restart: whether aneg restart is requested 1948 * 1949 * NOTE:The caller must have taken the MDIO bus lock. 1950 * 1951 * returns 0 or negative errno code 1952 */ 1953static int ytphy_check_and_restart_aneg(struct phy_device *phydev, bool restart) 1954{ 1955 int ret; 1956 1957 if (!restart) { 1958 /* Advertisement hasn't changed, but maybe aneg was never on to 1959 * begin with? Or maybe phy was isolated? 1960 */ 1961 ret = __phy_read(phydev, MII_BMCR); 1962 if (ret < 0) 1963 return ret; 1964 1965 if (!(ret & BMCR_ANENABLE) || (ret & BMCR_ISOLATE)) 1966 restart = true; 1967 } 1968 /* Enable and Restart Autonegotiation 1969 * Don't isolate the PHY if we're negotiating 1970 */ 1971 if (restart) 1972 return __phy_modify(phydev, MII_BMCR, BMCR_ISOLATE, 1973 BMCR_ANENABLE | BMCR_ANRESTART); 1974 1975 return 0; 1976} 1977 1978/** 1979 * yt8521_fiber_config_aneg - restart auto-negotiation or write 1980 * YTPHY_MISC_CONFIG_REG. 1981 * @phydev: target phy_device struct 1982 * 1983 * NOTE:The caller must have taken the MDIO bus lock. 1984 * 1985 * returns 0 or negative errno code 1986 */ 1987static int yt8521_fiber_config_aneg(struct phy_device *phydev) 1988{ 1989 int err, changed = 0; 1990 int bmcr; 1991 u16 adv; 1992 1993 if (phydev->autoneg != AUTONEG_ENABLE) 1994 return yt8521_fiber_setup_forced(phydev); 1995 1996 /* enable Fiber auto sensing */ 1997 err = ytphy_modify_ext(phydev, YT8521_LINK_TIMER_CFG2_REG, 1998 0, YT8521_LTCR_EN_AUTOSEN); 1999 if (err < 0) 2000 return err; 2001 2002 err = ytphy_modify_ext(phydev, YT8521_CHIP_CONFIG_REG, 2003 YT8521_CCR_SW_RST, 0); 2004 if (err < 0) 2005 return err; 2006 2007 bmcr = __phy_read(phydev, MII_BMCR); 2008 if (bmcr < 0) 2009 return bmcr; 2010 2011 /* When it is coming from fiber forced mode, add bmcr power down 2012 * and power up to let aneg work fine. 2013 */ 2014 if (!(bmcr & BMCR_ANENABLE)) { 2015 __phy_modify(phydev, MII_BMCR, 0, BMCR_PDOWN); 2016 usleep_range(1000, 1100); 2017 __phy_modify(phydev, MII_BMCR, BMCR_PDOWN, 0); 2018 } 2019 2020 adv = linkmode_adv_to_mii_adv_x(phydev->advertising, 2021 ETHTOOL_LINK_MODE_1000baseX_Full_BIT); 2022 2023 /* Setup fiber advertisement */ 2024 err = __phy_modify_changed(phydev, MII_ADVERTISE, 2025 ADVERTISE_1000XHALF | ADVERTISE_1000XFULL | 2026 ADVERTISE_1000XPAUSE | 2027 ADVERTISE_1000XPSE_ASYM, 2028 adv); 2029 if (err < 0) 2030 return err; 2031 2032 if (err > 0) 2033 changed = 1; 2034 2035 return ytphy_check_and_restart_aneg(phydev, changed); 2036} 2037 2038/** 2039 * ytphy_setup_master_slave 2040 * @phydev: target phy_device struct 2041 * 2042 * NOTE: The caller must have taken the MDIO bus lock. 2043 * 2044 * returns 0 or negative errno code 2045 */ 2046static int ytphy_setup_master_slave(struct phy_device *phydev) 2047{ 2048 u16 ctl = 0; 2049 2050 if (!phydev->is_gigabit_capable) 2051 return 0; 2052 2053 switch (phydev->master_slave_set) { 2054 case MASTER_SLAVE_CFG_MASTER_PREFERRED: 2055 ctl |= CTL1000_PREFER_MASTER; 2056 break; 2057 case MASTER_SLAVE_CFG_SLAVE_PREFERRED: 2058 break; 2059 case MASTER_SLAVE_CFG_MASTER_FORCE: 2060 ctl |= CTL1000_AS_MASTER; 2061 fallthrough; 2062 case MASTER_SLAVE_CFG_SLAVE_FORCE: 2063 ctl |= CTL1000_ENABLE_MASTER; 2064 break; 2065 case MASTER_SLAVE_CFG_UNKNOWN: 2066 case MASTER_SLAVE_CFG_UNSUPPORTED: 2067 return 0; 2068 default: 2069 phydev_warn(phydev, "Unsupported Master/Slave mode\n"); 2070 return -EOPNOTSUPP; 2071 } 2072 2073 return __phy_modify_changed(phydev, MII_CTRL1000, 2074 (CTL1000_ENABLE_MASTER | CTL1000_AS_MASTER | 2075 CTL1000_PREFER_MASTER), ctl); 2076} 2077 2078/** 2079 * ytphy_utp_config_advert - sanitize and advertise auto-negotiation parameters 2080 * @phydev: target phy_device struct 2081 * 2082 * NOTE: Writes MII_ADVERTISE with the appropriate values, 2083 * after sanitizing the values to make sure we only advertise 2084 * what is supported. Returns < 0 on error, 0 if the PHY's advertisement 2085 * hasn't changed, and > 0 if it has changed. 2086 * The caller must have taken the MDIO bus lock. 2087 * 2088 * returns 0 or negative errno code 2089 */ 2090static int ytphy_utp_config_advert(struct phy_device *phydev) 2091{ 2092 int err, bmsr, changed = 0; 2093 u32 adv; 2094 2095 /* Only allow advertising what this PHY supports */ 2096 linkmode_and(phydev->advertising, phydev->advertising, 2097 phydev->supported); 2098 2099 adv = linkmode_adv_to_mii_adv_t(phydev->advertising); 2100 2101 /* Setup standard advertisement */ 2102 err = __phy_modify_changed(phydev, MII_ADVERTISE, 2103 ADVERTISE_ALL | ADVERTISE_100BASE4 | 2104 ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM, 2105 adv); 2106 if (err < 0) 2107 return err; 2108 if (err > 0) 2109 changed = 1; 2110 2111 bmsr = __phy_read(phydev, MII_BMSR); 2112 if (bmsr < 0) 2113 return bmsr; 2114 2115 /* Per 802.3-2008, Section 22.2.4.2.16 Extended status all 2116 * 1000Mbits/sec capable PHYs shall have the BMSR_ESTATEN bit set to a 2117 * logical 1. 2118 */ 2119 if (!(bmsr & BMSR_ESTATEN)) 2120 return changed; 2121 2122 adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); 2123 2124 err = __phy_modify_changed(phydev, MII_CTRL1000, 2125 ADVERTISE_1000FULL | ADVERTISE_1000HALF, 2126 adv); 2127 if (err < 0) 2128 return err; 2129 if (err > 0) 2130 changed = 1; 2131 2132 return changed; 2133} 2134 2135/** 2136 * ytphy_utp_config_aneg - restart auto-negotiation or write BMCR 2137 * @phydev: target phy_device struct 2138 * @changed: whether autoneg is requested 2139 * 2140 * NOTE: If auto-negotiation is enabled, we configure the 2141 * advertising, and then restart auto-negotiation. If it is not 2142 * enabled, then we write the BMCR. 2143 * The caller must have taken the MDIO bus lock. 2144 * 2145 * returns 0 or negative errno code 2146 */ 2147static int ytphy_utp_config_aneg(struct phy_device *phydev, bool changed) 2148{ 2149 int err; 2150 u16 ctl; 2151 2152 err = ytphy_setup_master_slave(phydev); 2153 if (err < 0) 2154 return err; 2155 else if (err) 2156 changed = true; 2157 2158 if (phydev->autoneg != AUTONEG_ENABLE) { 2159 /* configures/forces speed/duplex from @phydev */ 2160 2161 ctl = mii_bmcr_encode_fixed(phydev->speed, phydev->duplex); 2162 2163 return __phy_modify(phydev, MII_BMCR, ~(BMCR_LOOPBACK | 2164 BMCR_ISOLATE | BMCR_PDOWN), ctl); 2165 } 2166 2167 err = ytphy_utp_config_advert(phydev); 2168 if (err < 0) /* error */ 2169 return err; 2170 else if (err) 2171 changed = true; 2172 2173 return ytphy_check_and_restart_aneg(phydev, changed); 2174} 2175 2176/** 2177 * yt8521_config_aneg_paged() - switch reg space then call genphy_config_aneg 2178 * of one page 2179 * @phydev: a pointer to a &struct phy_device 2180 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to 2181 * operate. 2182 * 2183 * returns 0 or negative errno code 2184 */ 2185static int yt8521_config_aneg_paged(struct phy_device *phydev, int page) 2186{ 2187 __ETHTOOL_DECLARE_LINK_MODE_MASK(fiber_supported); 2188 struct yt8521_priv *priv = phydev->priv; 2189 int old_page; 2190 int ret = 0; 2191 2192 page &= YT8521_RSSR_SPACE_MASK; 2193 2194 old_page = phy_select_page(phydev, page); 2195 if (old_page < 0) 2196 goto err_restore_page; 2197 2198 /* If reg_page is YT8521_RSSR_TO_BE_ARBITRATED, 2199 * phydev->advertising should be updated. 2200 */ 2201 if (priv->reg_page == YT8521_RSSR_TO_BE_ARBITRATED) { 2202 linkmode_zero(fiber_supported); 2203 yt8521_prepare_fiber_features(phydev, fiber_supported); 2204 2205 /* prepare fiber_supported, then setup advertising. */ 2206 if (page == YT8521_RSSR_FIBER_SPACE) { 2207 linkmode_set_bit(ETHTOOL_LINK_MODE_Pause_BIT, 2208 fiber_supported); 2209 linkmode_set_bit(ETHTOOL_LINK_MODE_Asym_Pause_BIT, 2210 fiber_supported); 2211 linkmode_and(phydev->advertising, 2212 priv->combo_advertising, fiber_supported); 2213 } else { 2214 /* ETHTOOL_LINK_MODE_Autoneg_BIT is also used in utp */ 2215 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, 2216 fiber_supported); 2217 linkmode_andnot(phydev->advertising, 2218 priv->combo_advertising, 2219 fiber_supported); 2220 } 2221 } 2222 2223 if (page == YT8521_RSSR_FIBER_SPACE) 2224 ret = yt8521_fiber_config_aneg(phydev); 2225 else 2226 ret = ytphy_utp_config_aneg(phydev, false); 2227 2228err_restore_page: 2229 return phy_restore_page(phydev, old_page, ret); 2230} 2231 2232/** 2233 * yt8521_config_aneg() - change reg space then call yt8521_config_aneg_paged 2234 * @phydev: a pointer to a &struct phy_device 2235 * 2236 * returns 0 or negative errno code 2237 */ 2238static int yt8521_config_aneg(struct phy_device *phydev) 2239{ 2240 struct yt8521_priv *priv = phydev->priv; 2241 int ret; 2242 2243 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 2244 ret = yt8521_config_aneg_paged(phydev, priv->reg_page); 2245 if (ret < 0) 2246 return ret; 2247 } else { 2248 /* If reg_page is YT8521_RSSR_TO_BE_ARBITRATED, 2249 * phydev->advertising need to be saved at first run. 2250 * Because it contains the advertising which supported by both 2251 * mac and yt8521(utp and fiber). 2252 */ 2253 if (linkmode_empty(priv->combo_advertising)) { 2254 linkmode_copy(priv->combo_advertising, 2255 phydev->advertising); 2256 } 2257 2258 ret = yt8521_config_aneg_paged(phydev, YT8521_RSSR_UTP_SPACE); 2259 if (ret < 0) 2260 return ret; 2261 2262 ret = yt8521_config_aneg_paged(phydev, YT8521_RSSR_FIBER_SPACE); 2263 if (ret < 0) 2264 return ret; 2265 2266 /* we don't known which will be link, so restore 2267 * phydev->advertising as default value. 2268 */ 2269 linkmode_copy(phydev->advertising, priv->combo_advertising); 2270 } 2271 return 0; 2272} 2273 2274/** 2275 * yt8521_aneg_done_paged() - determines the auto negotiation result of one 2276 * page. 2277 * @phydev: a pointer to a &struct phy_device 2278 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to 2279 * operate. 2280 * 2281 * returns 0(no link)or 1(fiber or utp link) or negative errno code 2282 */ 2283static int yt8521_aneg_done_paged(struct phy_device *phydev, int page) 2284{ 2285 int old_page; 2286 int ret = 0; 2287 int link; 2288 2289 old_page = phy_select_page(phydev, page & YT8521_RSSR_SPACE_MASK); 2290 if (old_page < 0) 2291 goto err_restore_page; 2292 2293 ret = __phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG); 2294 if (ret < 0) 2295 goto err_restore_page; 2296 2297 link = !!(ret & YTPHY_SSR_LINK); 2298 ret = link; 2299 2300err_restore_page: 2301 return phy_restore_page(phydev, old_page, ret); 2302} 2303 2304/** 2305 * yt8521_aneg_done() - determines the auto negotiation result 2306 * @phydev: a pointer to a &struct phy_device 2307 * 2308 * returns 0(no link)or 1(fiber or utp link) or negative errno code 2309 */ 2310static int yt8521_aneg_done(struct phy_device *phydev) 2311{ 2312 struct yt8521_priv *priv = phydev->priv; 2313 int link_fiber = 0; 2314 int link_utp; 2315 int link; 2316 2317 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 2318 link = yt8521_aneg_done_paged(phydev, priv->reg_page); 2319 } else { 2320 link_utp = yt8521_aneg_done_paged(phydev, 2321 YT8521_RSSR_UTP_SPACE); 2322 if (link_utp < 0) 2323 return link_utp; 2324 2325 if (!link_utp) { 2326 link_fiber = yt8521_aneg_done_paged(phydev, 2327 YT8521_RSSR_FIBER_SPACE); 2328 if (link_fiber < 0) 2329 return link_fiber; 2330 } 2331 link = link_fiber || link_utp; 2332 phydev_info(phydev, "%s, link_fiber: %d, link_utp: %d\n", 2333 __func__, link_fiber, link_utp); 2334 } 2335 2336 return link; 2337} 2338 2339/** 2340 * ytphy_utp_read_abilities - read PHY abilities from Clause 22 registers 2341 * @phydev: target phy_device struct 2342 * 2343 * NOTE: Reads the PHY's abilities and populates 2344 * phydev->supported accordingly. 2345 * The caller must have taken the MDIO bus lock. 2346 * 2347 * returns 0 or negative errno code 2348 */ 2349static int ytphy_utp_read_abilities(struct phy_device *phydev) 2350{ 2351 int val; 2352 2353 linkmode_set_bit_array(phy_basic_ports_array, 2354 ARRAY_SIZE(phy_basic_ports_array), 2355 phydev->supported); 2356 2357 val = __phy_read(phydev, MII_BMSR); 2358 if (val < 0) 2359 return val; 2360 2361 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported, 2362 val & BMSR_ANEGCAPABLE); 2363 2364 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Full_BIT, phydev->supported, 2365 val & BMSR_100FULL); 2366 linkmode_mod_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT, phydev->supported, 2367 val & BMSR_100HALF); 2368 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Full_BIT, phydev->supported, 2369 val & BMSR_10FULL); 2370 linkmode_mod_bit(ETHTOOL_LINK_MODE_10baseT_Half_BIT, phydev->supported, 2371 val & BMSR_10HALF); 2372 2373 if (val & BMSR_ESTATEN) { 2374 val = __phy_read(phydev, MII_ESTATUS); 2375 if (val < 0) 2376 return val; 2377 2378 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Full_BIT, 2379 phydev->supported, val & ESTATUS_1000_TFULL); 2380 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseT_Half_BIT, 2381 phydev->supported, val & ESTATUS_1000_THALF); 2382 linkmode_mod_bit(ETHTOOL_LINK_MODE_1000baseX_Full_BIT, 2383 phydev->supported, val & ESTATUS_1000_XFULL); 2384 } 2385 2386 return 0; 2387} 2388 2389/** 2390 * yt8521_get_features_paged() - read supported link modes for one page 2391 * @phydev: a pointer to a &struct phy_device 2392 * @page: The reg page(YT8521_RSSR_FIBER_SPACE/YT8521_RSSR_UTP_SPACE) to 2393 * operate. 2394 * 2395 * returns 0 or negative errno code 2396 */ 2397static int yt8521_get_features_paged(struct phy_device *phydev, int page) 2398{ 2399 int old_page; 2400 int ret = 0; 2401 2402 page &= YT8521_RSSR_SPACE_MASK; 2403 old_page = phy_select_page(phydev, page); 2404 if (old_page < 0) 2405 goto err_restore_page; 2406 2407 if (page == YT8521_RSSR_FIBER_SPACE) { 2408 linkmode_zero(phydev->supported); 2409 yt8521_prepare_fiber_features(phydev, phydev->supported); 2410 } else { 2411 ret = ytphy_utp_read_abilities(phydev); 2412 if (ret < 0) 2413 goto err_restore_page; 2414 } 2415 2416err_restore_page: 2417 return phy_restore_page(phydev, old_page, ret); 2418} 2419 2420/** 2421 * yt8521_get_features - switch reg space then call yt8521_get_features_paged 2422 * @phydev: target phy_device struct 2423 * 2424 * returns 0 or negative errno code 2425 */ 2426static int yt8521_get_features(struct phy_device *phydev) 2427{ 2428 struct yt8521_priv *priv = phydev->priv; 2429 int ret; 2430 2431 if (priv->reg_page != YT8521_RSSR_TO_BE_ARBITRATED) { 2432 ret = yt8521_get_features_paged(phydev, priv->reg_page); 2433 } else { 2434 ret = yt8521_get_features_paged(phydev, 2435 YT8521_RSSR_UTP_SPACE); 2436 if (ret < 0) 2437 return ret; 2438 2439 /* add fiber's features to phydev->supported */ 2440 yt8521_prepare_fiber_features(phydev, phydev->supported); 2441 } 2442 return ret; 2443} 2444 2445/** 2446 * yt8821_get_features - read mmd register to get 2.5G capability 2447 * @phydev: target phy_device struct 2448 * 2449 * Returns: 0 or negative errno code 2450 */ 2451static int yt8821_get_features(struct phy_device *phydev) 2452{ 2453 int ret; 2454 2455 ret = genphy_c45_pma_read_ext_abilities(phydev); 2456 if (ret < 0) 2457 return ret; 2458 2459 return genphy_read_abilities(phydev); 2460} 2461 2462/** 2463 * yt8821_get_rate_matching - read register to get phy chip mode 2464 * @phydev: target phy_device struct 2465 * @iface: PHY data interface type 2466 * 2467 * Returns: rate matching type or negative errno code 2468 */ 2469static int yt8821_get_rate_matching(struct phy_device *phydev, 2470 phy_interface_t iface) 2471{ 2472 int val; 2473 2474 val = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG); 2475 if (val < 0) 2476 return val; 2477 2478 if (FIELD_GET(YT8521_CCR_MODE_SEL_MASK, val) == 2479 YT8821_CHIP_MODE_FORCE_BX2500) 2480 return RATE_MATCH_PAUSE; 2481 2482 return RATE_MATCH_NONE; 2483} 2484 2485/** 2486 * yt8821_aneg_done() - determines the auto negotiation result 2487 * @phydev: a pointer to a &struct phy_device 2488 * 2489 * Returns: 0(no link)or 1(utp link) or negative errno code 2490 */ 2491static int yt8821_aneg_done(struct phy_device *phydev) 2492{ 2493 return yt8521_aneg_done_paged(phydev, YT8521_RSSR_UTP_SPACE); 2494} 2495 2496/** 2497 * yt8821_serdes_init() - serdes init 2498 * @phydev: a pointer to a &struct phy_device 2499 * 2500 * Returns: 0 or negative errno code 2501 */ 2502static int yt8821_serdes_init(struct phy_device *phydev) 2503{ 2504 int old_page; 2505 int ret = 0; 2506 u16 mask; 2507 u16 set; 2508 2509 old_page = phy_select_page(phydev, YT8521_RSSR_FIBER_SPACE); 2510 if (old_page < 0) { 2511 phydev_err(phydev, "Failed to select page: %d\n", 2512 old_page); 2513 goto err_restore_page; 2514 } 2515 2516 ret = __phy_modify(phydev, MII_BMCR, BMCR_ANENABLE, 0); 2517 if (ret < 0) 2518 goto err_restore_page; 2519 2520 mask = YT8821_SDS_EXT_CSR_VCO_LDO_EN | 2521 YT8821_SDS_EXT_CSR_VCO_BIAS_LPF_EN; 2522 set = YT8821_SDS_EXT_CSR_VCO_LDO_EN; 2523 ret = ytphy_modify_ext(phydev, YT8821_SDS_EXT_CSR_CTRL_REG, mask, 2524 set); 2525 2526err_restore_page: 2527 return phy_restore_page(phydev, old_page, ret); 2528} 2529 2530/** 2531 * yt8821_utp_init() - utp init 2532 * @phydev: a pointer to a &struct phy_device 2533 * 2534 * Returns: 0 or negative errno code 2535 */ 2536static int yt8821_utp_init(struct phy_device *phydev) 2537{ 2538 int old_page; 2539 int ret = 0; 2540 u16 mask; 2541 u16 save; 2542 u16 set; 2543 2544 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE); 2545 if (old_page < 0) { 2546 phydev_err(phydev, "Failed to select page: %d\n", 2547 old_page); 2548 goto err_restore_page; 2549 } 2550 2551 mask = YT8821_UTP_EXT_RPDN_BP_FFE_LNG_2500 | 2552 YT8821_UTP_EXT_RPDN_BP_FFE_SHT_2500 | 2553 YT8821_UTP_EXT_RPDN_IPR_SHT_2500; 2554 set = YT8821_UTP_EXT_RPDN_BP_FFE_LNG_2500 | 2555 YT8821_UTP_EXT_RPDN_BP_FFE_SHT_2500; 2556 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_RPDN_CTRL_REG, 2557 mask, set); 2558 if (ret < 0) 2559 goto err_restore_page; 2560 2561 mask = YT8821_UTP_EXT_VGA_LPF1_CAP_OTHER | 2562 YT8821_UTP_EXT_VGA_LPF1_CAP_2500; 2563 ret = ytphy_modify_ext(phydev, 2564 YT8821_UTP_EXT_VGA_LPF1_CAP_CTRL_REG, 2565 mask, 0); 2566 if (ret < 0) 2567 goto err_restore_page; 2568 2569 mask = YT8821_UTP_EXT_VGA_LPF2_CAP_OTHER | 2570 YT8821_UTP_EXT_VGA_LPF2_CAP_2500; 2571 ret = ytphy_modify_ext(phydev, 2572 YT8821_UTP_EXT_VGA_LPF2_CAP_CTRL_REG, 2573 mask, 0); 2574 if (ret < 0) 2575 goto err_restore_page; 2576 2577 mask = YT8821_UTP_EXT_TRACE_LNG_GAIN_THE_2500 | 2578 YT8821_UTP_EXT_TRACE_MED_GAIN_THE_2500; 2579 set = FIELD_PREP(YT8821_UTP_EXT_TRACE_LNG_GAIN_THE_2500, 0x5a) | 2580 FIELD_PREP(YT8821_UTP_EXT_TRACE_MED_GAIN_THE_2500, 0x3c); 2581 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_TRACE_CTRL_REG, 2582 mask, set); 2583 if (ret < 0) 2584 goto err_restore_page; 2585 2586 mask = YT8821_UTP_EXT_IPR_LNG_2500; 2587 set = FIELD_PREP(YT8821_UTP_EXT_IPR_LNG_2500, 0x6c); 2588 ret = ytphy_modify_ext(phydev, 2589 YT8821_UTP_EXT_ALPHA_IPR_CTRL_REG, 2590 mask, set); 2591 if (ret < 0) 2592 goto err_restore_page; 2593 2594 mask = YT8821_UTP_EXT_TRACE_LNG_GAIN_THR_1000; 2595 set = FIELD_PREP(YT8821_UTP_EXT_TRACE_LNG_GAIN_THR_1000, 0x2a); 2596 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_ECHO_CTRL_REG, 2597 mask, set); 2598 if (ret < 0) 2599 goto err_restore_page; 2600 2601 mask = YT8821_UTP_EXT_TRACE_MED_GAIN_THR_1000; 2602 set = FIELD_PREP(YT8821_UTP_EXT_TRACE_MED_GAIN_THR_1000, 0x22); 2603 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_GAIN_CTRL_REG, 2604 mask, set); 2605 if (ret < 0) 2606 goto err_restore_page; 2607 2608 mask = YT8821_UTP_EXT_TH_20DB_2500; 2609 set = FIELD_PREP(YT8821_UTP_EXT_TH_20DB_2500, 0x8000); 2610 ret = ytphy_modify_ext(phydev, 2611 YT8821_UTP_EXT_TH_20DB_2500_CTRL_REG, 2612 mask, set); 2613 if (ret < 0) 2614 goto err_restore_page; 2615 2616 mask = YT8821_UTP_EXT_MU_COARSE_FR_F_FFE | 2617 YT8821_UTP_EXT_MU_COARSE_FR_F_FBE; 2618 set = FIELD_PREP(YT8821_UTP_EXT_MU_COARSE_FR_F_FFE, 0x7) | 2619 FIELD_PREP(YT8821_UTP_EXT_MU_COARSE_FR_F_FBE, 0x7); 2620 ret = ytphy_modify_ext(phydev, 2621 YT8821_UTP_EXT_MU_COARSE_FR_CTRL_REG, 2622 mask, set); 2623 if (ret < 0) 2624 goto err_restore_page; 2625 2626 mask = YT8821_UTP_EXT_MU_FINE_FR_F_FFE | 2627 YT8821_UTP_EXT_MU_FINE_FR_F_FBE; 2628 set = FIELD_PREP(YT8821_UTP_EXT_MU_FINE_FR_F_FFE, 0x2) | 2629 FIELD_PREP(YT8821_UTP_EXT_MU_FINE_FR_F_FBE, 0x2); 2630 ret = ytphy_modify_ext(phydev, 2631 YT8821_UTP_EXT_MU_FINE_FR_CTRL_REG, 2632 mask, set); 2633 if (ret < 0) 2634 goto err_restore_page; 2635 2636 /* save YT8821_UTP_EXT_PI_CTRL_REG's val for use later */ 2637 ret = ytphy_read_ext(phydev, YT8821_UTP_EXT_PI_CTRL_REG); 2638 if (ret < 0) 2639 goto err_restore_page; 2640 2641 save = ret; 2642 2643 mask = YT8821_UTP_EXT_PI_TX_CLK_SEL_AFE | 2644 YT8821_UTP_EXT_PI_RX_CLK_3_SEL_AFE | 2645 YT8821_UTP_EXT_PI_RX_CLK_2_SEL_AFE | 2646 YT8821_UTP_EXT_PI_RX_CLK_1_SEL_AFE | 2647 YT8821_UTP_EXT_PI_RX_CLK_0_SEL_AFE; 2648 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_PI_CTRL_REG, 2649 mask, 0); 2650 if (ret < 0) 2651 goto err_restore_page; 2652 2653 /* restore YT8821_UTP_EXT_PI_CTRL_REG's val */ 2654 ret = ytphy_write_ext(phydev, YT8821_UTP_EXT_PI_CTRL_REG, save); 2655 if (ret < 0) 2656 goto err_restore_page; 2657 2658 mask = YT8821_UTP_EXT_FECHO_AMP_TH_HUGE; 2659 set = FIELD_PREP(YT8821_UTP_EXT_FECHO_AMP_TH_HUGE, 0x38); 2660 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_VCT_CFG6_CTRL_REG, 2661 mask, set); 2662 if (ret < 0) 2663 goto err_restore_page; 2664 2665 mask = YT8821_UTP_EXT_NFR_TX_ABILITY; 2666 set = YT8821_UTP_EXT_NFR_TX_ABILITY; 2667 ret = ytphy_modify_ext(phydev, 2668 YT8821_UTP_EXT_TXGE_NFR_FR_THP_CTRL_REG, 2669 mask, set); 2670 if (ret < 0) 2671 goto err_restore_page; 2672 2673 mask = YT8821_UTP_EXT_PLL_SPARE_CFG; 2674 set = FIELD_PREP(YT8821_UTP_EXT_PLL_SPARE_CFG, 0xe9); 2675 ret = ytphy_modify_ext(phydev, YT8821_UTP_EXT_PLL_CTRL_REG, 2676 mask, set); 2677 if (ret < 0) 2678 goto err_restore_page; 2679 2680 mask = YT8821_UTP_EXT_DAC_IMID_CH_3_10_ORG | 2681 YT8821_UTP_EXT_DAC_IMID_CH_2_10_ORG; 2682 set = FIELD_PREP(YT8821_UTP_EXT_DAC_IMID_CH_3_10_ORG, 0x64) | 2683 FIELD_PREP(YT8821_UTP_EXT_DAC_IMID_CH_2_10_ORG, 0x64); 2684 ret = ytphy_modify_ext(phydev, 2685 YT8821_UTP_EXT_DAC_IMID_CH_2_3_CTRL_REG, 2686 mask, set); 2687 if (ret < 0) 2688 goto err_restore_page; 2689 2690 mask = YT8821_UTP_EXT_DAC_IMID_CH_1_10_ORG | 2691 YT8821_UTP_EXT_DAC_IMID_CH_0_10_ORG; 2692 set = FIELD_PREP(YT8821_UTP_EXT_DAC_IMID_CH_1_10_ORG, 0x64) | 2693 FIELD_PREP(YT8821_UTP_EXT_DAC_IMID_CH_0_10_ORG, 0x64); 2694 ret = ytphy_modify_ext(phydev, 2695 YT8821_UTP_EXT_DAC_IMID_CH_0_1_CTRL_REG, 2696 mask, set); 2697 if (ret < 0) 2698 goto err_restore_page; 2699 2700 mask = YT8821_UTP_EXT_DAC_IMSB_CH_3_10_ORG | 2701 YT8821_UTP_EXT_DAC_IMSB_CH_2_10_ORG; 2702 set = FIELD_PREP(YT8821_UTP_EXT_DAC_IMSB_CH_3_10_ORG, 0x64) | 2703 FIELD_PREP(YT8821_UTP_EXT_DAC_IMSB_CH_2_10_ORG, 0x64); 2704 ret = ytphy_modify_ext(phydev, 2705 YT8821_UTP_EXT_DAC_IMSB_CH_2_3_CTRL_REG, 2706 mask, set); 2707 if (ret < 0) 2708 goto err_restore_page; 2709 2710 mask = YT8821_UTP_EXT_DAC_IMSB_CH_1_10_ORG | 2711 YT8821_UTP_EXT_DAC_IMSB_CH_0_10_ORG; 2712 set = FIELD_PREP(YT8821_UTP_EXT_DAC_IMSB_CH_1_10_ORG, 0x64) | 2713 FIELD_PREP(YT8821_UTP_EXT_DAC_IMSB_CH_0_10_ORG, 0x64); 2714 ret = ytphy_modify_ext(phydev, 2715 YT8821_UTP_EXT_DAC_IMSB_CH_0_1_CTRL_REG, 2716 mask, set); 2717 2718err_restore_page: 2719 return phy_restore_page(phydev, old_page, ret); 2720} 2721 2722/** 2723 * yt8821_auto_sleep_config() - phy auto sleep config 2724 * @phydev: a pointer to a &struct phy_device 2725 * @enable: true enable auto sleep, false disable auto sleep 2726 * 2727 * Returns: 0 or negative errno code 2728 */ 2729static int yt8821_auto_sleep_config(struct phy_device *phydev, 2730 bool enable) 2731{ 2732 int old_page; 2733 int ret = 0; 2734 2735 old_page = phy_select_page(phydev, YT8521_RSSR_UTP_SPACE); 2736 if (old_page < 0) { 2737 phydev_err(phydev, "Failed to select page: %d\n", 2738 old_page); 2739 goto err_restore_page; 2740 } 2741 2742 ret = ytphy_modify_ext(phydev, 2743 YT8521_EXTREG_SLEEP_CONTROL1_REG, 2744 YT8521_ESC1R_SLEEP_SW, 2745 enable ? 1 : 0); 2746 2747err_restore_page: 2748 return phy_restore_page(phydev, old_page, ret); 2749} 2750 2751/** 2752 * yt8821_soft_reset() - soft reset utp and serdes 2753 * @phydev: a pointer to a &struct phy_device 2754 * 2755 * Returns: 0 or negative errno code 2756 */ 2757static int yt8821_soft_reset(struct phy_device *phydev) 2758{ 2759 return ytphy_modify_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG, 2760 YT8521_CCR_SW_RST, 0); 2761} 2762 2763/** 2764 * yt8821_config_init() - phy initializatioin 2765 * @phydev: a pointer to a &struct phy_device 2766 * 2767 * Returns: 0 or negative errno code 2768 */ 2769static int yt8821_config_init(struct phy_device *phydev) 2770{ 2771 u8 mode = YT8821_CHIP_MODE_AUTO_BX2500_SGMII; 2772 int ret; 2773 u16 set; 2774 2775 if (phydev->interface == PHY_INTERFACE_MODE_2500BASEX) 2776 mode = YT8821_CHIP_MODE_FORCE_BX2500; 2777 2778 set = FIELD_PREP(YT8521_CCR_MODE_SEL_MASK, mode); 2779 ret = ytphy_modify_ext_with_lock(phydev, 2780 YT8521_CHIP_CONFIG_REG, 2781 YT8521_CCR_MODE_SEL_MASK, 2782 set); 2783 if (ret < 0) 2784 return ret; 2785 2786 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2787 phydev->possible_interfaces); 2788 2789 if (mode == YT8821_CHIP_MODE_AUTO_BX2500_SGMII) { 2790 __set_bit(PHY_INTERFACE_MODE_SGMII, 2791 phydev->possible_interfaces); 2792 2793 phydev->rate_matching = RATE_MATCH_NONE; 2794 } else if (mode == YT8821_CHIP_MODE_FORCE_BX2500) { 2795 phydev->rate_matching = RATE_MATCH_PAUSE; 2796 } 2797 2798 ret = yt8821_serdes_init(phydev); 2799 if (ret < 0) 2800 return ret; 2801 2802 ret = yt8821_utp_init(phydev); 2803 if (ret < 0) 2804 return ret; 2805 2806 /* disable auto sleep */ 2807 ret = yt8821_auto_sleep_config(phydev, false); 2808 if (ret < 0) 2809 return ret; 2810 2811 /* soft reset */ 2812 return yt8821_soft_reset(phydev); 2813} 2814 2815/** 2816 * yt8821_adjust_status() - update speed and duplex to phydev 2817 * @phydev: a pointer to a &struct phy_device 2818 * @val: read from YTPHY_SPECIFIC_STATUS_REG 2819 */ 2820static void yt8821_adjust_status(struct phy_device *phydev, int val) 2821{ 2822 int speed, duplex; 2823 int speed_mode; 2824 2825 duplex = FIELD_GET(YTPHY_SSR_DUPLEX, val); 2826 speed_mode = val & YTPHY_SSR_SPEED_MASK; 2827 switch (speed_mode) { 2828 case YTPHY_SSR_SPEED_10M: 2829 speed = SPEED_10; 2830 break; 2831 case YTPHY_SSR_SPEED_100M: 2832 speed = SPEED_100; 2833 break; 2834 case YTPHY_SSR_SPEED_1000M: 2835 speed = SPEED_1000; 2836 break; 2837 case YTPHY_SSR_SPEED_2500M: 2838 speed = SPEED_2500; 2839 break; 2840 default: 2841 speed = SPEED_UNKNOWN; 2842 break; 2843 } 2844 2845 phydev->speed = speed; 2846 phydev->duplex = duplex; 2847} 2848 2849/** 2850 * yt8821_update_interface() - update interface per current speed 2851 * @phydev: a pointer to a &struct phy_device 2852 */ 2853static void yt8821_update_interface(struct phy_device *phydev) 2854{ 2855 if (!phydev->link) 2856 return; 2857 2858 switch (phydev->speed) { 2859 case SPEED_2500: 2860 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; 2861 break; 2862 case SPEED_1000: 2863 case SPEED_100: 2864 case SPEED_10: 2865 phydev->interface = PHY_INTERFACE_MODE_SGMII; 2866 break; 2867 default: 2868 phydev_warn(phydev, "phy speed err :%d\n", phydev->speed); 2869 break; 2870 } 2871} 2872 2873/** 2874 * yt8821_read_status() - determines the negotiated speed and duplex 2875 * @phydev: a pointer to a &struct phy_device 2876 * 2877 * Returns: 0 or negative errno code 2878 */ 2879static int yt8821_read_status(struct phy_device *phydev) 2880{ 2881 int link; 2882 int ret; 2883 int val; 2884 2885 ret = ytphy_write_ext_with_lock(phydev, 2886 YT8521_REG_SPACE_SELECT_REG, 2887 YT8521_RSSR_UTP_SPACE); 2888 if (ret < 0) 2889 return ret; 2890 2891 ret = genphy_read_status(phydev); 2892 if (ret < 0) 2893 return ret; 2894 2895 if (phydev->autoneg_complete) { 2896 ret = genphy_c45_read_lpa(phydev); 2897 if (ret < 0) 2898 return ret; 2899 } 2900 2901 ret = phy_read(phydev, YTPHY_SPECIFIC_STATUS_REG); 2902 if (ret < 0) 2903 return ret; 2904 2905 val = ret; 2906 2907 link = val & YTPHY_SSR_LINK; 2908 if (link) 2909 yt8821_adjust_status(phydev, val); 2910 2911 if (link) { 2912 if (phydev->link == 0) 2913 phydev_dbg(phydev, 2914 "%s, phy addr: %d, link up\n", 2915 __func__, phydev->mdio.addr); 2916 phydev->link = 1; 2917 } else { 2918 if (phydev->link == 1) 2919 phydev_dbg(phydev, 2920 "%s, phy addr: %d, link down\n", 2921 __func__, phydev->mdio.addr); 2922 phydev->link = 0; 2923 } 2924 2925 val = ytphy_read_ext_with_lock(phydev, YT8521_CHIP_CONFIG_REG); 2926 if (val < 0) 2927 return val; 2928 2929 if (FIELD_GET(YT8521_CCR_MODE_SEL_MASK, val) == 2930 YT8821_CHIP_MODE_AUTO_BX2500_SGMII) 2931 yt8821_update_interface(phydev); 2932 2933 return 0; 2934} 2935 2936/** 2937 * yt8821_modify_utp_fiber_bmcr - bits modify a PHY's BMCR register 2938 * @phydev: the phy_device struct 2939 * @mask: bit mask of bits to clear 2940 * @set: bit mask of bits to set 2941 * 2942 * NOTE: Convenience function which allows a PHY's BMCR register to be 2943 * modified as new register value = (old register value & ~mask) | set. 2944 * 2945 * Returns: 0 or negative errno code 2946 */ 2947static int yt8821_modify_utp_fiber_bmcr(struct phy_device *phydev, 2948 u16 mask, u16 set) 2949{ 2950 int ret; 2951 2952 ret = yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_UTP_SPACE, 2953 mask, set); 2954 if (ret < 0) 2955 return ret; 2956 2957 return yt8521_modify_bmcr_paged(phydev, YT8521_RSSR_FIBER_SPACE, 2958 mask, set); 2959} 2960 2961/** 2962 * yt8821_suspend() - suspend the hardware 2963 * @phydev: a pointer to a &struct phy_device 2964 * 2965 * Returns: 0 or negative errno code 2966 */ 2967static int yt8821_suspend(struct phy_device *phydev) 2968{ 2969 int wol_config; 2970 2971 wol_config = ytphy_read_ext_with_lock(phydev, 2972 YTPHY_WOL_CONFIG_REG); 2973 if (wol_config < 0) 2974 return wol_config; 2975 2976 /* if wol enable, do nothing */ 2977 if (wol_config & YTPHY_WCR_ENABLE) 2978 return 0; 2979 2980 return yt8821_modify_utp_fiber_bmcr(phydev, 0, BMCR_PDOWN); 2981} 2982 2983/** 2984 * yt8821_resume() - resume the hardware 2985 * @phydev: a pointer to a &struct phy_device 2986 * 2987 * Returns: 0 or negative errno code 2988 */ 2989static int yt8821_resume(struct phy_device *phydev) 2990{ 2991 int wol_config; 2992 int ret; 2993 2994 /* disable auto sleep */ 2995 ret = yt8821_auto_sleep_config(phydev, false); 2996 if (ret < 0) 2997 return ret; 2998 2999 wol_config = ytphy_read_ext_with_lock(phydev, 3000 YTPHY_WOL_CONFIG_REG); 3001 if (wol_config < 0) 3002 return wol_config; 3003 3004 /* if wol enable, do nothing */ 3005 if (wol_config & YTPHY_WCR_ENABLE) 3006 return 0; 3007 3008 return yt8821_modify_utp_fiber_bmcr(phydev, BMCR_PDOWN, 0); 3009} 3010 3011static struct phy_driver motorcomm_phy_drvs[] = { 3012 { 3013 PHY_ID_MATCH_EXACT(PHY_ID_YT8511), 3014 .name = "YT8511 Gigabit Ethernet", 3015 .config_init = yt8511_config_init, 3016 .suspend = genphy_suspend, 3017 .resume = genphy_resume, 3018 .read_page = yt8511_read_page, 3019 .write_page = yt8511_write_page, 3020 }, 3021 { 3022 PHY_ID_MATCH_EXACT(PHY_ID_YT8521), 3023 .name = "YT8521 Gigabit Ethernet", 3024 .get_features = yt8521_get_features, 3025 .probe = yt8521_probe, 3026 .read_page = yt8521_read_page, 3027 .write_page = yt8521_write_page, 3028 .get_wol = ytphy_get_wol, 3029 .set_wol = ytphy_set_wol, 3030 .config_aneg = yt8521_config_aneg, 3031 .aneg_done = yt8521_aneg_done, 3032 .config_init = yt8521_config_init, 3033 .read_status = yt8521_read_status, 3034 .soft_reset = yt8521_soft_reset, 3035 .suspend = yt8521_suspend, 3036 .resume = yt8521_resume, 3037 .led_hw_is_supported = yt8521_led_hw_is_supported, 3038 .led_hw_control_set = yt8521_led_hw_control_set, 3039 .led_hw_control_get = yt8521_led_hw_control_get, 3040 }, 3041 { 3042 PHY_ID_MATCH_EXACT(PHY_ID_YT8531), 3043 .name = "YT8531 Gigabit Ethernet", 3044 .probe = yt8531_probe, 3045 .config_init = yt8531_config_init, 3046 .suspend = genphy_suspend, 3047 .resume = genphy_resume, 3048 .get_wol = ytphy_get_wol, 3049 .set_wol = yt8531_set_wol, 3050 .link_change_notify = yt8531_link_change_notify, 3051 .led_hw_is_supported = yt8521_led_hw_is_supported, 3052 .led_hw_control_set = yt8521_led_hw_control_set, 3053 .led_hw_control_get = yt8521_led_hw_control_get, 3054 }, 3055 { 3056 PHY_ID_MATCH_EXACT(PHY_ID_YT8531S), 3057 .name = "YT8531S Gigabit Ethernet", 3058 .get_features = yt8521_get_features, 3059 .probe = yt8521_probe, 3060 .read_page = yt8521_read_page, 3061 .write_page = yt8521_write_page, 3062 .get_wol = ytphy_get_wol, 3063 .set_wol = ytphy_set_wol, 3064 .config_aneg = yt8521_config_aneg, 3065 .aneg_done = yt8521_aneg_done, 3066 .config_init = yt8521_config_init, 3067 .read_status = yt8521_read_status, 3068 .soft_reset = yt8521_soft_reset, 3069 .suspend = yt8521_suspend, 3070 .resume = yt8521_resume, 3071 }, 3072 { 3073 PHY_ID_MATCH_EXACT(PHY_ID_YT8821), 3074 .name = "YT8821 2.5Gbps PHY", 3075 .get_features = yt8821_get_features, 3076 .read_page = yt8521_read_page, 3077 .write_page = yt8521_write_page, 3078 .get_wol = ytphy_get_wol, 3079 .set_wol = ytphy_set_wol, 3080 .config_aneg = genphy_config_aneg, 3081 .aneg_done = yt8821_aneg_done, 3082 .config_init = yt8821_config_init, 3083 .get_rate_matching = yt8821_get_rate_matching, 3084 .read_status = yt8821_read_status, 3085 .soft_reset = yt8821_soft_reset, 3086 .suspend = yt8821_suspend, 3087 .resume = yt8821_resume, 3088 }, 3089}; 3090 3091module_phy_driver(motorcomm_phy_drvs); 3092 3093MODULE_DESCRIPTION("Motorcomm 8511/8521/8531/8531S/8821 PHY driver"); 3094MODULE_AUTHOR("Peter Geis"); 3095MODULE_AUTHOR("Frank"); 3096MODULE_LICENSE("GPL"); 3097 3098static const struct mdio_device_id __maybe_unused motorcomm_tbl[] = { 3099 { PHY_ID_MATCH_EXACT(PHY_ID_YT8511) }, 3100 { PHY_ID_MATCH_EXACT(PHY_ID_YT8521) }, 3101 { PHY_ID_MATCH_EXACT(PHY_ID_YT8531) }, 3102 { PHY_ID_MATCH_EXACT(PHY_ID_YT8531S) }, 3103 { PHY_ID_MATCH_EXACT(PHY_ID_YT8821) }, 3104 { /* sentinel */ } 3105}; 3106 3107MODULE_DEVICE_TABLE(mdio, motorcomm_tbl);
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