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mtk.h
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linux-6.19.14/drivers/net/phy/mediatek/mtk.h
1/* SPDX-License-Identifier: GPL-2.0 2 * 3 * Common definition for Mediatek Ethernet PHYs 4 * Author: SkyLake Huang <SkyLake.Huang@mediatek.com> 5 * Copyright (c) 2024 MediaTek Inc. 6 */ 7 8#ifndef _MTK_EPHY_H_ 9#define _MTK_EPHY_H_ 10 11#define MTK_PHY_AUX_CTRL_AND_STATUS 0x14 12#define MTK_PHY_ENABLE_DOWNSHIFT BIT(4) 13 14#define MTK_EXT_PAGE_ACCESS 0x1f 15#define MTK_PHY_PAGE_EXTENDED_1 0x0001 16#define MTK_PHY_PAGE_STANDARD 0x0000 17#define MTK_PHY_PAGE_EXTENDED_52B5 0x52b5 18 19/* Registers on MDIO_MMD_VEND2 */ 20#define MTK_PHY_LED0_ON_CTRL 0x24 21#define MTK_PHY_LED1_ON_CTRL 0x26 22#define MTK_GPHY_LED_ON_MASK GENMASK(6, 0) 23#define MTK_2P5GPHY_LED_ON_MASK GENMASK(7, 0) 24#define MTK_PHY_LED_ON_LINK1000 BIT(0) 25#define MTK_PHY_LED_ON_LINK100 BIT(1) 26#define MTK_PHY_LED_ON_LINK10 BIT(2) 27#define MTK_PHY_LED_ON_LINKDOWN BIT(3) 28#define MTK_PHY_LED_ON_FDX BIT(4) /* Full duplex */ 29#define MTK_PHY_LED_ON_HDX BIT(5) /* Half duplex */ 30#define MTK_PHY_LED_ON_FORCE_ON BIT(6) 31#define MTK_PHY_LED_ON_LINK2500 BIT(7) 32#define MTK_PHY_LED_ON_POLARITY BIT(14) 33#define MTK_PHY_LED_ON_ENABLE BIT(15) 34 35#define MTK_PHY_LED0_BLINK_CTRL 0x25 36#define MTK_PHY_LED1_BLINK_CTRL 0x27 37#define MTK_PHY_LED_BLINK_1000TX BIT(0) 38#define MTK_PHY_LED_BLINK_1000RX BIT(1) 39#define MTK_PHY_LED_BLINK_100TX BIT(2) 40#define MTK_PHY_LED_BLINK_100RX BIT(3) 41#define MTK_PHY_LED_BLINK_10TX BIT(4) 42#define MTK_PHY_LED_BLINK_10RX BIT(5) 43#define MTK_PHY_LED_BLINK_COLLISION BIT(6) 44#define MTK_PHY_LED_BLINK_RX_CRC_ERR BIT(7) 45#define MTK_PHY_LED_BLINK_RX_IDLE_ERR BIT(8) 46#define MTK_PHY_LED_BLINK_FORCE_BLINK BIT(9) 47#define MTK_PHY_LED_BLINK_2500TX BIT(10) 48#define MTK_PHY_LED_BLINK_2500RX BIT(11) 49 50#define MTK_GPHY_LED_ON_SET (MTK_PHY_LED_ON_LINK1000 | \ 51 MTK_PHY_LED_ON_LINK100 | \ 52 MTK_PHY_LED_ON_LINK10) 53#define MTK_GPHY_LED_RX_BLINK_SET (MTK_PHY_LED_BLINK_1000RX | \ 54 MTK_PHY_LED_BLINK_100RX | \ 55 MTK_PHY_LED_BLINK_10RX) 56#define MTK_GPHY_LED_TX_BLINK_SET (MTK_PHY_LED_BLINK_1000RX | \ 57 MTK_PHY_LED_BLINK_100RX | \ 58 MTK_PHY_LED_BLINK_10RX) 59 60#define MTK_2P5GPHY_LED_ON_SET (MTK_PHY_LED_ON_LINK2500 | \ 61 MTK_GPHY_LED_ON_SET) 62#define MTK_2P5GPHY_LED_RX_BLINK_SET (MTK_PHY_LED_BLINK_2500RX | \ 63 MTK_GPHY_LED_RX_BLINK_SET) 64#define MTK_2P5GPHY_LED_TX_BLINK_SET (MTK_PHY_LED_BLINK_2500RX | \ 65 MTK_GPHY_LED_TX_BLINK_SET) 66 67#define MTK_PHY_LED_STATE_FORCE_ON 0 68#define MTK_PHY_LED_STATE_FORCE_BLINK 1 69#define MTK_PHY_LED_STATE_NETDEV 2 70 71struct mtk_socphy_priv { 72 unsigned long led_state; 73}; 74 75void __mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr, 76 u8 data_addr, u32 mask, u32 set); 77void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr, 78 u8 data_addr, u32 mask, u32 set); 79void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr, 80 u8 data_addr, u32 set); 81void __mtk_tr_clr_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr, 82 u8 data_addr, u32 clr); 83 84int mtk_phy_read_page(struct phy_device *phydev); 85int mtk_phy_write_page(struct phy_device *phydev, int page); 86 87int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, 88 unsigned long rules, 89 unsigned long supported_triggers); 90int mtk_phy_led_hw_ctrl_set(struct phy_device *phydev, u8 index, 91 unsigned long rules, u16 on_set, 92 u16 rx_blink_set, u16 tx_blink_set); 93int mtk_phy_led_hw_ctrl_get(struct phy_device *phydev, u8 index, 94 unsigned long *rules, u16 on_set, 95 u16 rx_blink_set, u16 tx_blink_set); 96int mtk_phy_led_num_dly_cfg(u8 index, unsigned long *delay_on, 97 unsigned long *delay_off, bool *blinking); 98int mtk_phy_hw_led_on_set(struct phy_device *phydev, u8 index, 99 u16 led_on_mask, bool on); 100int mtk_phy_hw_led_blink_set(struct phy_device *phydev, u8 index, 101 bool blinking); 102void mtk_phy_leds_state_init(struct phy_device *phydev); 103 104#endif /* _MTK_EPHY_H_ */
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