mtk-phy-lib.c

  1// SPDX-License-Identifier: GPL-2.0
  2#include <linux/phy.h>
  3#include <linux/module.h>
  4
  5#include <linux/netdevice.h>
  6
  7#include "mtk.h"
  8
  9/* Difference between functions with mtk_tr* and __mtk_tr* prefixes is
 10 * mtk_tr* functions: wrapped by page switching operations
 11 * __mtk_tr* functions: no page switching operations
 12 */
 13
 14static void __mtk_tr_access(struct phy_device *phydev, bool read, u8 ch_addr,
 15			    u8 node_addr, u8 data_addr)
 16{
 17	u16 tr_cmd = BIT(15); /* bit 14 & 0 are reserved */
 18
 19	if (read)
 20		tr_cmd |= BIT(13);
 21
 22	tr_cmd |= (((ch_addr & 0x3) << 11) |
 23		   ((node_addr & 0xf) << 7) |
 24		   ((data_addr & 0x3f) << 1));
 25	dev_dbg(&phydev->mdio.dev, "tr_cmd: 0x%x\n", tr_cmd);
 26	__phy_write(phydev, 0x10, tr_cmd);
 27}
 28
 29static void __mtk_tr_read(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
 30			  u8 data_addr, u16 *tr_high, u16 *tr_low)
 31{
 32	__mtk_tr_access(phydev, true, ch_addr, node_addr, data_addr);
 33	*tr_low = __phy_read(phydev, 0x11);
 34	*tr_high = __phy_read(phydev, 0x12);
 35	dev_dbg(&phydev->mdio.dev, "tr_high read: 0x%x, tr_low read: 0x%x\n",
 36		*tr_high, *tr_low);
 37}
 38
 39static void __mtk_tr_write(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
 40			   u8 data_addr, u32 tr_data)
 41{
 42	__phy_write(phydev, 0x11, tr_data & 0xffff);
 43	__phy_write(phydev, 0x12, tr_data >> 16);
 44	dev_dbg(&phydev->mdio.dev, "tr_high write: 0x%x, tr_low write: 0x%x\n",
 45		tr_data >> 16, tr_data & 0xffff);
 46	__mtk_tr_access(phydev, false, ch_addr, node_addr, data_addr);
 47}
 48
 49void __mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
 50		     u8 data_addr, u32 mask, u32 set)
 51{
 52	u32 tr_data;
 53	u16 tr_high;
 54	u16 tr_low;
 55
 56	__mtk_tr_read(phydev, ch_addr, node_addr, data_addr, &tr_high, &tr_low);
 57	tr_data = (tr_high << 16) | tr_low;
 58	tr_data = (tr_data & ~mask) | set;
 59	__mtk_tr_write(phydev, ch_addr, node_addr, data_addr, tr_data);
 60}
 61EXPORT_SYMBOL_GPL(__mtk_tr_modify);
 62
 63void mtk_tr_modify(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
 64		   u8 data_addr, u32 mask, u32 set)
 65{
 66	phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5);
 67	__mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, mask, set);
 68	phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0);
 69}
 70EXPORT_SYMBOL_GPL(mtk_tr_modify);
 71
 72void __mtk_tr_set_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
 73		       u8 data_addr, u32 set)
 74{
 75	__mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, 0, set);
 76}
 77EXPORT_SYMBOL_GPL(__mtk_tr_set_bits);
 78
 79void __mtk_tr_clr_bits(struct phy_device *phydev, u8 ch_addr, u8 node_addr,
 80		       u8 data_addr, u32 clr)
 81{
 82	__mtk_tr_modify(phydev, ch_addr, node_addr, data_addr, clr, 0);
 83}
 84EXPORT_SYMBOL_GPL(__mtk_tr_clr_bits);
 85
 86int mtk_phy_read_page(struct phy_device *phydev)
 87{
 88	return __phy_read(phydev, MTK_EXT_PAGE_ACCESS);
 89}
 90EXPORT_SYMBOL_GPL(mtk_phy_read_page);
 91
 92int mtk_phy_write_page(struct phy_device *phydev, int page)
 93{
 94	return __phy_write(phydev, MTK_EXT_PAGE_ACCESS, page);
 95}
 96EXPORT_SYMBOL_GPL(mtk_phy_write_page);
 97
 98int mtk_phy_led_hw_is_supported(struct phy_device *phydev, u8 index,
 99				unsigned long rules,
100				unsigned long supported_triggers)
101{
102	if (index > 1)
103		return -EINVAL;
104
105	/* All combinations of the supported triggers are allowed */
106	if (rules & ~supported_triggers)
107		return -EOPNOTSUPP;
108
109	return 0;
110}
111EXPORT_SYMBOL_GPL(mtk_phy_led_hw_is_supported);
112
113int mtk_phy_led_hw_ctrl_get(struct phy_device *phydev, u8 index,
114			    unsigned long *rules, u16 on_set,
115			    u16 rx_blink_set, u16 tx_blink_set)
116{
117	unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
118				 (index ? 16 : 0);
119	unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
120	unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
121	struct mtk_socphy_priv *priv = phydev->priv;
122	int on, blink;
123
124	if (index > 1)
125		return -EINVAL;
126
127	on = phy_read_mmd(phydev, MDIO_MMD_VEND2,
128			  index ? MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL);
129
130	if (on < 0)
131		return -EIO;
132
133	blink = phy_read_mmd(phydev, MDIO_MMD_VEND2,
134			     index ? MTK_PHY_LED1_BLINK_CTRL :
135				     MTK_PHY_LED0_BLINK_CTRL);
136	if (blink < 0)
137		return -EIO;
138
139	if ((on & (on_set | MTK_PHY_LED_ON_FDX |
140		   MTK_PHY_LED_ON_HDX | MTK_PHY_LED_ON_LINKDOWN)) ||
141	    (blink & (rx_blink_set | tx_blink_set)))
142		set_bit(bit_netdev, &priv->led_state);
143	else
144		clear_bit(bit_netdev, &priv->led_state);
145
146	if (on & MTK_PHY_LED_ON_FORCE_ON)
147		set_bit(bit_on, &priv->led_state);
148	else
149		clear_bit(bit_on, &priv->led_state);
150
151	if (blink & MTK_PHY_LED_BLINK_FORCE_BLINK)
152		set_bit(bit_blink, &priv->led_state);
153	else
154		clear_bit(bit_blink, &priv->led_state);
155
156	if (!rules)
157		return 0;
158
159	if (on & on_set)
160		*rules |= BIT(TRIGGER_NETDEV_LINK);
161
162	if (on & MTK_PHY_LED_ON_LINK10)
163		*rules |= BIT(TRIGGER_NETDEV_LINK_10);
164
165	if (on & MTK_PHY_LED_ON_LINK100)
166		*rules |= BIT(TRIGGER_NETDEV_LINK_100);
167
168	if (on & MTK_PHY_LED_ON_LINK1000)
169		*rules |= BIT(TRIGGER_NETDEV_LINK_1000);
170
171	if (on & MTK_PHY_LED_ON_LINK2500)
172		*rules |= BIT(TRIGGER_NETDEV_LINK_2500);
173
174	if (on & MTK_PHY_LED_ON_FDX)
175		*rules |= BIT(TRIGGER_NETDEV_FULL_DUPLEX);
176
177	if (on & MTK_PHY_LED_ON_HDX)
178		*rules |= BIT(TRIGGER_NETDEV_HALF_DUPLEX);
179
180	if (blink & rx_blink_set)
181		*rules |= BIT(TRIGGER_NETDEV_RX);
182
183	if (blink & tx_blink_set)
184		*rules |= BIT(TRIGGER_NETDEV_TX);
185
186	return 0;
187}
188EXPORT_SYMBOL_GPL(mtk_phy_led_hw_ctrl_get);
189
190int mtk_phy_led_hw_ctrl_set(struct phy_device *phydev, u8 index,
191			    unsigned long rules, u16 on_set,
192			    u16 rx_blink_set, u16 tx_blink_set)
193{
194	unsigned int bit_netdev = MTK_PHY_LED_STATE_NETDEV + (index ? 16 : 0);
195	struct mtk_socphy_priv *priv = phydev->priv;
196	u16 on = 0, blink = 0;
197	int ret;
198
199	if (index > 1)
200		return -EINVAL;
201
202	if (rules & BIT(TRIGGER_NETDEV_FULL_DUPLEX))
203		on |= MTK_PHY_LED_ON_FDX;
204
205	if (rules & BIT(TRIGGER_NETDEV_HALF_DUPLEX))
206		on |= MTK_PHY_LED_ON_HDX;
207
208	if (rules & (BIT(TRIGGER_NETDEV_LINK_10) | BIT(TRIGGER_NETDEV_LINK)))
209		on |= MTK_PHY_LED_ON_LINK10;
210
211	if (rules & (BIT(TRIGGER_NETDEV_LINK_100) | BIT(TRIGGER_NETDEV_LINK)))
212		on |= MTK_PHY_LED_ON_LINK100;
213
214	if (rules & (BIT(TRIGGER_NETDEV_LINK_1000) | BIT(TRIGGER_NETDEV_LINK)))
215		on |= MTK_PHY_LED_ON_LINK1000;
216
217	if (rules & (BIT(TRIGGER_NETDEV_LINK_2500) | BIT(TRIGGER_NETDEV_LINK)))
218		on |= MTK_PHY_LED_ON_LINK2500;
219
220	if (rules & BIT(TRIGGER_NETDEV_RX)) {
221		if (on & on_set) {
222			if (on & MTK_PHY_LED_ON_LINK10)
223				blink |= MTK_PHY_LED_BLINK_10RX;
224			if (on & MTK_PHY_LED_ON_LINK100)
225				blink |= MTK_PHY_LED_BLINK_100RX;
226			if (on & MTK_PHY_LED_ON_LINK1000)
227				blink |= MTK_PHY_LED_BLINK_1000RX;
228			if (on & MTK_PHY_LED_ON_LINK2500)
229				blink |= MTK_PHY_LED_BLINK_2500RX;
230		} else {
231			blink |= rx_blink_set;
232		}
233	}
234
235	if (rules & BIT(TRIGGER_NETDEV_TX)) {
236		if (on & on_set) {
237			if (on & MTK_PHY_LED_ON_LINK10)
238				blink |= MTK_PHY_LED_BLINK_10TX;
239			if (on & MTK_PHY_LED_ON_LINK100)
240				blink |= MTK_PHY_LED_BLINK_100TX;
241			if (on & MTK_PHY_LED_ON_LINK1000)
242				blink |= MTK_PHY_LED_BLINK_1000TX;
243			if (on & MTK_PHY_LED_ON_LINK2500)
244				blink |= MTK_PHY_LED_BLINK_2500TX;
245		} else {
246			blink |= tx_blink_set;
247		}
248	}
249
250	if (blink || on)
251		set_bit(bit_netdev, &priv->led_state);
252	else
253		clear_bit(bit_netdev, &priv->led_state);
254
255	ret = phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
256			     MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL,
257			     MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX | on_set,
258			     on);
259
260	if (ret)
261		return ret;
262
263	return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
264			     MTK_PHY_LED1_BLINK_CTRL :
265			     MTK_PHY_LED0_BLINK_CTRL, blink);
266}
267EXPORT_SYMBOL_GPL(mtk_phy_led_hw_ctrl_set);
268
269int mtk_phy_led_num_dly_cfg(u8 index, unsigned long *delay_on,
270			    unsigned long *delay_off, bool *blinking)
271{
272	if (index > 1)
273		return -EINVAL;
274
275	if (delay_on && delay_off && (*delay_on > 0) && (*delay_off > 0)) {
276		*blinking = true;
277		*delay_on = 50;
278		*delay_off = 50;
279	}
280
281	return 0;
282}
283EXPORT_SYMBOL_GPL(mtk_phy_led_num_dly_cfg);
284
285int mtk_phy_hw_led_on_set(struct phy_device *phydev, u8 index,
286			  u16 led_on_mask, bool on)
287{
288	unsigned int bit_on = MTK_PHY_LED_STATE_FORCE_ON + (index ? 16 : 0);
289	struct mtk_socphy_priv *priv = phydev->priv;
290	bool changed;
291
292	if (on)
293		changed = !test_and_set_bit(bit_on, &priv->led_state);
294	else
295		changed = !!test_and_clear_bit(bit_on, &priv->led_state);
296
297	changed |= !!test_and_clear_bit(MTK_PHY_LED_STATE_NETDEV +
298					(index ? 16 : 0), &priv->led_state);
299	if (changed)
300		return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ?
301				      MTK_PHY_LED1_ON_CTRL :
302				      MTK_PHY_LED0_ON_CTRL,
303				      led_on_mask,
304				      on ? MTK_PHY_LED_ON_FORCE_ON : 0);
305	else
306		return 0;
307}
308EXPORT_SYMBOL_GPL(mtk_phy_hw_led_on_set);
309
310int mtk_phy_hw_led_blink_set(struct phy_device *phydev, u8 index, bool blinking)
311{
312	unsigned int bit_blink = MTK_PHY_LED_STATE_FORCE_BLINK +
313				 (index ? 16 : 0);
314	struct mtk_socphy_priv *priv = phydev->priv;
315	bool changed;
316
317	if (blinking)
318		changed = !test_and_set_bit(bit_blink, &priv->led_state);
319	else
320		changed = !!test_and_clear_bit(bit_blink, &priv->led_state);
321
322	changed |= !!test_bit(MTK_PHY_LED_STATE_NETDEV +
323			      (index ? 16 : 0), &priv->led_state);
324	if (changed)
325		return phy_write_mmd(phydev, MDIO_MMD_VEND2, index ?
326				     MTK_PHY_LED1_BLINK_CTRL :
327				     MTK_PHY_LED0_BLINK_CTRL,
328				     blinking ?
329				     MTK_PHY_LED_BLINK_FORCE_BLINK : 0);
330	else
331		return 0;
332}
333EXPORT_SYMBOL_GPL(mtk_phy_hw_led_blink_set);
334
335void mtk_phy_leds_state_init(struct phy_device *phydev)
336{
337	int i;
338
339	for (i = 0; i < 2; ++i)
340		phydev->drv->led_hw_control_get(phydev, i, NULL);
341}
342EXPORT_SYMBOL_GPL(mtk_phy_leds_state_init);
343
344MODULE_DESCRIPTION("MediaTek Ethernet PHY driver common");
345MODULE_AUTHOR("Sky Huang <SkyLake.Huang@mediatek.com>");
346MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>");
347MODULE_LICENSE("GPL");