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mtk-ge-soc.c
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linux-6.19.14/drivers/net/phy/mediatek/mtk-ge-soc.c
1// SPDX-License-Identifier: GPL-2.0+ 2#include <linux/bitfield.h> 3#include <linux/bitmap.h> 4#include <linux/mfd/syscon.h> 5#include <linux/module.h> 6#include <linux/nvmem-consumer.h> 7#include <linux/pinctrl/consumer.h> 8#include <linux/phy.h> 9#include <linux/regmap.h> 10#include <linux/of.h> 11 12#include "../phylib.h" 13#include "mtk.h" 14 15#define MTK_PHY_MAX_LEDS 2 16 17#define MTK_GPHY_ID_MT7981 0x03a29461 18#define MTK_GPHY_ID_MT7988 0x03a29481 19#define MTK_GPHY_ID_AN7581 0x03a294c1 20#define MTK_GPHY_ID_AN7583 0xc0ff0420 21 22#define MTK_EXT_PAGE_ACCESS 0x1f 23#define MTK_PHY_PAGE_STANDARD 0x0000 24#define MTK_PHY_PAGE_EXTENDED_3 0x0003 25 26#define MTK_PHY_LPI_REG_14 0x14 27#define MTK_PHY_LPI_WAKE_TIMER_1000_MASK GENMASK(8, 0) 28 29#define MTK_PHY_LPI_REG_1c 0x1c 30#define MTK_PHY_SMI_DET_ON_THRESH_MASK GENMASK(13, 8) 31 32#define MTK_PHY_PAGE_EXTENDED_2A30 0x2a30 33 34/* Registers on Token Ring debug nodes */ 35/* ch_addr = 0x0, node_addr = 0x7, data_addr = 0x15 */ 36/* NormMseLoThresh */ 37#define NORMAL_MSE_LO_THRESH_MASK GENMASK(15, 8) 38 39/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */ 40/* RemAckCntLimitCtrl */ 41#define REMOTE_ACK_COUNT_LIMIT_CTRL_MASK GENMASK(2, 1) 42 43/* ch_addr = 0x1, node_addr = 0xd, data_addr = 0x20 */ 44/* VcoSlicerThreshBitsHigh */ 45#define VCO_SLICER_THRESH_HIGH_MASK GENMASK(23, 0) 46 47/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x0 */ 48/* DfeTailEnableVgaThresh1000 */ 49#define DFE_TAIL_EANBLE_VGA_TRHESH_1000 GENMASK(5, 1) 50 51/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x1 */ 52/* MrvlTrFix100Kp */ 53#define MRVL_TR_FIX_100KP_MASK GENMASK(22, 20) 54/* MrvlTrFix100Kf */ 55#define MRVL_TR_FIX_100KF_MASK GENMASK(19, 17) 56/* MrvlTrFix1000Kp */ 57#define MRVL_TR_FIX_1000KP_MASK GENMASK(16, 14) 58/* MrvlTrFix1000Kf */ 59#define MRVL_TR_FIX_1000KF_MASK GENMASK(13, 11) 60 61/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x12 */ 62/* VgaDecRate */ 63#define VGA_DECIMATION_RATE_MASK GENMASK(8, 5) 64 65/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x17 */ 66/* SlvDSPreadyTime */ 67#define SLAVE_DSP_READY_TIME_MASK GENMASK(22, 15) 68/* MasDSPreadyTime */ 69#define MASTER_DSP_READY_TIME_MASK GENMASK(14, 7) 70 71/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x18 */ 72/* EnabRandUpdTrig */ 73#define ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER BIT(8) 74 75/* ch_addr = 0x1, node_addr = 0xf, data_addr = 0x20 */ 76/* ResetSyncOffset */ 77#define RESET_SYNC_OFFSET_MASK GENMASK(11, 8) 78 79/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x0 */ 80/* FfeUpdGainForceVal */ 81#define FFE_UPDATE_GAIN_FORCE_VAL_MASK GENMASK(9, 7) 82/* FfeUpdGainForce */ 83#define FFE_UPDATE_GAIN_FORCE BIT(6) 84 85/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x3 */ 86/* TrFreeze */ 87#define TR_FREEZE_MASK GENMASK(11, 0) 88 89/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x6 */ 90/* SS: Steady-state, KP: Proportional Gain */ 91/* SSTrKp100 */ 92#define SS_TR_KP100_MASK GENMASK(21, 19) 93/* SSTrKf100 */ 94#define SS_TR_KF100_MASK GENMASK(18, 16) 95/* SSTrKp1000Mas */ 96#define SS_TR_KP1000_MASTER_MASK GENMASK(15, 13) 97/* SSTrKf1000Mas */ 98#define SS_TR_KF1000_MASTER_MASK GENMASK(12, 10) 99/* SSTrKp1000Slv */ 100#define SS_TR_KP1000_SLAVE_MASK GENMASK(9, 7) 101/* SSTrKf1000Slv */ 102#define SS_TR_KF1000_SLAVE_MASK GENMASK(6, 4) 103 104/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x8 */ 105/* clear this bit if wanna select from AFE */ 106/* Regsigdet_sel_1000 */ 107#define EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE BIT(4) 108 109/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xd */ 110/* RegEEE_st2TrKf1000 */ 111#define EEE1000_STAGE2_TR_KF_MASK GENMASK(13, 11) 112 113/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0xf */ 114/* RegEEE_slv_waketr_timer_tar */ 115#define SLAVE_WAKETR_TIMER_MASK GENMASK(20, 11) 116/* RegEEE_slv_remtx_timer_tar */ 117#define SLAVE_REMTX_TIMER_MASK GENMASK(10, 1) 118 119/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x10 */ 120/* RegEEE_slv_wake_int_timer_tar */ 121#define SLAVE_WAKEINT_TIMER_MASK GENMASK(10, 1) 122 123/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x14 */ 124/* RegEEE_trfreeze_timer2 */ 125#define TR_FREEZE_TIMER2_MASK GENMASK(9, 0) 126 127/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x1c */ 128/* RegEEE100Stg1_tar */ 129#define EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK GENMASK(8, 0) 130 131/* ch_addr = 0x2, node_addr = 0xd, data_addr = 0x25 */ 132/* REGEEE_wake_slv_tr_wait_dfesigdet_en */ 133#define WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN BIT(11) 134 135#define ANALOG_INTERNAL_OPERATION_MAX_US 20 136#define TXRESERVE_MIN 0 137#define TXRESERVE_MAX 7 138 139#define MTK_PHY_ANARG_RG 0x10 140#define MTK_PHY_TCLKOFFSET_MASK GENMASK(12, 8) 141 142/* Registers on MDIO_MMD_VEND1 */ 143#define MTK_PHY_TXVLD_DA_RG 0x12 144#define MTK_PHY_DA_TX_I2MPB_A_GBE_MASK GENMASK(15, 10) 145#define MTK_PHY_DA_TX_I2MPB_A_TBT_MASK GENMASK(5, 0) 146 147#define MTK_PHY_TX_I2MPB_TEST_MODE_A2 0x16 148#define MTK_PHY_DA_TX_I2MPB_A_HBT_MASK GENMASK(15, 10) 149#define MTK_PHY_DA_TX_I2MPB_A_TST_MASK GENMASK(5, 0) 150 151#define MTK_PHY_TX_I2MPB_TEST_MODE_B1 0x17 152#define MTK_PHY_DA_TX_I2MPB_B_GBE_MASK GENMASK(13, 8) 153#define MTK_PHY_DA_TX_I2MPB_B_TBT_MASK GENMASK(5, 0) 154 155#define MTK_PHY_TX_I2MPB_TEST_MODE_B2 0x18 156#define MTK_PHY_DA_TX_I2MPB_B_HBT_MASK GENMASK(13, 8) 157#define MTK_PHY_DA_TX_I2MPB_B_TST_MASK GENMASK(5, 0) 158 159#define MTK_PHY_TX_I2MPB_TEST_MODE_C1 0x19 160#define MTK_PHY_DA_TX_I2MPB_C_GBE_MASK GENMASK(13, 8) 161#define MTK_PHY_DA_TX_I2MPB_C_TBT_MASK GENMASK(5, 0) 162 163#define MTK_PHY_TX_I2MPB_TEST_MODE_C2 0x20 164#define MTK_PHY_DA_TX_I2MPB_C_HBT_MASK GENMASK(13, 8) 165#define MTK_PHY_DA_TX_I2MPB_C_TST_MASK GENMASK(5, 0) 166 167#define MTK_PHY_TX_I2MPB_TEST_MODE_D1 0x21 168#define MTK_PHY_DA_TX_I2MPB_D_GBE_MASK GENMASK(13, 8) 169#define MTK_PHY_DA_TX_I2MPB_D_TBT_MASK GENMASK(5, 0) 170 171#define MTK_PHY_TX_I2MPB_TEST_MODE_D2 0x22 172#define MTK_PHY_DA_TX_I2MPB_D_HBT_MASK GENMASK(13, 8) 173#define MTK_PHY_DA_TX_I2MPB_D_TST_MASK GENMASK(5, 0) 174 175#define MTK_PHY_RXADC_CTRL_RG7 0xc6 176#define MTK_PHY_DA_AD_BUF_BIAS_LP_MASK GENMASK(9, 8) 177 178#define MTK_PHY_RXADC_CTRL_RG9 0xc8 179#define MTK_PHY_DA_RX_PSBN_TBT_MASK GENMASK(14, 12) 180#define MTK_PHY_DA_RX_PSBN_HBT_MASK GENMASK(10, 8) 181#define MTK_PHY_DA_RX_PSBN_GBE_MASK GENMASK(6, 4) 182#define MTK_PHY_DA_RX_PSBN_LP_MASK GENMASK(2, 0) 183 184#define MTK_PHY_LDO_OUTPUT_V 0xd7 185 186#define MTK_PHY_RG_ANA_CAL_RG0 0xdb 187#define MTK_PHY_RG_CAL_CKINV BIT(12) 188#define MTK_PHY_RG_ANA_CALEN BIT(8) 189#define MTK_PHY_RG_ZCALEN_A BIT(0) 190 191#define MTK_PHY_RG_ANA_CAL_RG1 0xdc 192#define MTK_PHY_RG_ZCALEN_B BIT(12) 193#define MTK_PHY_RG_ZCALEN_C BIT(8) 194#define MTK_PHY_RG_ZCALEN_D BIT(4) 195#define MTK_PHY_RG_TXVOS_CALEN BIT(0) 196 197#define MTK_PHY_RG_ANA_CAL_RG5 0xe0 198#define MTK_PHY_RG_REXT_TRIM_MASK GENMASK(13, 8) 199 200#define MTK_PHY_RG_TX_FILTER 0xfe 201 202#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120 0x120 203#define MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK GENMASK(12, 8) 204#define MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK GENMASK(4, 0) 205 206#define MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122 0x122 207#define MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK GENMASK(7, 0) 208 209#define MTK_PHY_RG_TESTMUX_ADC_CTRL 0x144 210#define MTK_PHY_RG_TXEN_DIG_MASK GENMASK(5, 5) 211 212#define MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B 0x172 213#define MTK_PHY_CR_TX_AMP_OFFSET_A_MASK GENMASK(13, 8) 214#define MTK_PHY_CR_TX_AMP_OFFSET_B_MASK GENMASK(6, 0) 215 216#define MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D 0x173 217#define MTK_PHY_CR_TX_AMP_OFFSET_C_MASK GENMASK(13, 8) 218#define MTK_PHY_CR_TX_AMP_OFFSET_D_MASK GENMASK(6, 0) 219 220#define MTK_PHY_RG_AD_CAL_COMP 0x17a 221#define MTK_PHY_AD_CAL_COMP_OUT_MASK GENMASK(8, 8) 222 223#define MTK_PHY_RG_AD_CAL_CLK 0x17b 224#define MTK_PHY_DA_CAL_CLK BIT(0) 225 226#define MTK_PHY_RG_AD_CALIN 0x17c 227#define MTK_PHY_DA_CALIN_FLAG BIT(0) 228 229#define MTK_PHY_RG_DASN_DAC_IN0_A 0x17d 230#define MTK_PHY_DASN_DAC_IN0_A_MASK GENMASK(9, 0) 231 232#define MTK_PHY_RG_DASN_DAC_IN0_B 0x17e 233#define MTK_PHY_DASN_DAC_IN0_B_MASK GENMASK(9, 0) 234 235#define MTK_PHY_RG_DASN_DAC_IN0_C 0x17f 236#define MTK_PHY_DASN_DAC_IN0_C_MASK GENMASK(9, 0) 237 238#define MTK_PHY_RG_DASN_DAC_IN0_D 0x180 239#define MTK_PHY_DASN_DAC_IN0_D_MASK GENMASK(9, 0) 240 241#define MTK_PHY_RG_DASN_DAC_IN1_A 0x181 242#define MTK_PHY_DASN_DAC_IN1_A_MASK GENMASK(9, 0) 243 244#define MTK_PHY_RG_DASN_DAC_IN1_B 0x182 245#define MTK_PHY_DASN_DAC_IN1_B_MASK GENMASK(9, 0) 246 247#define MTK_PHY_RG_DASN_DAC_IN1_C 0x183 248#define MTK_PHY_DASN_DAC_IN1_C_MASK GENMASK(9, 0) 249 250#define MTK_PHY_RG_DASN_DAC_IN1_D 0x184 251#define MTK_PHY_DASN_DAC_IN1_D_MASK GENMASK(9, 0) 252 253#define MTK_PHY_RG_DEV1E_REG19b 0x19b 254#define MTK_PHY_BYPASS_DSP_LPI_READY BIT(8) 255 256#define MTK_PHY_RG_LP_IIR2_K1_L 0x22a 257#define MTK_PHY_RG_LP_IIR2_K1_U 0x22b 258#define MTK_PHY_RG_LP_IIR2_K2_L 0x22c 259#define MTK_PHY_RG_LP_IIR2_K2_U 0x22d 260#define MTK_PHY_RG_LP_IIR2_K3_L 0x22e 261#define MTK_PHY_RG_LP_IIR2_K3_U 0x22f 262#define MTK_PHY_RG_LP_IIR2_K4_L 0x230 263#define MTK_PHY_RG_LP_IIR2_K4_U 0x231 264#define MTK_PHY_RG_LP_IIR2_K5_L 0x232 265#define MTK_PHY_RG_LP_IIR2_K5_U 0x233 266 267#define MTK_PHY_RG_DEV1E_REG234 0x234 268#define MTK_PHY_TR_OPEN_LOOP_EN_MASK GENMASK(0, 0) 269#define MTK_PHY_LPF_X_AVERAGE_MASK GENMASK(7, 4) 270#define MTK_PHY_TR_LP_IIR_EEE_EN BIT(12) 271 272#define MTK_PHY_RG_LPF_CNT_VAL 0x235 273 274#define MTK_PHY_RG_DEV1E_REG238 0x238 275#define MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK GENMASK(8, 0) 276#define MTK_PHY_LPI_SLV_SEND_TX_EN BIT(12) 277 278#define MTK_PHY_RG_DEV1E_REG239 0x239 279#define MTK_PHY_LPI_SEND_LOC_TIMER_MASK GENMASK(8, 0) 280#define MTK_PHY_LPI_TXPCS_LOC_RCV BIT(12) 281 282#define MTK_PHY_RG_DEV1E_REG27C 0x27c 283#define MTK_PHY_VGASTATE_FFE_THR_ST1_MASK GENMASK(12, 8) 284#define MTK_PHY_RG_DEV1E_REG27D 0x27d 285#define MTK_PHY_VGASTATE_FFE_THR_ST2_MASK GENMASK(4, 0) 286 287#define MTK_PHY_RG_DEV1E_REG2C7 0x2c7 288#define MTK_PHY_MAX_GAIN_MASK GENMASK(4, 0) 289#define MTK_PHY_MIN_GAIN_MASK GENMASK(12, 8) 290 291#define MTK_PHY_RG_DEV1E_REG2D1 0x2d1 292#define MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK GENMASK(7, 0) 293#define MTK_PHY_LPI_SKIP_SD_SLV_TR BIT(8) 294#define MTK_PHY_LPI_TR_READY BIT(9) 295#define MTK_PHY_LPI_VCO_EEE_STG0_EN BIT(10) 296 297#define MTK_PHY_RG_DEV1E_REG323 0x323 298#define MTK_PHY_EEE_WAKE_MAS_INT_DC BIT(0) 299#define MTK_PHY_EEE_WAKE_SLV_INT_DC BIT(4) 300 301#define MTK_PHY_RG_DEV1E_REG324 0x324 302#define MTK_PHY_SMI_DETCNT_MAX_MASK GENMASK(5, 0) 303#define MTK_PHY_SMI_DET_MAX_EN BIT(8) 304 305#define MTK_PHY_RG_DEV1E_REG326 0x326 306#define MTK_PHY_LPI_MODE_SD_ON BIT(0) 307#define MTK_PHY_RESET_RANDUPD_CNT BIT(1) 308#define MTK_PHY_TREC_UPDATE_ENAB_CLR BIT(2) 309#define MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF BIT(4) 310#define MTK_PHY_TR_READY_SKIP_AFE_WAKEUP BIT(5) 311 312#define MTK_PHY_LDO_PUMP_EN_PAIRAB 0x502 313#define MTK_PHY_LDO_PUMP_EN_PAIRCD 0x503 314 315#define MTK_PHY_DA_TX_R50_PAIR_A 0x53d 316#define MTK_PHY_DA_TX_R50_PAIR_B 0x53e 317#define MTK_PHY_DA_TX_R50_PAIR_C 0x53f 318#define MTK_PHY_DA_TX_R50_PAIR_D 0x540 319 320/* Registers on MDIO_MMD_VEND2 */ 321#define MTK_PHY_LED1_DEFAULT_POLARITIES BIT(1) 322 323#define MTK_PHY_RG_BG_RASEL 0x115 324#define MTK_PHY_RG_BG_RASEL_MASK GENMASK(2, 0) 325 326/* 'boottrap' register reflecting the configuration of the 4 PHY LEDs */ 327#define RG_GPIO_MISC_TPBANK0 0x6f0 328#define RG_GPIO_MISC_TPBANK0_BOOTMODE GENMASK(11, 8) 329 330/* These macro privides efuse parsing for internal phy. */ 331#define EFS_DA_TX_I2MPB_A(x) (((x) >> 0) & GENMASK(5, 0)) 332#define EFS_DA_TX_I2MPB_B(x) (((x) >> 6) & GENMASK(5, 0)) 333#define EFS_DA_TX_I2MPB_C(x) (((x) >> 12) & GENMASK(5, 0)) 334#define EFS_DA_TX_I2MPB_D(x) (((x) >> 18) & GENMASK(5, 0)) 335#define EFS_DA_TX_AMP_OFFSET_A(x) (((x) >> 24) & GENMASK(5, 0)) 336 337#define EFS_DA_TX_AMP_OFFSET_B(x) (((x) >> 0) & GENMASK(5, 0)) 338#define EFS_DA_TX_AMP_OFFSET_C(x) (((x) >> 6) & GENMASK(5, 0)) 339#define EFS_DA_TX_AMP_OFFSET_D(x) (((x) >> 12) & GENMASK(5, 0)) 340#define EFS_DA_TX_R50_A(x) (((x) >> 18) & GENMASK(5, 0)) 341#define EFS_DA_TX_R50_B(x) (((x) >> 24) & GENMASK(5, 0)) 342 343#define EFS_DA_TX_R50_C(x) (((x) >> 0) & GENMASK(5, 0)) 344#define EFS_DA_TX_R50_D(x) (((x) >> 6) & GENMASK(5, 0)) 345 346#define EFS_RG_BG_RASEL(x) (((x) >> 4) & GENMASK(2, 0)) 347#define EFS_RG_REXT_TRIM(x) (((x) >> 7) & GENMASK(5, 0)) 348 349enum { 350 NO_PAIR, 351 PAIR_A, 352 PAIR_B, 353 PAIR_C, 354 PAIR_D, 355}; 356 357enum calibration_mode { 358 EFUSE_K, 359 SW_K 360}; 361 362enum CAL_ITEM { 363 REXT, 364 TX_OFFSET, 365 TX_AMP, 366 TX_R50, 367 TX_VCM 368}; 369 370enum CAL_MODE { 371 EFUSE_M, 372 SW_M 373}; 374 375struct mtk_socphy_shared { 376 u32 boottrap; 377 struct mtk_socphy_priv priv[4]; 378}; 379 380/* One calibration cycle consists of: 381 * 1.Set DA_CALIN_FLAG high to start calibration. Keep it high 382 * until AD_CAL_COMP is ready to output calibration result. 383 * 2.Wait until DA_CAL_CLK is available. 384 * 3.Fetch AD_CAL_COMP_OUT. 385 */ 386static int cal_cycle(struct phy_device *phydev, int devad, 387 u32 regnum, u16 mask, u16 cal_val) 388{ 389 int reg_val; 390 int ret; 391 392 phy_modify_mmd(phydev, devad, regnum, 393 mask, cal_val); 394 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, 395 MTK_PHY_DA_CALIN_FLAG); 396 397 ret = phy_read_mmd_poll_timeout(phydev, MDIO_MMD_VEND1, 398 MTK_PHY_RG_AD_CAL_CLK, reg_val, 399 reg_val & MTK_PHY_DA_CAL_CLK, 500, 400 ANALOG_INTERNAL_OPERATION_MAX_US, 401 false); 402 if (ret) { 403 phydev_err(phydev, "Calibration cycle timeout\n"); 404 return ret; 405 } 406 407 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CALIN, 408 MTK_PHY_DA_CALIN_FLAG); 409 ret = phy_read_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_AD_CAL_COMP); 410 if (ret < 0) 411 return ret; 412 ret = FIELD_GET(MTK_PHY_AD_CAL_COMP_OUT_MASK, ret); 413 phydev_dbg(phydev, "cal_val: 0x%x, ret: %d\n", cal_val, ret); 414 415 return ret; 416} 417 418static int rext_fill_result(struct phy_device *phydev, u16 *buf) 419{ 420 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG5, 421 MTK_PHY_RG_REXT_TRIM_MASK, buf[0] << 8); 422 phy_modify_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_RG_BG_RASEL, 423 MTK_PHY_RG_BG_RASEL_MASK, buf[1]); 424 425 return 0; 426} 427 428static int rext_cal_efuse(struct phy_device *phydev, u32 *buf) 429{ 430 u16 rext_cal_val[2]; 431 432 rext_cal_val[0] = EFS_RG_REXT_TRIM(buf[3]); 433 rext_cal_val[1] = EFS_RG_BG_RASEL(buf[3]); 434 rext_fill_result(phydev, rext_cal_val); 435 436 return 0; 437} 438 439static int tx_offset_fill_result(struct phy_device *phydev, u16 *buf) 440{ 441 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, 442 MTK_PHY_CR_TX_AMP_OFFSET_A_MASK, buf[0] << 8); 443 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_A_B, 444 MTK_PHY_CR_TX_AMP_OFFSET_B_MASK, buf[1]); 445 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, 446 MTK_PHY_CR_TX_AMP_OFFSET_C_MASK, buf[2] << 8); 447 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_CR_TX_AMP_OFFSET_C_D, 448 MTK_PHY_CR_TX_AMP_OFFSET_D_MASK, buf[3]); 449 450 return 0; 451} 452 453static int tx_offset_cal_efuse(struct phy_device *phydev, u32 *buf) 454{ 455 u16 tx_offset_cal_val[4]; 456 457 tx_offset_cal_val[0] = EFS_DA_TX_AMP_OFFSET_A(buf[0]); 458 tx_offset_cal_val[1] = EFS_DA_TX_AMP_OFFSET_B(buf[1]); 459 tx_offset_cal_val[2] = EFS_DA_TX_AMP_OFFSET_C(buf[1]); 460 tx_offset_cal_val[3] = EFS_DA_TX_AMP_OFFSET_D(buf[1]); 461 462 tx_offset_fill_result(phydev, tx_offset_cal_val); 463 464 return 0; 465} 466 467static int tx_amp_fill_result(struct phy_device *phydev, u16 *buf) 468{ 469 const int vals_9481[16] = { 10, 6, 6, 10, 470 10, 6, 6, 10, 471 10, 6, 6, 10, 472 10, 6, 6, 10 }; 473 const int vals_9461[16] = { 7, 1, 4, 7, 474 7, 1, 4, 7, 475 7, 1, 4, 7, 476 7, 1, 4, 7 }; 477 int bias[16] = {}; 478 int i; 479 480 switch (phydev->drv->phy_id) { 481 case MTK_GPHY_ID_MT7981: 482 /* We add some calibration to efuse values 483 * due to board level influence. 484 * GBE: +7, TBT: +1, HBT: +4, TST: +7 485 */ 486 memcpy(bias, (const void *)vals_9461, sizeof(bias)); 487 break; 488 case MTK_GPHY_ID_MT7988: 489 memcpy(bias, (const void *)vals_9481, sizeof(bias)); 490 break; 491 } 492 493 /* Prevent overflow */ 494 for (i = 0; i < 12; i++) { 495 if (buf[i >> 2] + bias[i] > 63) { 496 buf[i >> 2] = 63; 497 bias[i] = 0; 498 } 499 } 500 501 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, 502 MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, 503 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_GBE_MASK, 504 buf[0] + bias[0])); 505 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TXVLD_DA_RG, 506 MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, 507 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TBT_MASK, 508 buf[0] + bias[1])); 509 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, 510 MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, 511 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_HBT_MASK, 512 buf[0] + bias[2])); 513 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_A2, 514 MTK_PHY_DA_TX_I2MPB_A_TST_MASK, 515 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_A_TST_MASK, 516 buf[0] + bias[3])); 517 518 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, 519 MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, 520 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_GBE_MASK, 521 buf[1] + bias[4])); 522 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B1, 523 MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, 524 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TBT_MASK, 525 buf[1] + bias[5])); 526 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, 527 MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, 528 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_HBT_MASK, 529 buf[1] + bias[6])); 530 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_B2, 531 MTK_PHY_DA_TX_I2MPB_B_TST_MASK, 532 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_B_TST_MASK, 533 buf[1] + bias[7])); 534 535 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, 536 MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, 537 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_GBE_MASK, 538 buf[2] + bias[8])); 539 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C1, 540 MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, 541 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TBT_MASK, 542 buf[2] + bias[9])); 543 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, 544 MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, 545 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_HBT_MASK, 546 buf[2] + bias[10])); 547 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_C2, 548 MTK_PHY_DA_TX_I2MPB_C_TST_MASK, 549 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_C_TST_MASK, 550 buf[2] + bias[11])); 551 552 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, 553 MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, 554 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_GBE_MASK, 555 buf[3] + bias[12])); 556 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D1, 557 MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, 558 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TBT_MASK, 559 buf[3] + bias[13])); 560 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, 561 MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, 562 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_HBT_MASK, 563 buf[3] + bias[14])); 564 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_TX_I2MPB_TEST_MODE_D2, 565 MTK_PHY_DA_TX_I2MPB_D_TST_MASK, 566 FIELD_PREP(MTK_PHY_DA_TX_I2MPB_D_TST_MASK, 567 buf[3] + bias[15])); 568 569 return 0; 570} 571 572static int tx_amp_cal_efuse(struct phy_device *phydev, u32 *buf) 573{ 574 u16 tx_amp_cal_val[4]; 575 576 tx_amp_cal_val[0] = EFS_DA_TX_I2MPB_A(buf[0]); 577 tx_amp_cal_val[1] = EFS_DA_TX_I2MPB_B(buf[0]); 578 tx_amp_cal_val[2] = EFS_DA_TX_I2MPB_C(buf[0]); 579 tx_amp_cal_val[3] = EFS_DA_TX_I2MPB_D(buf[0]); 580 tx_amp_fill_result(phydev, tx_amp_cal_val); 581 582 return 0; 583} 584 585static int tx_r50_fill_result(struct phy_device *phydev, u16 tx_r50_cal_val, 586 u8 txg_calen_x) 587{ 588 int bias = 0; 589 u16 reg, val; 590 591 if (phydev->drv->phy_id == MTK_GPHY_ID_MT7988) 592 bias = -1; 593 594 val = clamp_val(bias + tx_r50_cal_val, 0, 63); 595 596 switch (txg_calen_x) { 597 case PAIR_A: 598 reg = MTK_PHY_DA_TX_R50_PAIR_A; 599 break; 600 case PAIR_B: 601 reg = MTK_PHY_DA_TX_R50_PAIR_B; 602 break; 603 case PAIR_C: 604 reg = MTK_PHY_DA_TX_R50_PAIR_C; 605 break; 606 case PAIR_D: 607 reg = MTK_PHY_DA_TX_R50_PAIR_D; 608 break; 609 default: 610 return -EINVAL; 611 } 612 613 phy_write_mmd(phydev, MDIO_MMD_VEND1, reg, val | val << 8); 614 615 return 0; 616} 617 618static int tx_r50_cal_efuse(struct phy_device *phydev, u32 *buf, 619 u8 txg_calen_x) 620{ 621 u16 tx_r50_cal_val; 622 623 switch (txg_calen_x) { 624 case PAIR_A: 625 tx_r50_cal_val = EFS_DA_TX_R50_A(buf[1]); 626 break; 627 case PAIR_B: 628 tx_r50_cal_val = EFS_DA_TX_R50_B(buf[1]); 629 break; 630 case PAIR_C: 631 tx_r50_cal_val = EFS_DA_TX_R50_C(buf[2]); 632 break; 633 case PAIR_D: 634 tx_r50_cal_val = EFS_DA_TX_R50_D(buf[2]); 635 break; 636 default: 637 return -EINVAL; 638 } 639 tx_r50_fill_result(phydev, tx_r50_cal_val, txg_calen_x); 640 641 return 0; 642} 643 644static int tx_vcm_cal_sw(struct phy_device *phydev, u8 rg_txreserve_x) 645{ 646 u8 lower_idx, upper_idx, txreserve_val; 647 u8 lower_ret, upper_ret; 648 int ret; 649 650 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 651 MTK_PHY_RG_ANA_CALEN); 652 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 653 MTK_PHY_RG_CAL_CKINV); 654 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 655 MTK_PHY_RG_TXVOS_CALEN); 656 657 switch (rg_txreserve_x) { 658 case PAIR_A: 659 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 660 MTK_PHY_RG_DASN_DAC_IN0_A, 661 MTK_PHY_DASN_DAC_IN0_A_MASK); 662 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 663 MTK_PHY_RG_DASN_DAC_IN1_A, 664 MTK_PHY_DASN_DAC_IN1_A_MASK); 665 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 666 MTK_PHY_RG_ANA_CAL_RG0, 667 MTK_PHY_RG_ZCALEN_A); 668 break; 669 case PAIR_B: 670 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 671 MTK_PHY_RG_DASN_DAC_IN0_B, 672 MTK_PHY_DASN_DAC_IN0_B_MASK); 673 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 674 MTK_PHY_RG_DASN_DAC_IN1_B, 675 MTK_PHY_DASN_DAC_IN1_B_MASK); 676 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 677 MTK_PHY_RG_ANA_CAL_RG1, 678 MTK_PHY_RG_ZCALEN_B); 679 break; 680 case PAIR_C: 681 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 682 MTK_PHY_RG_DASN_DAC_IN0_C, 683 MTK_PHY_DASN_DAC_IN0_C_MASK); 684 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 685 MTK_PHY_RG_DASN_DAC_IN1_C, 686 MTK_PHY_DASN_DAC_IN1_C_MASK); 687 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 688 MTK_PHY_RG_ANA_CAL_RG1, 689 MTK_PHY_RG_ZCALEN_C); 690 break; 691 case PAIR_D: 692 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 693 MTK_PHY_RG_DASN_DAC_IN0_D, 694 MTK_PHY_DASN_DAC_IN0_D_MASK); 695 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 696 MTK_PHY_RG_DASN_DAC_IN1_D, 697 MTK_PHY_DASN_DAC_IN1_D_MASK); 698 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 699 MTK_PHY_RG_ANA_CAL_RG1, 700 MTK_PHY_RG_ZCALEN_D); 701 break; 702 default: 703 ret = -EINVAL; 704 goto restore; 705 } 706 707 lower_idx = TXRESERVE_MIN; 708 upper_idx = TXRESERVE_MAX; 709 710 phydev_dbg(phydev, "Start TX-VCM SW cal.\n"); 711 while ((upper_idx - lower_idx) > 1) { 712 txreserve_val = DIV_ROUND_CLOSEST(lower_idx + upper_idx, 2); 713 ret = cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, 714 MTK_PHY_DA_RX_PSBN_TBT_MASK | 715 MTK_PHY_DA_RX_PSBN_HBT_MASK | 716 MTK_PHY_DA_RX_PSBN_GBE_MASK | 717 MTK_PHY_DA_RX_PSBN_LP_MASK, 718 txreserve_val << 12 | txreserve_val << 8 | 719 txreserve_val << 4 | txreserve_val); 720 if (ret == 1) { 721 upper_idx = txreserve_val; 722 upper_ret = ret; 723 } else if (ret == 0) { 724 lower_idx = txreserve_val; 725 lower_ret = ret; 726 } else { 727 goto restore; 728 } 729 } 730 731 if (lower_idx == TXRESERVE_MIN) { 732 lower_ret = cal_cycle(phydev, MDIO_MMD_VEND1, 733 MTK_PHY_RXADC_CTRL_RG9, 734 MTK_PHY_DA_RX_PSBN_TBT_MASK | 735 MTK_PHY_DA_RX_PSBN_HBT_MASK | 736 MTK_PHY_DA_RX_PSBN_GBE_MASK | 737 MTK_PHY_DA_RX_PSBN_LP_MASK, 738 lower_idx << 12 | lower_idx << 8 | 739 lower_idx << 4 | lower_idx); 740 ret = lower_ret; 741 } else if (upper_idx == TXRESERVE_MAX) { 742 upper_ret = cal_cycle(phydev, MDIO_MMD_VEND1, 743 MTK_PHY_RXADC_CTRL_RG9, 744 MTK_PHY_DA_RX_PSBN_TBT_MASK | 745 MTK_PHY_DA_RX_PSBN_HBT_MASK | 746 MTK_PHY_DA_RX_PSBN_GBE_MASK | 747 MTK_PHY_DA_RX_PSBN_LP_MASK, 748 upper_idx << 12 | upper_idx << 8 | 749 upper_idx << 4 | upper_idx); 750 ret = upper_ret; 751 } 752 if (ret < 0) 753 goto restore; 754 755 /* We calibrate TX-VCM in different logic. Check upper index and then 756 * lower index. If this calibration is valid, apply lower index's 757 * result. 758 */ 759 ret = upper_ret - lower_ret; 760 if (ret == 1) { 761 ret = 0; 762 /* Make sure we use upper_idx in our calibration system */ 763 cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, 764 MTK_PHY_DA_RX_PSBN_TBT_MASK | 765 MTK_PHY_DA_RX_PSBN_HBT_MASK | 766 MTK_PHY_DA_RX_PSBN_GBE_MASK | 767 MTK_PHY_DA_RX_PSBN_LP_MASK, 768 upper_idx << 12 | upper_idx << 8 | 769 upper_idx << 4 | upper_idx); 770 phydev_dbg(phydev, "TX-VCM SW cal result: 0x%x\n", upper_idx); 771 } else if (lower_idx == TXRESERVE_MIN && upper_ret == 1 && 772 lower_ret == 1) { 773 ret = 0; 774 cal_cycle(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG9, 775 MTK_PHY_DA_RX_PSBN_TBT_MASK | 776 MTK_PHY_DA_RX_PSBN_HBT_MASK | 777 MTK_PHY_DA_RX_PSBN_GBE_MASK | 778 MTK_PHY_DA_RX_PSBN_LP_MASK, 779 lower_idx << 12 | lower_idx << 8 | 780 lower_idx << 4 | lower_idx); 781 phydev_warn(phydev, "TX-VCM SW cal result at low margin 0x%x\n", 782 lower_idx); 783 } else if (upper_idx == TXRESERVE_MAX && upper_ret == 0 && 784 lower_ret == 0) { 785 ret = 0; 786 phydev_warn(phydev, 787 "TX-VCM SW cal result at high margin 0x%x\n", 788 upper_idx); 789 } else { 790 ret = -EINVAL; 791 } 792 793restore: 794 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 795 MTK_PHY_RG_ANA_CALEN); 796 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 797 MTK_PHY_RG_TXVOS_CALEN); 798 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG0, 799 MTK_PHY_RG_ZCALEN_A); 800 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_ANA_CAL_RG1, 801 MTK_PHY_RG_ZCALEN_B | MTK_PHY_RG_ZCALEN_C | 802 MTK_PHY_RG_ZCALEN_D); 803 804 return ret; 805} 806 807static void mt798x_phy_common_finetune(struct phy_device *phydev) 808{ 809 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 810 __mtk_tr_modify(phydev, 0x1, 0xf, 0x17, 811 SLAVE_DSP_READY_TIME_MASK | MASTER_DSP_READY_TIME_MASK, 812 FIELD_PREP(SLAVE_DSP_READY_TIME_MASK, 0x18) | 813 FIELD_PREP(MASTER_DSP_READY_TIME_MASK, 0x18)); 814 815 __mtk_tr_set_bits(phydev, 0x1, 0xf, 0x18, 816 ENABLE_RANDOM_UPDOWN_COUNTER_TRIGGER); 817 818 __mtk_tr_modify(phydev, 0x0, 0x7, 0x15, 819 NORMAL_MSE_LO_THRESH_MASK, 820 FIELD_PREP(NORMAL_MSE_LO_THRESH_MASK, 0x55)); 821 822 __mtk_tr_modify(phydev, 0x2, 0xd, 0x0, 823 FFE_UPDATE_GAIN_FORCE_VAL_MASK, 824 FIELD_PREP(FFE_UPDATE_GAIN_FORCE_VAL_MASK, 0x4) | 825 FFE_UPDATE_GAIN_FORCE); 826 827 __mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x3, TR_FREEZE_MASK); 828 829 __mtk_tr_modify(phydev, 0x2, 0xd, 0x6, 830 SS_TR_KP100_MASK | SS_TR_KF100_MASK | 831 SS_TR_KP1000_MASTER_MASK | SS_TR_KF1000_MASTER_MASK | 832 SS_TR_KP1000_SLAVE_MASK | SS_TR_KF1000_SLAVE_MASK, 833 FIELD_PREP(SS_TR_KP100_MASK, 0x5) | 834 FIELD_PREP(SS_TR_KF100_MASK, 0x6) | 835 FIELD_PREP(SS_TR_KP1000_MASTER_MASK, 0x5) | 836 FIELD_PREP(SS_TR_KF1000_MASTER_MASK, 0x6) | 837 FIELD_PREP(SS_TR_KP1000_SLAVE_MASK, 0x5) | 838 FIELD_PREP(SS_TR_KF1000_SLAVE_MASK, 0x6)); 839 840 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 841} 842 843static void mt7981_phy_finetune(struct phy_device *phydev) 844{ 845 u16 val[8] = { 0x01ce, 0x01c1, 846 0x020f, 0x0202, 847 0x03d0, 0x03c0, 848 0x0013, 0x0005 }; 849 int i, k; 850 851 /* 100M eye finetune: 852 * Keep middle level of TX MLT3 shapper as default. 853 * Only change TX MLT3 overshoot level here. 854 */ 855 for (k = 0, i = 1; i < 12; i++) { 856 if (i % 3 == 0) 857 continue; 858 phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[k++]); 859 } 860 861 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 862 __mtk_tr_modify(phydev, 0x1, 0xf, 0x20, 863 RESET_SYNC_OFFSET_MASK, 864 FIELD_PREP(RESET_SYNC_OFFSET_MASK, 0x6)); 865 866 __mtk_tr_modify(phydev, 0x1, 0xf, 0x12, 867 VGA_DECIMATION_RATE_MASK, 868 FIELD_PREP(VGA_DECIMATION_RATE_MASK, 0x1)); 869 870 /* MrvlTrFix100Kp = 3, MrvlTrFix100Kf = 2, 871 * MrvlTrFix1000Kp = 3, MrvlTrFix1000Kf = 2 872 */ 873 __mtk_tr_modify(phydev, 0x1, 0xf, 0x1, 874 MRVL_TR_FIX_100KP_MASK | MRVL_TR_FIX_100KF_MASK | 875 MRVL_TR_FIX_1000KP_MASK | MRVL_TR_FIX_1000KF_MASK, 876 FIELD_PREP(MRVL_TR_FIX_100KP_MASK, 0x3) | 877 FIELD_PREP(MRVL_TR_FIX_100KF_MASK, 0x2) | 878 FIELD_PREP(MRVL_TR_FIX_1000KP_MASK, 0x3) | 879 FIELD_PREP(MRVL_TR_FIX_1000KF_MASK, 0x2)); 880 881 /* VcoSlicerThreshBitsHigh */ 882 __mtk_tr_modify(phydev, 0x1, 0xd, 0x20, 883 VCO_SLICER_THRESH_HIGH_MASK, 884 FIELD_PREP(VCO_SLICER_THRESH_HIGH_MASK, 0x555555)); 885 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 886 887 /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 9 */ 888 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, 889 MTK_PHY_TR_OPEN_LOOP_EN_MASK | 890 MTK_PHY_LPF_X_AVERAGE_MASK, 891 BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0x9)); 892 893 /* rg_tr_lpf_cnt_val = 512 */ 894 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x200); 895 896 /* IIR2 related */ 897 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_L, 0x82); 898 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K1_U, 0x0); 899 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_L, 0x103); 900 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K2_U, 0x0); 901 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_L, 0x82); 902 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K3_U, 0x0); 903 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_L, 0xd177); 904 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K4_U, 0x3); 905 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_L, 0x2c82); 906 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LP_IIR2_K5_U, 0xe); 907 908 /* FFE peaking */ 909 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27C, 910 MTK_PHY_VGASTATE_FFE_THR_ST1_MASK, 0x1b << 8); 911 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG27D, 912 MTK_PHY_VGASTATE_FFE_THR_ST2_MASK, 0x1e); 913 914 /* Disable LDO pump */ 915 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRAB, 0x0); 916 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_PUMP_EN_PAIRCD, 0x0); 917 /* Adjust LDO output voltage */ 918 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LDO_OUTPUT_V, 0x2222); 919} 920 921static void mt7988_phy_finetune(struct phy_device *phydev) 922{ 923 u16 val[12] = { 0x0187, 0x01cd, 0x01c8, 0x0182, 924 0x020d, 0x0206, 0x0384, 0x03d0, 925 0x03c6, 0x030a, 0x0011, 0x0005 }; 926 int i; 927 928 /* Set default MLT3 shaper first */ 929 for (i = 0; i < 12; i++) 930 phy_write_mmd(phydev, MDIO_MMD_VEND1, i, val[i]); 931 932 /* TCT finetune */ 933 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_TX_FILTER, 0x5); 934 935 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 936 __mtk_tr_modify(phydev, 0x1, 0xf, 0x20, 937 RESET_SYNC_OFFSET_MASK, 938 FIELD_PREP(RESET_SYNC_OFFSET_MASK, 0x5)); 939 940 /* VgaDecRate is 1 at default on mt7988 */ 941 942 __mtk_tr_modify(phydev, 0x1, 0xf, 0x1, 943 MRVL_TR_FIX_100KP_MASK | MRVL_TR_FIX_100KF_MASK | 944 MRVL_TR_FIX_1000KP_MASK | MRVL_TR_FIX_1000KF_MASK, 945 FIELD_PREP(MRVL_TR_FIX_100KP_MASK, 0x6) | 946 FIELD_PREP(MRVL_TR_FIX_100KF_MASK, 0x7) | 947 FIELD_PREP(MRVL_TR_FIX_1000KP_MASK, 0x6) | 948 FIELD_PREP(MRVL_TR_FIX_1000KF_MASK, 0x7)); 949 950 __mtk_tr_modify(phydev, 0x0, 0xf, 0x3c, 951 REMOTE_ACK_COUNT_LIMIT_CTRL_MASK, 952 FIELD_PREP(REMOTE_ACK_COUNT_LIMIT_CTRL_MASK, 0x1)); 953 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 954 955 /* TR_OPEN_LOOP_EN = 1, lpf_x_average = 10 */ 956 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG234, 957 MTK_PHY_TR_OPEN_LOOP_EN_MASK | 958 MTK_PHY_LPF_X_AVERAGE_MASK, 959 BIT(0) | FIELD_PREP(MTK_PHY_LPF_X_AVERAGE_MASK, 0xa)); 960 961 /* rg_tr_lpf_cnt_val = 1023 */ 962 phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_LPF_CNT_VAL, 0x3ff); 963} 964 965static void mt798x_phy_eee(struct phy_device *phydev) 966{ 967 phy_modify_mmd(phydev, MDIO_MMD_VEND1, 968 MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG120, 969 MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK | 970 MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 971 FIELD_PREP(MTK_PHY_LPI_SIG_EN_LO_THRESH1000_MASK, 0x0) | 972 FIELD_PREP(MTK_PHY_LPI_SIG_EN_HI_THRESH1000_MASK, 0x14)); 973 974 phy_modify_mmd(phydev, MDIO_MMD_VEND1, 975 MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, 976 MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 977 FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 978 0xff)); 979 980 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 981 MTK_PHY_RG_TESTMUX_ADC_CTRL, 982 MTK_PHY_RG_TXEN_DIG_MASK); 983 984 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, 985 MTK_PHY_RG_DEV1E_REG19b, MTK_PHY_BYPASS_DSP_LPI_READY); 986 987 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, 988 MTK_PHY_RG_DEV1E_REG234, MTK_PHY_TR_LP_IIR_EEE_EN); 989 990 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG238, 991 MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK | 992 MTK_PHY_LPI_SLV_SEND_TX_EN, 993 FIELD_PREP(MTK_PHY_LPI_SLV_SEND_TX_TIMER_MASK, 0x120)); 994 995 /* Keep MTK_PHY_LPI_SEND_LOC_TIMER as 375 */ 996 phy_clear_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG239, 997 MTK_PHY_LPI_TXPCS_LOC_RCV); 998 999 /* This also fixes some IoT issues, such as CH340 */ 1000 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2C7, 1001 MTK_PHY_MAX_GAIN_MASK | MTK_PHY_MIN_GAIN_MASK, 1002 FIELD_PREP(MTK_PHY_MAX_GAIN_MASK, 0x8) | 1003 FIELD_PREP(MTK_PHY_MIN_GAIN_MASK, 0x13)); 1004 1005 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG2D1, 1006 MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, 1007 FIELD_PREP(MTK_PHY_VCO_SLICER_THRESH_BITS_HIGH_EEE_MASK, 1008 0x33) | 1009 MTK_PHY_LPI_SKIP_SD_SLV_TR | MTK_PHY_LPI_TR_READY | 1010 MTK_PHY_LPI_VCO_EEE_STG0_EN); 1011 1012 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG323, 1013 MTK_PHY_EEE_WAKE_MAS_INT_DC | 1014 MTK_PHY_EEE_WAKE_SLV_INT_DC); 1015 1016 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG324, 1017 MTK_PHY_SMI_DETCNT_MAX_MASK, 1018 FIELD_PREP(MTK_PHY_SMI_DETCNT_MAX_MASK, 0x3f) | 1019 MTK_PHY_SMI_DET_MAX_EN); 1020 1021 phy_set_bits_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RG_DEV1E_REG326, 1022 MTK_PHY_LPI_MODE_SD_ON | MTK_PHY_RESET_RANDUPD_CNT | 1023 MTK_PHY_TREC_UPDATE_ENAB_CLR | 1024 MTK_PHY_LPI_QUIT_WAIT_DFE_SIG_DET_OFF | 1025 MTK_PHY_TR_READY_SKIP_AFE_WAKEUP); 1026 1027 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_52B5); 1028 __mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x8, 1029 EEE1000_SELECT_SIGNAL_DETECTION_FROM_DFE); 1030 1031 __mtk_tr_modify(phydev, 0x2, 0xd, 0xd, 1032 EEE1000_STAGE2_TR_KF_MASK, 1033 FIELD_PREP(EEE1000_STAGE2_TR_KF_MASK, 0x2)); 1034 1035 __mtk_tr_modify(phydev, 0x2, 0xd, 0xf, 1036 SLAVE_WAKETR_TIMER_MASK | SLAVE_REMTX_TIMER_MASK, 1037 FIELD_PREP(SLAVE_WAKETR_TIMER_MASK, 0x6) | 1038 FIELD_PREP(SLAVE_REMTX_TIMER_MASK, 0x14)); 1039 1040 __mtk_tr_modify(phydev, 0x2, 0xd, 0x10, 1041 SLAVE_WAKEINT_TIMER_MASK, 1042 FIELD_PREP(SLAVE_WAKEINT_TIMER_MASK, 0x8)); 1043 1044 __mtk_tr_modify(phydev, 0x2, 0xd, 0x14, 1045 TR_FREEZE_TIMER2_MASK, 1046 FIELD_PREP(TR_FREEZE_TIMER2_MASK, 0x24a)); 1047 1048 __mtk_tr_modify(phydev, 0x2, 0xd, 0x1c, 1049 EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK, 1050 FIELD_PREP(EEE100_LPSYNC_STAGE1_UPDATE_TIMER_MASK, 1051 0x10)); 1052 1053 __mtk_tr_clr_bits(phydev, 0x2, 0xd, 0x25, 1054 WAKE_SLAVE_TR_WAIT_DFE_DETECTION_EN); 1055 1056 __mtk_tr_modify(phydev, 0x1, 0xf, 0x0, 1057 DFE_TAIL_EANBLE_VGA_TRHESH_1000, 1058 FIELD_PREP(DFE_TAIL_EANBLE_VGA_TRHESH_1000, 0x1b)); 1059 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 1060 1061 phy_select_page(phydev, MTK_PHY_PAGE_EXTENDED_3); 1062 __phy_modify(phydev, MTK_PHY_LPI_REG_14, 1063 MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 1064 FIELD_PREP(MTK_PHY_LPI_WAKE_TIMER_1000_MASK, 0x19c)); 1065 1066 __phy_modify(phydev, MTK_PHY_LPI_REG_1c, MTK_PHY_SMI_DET_ON_THRESH_MASK, 1067 FIELD_PREP(MTK_PHY_SMI_DET_ON_THRESH_MASK, 0xc)); 1068 phy_restore_page(phydev, MTK_PHY_PAGE_STANDARD, 0); 1069 1070 phy_modify_mmd(phydev, MDIO_MMD_VEND1, 1071 MTK_PHY_RG_LPI_PCS_DSP_CTRL_REG122, 1072 MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 1073 FIELD_PREP(MTK_PHY_LPI_NORM_MSE_HI_THRESH1000_MASK, 1074 0xff)); 1075} 1076 1077static int cal_sw(struct phy_device *phydev, enum CAL_ITEM cal_item, 1078 u8 start_pair, u8 end_pair) 1079{ 1080 u8 pair_n; 1081 int ret; 1082 1083 for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { 1084 /* TX_OFFSET & TX_AMP have no SW calibration. */ 1085 switch (cal_item) { 1086 case TX_VCM: 1087 ret = tx_vcm_cal_sw(phydev, pair_n); 1088 break; 1089 default: 1090 return -EINVAL; 1091 } 1092 if (ret) 1093 return ret; 1094 } 1095 return 0; 1096} 1097 1098static int cal_efuse(struct phy_device *phydev, enum CAL_ITEM cal_item, 1099 u8 start_pair, u8 end_pair, u32 *buf) 1100{ 1101 u8 pair_n; 1102 int ret; 1103 1104 for (pair_n = start_pair; pair_n <= end_pair; pair_n++) { 1105 /* TX_VCM has no efuse calibration. */ 1106 switch (cal_item) { 1107 case REXT: 1108 ret = rext_cal_efuse(phydev, buf); 1109 break; 1110 case TX_OFFSET: 1111 ret = tx_offset_cal_efuse(phydev, buf); 1112 break; 1113 case TX_AMP: 1114 ret = tx_amp_cal_efuse(phydev, buf); 1115 break; 1116 case TX_R50: 1117 ret = tx_r50_cal_efuse(phydev, buf, pair_n); 1118 break; 1119 default: 1120 return -EINVAL; 1121 } 1122 if (ret) 1123 return ret; 1124 } 1125 1126 return 0; 1127} 1128 1129static int start_cal(struct phy_device *phydev, enum CAL_ITEM cal_item, 1130 enum CAL_MODE cal_mode, u8 start_pair, 1131 u8 end_pair, u32 *buf) 1132{ 1133 int ret; 1134 1135 switch (cal_mode) { 1136 case EFUSE_M: 1137 ret = cal_efuse(phydev, cal_item, start_pair, 1138 end_pair, buf); 1139 break; 1140 case SW_M: 1141 ret = cal_sw(phydev, cal_item, start_pair, end_pair); 1142 break; 1143 default: 1144 return -EINVAL; 1145 } 1146 1147 if (ret) { 1148 phydev_err(phydev, "cal %d failed\n", cal_item); 1149 return -EIO; 1150 } 1151 1152 return 0; 1153} 1154 1155static int mt798x_phy_calibration(struct phy_device *phydev) 1156{ 1157 struct nvmem_cell *cell; 1158 int ret = 0; 1159 size_t len; 1160 u32 *buf; 1161 1162 cell = nvmem_cell_get(&phydev->mdio.dev, "phy-cal-data"); 1163 if (IS_ERR(cell)) { 1164 if (PTR_ERR(cell) == -EPROBE_DEFER) 1165 return PTR_ERR(cell); 1166 return 0; 1167 } 1168 1169 buf = (u32 *)nvmem_cell_read(cell, &len); 1170 nvmem_cell_put(cell); 1171 if (IS_ERR(buf)) 1172 return PTR_ERR(buf); 1173 1174 if (!buf[0] || !buf[1] || !buf[2] || !buf[3] || len < 4 * sizeof(u32)) { 1175 phydev_err(phydev, "invalid efuse data\n"); 1176 ret = -EINVAL; 1177 goto out; 1178 } 1179 1180 ret = start_cal(phydev, REXT, EFUSE_M, NO_PAIR, NO_PAIR, buf); 1181 if (ret) 1182 goto out; 1183 ret = start_cal(phydev, TX_OFFSET, EFUSE_M, NO_PAIR, NO_PAIR, buf); 1184 if (ret) 1185 goto out; 1186 ret = start_cal(phydev, TX_AMP, EFUSE_M, NO_PAIR, NO_PAIR, buf); 1187 if (ret) 1188 goto out; 1189 ret = start_cal(phydev, TX_R50, EFUSE_M, PAIR_A, PAIR_D, buf); 1190 if (ret) 1191 goto out; 1192 ret = start_cal(phydev, TX_VCM, SW_M, PAIR_A, PAIR_A, buf); 1193 if (ret) 1194 goto out; 1195 1196out: 1197 kfree(buf); 1198 return ret; 1199} 1200 1201static int mt798x_phy_config_init(struct phy_device *phydev) 1202{ 1203 switch (phydev->drv->phy_id) { 1204 case MTK_GPHY_ID_MT7981: 1205 mt7981_phy_finetune(phydev); 1206 break; 1207 case MTK_GPHY_ID_MT7988: 1208 mt7988_phy_finetune(phydev); 1209 break; 1210 } 1211 1212 mt798x_phy_common_finetune(phydev); 1213 mt798x_phy_eee(phydev); 1214 1215 return mt798x_phy_calibration(phydev); 1216} 1217 1218static int mt798x_phy_led_blink_set(struct phy_device *phydev, u8 index, 1219 unsigned long *delay_on, 1220 unsigned long *delay_off) 1221{ 1222 bool blinking = false; 1223 int err; 1224 1225 err = mtk_phy_led_num_dly_cfg(index, delay_on, delay_off, &blinking); 1226 if (err < 0) 1227 return err; 1228 1229 err = mtk_phy_hw_led_blink_set(phydev, index, blinking); 1230 if (err) 1231 return err; 1232 1233 return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK, 1234 false); 1235} 1236 1237static int mt798x_phy_led_brightness_set(struct phy_device *phydev, 1238 u8 index, enum led_brightness value) 1239{ 1240 int err; 1241 1242 err = mtk_phy_hw_led_blink_set(phydev, index, false); 1243 if (err) 1244 return err; 1245 1246 return mtk_phy_hw_led_on_set(phydev, index, MTK_GPHY_LED_ON_MASK, 1247 (value != LED_OFF)); 1248} 1249 1250static const unsigned long supported_triggers = 1251 BIT(TRIGGER_NETDEV_FULL_DUPLEX) | 1252 BIT(TRIGGER_NETDEV_HALF_DUPLEX) | 1253 BIT(TRIGGER_NETDEV_LINK) | 1254 BIT(TRIGGER_NETDEV_LINK_10) | 1255 BIT(TRIGGER_NETDEV_LINK_100) | 1256 BIT(TRIGGER_NETDEV_LINK_1000) | 1257 BIT(TRIGGER_NETDEV_RX) | 1258 BIT(TRIGGER_NETDEV_TX); 1259 1260static int mt798x_phy_led_hw_is_supported(struct phy_device *phydev, u8 index, 1261 unsigned long rules) 1262{ 1263 return mtk_phy_led_hw_is_supported(phydev, index, rules, 1264 supported_triggers); 1265} 1266 1267static int mt798x_phy_led_hw_control_get(struct phy_device *phydev, u8 index, 1268 unsigned long *rules) 1269{ 1270 return mtk_phy_led_hw_ctrl_get(phydev, index, rules, 1271 MTK_GPHY_LED_ON_SET, 1272 MTK_GPHY_LED_RX_BLINK_SET, 1273 MTK_GPHY_LED_TX_BLINK_SET); 1274}; 1275 1276static int mt798x_phy_led_hw_control_set(struct phy_device *phydev, u8 index, 1277 unsigned long rules) 1278{ 1279 return mtk_phy_led_hw_ctrl_set(phydev, index, rules, 1280 MTK_GPHY_LED_ON_SET, 1281 MTK_GPHY_LED_RX_BLINK_SET, 1282 MTK_GPHY_LED_TX_BLINK_SET); 1283}; 1284 1285static bool mt7988_phy_led_get_polarity(struct phy_device *phydev, int led_num) 1286{ 1287 struct mtk_socphy_shared *priv = phy_package_get_priv(phydev); 1288 u32 polarities; 1289 1290 if (led_num == 0) 1291 polarities = ~(priv->boottrap); 1292 else 1293 polarities = MTK_PHY_LED1_DEFAULT_POLARITIES; 1294 1295 if (polarities & BIT(phydev->mdio.addr)) 1296 return true; 1297 1298 return false; 1299} 1300 1301static int mt7988_phy_fix_leds_polarities(struct phy_device *phydev) 1302{ 1303 struct pinctrl *pinctrl; 1304 int index; 1305 1306 /* Setup LED polarity according to bootstrap use of LED pins */ 1307 for (index = 0; index < 2; ++index) 1308 phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? 1309 MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, 1310 MTK_PHY_LED_ON_POLARITY, 1311 mt7988_phy_led_get_polarity(phydev, index) ? 1312 MTK_PHY_LED_ON_POLARITY : 0); 1313 1314 /* Only now setup pinctrl to avoid bogus blinking */ 1315 pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); 1316 if (IS_ERR(pinctrl)) 1317 dev_err(&phydev->mdio.bus->dev, 1318 "Failed to setup PHY LED pinctrl\n"); 1319 1320 return 0; 1321} 1322 1323static int mt7988_phy_probe_shared(struct phy_device *phydev) 1324{ 1325 struct device_node *np = dev_of_node(&phydev->mdio.bus->dev); 1326 struct mtk_socphy_shared *shared = phy_package_get_priv(phydev); 1327 struct device_node *pio_np; 1328 struct regmap *regmap; 1329 u32 reg; 1330 int ret; 1331 1332 /* The LED0 of the 4 PHYs in MT7988 are wired to SoC pins LED_A, LED_B, 1333 * LED_C and LED_D respectively. At the same time those pins are used to 1334 * bootstrap configuration of the reference clock source (LED_A), 1335 * DRAM DDRx16b x2/x1 (LED_B) and boot device (LED_C, LED_D). 1336 * In practice this is done using a LED and a resistor pulling the pin 1337 * either to GND or to VIO. 1338 * The detected value at boot time is accessible at run-time using the 1339 * TPBANK0 register located in the gpio base of the pinctrl, in order 1340 * to read it here it needs to be referenced by a phandle called 1341 * 'mediatek,pio' in the MDIO bus hosting the PHY. 1342 * The 4 bits in TPBANK0 are kept as package shared data and are used to 1343 * set LED polarity for each of the LED0. 1344 */ 1345 pio_np = of_parse_phandle(np, "mediatek,pio", 0); 1346 if (!pio_np) 1347 return -ENODEV; 1348 1349 regmap = device_node_to_regmap(pio_np); 1350 of_node_put(pio_np); 1351 1352 if (IS_ERR(regmap)) 1353 return PTR_ERR(regmap); 1354 1355 ret = regmap_read(regmap, RG_GPIO_MISC_TPBANK0, ®); 1356 if (ret) 1357 return ret; 1358 1359 shared->boottrap = FIELD_GET(RG_GPIO_MISC_TPBANK0_BOOTMODE, reg); 1360 1361 return 0; 1362} 1363 1364static int mt7988_phy_probe(struct phy_device *phydev) 1365{ 1366 struct mtk_socphy_shared *shared; 1367 struct mtk_socphy_priv *priv; 1368 int err; 1369 1370 if (phydev->mdio.addr > 3) 1371 return -EINVAL; 1372 1373 err = devm_phy_package_join(&phydev->mdio.dev, phydev, 0, 1374 sizeof(struct mtk_socphy_shared)); 1375 if (err) 1376 return err; 1377 1378 if (phy_package_probe_once(phydev)) { 1379 err = mt7988_phy_probe_shared(phydev); 1380 if (err) 1381 return err; 1382 } 1383 1384 shared = phy_package_get_priv(phydev); 1385 priv = &shared->priv[phydev->mdio.addr]; 1386 1387 phydev->priv = priv; 1388 1389 mtk_phy_leds_state_init(phydev); 1390 1391 err = mt7988_phy_fix_leds_polarities(phydev); 1392 if (err) 1393 return err; 1394 1395 /* Disable TX power saving at probing to: 1396 * 1. Meet common mode compliance test criteria 1397 * 2. Make sure that TX-VCM calibration works fine 1398 */ 1399 phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_RXADC_CTRL_RG7, 1400 MTK_PHY_DA_AD_BUF_BIAS_LP_MASK, 0x3 << 8); 1401 1402 return mt798x_phy_calibration(phydev); 1403} 1404 1405static int mt7981_phy_probe(struct phy_device *phydev) 1406{ 1407 struct mtk_socphy_priv *priv; 1408 1409 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv), 1410 GFP_KERNEL); 1411 if (!priv) 1412 return -ENOMEM; 1413 1414 phydev->priv = priv; 1415 1416 mtk_phy_leds_state_init(phydev); 1417 1418 return mt798x_phy_calibration(phydev); 1419} 1420 1421static int an7581_phy_probe(struct phy_device *phydev) 1422{ 1423 struct mtk_socphy_priv *priv; 1424 struct pinctrl *pinctrl; 1425 1426 /* Toggle pinctrl to enable PHY LED */ 1427 pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "gbe-led"); 1428 if (IS_ERR(pinctrl)) 1429 dev_err(&phydev->mdio.bus->dev, 1430 "Failed to setup PHY LED pinctrl\n"); 1431 1432 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); 1433 if (!priv) 1434 return -ENOMEM; 1435 1436 phydev->priv = priv; 1437 1438 return 0; 1439} 1440 1441static int an7581_phy_led_polarity_set(struct phy_device *phydev, int index, 1442 unsigned long modes) 1443{ 1444 u16 val = 0; 1445 u32 mode; 1446 1447 if (index >= MTK_PHY_MAX_LEDS) 1448 return -EINVAL; 1449 1450 for_each_set_bit(mode, &modes, __PHY_LED_MODES_NUM) { 1451 switch (mode) { 1452 case PHY_LED_ACTIVE_LOW: 1453 val = MTK_PHY_LED_ON_POLARITY; 1454 break; 1455 case PHY_LED_ACTIVE_HIGH: 1456 break; 1457 default: 1458 return -EINVAL; 1459 } 1460 } 1461 1462 return phy_modify_mmd(phydev, MDIO_MMD_VEND2, index ? 1463 MTK_PHY_LED1_ON_CTRL : MTK_PHY_LED0_ON_CTRL, 1464 MTK_PHY_LED_ON_POLARITY, val); 1465} 1466 1467static int an7583_phy_config_init(struct phy_device *phydev) 1468{ 1469 /* BMCR_PDOWN is enabled by default */ 1470 return phy_clear_bits(phydev, MII_BMCR, BMCR_PDOWN); 1471} 1472 1473static struct phy_driver mtk_socphy_driver[] = { 1474 { 1475 PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981), 1476 .name = "MediaTek MT7981 PHY", 1477 .config_init = mt798x_phy_config_init, 1478 .config_intr = genphy_no_config_intr, 1479 .handle_interrupt = genphy_handle_interrupt_no_ack, 1480 .probe = mt7981_phy_probe, 1481 .suspend = genphy_suspend, 1482 .resume = genphy_resume, 1483 .read_page = mtk_phy_read_page, 1484 .write_page = mtk_phy_write_page, 1485 .led_blink_set = mt798x_phy_led_blink_set, 1486 .led_brightness_set = mt798x_phy_led_brightness_set, 1487 .led_hw_is_supported = mt798x_phy_led_hw_is_supported, 1488 .led_hw_control_set = mt798x_phy_led_hw_control_set, 1489 .led_hw_control_get = mt798x_phy_led_hw_control_get, 1490 }, 1491 { 1492 PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988), 1493 .name = "MediaTek MT7988 PHY", 1494 .config_init = mt798x_phy_config_init, 1495 .config_intr = genphy_no_config_intr, 1496 .handle_interrupt = genphy_handle_interrupt_no_ack, 1497 .probe = mt7988_phy_probe, 1498 .suspend = genphy_suspend, 1499 .resume = genphy_resume, 1500 .read_page = mtk_phy_read_page, 1501 .write_page = mtk_phy_write_page, 1502 .led_blink_set = mt798x_phy_led_blink_set, 1503 .led_brightness_set = mt798x_phy_led_brightness_set, 1504 .led_hw_is_supported = mt798x_phy_led_hw_is_supported, 1505 .led_hw_control_set = mt798x_phy_led_hw_control_set, 1506 .led_hw_control_get = mt798x_phy_led_hw_control_get, 1507 }, 1508 { 1509 PHY_ID_MATCH_EXACT(MTK_GPHY_ID_AN7581), 1510 .name = "Airoha AN7581 PHY", 1511 .probe = an7581_phy_probe, 1512 .led_blink_set = mt798x_phy_led_blink_set, 1513 .led_brightness_set = mt798x_phy_led_brightness_set, 1514 .led_hw_is_supported = mt798x_phy_led_hw_is_supported, 1515 .led_hw_control_set = mt798x_phy_led_hw_control_set, 1516 .led_hw_control_get = mt798x_phy_led_hw_control_get, 1517 .led_polarity_set = an7581_phy_led_polarity_set, 1518 }, 1519 { 1520 PHY_ID_MATCH_EXACT(MTK_GPHY_ID_AN7583), 1521 .name = "Airoha AN7583 PHY", 1522 .config_init = an7583_phy_config_init, 1523 .probe = an7581_phy_probe, 1524 .led_blink_set = mt798x_phy_led_blink_set, 1525 .led_brightness_set = mt798x_phy_led_brightness_set, 1526 .led_hw_is_supported = mt798x_phy_led_hw_is_supported, 1527 .led_hw_control_set = mt798x_phy_led_hw_control_set, 1528 .led_hw_control_get = mt798x_phy_led_hw_control_get, 1529 .led_polarity_set = an7581_phy_led_polarity_set, 1530 }, 1531}; 1532 1533module_phy_driver(mtk_socphy_driver); 1534 1535static const struct mdio_device_id __maybe_unused mtk_socphy_tbl[] = { 1536 { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7981) }, 1537 { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_MT7988) }, 1538 { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_AN7581) }, 1539 { PHY_ID_MATCH_EXACT(MTK_GPHY_ID_AN7583) }, 1540 { } 1541}; 1542 1543MODULE_DESCRIPTION("MediaTek SoC Gigabit Ethernet PHY driver"); 1544MODULE_AUTHOR("Daniel Golle <daniel@makrotopia.org>"); 1545MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>"); 1546MODULE_LICENSE("GPL"); 1547 1548MODULE_DEVICE_TABLE(mdio, mtk_socphy_tbl);
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