mtk-2p5ge.c

  1// SPDX-License-Identifier: GPL-2.0+
  2#include <linux/bitfield.h>
  3#include <linux/firmware.h>
  4#include <linux/module.h>
  5#include <linux/of_address.h>
  6#include <linux/of_platform.h>
  7#include <linux/pinctrl/consumer.h>
  8#include <linux/phy.h>
  9
 10#include "mtk.h"
 11
 12#define MTK_2P5GPHY_ID_MT7988		0x00339c11
 13
 14#define MT7988_2P5GE_PMB_FW		"mediatek/mt7988/i2p5ge-phy-pmb.bin"
 15#define MT7988_2P5GE_PMB_FW_SIZE	0x20000
 16#define MT7988_2P5GE_PMB_FW_BASE	0x0f100000
 17#define MT7988_2P5GE_PMB_FW_LEN		0x20000
 18#define MTK_2P5GPHY_MCU_CSR_BASE	0x0f0f0000
 19#define MTK_2P5GPHY_MCU_CSR_LEN		0x20
 20#define MD32_EN_CFG			0x18
 21#define   MD32_EN			BIT(0)
 22
 23#define BASE100T_STATUS_EXTEND		0x10
 24#define BASE1000T_STATUS_EXTEND		0x11
 25#define EXTEND_CTRL_AND_STATUS		0x16
 26
 27#define PHY_AUX_CTRL_STATUS		0x1d
 28#define   PHY_AUX_DPX_MASK		GENMASK(5, 5)
 29#define   PHY_AUX_SPEED_MASK		GENMASK(4, 2)
 30
 31/* Registers on MDIO_MMD_VEND1 */
 32#define MTK_PHY_LPI_PCS_DSP_CTRL		0x121
 33#define   MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK	GENMASK(12, 8)
 34
 35#define MTK_PHY_HOST_CMD1		0x800e
 36#define MTK_PHY_HOST_CMD2		0x800f
 37/* Registers on Token Ring debug nodes */
 38/* ch_addr = 0x0, node_addr = 0xf, data_addr = 0x3c */
 39#define AUTO_NP_10XEN				BIT(6)
 40
 41enum {
 42	PHY_AUX_SPD_10 = 0,
 43	PHY_AUX_SPD_100,
 44	PHY_AUX_SPD_1000,
 45	PHY_AUX_SPD_2500,
 46};
 47
 48static int mt798x_2p5ge_phy_load_fw(struct phy_device *phydev)
 49{
 50	struct device *dev = &phydev->mdio.dev;
 51	void __iomem *mcu_csr_base, *pmb_addr;
 52	const struct firmware *fw;
 53	int ret, i;
 54	u32 reg;
 55
 56	pmb_addr = ioremap(MT7988_2P5GE_PMB_FW_BASE, MT7988_2P5GE_PMB_FW_LEN);
 57	if (!pmb_addr)
 58		return -ENOMEM;
 59	mcu_csr_base = ioremap(MTK_2P5GPHY_MCU_CSR_BASE,
 60			       MTK_2P5GPHY_MCU_CSR_LEN);
 61	if (!mcu_csr_base) {
 62		ret = -ENOMEM;
 63		goto free_pmb;
 64	}
 65
 66	ret = request_firmware_direct(&fw, MT7988_2P5GE_PMB_FW, dev);
 67	if (ret) {
 68		dev_err(dev, "failed to load firmware: %s, ret: %d\n",
 69			MT7988_2P5GE_PMB_FW, ret);
 70		goto free;
 71	}
 72
 73	if (fw->size != MT7988_2P5GE_PMB_FW_SIZE) {
 74		dev_err(dev, "Firmware size 0x%zx != 0x%x\n",
 75			fw->size, MT7988_2P5GE_PMB_FW_SIZE);
 76		ret = -EINVAL;
 77		goto release_fw;
 78	}
 79
 80	reg = readw(mcu_csr_base + MD32_EN_CFG);
 81	if (reg & MD32_EN) {
 82		phy_set_bits(phydev, MII_BMCR, BMCR_RESET);
 83		usleep_range(10000, 11000);
 84	}
 85	phy_set_bits(phydev, MII_BMCR, BMCR_PDOWN);
 86
 87	/* Write magic number to safely stall MCU */
 88	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_HOST_CMD1, 0x1100);
 89	phy_write_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_HOST_CMD2, 0x00df);
 90
 91	for (i = 0; i < MT7988_2P5GE_PMB_FW_SIZE - 1; i += 4)
 92		writel(*((uint32_t *)(fw->data + i)), pmb_addr + i);
 93
 94	writew(reg & ~MD32_EN, mcu_csr_base + MD32_EN_CFG);
 95	writew(reg | MD32_EN, mcu_csr_base + MD32_EN_CFG);
 96	phy_set_bits(phydev, MII_BMCR, BMCR_RESET);
 97	/* We need a delay here to stabilize initialization of MCU */
 98	usleep_range(7000, 8000);
 99
100	dev_info(dev, "Firmware date code: %x/%x/%x, version: %x.%x\n",
101		 be16_to_cpu(*((__be16 *)(fw->data +
102					  MT7988_2P5GE_PMB_FW_SIZE - 8))),
103		 *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 6),
104		 *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 5),
105		 *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 2),
106		 *(fw->data + MT7988_2P5GE_PMB_FW_SIZE - 1));
107
108release_fw:
109	release_firmware(fw);
110free:
111	iounmap(mcu_csr_base);
112free_pmb:
113	iounmap(pmb_addr);
114
115	return ret;
116}
117
118static int mt798x_2p5ge_phy_config_init(struct phy_device *phydev)
119{
120	/* Check if PHY interface type is compatible */
121	if (phydev->interface != PHY_INTERFACE_MODE_INTERNAL)
122		return -ENODEV;
123
124	phy_modify_mmd(phydev, MDIO_MMD_VEND1, MTK_PHY_LPI_PCS_DSP_CTRL,
125		       MTK_PHY_LPI_SIG_EN_LO_THRESH100_MASK, 0);
126
127	/* Enable 16-bit next page exchange bit if 1000-BT isn't advertising */
128	mtk_tr_modify(phydev, 0x0, 0xf, 0x3c, AUTO_NP_10XEN,
129		      FIELD_PREP(AUTO_NP_10XEN, 0x1));
130
131	/* Enable HW auto downshift */
132	phy_modify_paged(phydev, MTK_PHY_PAGE_EXTENDED_1,
133			 MTK_PHY_AUX_CTRL_AND_STATUS,
134			 0, MTK_PHY_ENABLE_DOWNSHIFT);
135
136	return 0;
137}
138
139static int mt798x_2p5ge_phy_config_aneg(struct phy_device *phydev)
140{
141	bool changed = false;
142	u32 adv;
143	int ret;
144
145	ret = genphy_c45_an_config_aneg(phydev);
146	if (ret < 0)
147		return ret;
148	if (ret > 0)
149		changed = true;
150
151	/* Clause 45 doesn't define 1000BaseT support. Use Clause 22 instead in
152	 * our design.
153	 */
154	adv = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising);
155	ret = phy_modify_changed(phydev, MII_CTRL1000, ADVERTISE_1000FULL, adv);
156	if (ret < 0)
157		return ret;
158	if (ret > 0)
159		changed = true;
160
161	return genphy_c45_check_and_restart_aneg(phydev, changed);
162}
163
164static int mt798x_2p5ge_phy_get_features(struct phy_device *phydev)
165{
166	int ret;
167
168	ret = genphy_c45_pma_read_abilities(phydev);
169	if (ret)
170		return ret;
171
172	/* This phy can't handle collision, and neither can (XFI)MAC it's
173	 * connected to. Although it can do HDX handshake, it doesn't support
174	 * CSMA/CD that HDX requires.
175	 */
176	linkmode_clear_bit(ETHTOOL_LINK_MODE_100baseT_Half_BIT,
177			   phydev->supported);
178
179	return 0;
180}
181
182static int mt798x_2p5ge_phy_read_status(struct phy_device *phydev)
183{
184	int ret;
185
186	/* When MDIO_STAT1_LSTATUS is raised genphy_c45_read_link(), this phy
187	 * actually hasn't finished AN. So use CL22's link update function
188	 * instead.
189	 */
190	ret = genphy_update_link(phydev);
191	if (ret)
192		return ret;
193
194	phydev->speed = SPEED_UNKNOWN;
195	phydev->duplex = DUPLEX_UNKNOWN;
196	phydev->pause = 0;
197	phydev->asym_pause = 0;
198
199	/* We'll read link speed through vendor specific registers down below.
200	 * So remove phy_resolve_aneg_linkmode (AN on) & genphy_c45_read_pma
201	 * (AN off).
202	 */
203	if (phydev->autoneg == AUTONEG_ENABLE && phydev->autoneg_complete) {
204		ret = genphy_c45_read_lpa(phydev);
205		if (ret < 0)
206			return ret;
207
208		/* Clause 45 doesn't define 1000BaseT support. Read the link
209		 * partner's 1G advertisement via Clause 22.
210		 */
211		ret = phy_read(phydev, MII_STAT1000);
212		if (ret < 0)
213			return ret;
214		mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, ret);
215	} else if (phydev->autoneg == AUTONEG_DISABLE) {
216		linkmode_zero(phydev->lp_advertising);
217	}
218
219	if (phydev->link) {
220		ret = phy_read(phydev, PHY_AUX_CTRL_STATUS);
221		if (ret < 0)
222			return ret;
223
224		switch (FIELD_GET(PHY_AUX_SPEED_MASK, ret)) {
225		case PHY_AUX_SPD_10:
226			phydev->speed = SPEED_10;
227			break;
228		case PHY_AUX_SPD_100:
229			phydev->speed = SPEED_100;
230			break;
231		case PHY_AUX_SPD_1000:
232			phydev->speed = SPEED_1000;
233			break;
234		case PHY_AUX_SPD_2500:
235			phydev->speed = SPEED_2500;
236			break;
237		}
238
239		phydev->duplex = DUPLEX_FULL;
240		phydev->rate_matching = RATE_MATCH_PAUSE;
241	}
242
243	return 0;
244}
245
246static int mt798x_2p5ge_phy_get_rate_matching(struct phy_device *phydev,
247					      phy_interface_t iface)
248{
249	return RATE_MATCH_PAUSE;
250}
251
252static const unsigned long supported_triggers =
253	BIT(TRIGGER_NETDEV_FULL_DUPLEX) |
254	BIT(TRIGGER_NETDEV_LINK)        |
255	BIT(TRIGGER_NETDEV_LINK_10)     |
256	BIT(TRIGGER_NETDEV_LINK_100)    |
257	BIT(TRIGGER_NETDEV_LINK_1000)   |
258	BIT(TRIGGER_NETDEV_LINK_2500)   |
259	BIT(TRIGGER_NETDEV_RX)          |
260	BIT(TRIGGER_NETDEV_TX);
261
262static int mt798x_2p5ge_phy_led_blink_set(struct phy_device *phydev, u8 index,
263					  unsigned long *delay_on,
264					  unsigned long *delay_off)
265{
266	bool blinking = false;
267	int err = 0;
268
269	err = mtk_phy_led_num_dly_cfg(index, delay_on, delay_off, &blinking);
270	if (err < 0)
271		return err;
272
273	err = mtk_phy_hw_led_blink_set(phydev, index, blinking);
274	if (err)
275		return err;
276
277	if (blinking)
278		mtk_phy_hw_led_on_set(phydev, index, MTK_2P5GPHY_LED_ON_MASK,
279				      false);
280
281	return 0;
282}
283
284static int mt798x_2p5ge_phy_led_brightness_set(struct phy_device *phydev,
285					       u8 index,
286					       enum led_brightness value)
287{
288	int err;
289
290	err = mtk_phy_hw_led_blink_set(phydev, index, false);
291	if (err)
292		return err;
293
294	return mtk_phy_hw_led_on_set(phydev, index, MTK_2P5GPHY_LED_ON_MASK,
295				     (value != LED_OFF));
296}
297
298static int mt798x_2p5ge_phy_led_hw_is_supported(struct phy_device *phydev,
299						u8 index, unsigned long rules)
300{
301	return mtk_phy_led_hw_is_supported(phydev, index, rules,
302					   supported_triggers);
303}
304
305static int mt798x_2p5ge_phy_led_hw_control_get(struct phy_device *phydev,
306					       u8 index, unsigned long *rules)
307{
308	return mtk_phy_led_hw_ctrl_get(phydev, index, rules,
309				       MTK_2P5GPHY_LED_ON_SET,
310				       MTK_2P5GPHY_LED_RX_BLINK_SET,
311				       MTK_2P5GPHY_LED_TX_BLINK_SET);
312};
313
314static int mt798x_2p5ge_phy_led_hw_control_set(struct phy_device *phydev,
315					       u8 index, unsigned long rules)
316{
317	return mtk_phy_led_hw_ctrl_set(phydev, index, rules,
318				       MTK_2P5GPHY_LED_ON_SET,
319				       MTK_2P5GPHY_LED_RX_BLINK_SET,
320				       MTK_2P5GPHY_LED_TX_BLINK_SET);
321};
322
323static int mt798x_2p5ge_phy_probe(struct phy_device *phydev)
324{
325	struct mtk_socphy_priv *priv;
326	struct pinctrl *pinctrl;
327	int ret;
328
329	switch (phydev->drv->phy_id) {
330	case MTK_2P5GPHY_ID_MT7988:
331		/* This built-in 2.5GbE hardware only sets MDIO_DEVS_PMAPMD.
332		 * Set the rest by this driver since PCS/AN/VEND1/VEND2 MDIO
333		 * manageable devices actually exist.
334		 */
335		phydev->c45_ids.mmds_present |= MDIO_DEVS_PCS |
336						MDIO_DEVS_AN |
337						MDIO_DEVS_VEND1 |
338						MDIO_DEVS_VEND2;
339		break;
340	default:
341		return -EINVAL;
342	}
343
344	ret = mt798x_2p5ge_phy_load_fw(phydev);
345	if (ret < 0)
346		return ret;
347
348	/* Setup LED. On default, LED0 is on/off when link is up/down. As for
349	 * LED1, it blinks as tx/rx transmission takes place.
350	 */
351	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_ON_CTRL,
352			 MTK_PHY_LED_ON_POLARITY | MTK_2P5GPHY_LED_ON_SET);
353	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED0_BLINK_CTRL,
354			   MTK_2P5GPHY_LED_TX_BLINK_SET |
355			   MTK_2P5GPHY_LED_RX_BLINK_SET);
356	phy_clear_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_ON_CTRL,
357			   MTK_PHY_LED_ON_FDX | MTK_PHY_LED_ON_HDX |
358			   MTK_2P5GPHY_LED_ON_SET);
359	phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, MTK_PHY_LED1_BLINK_CTRL,
360			 MTK_2P5GPHY_LED_TX_BLINK_SET |
361			 MTK_2P5GPHY_LED_RX_BLINK_SET);
362
363	/* Switch pinctrl after setting polarity to avoid bogus blinking */
364	pinctrl = devm_pinctrl_get_select(&phydev->mdio.dev, "i2p5gbe-led");
365	if (IS_ERR(pinctrl))
366		dev_err(&phydev->mdio.dev, "Fail to set LED pins!\n");
367
368	priv = devm_kzalloc(&phydev->mdio.dev, sizeof(struct mtk_socphy_priv),
369			    GFP_KERNEL);
370	if (!priv)
371		return -ENOMEM;
372	phydev->priv = priv;
373
374	mtk_phy_leds_state_init(phydev);
375
376	return 0;
377}
378
379static struct phy_driver mtk_2p5gephy_driver[] = {
380	{
381		PHY_ID_MATCH_MODEL(MTK_2P5GPHY_ID_MT7988),
382		.name = "MediaTek MT7988 2.5GbE PHY",
383		.probe = mt798x_2p5ge_phy_probe,
384		.config_init = mt798x_2p5ge_phy_config_init,
385		.config_aneg = mt798x_2p5ge_phy_config_aneg,
386		.get_features = mt798x_2p5ge_phy_get_features,
387		.read_status = mt798x_2p5ge_phy_read_status,
388		.get_rate_matching = mt798x_2p5ge_phy_get_rate_matching,
389		.suspend = genphy_suspend,
390		.resume = genphy_resume,
391		.read_page = mtk_phy_read_page,
392		.write_page = mtk_phy_write_page,
393		.led_blink_set = mt798x_2p5ge_phy_led_blink_set,
394		.led_brightness_set = mt798x_2p5ge_phy_led_brightness_set,
395		.led_hw_is_supported = mt798x_2p5ge_phy_led_hw_is_supported,
396		.led_hw_control_get = mt798x_2p5ge_phy_led_hw_control_get,
397		.led_hw_control_set = mt798x_2p5ge_phy_led_hw_control_set,
398	},
399};
400
401module_phy_driver(mtk_2p5gephy_driver);
402
403static struct mdio_device_id __maybe_unused mtk_2p5ge_phy_tbl[] = {
404	{ PHY_ID_MATCH_VENDOR(0x00339c00) },
405	{ }
406};
407
408MODULE_DESCRIPTION("MediaTek 2.5Gb Ethernet PHY driver");
409MODULE_AUTHOR("SkyLake Huang <SkyLake.Huang@mediatek.com>");
410MODULE_LICENSE("GPL");
411
412MODULE_DEVICE_TABLE(mdio, mtk_2p5ge_phy_tbl);
413MODULE_FIRMWARE(MT7988_2P5GE_PMB_FW);