dp83tg720.c

  1// SPDX-License-Identifier: GPL-2.0
  2/* Driver for the Texas Instruments DP83TG720 PHY
  3 * Copyright (c) 2023 Pengutronix, Oleksij Rempel <kernel@pengutronix.de>
  4 */
  5#include <linux/bitfield.h>
  6#include <linux/ethtool_netlink.h>
  7#include <linux/jiffies.h>
  8#include <linux/kernel.h>
  9#include <linux/module.h>
 10#include <linux/phy.h>
 11#include <linux/random.h>
 12
 13#include "open_alliance_helpers.h"
 14
 15/*
 16 * DP83TG720 PHY Limitations and Workarounds
 17 *
 18 * The DP83TG720 1000BASE-T1 PHY has several limitations that require
 19 * software-side mitigations. These workarounds are implemented throughout
 20 * this driver. This section documents the known issues and their corresponding
 21 * mitigation strategies.
 22 *
 23 * 1. Unreliable Link Detection and Synchronized Reset Deadlock
 24 * ------------------------------------------------------------
 25 * After a link loss or during link establishment, the DP83TG720 PHY may fail
 26 * to detect or report link status correctly. As of June 2025, no public
 27 * errata sheet for the DP83TG720 PHY documents this behavior.
 28 * The "DP83TC81x, DP83TG72x Software Implementation Guide" application note
 29 * (SNLA404, available at https://www.ti.com/lit/an/snla404/snla404.pdf)
 30 * recommends performing a soft restart if polling for a link fails to establish
 31 * a connection after 100ms. This procedure is adopted as the workaround for the
 32 * observed link detection issue.
 33 *
 34 * However, in point-to-point setups where both link partners use the same
 35 * driver (e.g. Linux on both sides), a synchronized reset pattern may emerge.
 36 * This leads to a deadlock, where both PHYs reset at the same time and
 37 * continuously miss each other during auto-negotiation.
 38 *
 39 * To address this, the reset procedure includes two components:
 40 *
 41 * - A **fixed minimum delay of 1ms** after a hardware reset. The datasheet
 42 *   "DP83TG720S-Q1 1000BASE-T1 Automotive Ethernet PHY with SGMII and RGMII"
 43 *   specifies this as the "Post reset stabilization-time prior to MDC preamble
 44 *   for register access" (T6.2), ensuring the PHY is ready for MDIO
 45 *   operations.
 46 *
 47 * - An **additional asymmetric delay**, empirically chosen based on
 48 *   master/slave role. This reduces the risk of synchronized resets on both
 49 *   link partners. Values are selected to avoid periodic overlap and ensure
 50 *   the link is re-established within a few cycles.
 51 *
 52 * The functions that implement this logic are:
 53 * - dp83tg720_soft_reset()
 54 * - dp83tg720_get_next_update_time()
 55 *
 56 * 2. Polling-Based Link Detection and IRQ Support
 57 * -----------------------------------------------
 58 * Due to the PHY-specific limitation described in section 1, link-up events
 59 * cannot be reliably detected via interrupts on the DP83TG720. Therefore,
 60 * polling is required to detect transitions from link-down to link-up.
 61 *
 62 * While link-down events *can* be detected via IRQs on this PHY, this driver
 63 * currently does **not** implement interrupt support. As a result, all link
 64 * state changes must be detected using polling.
 65 *
 66 * Polling behavior:
 67 * - When the link is up: slow polling (e.g. 1s).
 68 * - When the link just went down: fast polling for a short time.
 69 * - When the link stays down: fallback to slow polling.
 70 *
 71 * This design balances responsiveness and CPU usage. It sacrifices fast link-up
 72 * times in cases where the link is expected to remain down for extended periods,
 73 * assuming that such systems do not require immediate reactivity.
 74 */
 75
 76/*
 77 * DP83TG720S_POLL_ACTIVE_LINK - Polling interval in milliseconds when the link
 78 *				 is active.
 79 * DP83TG720S_POLL_NO_LINK     - Polling interval in milliseconds when the
 80 *				 link is down.
 81 * DP83TG720S_FAST_POLL_DURATION_MS - Timeout in milliseconds for no-link
 82 *				 polling after which polling interval is
 83 *				 increased.
 84 * DP83TG720S_POLL_SLOW	       - Slow polling interval when there is no
 85 *				 link for a prolongued period.
 86 * DP83TG720S_RESET_DELAY_MS_MASTER - Delay after a reset before attempting
 87 *				 to establish a link again for master phy.
 88 * DP83TG720S_RESET_DELAY_MS_SLAVE  - Delay after a reset before attempting
 89 *				 to establish a link again for slave phy.
 90 *
 91 * These values are not documented or officially recommended by the vendor but
 92 * were determined through empirical testing. They achieve a good balance in
 93 * minimizing the number of reset retries while ensuring reliable link recovery
 94 * within a reasonable timeframe.
 95 */
 96#define DP83TG720S_POLL_ACTIVE_LINK		421
 97#define DP83TG720S_POLL_NO_LINK			149
 98#define DP83TG720S_FAST_POLL_DURATION_MS	6000
 99#define DP83TG720S_POLL_SLOW			1117
100#define DP83TG720S_RESET_DELAY_MS_MASTER	97
101#define DP83TG720S_RESET_DELAY_MS_SLAVE		149
102
103#define DP83TG720S_PHY_ID			0x2000a284
104
105/* MDIO_MMD_VEND2 registers */
106#define DP83TG720S_MII_REG_10			0x10
107#define DP83TG720S_STS_MII_INT			BIT(7)
108#define DP83TG720S_LINK_STATUS			BIT(0)
109
110/* TDR Configuration Register (0x1E) */
111#define DP83TG720S_TDR_CFG			0x1e
112/* 1b = TDR start, 0b = No TDR */
113#define DP83TG720S_TDR_START			BIT(15)
114/* 1b = TDR auto on link down, 0b = Manual TDR start */
115#define DP83TG720S_CFG_TDR_AUTO_RUN		BIT(14)
116/* 1b = TDR done, 0b = TDR in progress */
117#define DP83TG720S_TDR_DONE			BIT(1)
118/* 1b = TDR fail, 0b = TDR success */
119#define DP83TG720S_TDR_FAIL			BIT(0)
120
121#define DP83TG720S_PHY_RESET			0x1f
122#define DP83TG720S_HW_RESET			BIT(15)
123
124#define DP83TG720S_LPS_CFG3			0x18c
125/* Power modes are documented as bit fields but used as values */
126/* Power Mode 0 is Normal mode */
127#define DP83TG720S_LPS_CFG3_PWR_MODE_0		BIT(0)
128
129/* Open Aliance 1000BaseT1 compatible HDD.TDR Fault Status Register */
130#define DP83TG720S_TDR_FAULT_STATUS		0x30f
131
132/* Register 0x0301: TDR Configuration 2 */
133#define DP83TG720S_TDR_CFG2			0x301
134
135/* Register 0x0303: TDR Configuration 3 */
136#define DP83TG720S_TDR_CFG3			0x303
137
138/* Register 0x0304: TDR Configuration 4 */
139#define DP83TG720S_TDR_CFG4			0x304
140
141/* Register 0x0405: Unknown Register */
142#define DP83TG720S_UNKNOWN_0405			0x405
143
144#define DP83TG720S_LINK_QUAL_3			0x547
145#define DP83TG720S_LINK_LOSS_CNT_MASK		GENMASK(15, 10)
146
147/* Register 0x0576: TDR Master Link Down Control */
148#define DP83TG720S_TDR_MASTER_LINK_DOWN		0x576
149
150#define DP83TG720S_RGMII_DELAY_CTRL		0x602
151/* In RGMII mode, Enable or disable the internal delay for RXD */
152#define DP83TG720S_RGMII_RX_CLK_SEL		BIT(1)
153/* In RGMII mode, Enable or disable the internal delay for TXD */
154#define DP83TG720S_RGMII_TX_CLK_SEL		BIT(0)
155
156/*
157 * DP83TG720S_PKT_STAT_x registers correspond to similarly named registers
158 * in the datasheet (PKT_STAT_1 through PKT_STAT_6). These registers store
159 * 32-bit or 16-bit counters for TX and RX statistics and must be read in
160 * sequence to ensure the counters are cleared correctly.
161 *
162 * - DP83TG720S_PKT_STAT_1: Contains TX packet count bits [15:0].
163 * - DP83TG720S_PKT_STAT_2: Contains TX packet count bits [31:16].
164 * - DP83TG720S_PKT_STAT_3: Contains TX error packet count.
165 * - DP83TG720S_PKT_STAT_4: Contains RX packet count bits [15:0].
166 * - DP83TG720S_PKT_STAT_5: Contains RX packet count bits [31:16].
167 * - DP83TG720S_PKT_STAT_6: Contains RX error packet count.
168 *
169 * Keeping the register names as defined in the datasheet helps maintain
170 * clarity and alignment with the documentation.
171 */
172#define DP83TG720S_PKT_STAT_1			0x639
173#define DP83TG720S_PKT_STAT_2			0x63a
174#define DP83TG720S_PKT_STAT_3			0x63b
175#define DP83TG720S_PKT_STAT_4			0x63c
176#define DP83TG720S_PKT_STAT_5			0x63d
177#define DP83TG720S_PKT_STAT_6			0x63e
178
179/* Register 0x083F: Unknown Register */
180#define DP83TG720S_UNKNOWN_083F			0x83f
181
182#define DP83TG720S_SQI_REG_1			0x871
183#define DP83TG720S_SQI_OUT_WORST		GENMASK(7, 5)
184#define DP83TG720S_SQI_OUT			GENMASK(3, 1)
185
186#define DP83TG720_SQI_MAX			7
187
188struct dp83tg720_stats {
189	u64 link_loss_cnt;
190	u64 tx_pkt_cnt;
191	u64 tx_err_pkt_cnt;
192	u64 rx_pkt_cnt;
193	u64 rx_err_pkt_cnt;
194};
195
196struct dp83tg720_priv {
197	struct dp83tg720_stats stats;
198	unsigned long last_link_down_jiffies;
199};
200
201/**
202 * dp83tg720_update_stats - Update the PHY statistics for the DP83TD510 PHY.
203 * @phydev: Pointer to the phy_device structure.
204 *
205 * The function reads the PHY statistics registers and updates the statistics
206 * structure.
207 *
208 * Returns: 0 on success or a negative error code on failure.
209 */
210static int dp83tg720_update_stats(struct phy_device *phydev)
211{
212	struct dp83tg720_priv *priv = phydev->priv;
213	u32 count;
214	int ret;
215
216	/* Read the link loss count */
217	ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_LINK_QUAL_3);
218	if (ret < 0)
219		return ret;
220	/* link_loss_cnt */
221	count = FIELD_GET(DP83TG720S_LINK_LOSS_CNT_MASK, ret);
222	priv->stats.link_loss_cnt += count;
223
224	/* The DP83TG720S_PKT_STAT registers are divided into two groups:
225	 * - Group 1 (TX stats): DP83TG720S_PKT_STAT_1 to DP83TG720S_PKT_STAT_3
226	 * - Group 2 (RX stats): DP83TG720S_PKT_STAT_4 to DP83TG720S_PKT_STAT_6
227	 *
228	 * Registers in each group are cleared only after reading them in a
229	 * plain sequence (e.g., 1, 2, 3 for Group 1 or 4, 5, 6 for Group 2).
230	 * Any deviation from the sequence, such as reading 1, 2, 1, 2, 3, will
231	 * prevent the group from being cleared. Additionally, the counters
232	 * for a group are frozen as soon as the first register in that group
233	 * is accessed.
234	 */
235	ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_PKT_STAT_1);
236	if (ret < 0)
237		return ret;
238	/* tx_pkt_cnt_15_0 */
239	count = ret;
240
241	ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_PKT_STAT_2);
242	if (ret < 0)
243		return ret;
244	/* tx_pkt_cnt_31_16 */
245	count |= ret << 16;
246	priv->stats.tx_pkt_cnt += count;
247
248	ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_PKT_STAT_3);
249	if (ret < 0)
250		return ret;
251	/* tx_err_pkt_cnt */
252	priv->stats.tx_err_pkt_cnt += ret;
253
254	ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_PKT_STAT_4);
255	if (ret < 0)
256		return ret;
257	/* rx_pkt_cnt_15_0 */
258	count = ret;
259
260	ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_PKT_STAT_5);
261	if (ret < 0)
262		return ret;
263	/* rx_pkt_cnt_31_16 */
264	count |= ret << 16;
265	priv->stats.rx_pkt_cnt += count;
266
267	ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_PKT_STAT_6);
268	if (ret < 0)
269		return ret;
270	/* rx_err_pkt_cnt */
271	priv->stats.rx_err_pkt_cnt += ret;
272
273	return 0;
274}
275
276static int dp83tg720_soft_reset(struct phy_device *phydev)
277{
278	int ret;
279
280	ret = phy_write(phydev, DP83TG720S_PHY_RESET, DP83TG720S_HW_RESET);
281	if (ret)
282		return ret;
283
284	/* Include mandatory MDC-access delay (1ms) + extra asymmetric delay to
285	 * avoid synchronized reset deadlock. See section 1 in the top-of-file
286	 * comment block.
287	 */
288	if (phydev->master_slave_state == MASTER_SLAVE_STATE_SLAVE)
289		msleep(DP83TG720S_RESET_DELAY_MS_SLAVE);
290	else
291		msleep(DP83TG720S_RESET_DELAY_MS_MASTER);
292
293	return ret;
294}
295
296static void dp83tg720_get_link_stats(struct phy_device *phydev,
297				     struct ethtool_link_ext_stats *link_stats)
298{
299	struct dp83tg720_priv *priv = phydev->priv;
300
301	link_stats->link_down_events = priv->stats.link_loss_cnt;
302}
303
304static void dp83tg720_get_phy_stats(struct phy_device *phydev,
305				    struct ethtool_eth_phy_stats *eth_stats,
306				    struct ethtool_phy_stats *stats)
307{
308	struct dp83tg720_priv *priv = phydev->priv;
309
310	stats->tx_packets = priv->stats.tx_pkt_cnt;
311	stats->tx_errors = priv->stats.tx_err_pkt_cnt;
312	stats->rx_packets = priv->stats.rx_pkt_cnt;
313	stats->rx_errors = priv->stats.rx_err_pkt_cnt;
314}
315
316/**
317 * dp83tg720_cable_test_start - Start the cable test for the DP83TG720 PHY.
318 * @phydev: Pointer to the phy_device structure.
319 *
320 * This sequence is based on the documented procedure for the DP83TG720 PHY.
321 *
322 * Returns: 0 on success, a negative error code on failure.
323 */
324static int dp83tg720_cable_test_start(struct phy_device *phydev)
325{
326	int ret;
327
328	/* Initialize the PHY to run the TDR test as described in the
329	 * "DP83TG720S-Q1: Configuring for Open Alliance Specification
330	 * Compliance (Rev. B)" application note.
331	 * Most of the registers are not documented. Some of register names
332	 * are guessed by comparing the register offsets with the DP83TD510E.
333	 */
334
335	/* Force master link down */
336	ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2,
337			       DP83TG720S_TDR_MASTER_LINK_DOWN, 0x0400);
338	if (ret)
339		return ret;
340
341	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG2,
342			    0xa008);
343	if (ret)
344		return ret;
345
346	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG3,
347			    0x0928);
348	if (ret)
349		return ret;
350
351	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG4,
352			    0x0004);
353	if (ret)
354		return ret;
355
356	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_UNKNOWN_0405,
357			    0x6400);
358	if (ret)
359		return ret;
360
361	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_UNKNOWN_083F,
362			    0x3003);
363	if (ret)
364		return ret;
365
366	/* Start the TDR */
367	ret = phy_set_bits_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG,
368			       DP83TG720S_TDR_START);
369	if (ret)
370		return ret;
371
372	return 0;
373}
374
375/**
376 * dp83tg720_cable_test_get_status - Get the status of the cable test for the
377 *                                   DP83TG720 PHY.
378 * @phydev: Pointer to the phy_device structure.
379 * @finished: Pointer to a boolean that indicates whether the test is finished.
380 *
381 * The function sets the @finished flag to true if the test is complete.
382 *
383 * Returns: 0 on success or a negative error code on failure.
384 */
385static int dp83tg720_cable_test_get_status(struct phy_device *phydev,
386					   bool *finished)
387{
388	int ret, stat;
389
390	*finished = false;
391
392	/* Read the TDR status */
393	ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_TDR_CFG);
394	if (ret < 0)
395		return ret;
396
397	/* Check if the TDR test is done */
398	if (!(ret & DP83TG720S_TDR_DONE))
399		return 0;
400
401	/* Check for TDR test failure */
402	if (!(ret & DP83TG720S_TDR_FAIL)) {
403		int location;
404
405		/* Read fault status */
406		ret = phy_read_mmd(phydev, MDIO_MMD_VEND2,
407				   DP83TG720S_TDR_FAULT_STATUS);
408		if (ret < 0)
409			return ret;
410
411		/* Get fault type */
412		stat = oa_1000bt1_get_ethtool_cable_result_code(ret);
413
414		/* Determine fault location */
415		location = oa_1000bt1_get_tdr_distance(ret);
416		if (location > 0)
417			ethnl_cable_test_fault_length(phydev,
418						      ETHTOOL_A_CABLE_PAIR_A,
419						      location);
420	} else {
421		/* Active link partner or other issues */
422		stat = ETHTOOL_A_CABLE_RESULT_CODE_UNSPEC;
423	}
424
425	*finished = true;
426
427	ethnl_cable_test_result(phydev, ETHTOOL_A_CABLE_PAIR_A, stat);
428
429	/* save the current stats before resetting the PHY */
430	ret = dp83tg720_update_stats(phydev);
431	if (ret)
432		return ret;
433
434	return phy_init_hw(phydev);
435}
436
437static int dp83tg720_config_aneg(struct phy_device *phydev)
438{
439	int ret;
440
441	/* Autoneg is not supported and this PHY supports only one speed.
442	 * We need to care only about master/slave configuration if it was
443	 * changed by user.
444	 */
445	ret = genphy_c45_pma_baset1_setup_master_slave(phydev);
446	if (ret)
447		return ret;
448
449	/* Re-read role configuration to make changes visible even if
450	 * the link is in administrative down state.
451	 */
452	return genphy_c45_pma_baset1_read_master_slave(phydev);
453}
454
455static int dp83tg720_read_status(struct phy_device *phydev)
456{
457	u16 phy_sts;
458	int ret;
459
460	phydev->pause = 0;
461	phydev->asym_pause = 0;
462
463	/* Most of Clause 45 registers are not present, so we can't use
464	 * genphy_c45_read_status() here.
465	 */
466	phy_sts = phy_read(phydev, DP83TG720S_MII_REG_10);
467	phydev->link = !!(phy_sts & DP83TG720S_LINK_STATUS);
468	if (!phydev->link) {
469		/* save the current stats before resetting the PHY */
470		ret = dp83tg720_update_stats(phydev);
471		if (ret)
472			return ret;
473
474		/* According to the "DP83TC81x, DP83TG72x Software
475		 * Implementation Guide", the PHY needs to be reset after a
476		 * link loss or if no link is created after at least 100ms.
477		 */
478		ret = phy_init_hw(phydev);
479		if (ret)
480			return ret;
481
482		/* After HW reset we need to restore master/slave configuration.
483		 * genphy_c45_pma_baset1_read_master_slave() call will be done
484		 * by the dp83tg720_config_aneg() function.
485		 */
486		ret = dp83tg720_config_aneg(phydev);
487		if (ret)
488			return ret;
489
490		phydev->speed = SPEED_UNKNOWN;
491		phydev->duplex = DUPLEX_UNKNOWN;
492	} else {
493		/* PMA/PMD control 1 register (Register 1.0) is present, but it
494		 * doesn't contain the link speed information.
495		 * So genphy_c45_read_pma() can't be used here.
496		 */
497		ret = genphy_c45_pma_baset1_read_master_slave(phydev);
498		if (ret)
499			return ret;
500
501		phydev->duplex = DUPLEX_FULL;
502		phydev->speed = SPEED_1000;
503	}
504
505	return 0;
506}
507
508static int dp83tg720_get_sqi(struct phy_device *phydev)
509{
510	int ret;
511
512	if (!phydev->link)
513		return 0;
514
515	ret = phy_read_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_SQI_REG_1);
516	if (ret < 0)
517		return ret;
518
519	return FIELD_GET(DP83TG720S_SQI_OUT, ret);
520}
521
522static int dp83tg720_get_sqi_max(struct phy_device *phydev)
523{
524	return DP83TG720_SQI_MAX;
525}
526
527static int dp83tg720_config_rgmii_delay(struct phy_device *phydev)
528{
529	u16 rgmii_delay_mask;
530	u16 rgmii_delay = 0;
531
532	switch (phydev->interface) {
533	case PHY_INTERFACE_MODE_RGMII:
534		rgmii_delay = 0;
535		break;
536	case PHY_INTERFACE_MODE_RGMII_ID:
537		rgmii_delay = DP83TG720S_RGMII_RX_CLK_SEL |
538				DP83TG720S_RGMII_TX_CLK_SEL;
539		break;
540	case PHY_INTERFACE_MODE_RGMII_RXID:
541		rgmii_delay = DP83TG720S_RGMII_RX_CLK_SEL;
542		break;
543	case PHY_INTERFACE_MODE_RGMII_TXID:
544		rgmii_delay = DP83TG720S_RGMII_TX_CLK_SEL;
545		break;
546	default:
547		return 0;
548	}
549
550	rgmii_delay_mask = DP83TG720S_RGMII_RX_CLK_SEL |
551		DP83TG720S_RGMII_TX_CLK_SEL;
552
553	return phy_modify_mmd(phydev, MDIO_MMD_VEND2,
554			      DP83TG720S_RGMII_DELAY_CTRL, rgmii_delay_mask,
555			      rgmii_delay);
556}
557
558static int dp83tg720_config_init(struct phy_device *phydev)
559{
560	int ret;
561
562	/* Reset the PHY to recover from a link failure */
563	ret = dp83tg720_soft_reset(phydev);
564	if (ret)
565		return ret;
566
567	if (phy_interface_is_rgmii(phydev)) {
568		ret = dp83tg720_config_rgmii_delay(phydev);
569		if (ret)
570			return ret;
571	}
572
573	/* In case the PHY is bootstrapped in managed mode, we need to
574	 * wake it.
575	 */
576	ret = phy_write_mmd(phydev, MDIO_MMD_VEND2, DP83TG720S_LPS_CFG3,
577			    DP83TG720S_LPS_CFG3_PWR_MODE_0);
578	if (ret)
579		return ret;
580
581	/* Make role configuration visible for ethtool on init and after
582	 * rest.
583	 */
584	return genphy_c45_pma_baset1_read_master_slave(phydev);
585}
586
587static int dp83tg720_probe(struct phy_device *phydev)
588{
589	struct device *dev = &phydev->mdio.dev;
590	struct dp83tg720_priv *priv;
591
592	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
593	if (!priv)
594		return -ENOMEM;
595
596	phydev->priv = priv;
597
598	return 0;
599}
600
601/**
602 * dp83tg720_get_next_update_time - Return next polling interval for PHY state
603 * @phydev: Pointer to the phy_device structure
604 *
605 * Implements adaptive polling interval logic depending on link state and
606 * downtime duration. See the "2. Polling-Based Link Detection and IRQ Support"
607 * section at the top of this file for details.
608 *
609 * Return: Time (in jiffies) until the next poll
610 */
611static unsigned int dp83tg720_get_next_update_time(struct phy_device *phydev)
612{
613	struct dp83tg720_priv *priv = phydev->priv;
614	unsigned int next_time_jiffies;
615
616	if (phydev->link) {
617		priv->last_link_down_jiffies = 0;
618
619		/* When the link is up, use a slower interval (in jiffies) */
620		next_time_jiffies =
621			msecs_to_jiffies(DP83TG720S_POLL_ACTIVE_LINK);
622	} else {
623		unsigned long now = jiffies;
624
625		if (!priv->last_link_down_jiffies)
626			priv->last_link_down_jiffies = now;
627
628		if (time_before(now, priv->last_link_down_jiffies +
629			  msecs_to_jiffies(DP83TG720S_FAST_POLL_DURATION_MS))) {
630			/* Link recently went down: fast polling */
631			next_time_jiffies =
632				msecs_to_jiffies(DP83TG720S_POLL_NO_LINK);
633		} else {
634			/* Link has been down for a while: slow polling */
635			next_time_jiffies =
636				msecs_to_jiffies(DP83TG720S_POLL_SLOW);
637		}
638	}
639
640	/* Ensure the polling time is at least one jiffy */
641	return max(next_time_jiffies, 1U);
642}
643
644static struct phy_driver dp83tg720_driver[] = {
645{
646	PHY_ID_MATCH_MODEL(DP83TG720S_PHY_ID),
647	.name		= "TI DP83TG720S",
648
649	.flags          = PHY_POLL_CABLE_TEST,
650	.probe		= dp83tg720_probe,
651	.soft_reset	= dp83tg720_soft_reset,
652	.config_aneg	= dp83tg720_config_aneg,
653	.read_status	= dp83tg720_read_status,
654	.get_features	= genphy_c45_pma_read_ext_abilities,
655	.config_init	= dp83tg720_config_init,
656	.get_sqi	= dp83tg720_get_sqi,
657	.get_sqi_max	= dp83tg720_get_sqi_max,
658	.cable_test_start = dp83tg720_cable_test_start,
659	.cable_test_get_status = dp83tg720_cable_test_get_status,
660	.get_link_stats	= dp83tg720_get_link_stats,
661	.get_phy_stats	= dp83tg720_get_phy_stats,
662	.update_stats	= dp83tg720_update_stats,
663	.get_next_update_time = dp83tg720_get_next_update_time,
664
665	.suspend	= genphy_suspend,
666	.resume		= genphy_resume,
667} };
668module_phy_driver(dp83tg720_driver);
669
670static const struct mdio_device_id __maybe_unused dp83tg720_tbl[] = {
671	{ PHY_ID_MATCH_MODEL(DP83TG720S_PHY_ID) },
672	{ }
673};
674MODULE_DEVICE_TABLE(mdio, dp83tg720_tbl);
675
676MODULE_DESCRIPTION("Texas Instruments DP83TG720S PHY driver");
677MODULE_AUTHOR("Oleksij Rempel <kernel@pengutronix.de>");
678MODULE_LICENSE("GPL");