pcs-rzn1-miic.c

  1// SPDX-License-Identifier: GPL-2.0
  2/*
  3 * Copyright (C) 2022 Schneider Electric
  4 *
  5 * Clément Léger <clement.leger@bootlin.com>
  6 */
  7
  8#include <linux/array_size.h>
  9#include <linux/bits.h>
 10#include <linux/bitops.h>
 11#include <linux/clk.h>
 12#include <linux/device.h>
 13#include <linux/device/devres.h>
 14#include <linux/mdio.h>
 15#include <linux/of.h>
 16#include <linux/of_platform.h>
 17#include <linux/pcs-rzn1-miic.h>
 18#include <linux/phylink.h>
 19#include <linux/platform_device.h>
 20#include <linux/pm_runtime.h>
 21#include <linux/reset.h>
 22#include <linux/slab.h>
 23#include <dt-bindings/net/pcs-rzn1-miic.h>
 24#include <dt-bindings/net/renesas,r9a09g077-pcs-miic.h>
 25
 26#define MIIC_PRCMD			0x0
 27#define MIIC_ESID_CODE			0x4
 28
 29#define MIIC_MODCTRL			0x8
 30
 31#define MIIC_CONVCTRL(port)		(0x100 + (port) * 4)
 32
 33#define MIIC_CONVCTRL_CONV_SPEED	GENMASK(1, 0)
 34#define CONV_MODE_10MBPS		0
 35#define CONV_MODE_100MBPS		1
 36#define CONV_MODE_1000MBPS		2
 37
 38#define MIIC_CONVCTRL_CONV_MODE		GENMASK(3, 2)
 39#define CONV_MODE_MII			0
 40#define CONV_MODE_RMII			1
 41#define CONV_MODE_RGMII			2
 42
 43#define MIIC_CONVCTRL_FULLD		BIT(8)
 44#define MIIC_CONVCTRL_RGMII_LINK	BIT(12)
 45#define MIIC_CONVCTRL_RGMII_DUPLEX	BIT(13)
 46#define MIIC_CONVCTRL_RGMII_SPEED	GENMASK(15, 14)
 47
 48#define MIIC_CONVRST			0x114
 49#define MIIC_CONVRST_PHYIF_RST(port)	BIT(port)
 50#define MIIC_CONVRST_PHYIF_RST_MASK	GENMASK(4, 0)
 51
 52#define MIIC_SWCTRL			0x304
 53#define MIIC_SWDUPC			0x308
 54
 55#define MIIC_MODCTRL_CONF_CONV_MAX	6
 56#define MIIC_MODCTRL_CONF_NONE		-1
 57
 58#define MIIC_MAX_NUM_RSTS		2
 59
 60/**
 61 * struct modctrl_match - Matching table entry for  convctrl configuration
 62 *			  See section 8.2.1 of manual.
 63 * @mode_cfg: Configuration value for convctrl
 64 * @conv: Configuration of ethernet port muxes. First index is SWITCH_PORTIN,
 65 *	  then index 1 - 5 are CONV1 - CONV5 for RZ/N1 SoCs. In case
 66 *	  of RZ/T2H and RZ/N2H SoCs, the first index is SWITCH_PORTIN then
 67 *	  index 0 - 3 are CONV0 - CONV3.
 68 */
 69struct modctrl_match {
 70	u32 mode_cfg;
 71	u8 conv[MIIC_MODCTRL_CONF_CONV_MAX];
 72};
 73
 74static struct modctrl_match modctrl_match_table[] = {
 75	{0x0, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
 76	       MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}},
 77	{0x1, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
 78	       MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
 79	{0x2, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
 80	       MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
 81	{0x3, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
 82	       MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}},
 83
 84	{0x8, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
 85	       MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}},
 86	{0x9, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
 87	       MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
 88	{0xA, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
 89	       MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
 90	{0xB, {MIIC_RTOS_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
 91	       MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}},
 92
 93	{0x10, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
 94		MIIC_SWITCH_PORTC, MIIC_SERCOS_PORTB, MIIC_SERCOS_PORTA}},
 95	{0x11, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
 96		MIIC_SWITCH_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
 97	{0x12, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
 98		MIIC_ETHERCAT_PORTC, MIIC_ETHERCAT_PORTB, MIIC_ETHERCAT_PORTA}},
 99	{0x13, {MIIC_GMAC2_PORT, MIIC_GMAC1_PORT, MIIC_SWITCH_PORTD,
100		MIIC_SWITCH_PORTC, MIIC_SWITCH_PORTB, MIIC_SWITCH_PORTA}}
101};
102
103static const char * const conf_to_string[] = {
104	[MIIC_GMAC1_PORT]	= "GMAC1_PORT",
105	[MIIC_GMAC2_PORT]	= "GMAC2_PORT",
106	[MIIC_RTOS_PORT]	= "RTOS_PORT",
107	[MIIC_SERCOS_PORTA]	= "SERCOS_PORTA",
108	[MIIC_SERCOS_PORTB]	= "SERCOS_PORTB",
109	[MIIC_ETHERCAT_PORTA]	= "ETHERCAT_PORTA",
110	[MIIC_ETHERCAT_PORTB]	= "ETHERCAT_PORTB",
111	[MIIC_ETHERCAT_PORTC]	= "ETHERCAT_PORTC",
112	[MIIC_SWITCH_PORTA]	= "SWITCH_PORTA",
113	[MIIC_SWITCH_PORTB]	= "SWITCH_PORTB",
114	[MIIC_SWITCH_PORTC]	= "SWITCH_PORTC",
115	[MIIC_SWITCH_PORTD]	= "SWITCH_PORTD",
116	[MIIC_HSR_PORTA]	= "HSR_PORTA",
117	[MIIC_HSR_PORTB]	= "HSR_PORTB",
118};
119
120static const char * const index_to_string[] = {
121	"SWITCH_PORTIN",
122	"CONV1",
123	"CONV2",
124	"CONV3",
125	"CONV4",
126	"CONV5",
127};
128
129static struct modctrl_match rzt2h_modctrl_match_table[] = {
130	{0x0, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ETHSW_PORT1,
131	       ETHSS_ETHSW_PORT2, ETHSS_GMAC1_PORT}},
132
133	{0x1, {MIIC_MODCTRL_CONF_NONE, ETHSS_ESC_PORT0, ETHSS_ESC_PORT1,
134	       ETHSS_GMAC2_PORT, ETHSS_GMAC1_PORT}},
135
136	{0x2, {ETHSS_GMAC0_PORT, ETHSS_ESC_PORT0, ETHSS_ESC_PORT1,
137		ETHSS_ETHSW_PORT2, ETHSS_GMAC1_PORT}},
138
139	{0x3, {MIIC_MODCTRL_CONF_NONE, ETHSS_ESC_PORT0, ETHSS_ESC_PORT1,
140	       ETHSS_ESC_PORT2, ETHSS_GMAC1_PORT}},
141
142	{0x4, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ESC_PORT1,
143	       ETHSS_ESC_PORT2, ETHSS_GMAC1_PORT}},
144
145	{0x5, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ESC_PORT1,
146	       ETHSS_ETHSW_PORT2, ETHSS_GMAC1_PORT}},
147
148	{0x6, {ETHSS_GMAC0_PORT, ETHSS_ETHSW_PORT0, ETHSS_ETHSW_PORT1,
149	       ETHSS_GMAC2_PORT, ETHSS_GMAC1_PORT}},
150
151	{0x7, {MIIC_MODCTRL_CONF_NONE, ETHSS_GMAC0_PORT, ETHSS_GMAC1_PORT,
152		ETHSS_GMAC2_PORT, MIIC_MODCTRL_CONF_NONE}}
153};
154
155static const char * const rzt2h_conf_to_string[] = {
156	[ETHSS_GMAC0_PORT]	= "GMAC0_PORT",
157	[ETHSS_GMAC1_PORT]	= "GMAC1_PORT",
158	[ETHSS_GMAC2_PORT]	= "GMAC2_PORT",
159	[ETHSS_ESC_PORT0]	= "ETHERCAT_PORT0",
160	[ETHSS_ESC_PORT1]	= "ETHERCAT_PORT1",
161	[ETHSS_ESC_PORT2]	= "ETHERCAT_PORT2",
162	[ETHSS_ETHSW_PORT0]	= "SWITCH_PORT0",
163	[ETHSS_ETHSW_PORT1]	= "SWITCH_PORT1",
164	[ETHSS_ETHSW_PORT2]	= "SWITCH_PORT2",
165};
166
167static const char * const rzt2h_index_to_string[] = {
168	"SWITCH_PORTIN",
169	"CONV0",
170	"CONV1",
171	"CONV2",
172	"CONV3",
173};
174
175static const char * const rzt2h_reset_ids[] = {
176	"rst",
177	"crst",
178};
179
180/**
181 * struct miic - MII converter structure
182 * @base: base address of the MII converter
183 * @dev: Device associated to the MII converter
184 * @lock: Lock used for read-modify-write access
185 * @rsts: Reset controls for the MII converter
186 * @of_data: Pointer to OF data
187 */
188struct miic {
189	void __iomem *base;
190	struct device *dev;
191	spinlock_t lock;
192	struct reset_control_bulk_data rsts[MIIC_MAX_NUM_RSTS];
193	const struct miic_of_data *of_data;
194};
195
196/**
197 * struct miic_of_data - OF data for MII converter
198 * @match_table: Matching table for convctrl configuration
199 * @match_table_count: Number of entries in the matching table
200 * @conf_conv_count: Number of entries in the conf_conv array
201 * @conf_to_string: String representations of the configuration values
202 * @conf_to_string_count: Number of entries in the conf_to_string array
203 * @index_to_string: String representations of the index values
204 * @index_to_string_count: Number of entries in the index_to_string array
205 * @miic_port_start: MIIC port start number
206 * @miic_port_max: Maximum MIIC supported
207 * @sw_mode_mask: Switch mode mask
208 * @reset_ids: Reset names array
209 * @reset_count: Number of entries in the reset_ids array
210 * @init_unlock_lock_regs: Flag to indicate if registers need to be unlocked
211 *  before access.
212 * @miic_write: Function pointer to write a value to a MIIC register
213 */
214struct miic_of_data {
215	struct modctrl_match *match_table;
216	u8 match_table_count;
217	u8 conf_conv_count;
218	const char * const *conf_to_string;
219	u8 conf_to_string_count;
220	const char * const *index_to_string;
221	u8 index_to_string_count;
222	u8 miic_port_start;
223	u8 miic_port_max;
224	u8 sw_mode_mask;
225	const char * const *reset_ids;
226	u8 reset_count;
227	bool init_unlock_lock_regs;
228	void (*miic_write)(struct miic *miic, int offset, u32 value);
229};
230
231/**
232 * struct miic_port - Per port MII converter struct
233 * @miic: backiling to MII converter structure
234 * @pcs: PCS structure associated to the port
235 * @port: port number
236 * @interface: interface mode of the port
237 */
238struct miic_port {
239	struct miic *miic;
240	struct phylink_pcs pcs;
241	int port;
242	phy_interface_t interface;
243};
244
245static struct miic_port *phylink_pcs_to_miic_port(struct phylink_pcs *pcs)
246{
247	return container_of(pcs, struct miic_port, pcs);
248}
249
250static void miic_unlock_regs(struct miic *miic)
251{
252	/* Unprotect register writes */
253	writel(0x00A5, miic->base + MIIC_PRCMD);
254	writel(0x0001, miic->base + MIIC_PRCMD);
255	writel(0xFFFE, miic->base + MIIC_PRCMD);
256	writel(0x0001, miic->base + MIIC_PRCMD);
257}
258
259static void miic_lock_regs(struct miic *miic)
260{
261	/* Protect register writes */
262	writel(0x0000, miic->base + MIIC_PRCMD);
263}
264
265static void miic_reg_writel_unlocked(struct miic *miic, int offset, u32 value)
266{
267	writel(value, miic->base + offset);
268}
269
270static void miic_reg_writel_locked(struct miic *miic, int offset, u32 value)
271{
272	miic_unlock_regs(miic);
273	writel(value, miic->base + offset);
274	miic_lock_regs(miic);
275}
276
277static void miic_reg_writel(struct miic *miic, int offset, u32 value)
278{
279	miic->of_data->miic_write(miic, offset, value);
280}
281
282static u32 miic_reg_readl(struct miic *miic, int offset)
283{
284	return readl(miic->base + offset);
285}
286
287static void miic_reg_rmw(struct miic *miic, int offset, u32 mask, u32 val)
288{
289	u32 reg;
290
291	spin_lock(&miic->lock);
292
293	reg = miic_reg_readl(miic, offset);
294	reg &= ~mask;
295	reg |= val;
296	miic_reg_writel(miic, offset, reg);
297
298	spin_unlock(&miic->lock);
299}
300
301static void miic_converter_enable(struct miic *miic, int port, int enable)
302{
303	u32 val = 0;
304
305	if (enable)
306		val = MIIC_CONVRST_PHYIF_RST(port);
307
308	miic_reg_rmw(miic, MIIC_CONVRST, MIIC_CONVRST_PHYIF_RST(port), val);
309}
310
311static int miic_config(struct phylink_pcs *pcs, unsigned int neg_mode,
312		       phy_interface_t interface,
313		       const unsigned long *advertising, bool permit)
314{
315	struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs);
316	struct miic *miic = miic_port->miic;
317	u32 speed, conv_mode, val, mask;
318	int port = miic_port->port;
319
320	switch (interface) {
321	case PHY_INTERFACE_MODE_RMII:
322		conv_mode = CONV_MODE_RMII;
323		speed = CONV_MODE_100MBPS;
324		break;
325	case PHY_INTERFACE_MODE_RGMII:
326	case PHY_INTERFACE_MODE_RGMII_ID:
327	case PHY_INTERFACE_MODE_RGMII_TXID:
328	case PHY_INTERFACE_MODE_RGMII_RXID:
329		conv_mode = CONV_MODE_RGMII;
330		speed = CONV_MODE_1000MBPS;
331		break;
332	case PHY_INTERFACE_MODE_MII:
333		conv_mode = CONV_MODE_MII;
334		/* When in MII mode, speed should be set to 0 (which is actually
335		 * CONV_MODE_10MBPS)
336		 */
337		speed = CONV_MODE_10MBPS;
338		break;
339	default:
340		return -EOPNOTSUPP;
341	}
342
343	val = FIELD_PREP(MIIC_CONVCTRL_CONV_MODE, conv_mode);
344	mask = MIIC_CONVCTRL_CONV_MODE;
345
346	/* Update speed only if we are going to change the interface because
347	 * the link might already be up and it would break it if the speed is
348	 * changed.
349	 */
350	if (interface != miic_port->interface) {
351		val |= FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, speed);
352		mask |= MIIC_CONVCTRL_CONV_SPEED;
353		miic_port->interface = interface;
354	}
355
356	miic_reg_rmw(miic, MIIC_CONVCTRL(port), mask, val);
357	miic_converter_enable(miic, miic_port->port, 1);
358
359	return 0;
360}
361
362static void miic_link_up(struct phylink_pcs *pcs, unsigned int neg_mode,
363			 phy_interface_t interface, int speed, int duplex)
364{
365	struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs);
366	struct miic *miic = miic_port->miic;
367	u32 conv_speed = 0, val = 0;
368	int port = miic_port->port;
369
370	if (duplex == DUPLEX_FULL)
371		val |= MIIC_CONVCTRL_FULLD;
372
373	/* No speed in MII through-mode */
374	if (interface != PHY_INTERFACE_MODE_MII) {
375		switch (speed) {
376		case SPEED_1000:
377			conv_speed = CONV_MODE_1000MBPS;
378			break;
379		case SPEED_100:
380			conv_speed = CONV_MODE_100MBPS;
381			break;
382		case SPEED_10:
383			conv_speed = CONV_MODE_10MBPS;
384			break;
385		default:
386			return;
387		}
388	}
389
390	val |= FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, conv_speed);
391
392	miic_reg_rmw(miic, MIIC_CONVCTRL(port),
393		     (MIIC_CONVCTRL_CONV_SPEED | MIIC_CONVCTRL_FULLD), val);
394}
395
396static int miic_pre_init(struct phylink_pcs *pcs)
397{
398	struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs);
399	struct miic *miic = miic_port->miic;
400	u32 val, mask;
401
402	/* Start RX clock if required */
403	if (pcs->rxc_always_on) {
404		/* In MII through mode, the clock signals will be driven by the
405		 * external PHY, which might not be initialized yet. Set RMII
406		 * as default mode to ensure that a reference clock signal is
407		 * generated.
408		 */
409		miic_port->interface = PHY_INTERFACE_MODE_RMII;
410
411		val = FIELD_PREP(MIIC_CONVCTRL_CONV_MODE, CONV_MODE_RMII) |
412		      FIELD_PREP(MIIC_CONVCTRL_CONV_SPEED, CONV_MODE_100MBPS);
413		mask = MIIC_CONVCTRL_CONV_MODE | MIIC_CONVCTRL_CONV_SPEED;
414
415		miic_reg_rmw(miic, MIIC_CONVCTRL(miic_port->port), mask, val);
416
417		miic_converter_enable(miic, miic_port->port, 1);
418	}
419
420	return 0;
421}
422
423static const struct phylink_pcs_ops miic_phylink_ops = {
424	.pcs_config = miic_config,
425	.pcs_link_up = miic_link_up,
426	.pcs_pre_init = miic_pre_init,
427};
428
429struct phylink_pcs *miic_create(struct device *dev, struct device_node *np)
430{
431	const struct miic_of_data *of_data;
432	struct platform_device *pdev;
433	struct miic_port *miic_port;
434	struct device_node *pcs_np;
435	struct miic *miic;
436	u32 port;
437
438	if (!of_device_is_available(np))
439		return ERR_PTR(-ENODEV);
440
441	if (of_property_read_u32(np, "reg", &port))
442		return ERR_PTR(-EINVAL);
443
444	/* The PCS pdev is attached to the parent node */
445	pcs_np = of_get_parent(np);
446	if (!pcs_np)
447		return ERR_PTR(-ENODEV);
448
449	if (!of_device_is_available(pcs_np)) {
450		of_node_put(pcs_np);
451		return ERR_PTR(-ENODEV);
452	}
453
454	pdev = of_find_device_by_node(pcs_np);
455	of_node_put(pcs_np);
456	if (!pdev || !platform_get_drvdata(pdev)) {
457		if (pdev)
458			put_device(&pdev->dev);
459		return ERR_PTR(-EPROBE_DEFER);
460	}
461
462	miic = platform_get_drvdata(pdev);
463	of_data = miic->of_data;
464	if (port > of_data->miic_port_max || port < of_data->miic_port_start) {
465		put_device(&pdev->dev);
466		return ERR_PTR(-EINVAL);
467	}
468
469	miic_port = kzalloc(sizeof(*miic_port), GFP_KERNEL);
470	if (!miic_port) {
471		put_device(&pdev->dev);
472		return ERR_PTR(-ENOMEM);
473	}
474
475	device_link_add(dev, miic->dev, DL_FLAG_AUTOREMOVE_CONSUMER);
476	put_device(&pdev->dev);
477
478	miic_port->miic = miic;
479	miic_port->port = port - of_data->miic_port_start;
480	miic_port->pcs.ops = &miic_phylink_ops;
481
482	phy_interface_set_rgmii(miic_port->pcs.supported_interfaces);
483	__set_bit(PHY_INTERFACE_MODE_RMII, miic_port->pcs.supported_interfaces);
484	__set_bit(PHY_INTERFACE_MODE_MII, miic_port->pcs.supported_interfaces);
485
486	return &miic_port->pcs;
487}
488EXPORT_SYMBOL(miic_create);
489
490void miic_destroy(struct phylink_pcs *pcs)
491{
492	struct miic_port *miic_port = phylink_pcs_to_miic_port(pcs);
493
494	miic_converter_enable(miic_port->miic, miic_port->port, 0);
495	kfree(miic_port);
496}
497EXPORT_SYMBOL(miic_destroy);
498
499static int miic_init_hw(struct miic *miic, u32 cfg_mode)
500{
501	u8 sw_mode_mask = miic->of_data->sw_mode_mask;
502	int port;
503
504	/* Unlock write access to accessory registers (cf datasheet). If this
505	 * is going to be used in conjunction with the Cortex-M3, this sequence
506	 * will have to be moved in register write
507	 */
508	if (miic->of_data->init_unlock_lock_regs)
509		miic_unlock_regs(miic);
510
511	/* TODO: Replace with FIELD_PREP() when compile-time constant
512	 * restriction is lifted. Currently __ffs() returns 0 for sw_mode_mask.
513	 */
514	miic_reg_writel(miic, MIIC_MODCTRL,
515			((cfg_mode << __ffs(sw_mode_mask)) & sw_mode_mask));
516
517	for (port = 0; port < miic->of_data->miic_port_max; port++) {
518		miic_converter_enable(miic, port, 0);
519		/* Disable speed/duplex control from these registers, datasheet
520		 * says switch registers should be used to setup switch port
521		 * speed and duplex.
522		 */
523		miic_reg_writel(miic, MIIC_SWCTRL, 0x0);
524		miic_reg_writel(miic, MIIC_SWDUPC, 0x0);
525	}
526
527	return 0;
528}
529
530static bool miic_modctrl_match(s8 *table_val, s8 *dt_val, u8 count)
531{
532	int i;
533
534	for (i = 0; i < count; i++) {
535		if (dt_val[i] == MIIC_MODCTRL_CONF_NONE)
536			continue;
537
538		if (dt_val[i] != table_val[i])
539			return false;
540	}
541
542	return true;
543}
544
545static void miic_dump_conf(struct miic *miic, s8 *conf)
546{
547	const struct miic_of_data *of_data = miic->of_data;
548	const char *conf_name;
549	int i;
550
551	for (i = 0; i < of_data->conf_conv_count; i++) {
552		if (conf[i] != MIIC_MODCTRL_CONF_NONE)
553			conf_name = of_data->conf_to_string[conf[i]];
554		else
555			conf_name = "NONE";
556
557		dev_err(miic->dev, "%s: %s\n",
558			of_data->index_to_string[i], conf_name);
559	}
560}
561
562static int miic_match_dt_conf(struct miic *miic, s8 *dt_val, u32 *mode_cfg)
563{
564	const struct miic_of_data *of_data = miic->of_data;
565	struct modctrl_match *table_entry;
566	int i;
567
568	for (i = 0; i < of_data->match_table_count; i++) {
569		table_entry = &of_data->match_table[i];
570
571		if (miic_modctrl_match(table_entry->conv, dt_val,
572				       miic->of_data->conf_conv_count)) {
573			*mode_cfg = table_entry->mode_cfg;
574			return 0;
575		}
576	}
577
578	dev_err(miic->dev, "Failed to apply requested configuration\n");
579	miic_dump_conf(miic, dt_val);
580
581	return -EINVAL;
582}
583
584static int miic_parse_dt(struct miic *miic, u32 *mode_cfg)
585{
586	struct device_node *np = miic->dev->of_node;
587	struct device_node *conv;
588	int port, ret;
589	s8 *dt_val;
590	u32 conf;
591
592	dt_val = kmalloc_array(miic->of_data->conf_conv_count,
593			       sizeof(*dt_val), GFP_KERNEL);
594	if (!dt_val)
595		return -ENOMEM;
596
597	memset(dt_val, MIIC_MODCTRL_CONF_NONE, sizeof(*dt_val));
598
599	if (of_property_read_u32(np, "renesas,miic-switch-portin", &conf) == 0)
600		dt_val[0] = conf;
601
602	for_each_available_child_of_node(np, conv) {
603		if (of_property_read_u32(conv, "reg", &port))
604			continue;
605
606		/* Adjust for 0 based index */
607		port += !miic->of_data->miic_port_start;
608		if (of_property_read_u32(conv, "renesas,miic-input", &conf) == 0)
609			dt_val[port] = conf;
610	}
611
612	ret = miic_match_dt_conf(miic, dt_val, mode_cfg);
613	kfree(dt_val);
614
615	return ret;
616}
617
618static void miic_reset_control_bulk_assert(void *data)
619{
620	struct miic *miic = data;
621	int ret;
622
623	ret = reset_control_bulk_assert(miic->of_data->reset_count, miic->rsts);
624	if (ret)
625		dev_err(miic->dev, "failed to assert reset lines\n");
626}
627
628static int miic_reset_control_init(struct miic *miic)
629{
630	const struct miic_of_data *of_data = miic->of_data;
631	struct device *dev = miic->dev;
632	int ret;
633	u8 i;
634
635	if (!of_data->reset_count)
636		return 0;
637
638	for (i = 0; i < of_data->reset_count; i++)
639		miic->rsts[i].id = of_data->reset_ids[i];
640
641	ret = devm_reset_control_bulk_get_exclusive(dev, of_data->reset_count,
642						    miic->rsts);
643	if (ret)
644		return dev_err_probe(dev, ret,
645				     "failed to get bulk reset lines\n");
646
647	ret = reset_control_bulk_deassert(of_data->reset_count, miic->rsts);
648	if (ret)
649		return dev_err_probe(dev, ret,
650				     "failed to deassert reset lines\n");
651
652	ret = devm_add_action_or_reset(dev, miic_reset_control_bulk_assert,
653				       miic);
654	if (ret)
655		return dev_err_probe(dev, ret, "failed to add reset action\n");
656
657	return 0;
658}
659
660static int miic_probe(struct platform_device *pdev)
661{
662	struct device *dev = &pdev->dev;
663	struct miic *miic;
664	u32 mode_cfg;
665	int ret;
666
667	miic = devm_kzalloc(dev, sizeof(*miic), GFP_KERNEL);
668	if (!miic)
669		return -ENOMEM;
670
671	miic->of_data = of_device_get_match_data(dev);
672	miic->dev = dev;
673
674	ret = miic_parse_dt(miic, &mode_cfg);
675	if (ret < 0)
676		return ret;
677
678	spin_lock_init(&miic->lock);
679	miic->base = devm_platform_ioremap_resource(pdev, 0);
680	if (IS_ERR(miic->base))
681		return PTR_ERR(miic->base);
682
683	ret = miic_reset_control_init(miic);
684	if (ret)
685		return ret;
686
687	ret = devm_pm_runtime_enable(dev);
688	if (ret < 0)
689		return ret;
690
691	ret = pm_runtime_resume_and_get(dev);
692	if (ret < 0)
693		return ret;
694
695	ret = miic_init_hw(miic, mode_cfg);
696	if (ret)
697		goto disable_runtime_pm;
698
699	/* miic_create() relies on that fact that data are attached to the
700	 * platform device to determine if the driver is ready so this needs to
701	 * be the last thing to be done after everything is initialized
702	 * properly.
703	 */
704	platform_set_drvdata(pdev, miic);
705
706	return 0;
707
708disable_runtime_pm:
709	pm_runtime_put(dev);
710
711	return ret;
712}
713
714static void miic_remove(struct platform_device *pdev)
715{
716	pm_runtime_put(&pdev->dev);
717}
718
719static struct miic_of_data rzn1_miic_of_data = {
720	.match_table = modctrl_match_table,
721	.match_table_count = ARRAY_SIZE(modctrl_match_table),
722	.conf_conv_count = MIIC_MODCTRL_CONF_CONV_MAX,
723	.conf_to_string = conf_to_string,
724	.conf_to_string_count = ARRAY_SIZE(conf_to_string),
725	.index_to_string = index_to_string,
726	.index_to_string_count = ARRAY_SIZE(index_to_string),
727	.miic_port_start = 1,
728	.miic_port_max = 5,
729	.sw_mode_mask = GENMASK(4, 0),
730	.init_unlock_lock_regs = true,
731	.miic_write = miic_reg_writel_unlocked,
732};
733
734static struct miic_of_data rzt2h_miic_of_data = {
735	.match_table = rzt2h_modctrl_match_table,
736	.match_table_count = ARRAY_SIZE(rzt2h_modctrl_match_table),
737	.conf_conv_count = 5,
738	.conf_to_string = rzt2h_conf_to_string,
739	.conf_to_string_count = ARRAY_SIZE(rzt2h_conf_to_string),
740	.index_to_string = rzt2h_index_to_string,
741	.index_to_string_count = ARRAY_SIZE(rzt2h_index_to_string),
742	.miic_port_start = 0,
743	.miic_port_max = 4,
744	.sw_mode_mask = GENMASK(2, 0),
745	.reset_ids = rzt2h_reset_ids,
746	.reset_count = ARRAY_SIZE(rzt2h_reset_ids),
747	.miic_write = miic_reg_writel_locked,
748};
749
750static const struct of_device_id miic_of_mtable[] = {
751	{ .compatible = "renesas,r9a09g077-miic", .data = &rzt2h_miic_of_data },
752	{ .compatible = "renesas,rzn1-miic", .data = &rzn1_miic_of_data },
753	{ /* sentinel */ }
754};
755MODULE_DEVICE_TABLE(of, miic_of_mtable);
756
757static struct platform_driver miic_driver = {
758	.driver = {
759		.name	 = "rzn1_miic",
760		.suppress_bind_attrs = true,
761		.of_match_table = miic_of_mtable,
762	},
763	.probe = miic_probe,
764	.remove = miic_remove,
765};
766module_platform_driver(miic_driver);
767
768MODULE_LICENSE("GPL");
769MODULE_DESCRIPTION("Renesas MII converter PCS driver");
770MODULE_AUTHOR("Clément Léger <clement.leger@bootlin.com>");