mdio-realtek-rtl9300.c

  1// SPDX-License-Identifier: GPL-2.0-only
  2/*
  3 * MDIO controller for RTL9300 switches with integrated SoC.
  4 *
  5 * The MDIO communication is abstracted by the switch. At the software level
  6 * communication uses the switch port to address the PHY. We work out the
  7 * mapping based on the MDIO bus described in device tree and phandles on the
  8 * ethernet-ports property.
  9 */
 10
 11#include <linux/bitfield.h>
 12#include <linux/bitmap.h>
 13#include <linux/bits.h>
 14#include <linux/find.h>
 15#include <linux/mdio.h>
 16#include <linux/mfd/syscon.h>
 17#include <linux/mod_devicetable.h>
 18#include <linux/mutex.h>
 19#include <linux/of_mdio.h>
 20#include <linux/phy.h>
 21#include <linux/platform_device.h>
 22#include <linux/property.h>
 23#include <linux/regmap.h>
 24
 25#define SMI_GLB_CTRL			0xca00
 26#define   GLB_CTRL_INTF_SEL(intf)	BIT(16 + (intf))
 27#define SMI_PORT0_15_POLLING_SEL	0xca08
 28#define SMI_ACCESS_PHY_CTRL_0		0xcb70
 29#define SMI_ACCESS_PHY_CTRL_1		0xcb74
 30#define   PHY_CTRL_REG_ADDR		GENMASK(24, 20)
 31#define   PHY_CTRL_PARK_PAGE		GENMASK(19, 15)
 32#define   PHY_CTRL_MAIN_PAGE		GENMASK(14, 3)
 33#define   PHY_CTRL_WRITE		BIT(2)
 34#define   PHY_CTRL_READ			0
 35#define   PHY_CTRL_TYPE_C45		BIT(1)
 36#define   PHY_CTRL_TYPE_C22		0
 37#define   PHY_CTRL_CMD			BIT(0)
 38#define   PHY_CTRL_FAIL			BIT(25)
 39#define SMI_ACCESS_PHY_CTRL_2		0xcb78
 40#define   PHY_CTRL_INDATA		GENMASK(31, 16)
 41#define   PHY_CTRL_DATA			GENMASK(15, 0)
 42#define SMI_ACCESS_PHY_CTRL_3		0xcb7c
 43#define   PHY_CTRL_MMD_DEVAD		GENMASK(20, 16)
 44#define   PHY_CTRL_MMD_REG		GENMASK(15, 0)
 45#define SMI_PORT0_5_ADDR_CTRL		0xcb80
 46
 47#define MAX_PORTS       28
 48#define MAX_SMI_BUSSES  4
 49#define MAX_SMI_ADDR	0x1f
 50
 51struct rtl9300_mdio_priv {
 52	struct regmap *regmap;
 53	struct mutex lock; /* protect HW access */
 54	DECLARE_BITMAP(valid_ports, MAX_PORTS);
 55	u8 smi_bus[MAX_PORTS];
 56	u8 smi_addr[MAX_PORTS];
 57	bool smi_bus_is_c45[MAX_SMI_BUSSES];
 58	struct mii_bus *bus[MAX_SMI_BUSSES];
 59};
 60
 61struct rtl9300_mdio_chan {
 62	struct rtl9300_mdio_priv *priv;
 63	u8 mdio_bus;
 64};
 65
 66static int rtl9300_mdio_phy_to_port(struct mii_bus *bus, int phy_id)
 67{
 68	struct rtl9300_mdio_chan *chan = bus->priv;
 69	struct rtl9300_mdio_priv *priv;
 70	int i;
 71
 72	priv = chan->priv;
 73
 74	for_each_set_bit(i, priv->valid_ports, MAX_PORTS)
 75		if (priv->smi_bus[i] == chan->mdio_bus &&
 76		    priv->smi_addr[i] == phy_id)
 77			return i;
 78
 79	return -ENOENT;
 80}
 81
 82static int rtl9300_mdio_wait_ready(struct rtl9300_mdio_priv *priv)
 83{
 84	struct regmap *regmap = priv->regmap;
 85	u32 val;
 86
 87	lockdep_assert_held(&priv->lock);
 88
 89	return regmap_read_poll_timeout(regmap, SMI_ACCESS_PHY_CTRL_1,
 90					val, !(val & PHY_CTRL_CMD), 10, 1000);
 91}
 92
 93static int rtl9300_mdio_read_c22(struct mii_bus *bus, int phy_id, int regnum)
 94{
 95	struct rtl9300_mdio_chan *chan = bus->priv;
 96	struct rtl9300_mdio_priv *priv;
 97	struct regmap *regmap;
 98	int port;
 99	u32 val;
100	int err;
101
102	priv = chan->priv;
103	regmap = priv->regmap;
104
105	port = rtl9300_mdio_phy_to_port(bus, phy_id);
106	if (port < 0)
107		return port;
108
109	mutex_lock(&priv->lock);
110	err = rtl9300_mdio_wait_ready(priv);
111	if (err)
112		goto out_err;
113
114	err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_2, FIELD_PREP(PHY_CTRL_INDATA, port));
115	if (err)
116		goto out_err;
117
118	val = FIELD_PREP(PHY_CTRL_REG_ADDR, regnum) |
119	      FIELD_PREP(PHY_CTRL_PARK_PAGE, 0x1f) |
120	      FIELD_PREP(PHY_CTRL_MAIN_PAGE, 0xfff) |
121	      PHY_CTRL_READ | PHY_CTRL_TYPE_C22 | PHY_CTRL_CMD;
122	err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_1, val);
123	if (err)
124		goto out_err;
125
126	err = rtl9300_mdio_wait_ready(priv);
127	if (err)
128		goto out_err;
129
130	err = regmap_read(regmap, SMI_ACCESS_PHY_CTRL_2, &val);
131	if (err)
132		goto out_err;
133
134	mutex_unlock(&priv->lock);
135	return FIELD_GET(PHY_CTRL_DATA, val);
136
137out_err:
138	mutex_unlock(&priv->lock);
139	return err;
140}
141
142static int rtl9300_mdio_write_c22(struct mii_bus *bus, int phy_id, int regnum, u16 value)
143{
144	struct rtl9300_mdio_chan *chan = bus->priv;
145	struct rtl9300_mdio_priv *priv;
146	struct regmap *regmap;
147	int port;
148	u32 val;
149	int err;
150
151	priv = chan->priv;
152	regmap = priv->regmap;
153
154	port = rtl9300_mdio_phy_to_port(bus, phy_id);
155	if (port < 0)
156		return port;
157
158	mutex_lock(&priv->lock);
159	err = rtl9300_mdio_wait_ready(priv);
160	if (err)
161		goto out_err;
162
163	err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_0, BIT(port));
164	if (err)
165		goto out_err;
166
167	err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_2, FIELD_PREP(PHY_CTRL_INDATA, value));
168	if (err)
169		goto out_err;
170
171	val = FIELD_PREP(PHY_CTRL_REG_ADDR, regnum) |
172	      FIELD_PREP(PHY_CTRL_PARK_PAGE, 0x1f) |
173	      FIELD_PREP(PHY_CTRL_MAIN_PAGE, 0xfff) |
174	      PHY_CTRL_WRITE | PHY_CTRL_TYPE_C22 | PHY_CTRL_CMD;
175	err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_1, val);
176	if (err)
177		goto out_err;
178
179	err = regmap_read_poll_timeout(regmap, SMI_ACCESS_PHY_CTRL_1,
180				       val, !(val & PHY_CTRL_CMD), 10, 100);
181	if (err)
182		goto out_err;
183
184	if (val & PHY_CTRL_FAIL) {
185		err = -ENXIO;
186		goto out_err;
187	}
188
189	mutex_unlock(&priv->lock);
190	return 0;
191
192out_err:
193	mutex_unlock(&priv->lock);
194	return err;
195}
196
197static int rtl9300_mdio_read_c45(struct mii_bus *bus, int phy_id, int dev_addr, int regnum)
198{
199	struct rtl9300_mdio_chan *chan = bus->priv;
200	struct rtl9300_mdio_priv *priv;
201	struct regmap *regmap;
202	int port;
203	u32 val;
204	int err;
205
206	priv = chan->priv;
207	regmap = priv->regmap;
208
209	port = rtl9300_mdio_phy_to_port(bus, phy_id);
210	if (port < 0)
211		return port;
212
213	mutex_lock(&priv->lock);
214	err = rtl9300_mdio_wait_ready(priv);
215	if (err)
216		goto out_err;
217
218	val = FIELD_PREP(PHY_CTRL_INDATA, port);
219	err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_2, val);
220	if (err)
221		goto out_err;
222
223	val = FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) |
224	      FIELD_PREP(PHY_CTRL_MMD_REG, regnum);
225	err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_3, val);
226	if (err)
227		goto out_err;
228
229	err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_1,
230			   PHY_CTRL_READ | PHY_CTRL_TYPE_C45 | PHY_CTRL_CMD);
231	if (err)
232		goto out_err;
233
234	err = rtl9300_mdio_wait_ready(priv);
235	if (err)
236		goto out_err;
237
238	err = regmap_read(regmap, SMI_ACCESS_PHY_CTRL_2, &val);
239	if (err)
240		goto out_err;
241
242	mutex_unlock(&priv->lock);
243	return FIELD_GET(PHY_CTRL_DATA, val);
244
245out_err:
246	mutex_unlock(&priv->lock);
247	return err;
248}
249
250static int rtl9300_mdio_write_c45(struct mii_bus *bus, int phy_id, int dev_addr,
251				  int regnum, u16 value)
252{
253	struct rtl9300_mdio_chan *chan = bus->priv;
254	struct rtl9300_mdio_priv *priv;
255	struct regmap *regmap;
256	int port;
257	u32 val;
258	int err;
259
260	priv = chan->priv;
261	regmap = priv->regmap;
262
263	port = rtl9300_mdio_phy_to_port(bus, phy_id);
264	if (port < 0)
265		return port;
266
267	mutex_lock(&priv->lock);
268	err = rtl9300_mdio_wait_ready(priv);
269	if (err)
270		goto out_err;
271
272	err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_0, BIT(port));
273	if (err)
274		goto out_err;
275
276	val = FIELD_PREP(PHY_CTRL_INDATA, value);
277	err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_2, val);
278	if (err)
279		goto out_err;
280
281	val = FIELD_PREP(PHY_CTRL_MMD_DEVAD, dev_addr) |
282	      FIELD_PREP(PHY_CTRL_MMD_REG, regnum);
283	err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_3, val);
284	if (err)
285		goto out_err;
286
287	err = regmap_write(regmap, SMI_ACCESS_PHY_CTRL_1,
288			   PHY_CTRL_TYPE_C45 | PHY_CTRL_WRITE | PHY_CTRL_CMD);
289	if (err)
290		goto out_err;
291
292	err = regmap_read_poll_timeout(regmap, SMI_ACCESS_PHY_CTRL_1,
293				       val, !(val & PHY_CTRL_CMD), 10, 100);
294	if (err)
295		goto out_err;
296
297	if (val & PHY_CTRL_FAIL) {
298		err = -ENXIO;
299		goto out_err;
300	}
301
302	mutex_unlock(&priv->lock);
303	return 0;
304
305out_err:
306	mutex_unlock(&priv->lock);
307	return err;
308}
309
310static int rtl9300_mdiobus_init(struct rtl9300_mdio_priv *priv)
311{
312	u32 glb_ctrl_mask = 0, glb_ctrl_val = 0;
313	struct regmap *regmap = priv->regmap;
314	u32 port_addr[5] = { 0 };
315	u32 poll_sel[2] = { 0 };
316	int i, err;
317
318	/* Associate the port with the SMI interface and PHY */
319	for_each_set_bit(i, priv->valid_ports, MAX_PORTS) {
320		int pos;
321
322		pos = (i % 6) * 5;
323		port_addr[i / 6] |= (priv->smi_addr[i] & 0x1f) << pos;
324
325		pos = (i % 16) * 2;
326		poll_sel[i / 16] |= (priv->smi_bus[i] & 0x3) << pos;
327	}
328
329	/* Put the interfaces into C45 mode if required */
330	glb_ctrl_mask = GENMASK(19, 16);
331	for (i = 0; i < MAX_SMI_BUSSES; i++)
332		if (priv->smi_bus_is_c45[i])
333			glb_ctrl_val |= GLB_CTRL_INTF_SEL(i);
334
335	err = regmap_bulk_write(regmap, SMI_PORT0_5_ADDR_CTRL,
336				port_addr, 5);
337	if (err)
338		return err;
339
340	err = regmap_bulk_write(regmap, SMI_PORT0_15_POLLING_SEL,
341				poll_sel, 2);
342	if (err)
343		return err;
344
345	err = regmap_update_bits(regmap, SMI_GLB_CTRL,
346				 glb_ctrl_mask, glb_ctrl_val);
347	if (err)
348		return err;
349
350	return 0;
351}
352
353static int rtl9300_mdiobus_probe_one(struct device *dev, struct rtl9300_mdio_priv *priv,
354				     struct fwnode_handle *node)
355{
356	struct rtl9300_mdio_chan *chan;
357	struct mii_bus *bus;
358	u32 mdio_bus;
359	int err;
360
361	err = fwnode_property_read_u32(node, "reg", &mdio_bus);
362	if (err)
363		return err;
364
365	/* The MDIO accesses from the kernel work with the PHY polling unit in
366	 * the switch. We need to tell the PPU to operate either in GPHY (i.e.
367	 * clause 22) or 10GPHY mode (i.e. clause 45).
368	 *
369	 * We select 10GPHY mode if there is at least one PHY that declares
370	 * compatible = "ethernet-phy-ieee802.3-c45". This does mean we can't
371	 * support both c45 and c22 on the same MDIO bus.
372	 */
373	fwnode_for_each_child_node_scoped(node, child)
374		if (fwnode_device_is_compatible(child, "ethernet-phy-ieee802.3-c45"))
375			priv->smi_bus_is_c45[mdio_bus] = true;
376
377	bus = devm_mdiobus_alloc_size(dev, sizeof(*chan));
378	if (!bus)
379		return -ENOMEM;
380
381	bus->name = "Realtek Switch MDIO Bus";
382	if (priv->smi_bus_is_c45[mdio_bus]) {
383		bus->read_c45 = rtl9300_mdio_read_c45;
384		bus->write_c45 =  rtl9300_mdio_write_c45;
385	} else {
386		bus->read = rtl9300_mdio_read_c22;
387		bus->write = rtl9300_mdio_write_c22;
388	}
389	bus->parent = dev;
390	chan = bus->priv;
391	chan->mdio_bus = mdio_bus;
392	chan->priv = priv;
393
394	snprintf(bus->id, MII_BUS_ID_SIZE, "%s-%d", dev_name(dev), mdio_bus);
395
396	err = devm_of_mdiobus_register(dev, bus, to_of_node(node));
397	if (err)
398		return dev_err_probe(dev, err, "cannot register MDIO bus\n");
399
400	return 0;
401}
402
403/* The mdio-controller is part of a switch block so we parse the sibling
404 * ethernet-ports node and build a mapping of the switch port to MDIO bus/addr
405 * based on the phy-handle.
406 */
407static int rtl9300_mdiobus_map_ports(struct device *dev)
408{
409	struct rtl9300_mdio_priv *priv = dev_get_drvdata(dev);
410	struct device *parent = dev->parent;
411	int err;
412
413	struct fwnode_handle *ports __free(fwnode_handle) =
414		device_get_named_child_node(parent, "ethernet-ports");
415	if (!ports)
416		return dev_err_probe(dev, -EINVAL, "%pfwP missing ethernet-ports\n",
417				     dev_fwnode(parent));
418
419	fwnode_for_each_child_node_scoped(ports, port) {
420		struct device_node *mdio_dn;
421		u32 addr;
422		u32 bus;
423		u32 pn;
424
425		struct device_node *phy_dn __free(device_node) =
426			of_parse_phandle(to_of_node(port), "phy-handle", 0);
427		/* skip ports without phys */
428		if (!phy_dn)
429			continue;
430
431		mdio_dn = phy_dn->parent;
432		/* only map ports that are connected to this mdio-controller */
433		if (mdio_dn->parent != dev->of_node)
434			continue;
435
436		err = fwnode_property_read_u32(port, "reg", &pn);
437		if (err)
438			return err;
439
440		if (pn >= MAX_PORTS)
441			return dev_err_probe(dev, -EINVAL, "illegal port number %d\n", pn);
442
443		if (test_bit(pn, priv->valid_ports))
444			return dev_err_probe(dev, -EINVAL, "duplicated port number %d\n", pn);
445
446		err = of_property_read_u32(mdio_dn, "reg", &bus);
447		if (err)
448			return err;
449
450		if (bus >= MAX_SMI_BUSSES)
451			return dev_err_probe(dev, -EINVAL, "illegal smi bus number %d\n", bus);
452
453		err = of_property_read_u32(phy_dn, "reg", &addr);
454		if (err)
455			return err;
456
457		__set_bit(pn, priv->valid_ports);
458		priv->smi_bus[pn] = bus;
459		priv->smi_addr[pn] = addr;
460	}
461
462	return 0;
463}
464
465static int rtl9300_mdiobus_probe(struct platform_device *pdev)
466{
467	struct device *dev = &pdev->dev;
468	struct rtl9300_mdio_priv *priv;
469	int err;
470
471	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
472	if (!priv)
473		return -ENOMEM;
474
475	err = devm_mutex_init(dev, &priv->lock);
476	if (err)
477		return err;
478
479	priv->regmap = syscon_node_to_regmap(dev->parent->of_node);
480	if (IS_ERR(priv->regmap))
481		return PTR_ERR(priv->regmap);
482
483	platform_set_drvdata(pdev, priv);
484
485	err = rtl9300_mdiobus_map_ports(dev);
486	if (err)
487		return err;
488
489	device_for_each_child_node_scoped(dev, child) {
490		err = rtl9300_mdiobus_probe_one(dev, priv, child);
491		if (err)
492			return err;
493	}
494
495	err = rtl9300_mdiobus_init(priv);
496	if (err)
497		return dev_err_probe(dev, err, "failed to initialise MDIO bus controller\n");
498
499	return 0;
500}
501
502static const struct of_device_id rtl9300_mdio_ids[] = {
503	{ .compatible = "realtek,rtl9301-mdio" },
504	{}
505};
506MODULE_DEVICE_TABLE(of, rtl9300_mdio_ids);
507
508static struct platform_driver rtl9300_mdio_driver = {
509	.probe = rtl9300_mdiobus_probe,
510	.driver = {
511		.name = "mdio-rtl9300",
512		.of_match_table = rtl9300_mdio_ids,
513	},
514};
515
516module_platform_driver(rtl9300_mdio_driver);
517
518MODULE_DESCRIPTION("RTL9300 MDIO driver");
519MODULE_LICENSE("GPL");