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ipa_reg-v4.7.c
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linux-6.19.14/drivers/net/ipa/reg/ipa_reg-v4.7.c
1// SPDX-License-Identifier: GPL-2.0 2 3/* Copyright (C) 2022-2024 Linaro Ltd. */ 4 5#include <linux/array_size.h> 6#include <linux/bits.h> 7#include <linux/types.h> 8 9#include "../ipa_reg.h" 10#include "../ipa_version.h" 11 12static const u32 reg_comp_cfg_fmask[] = { 13 [RAM_ARB_PRI_CLIENT_SAMP_FIX_DIS] = BIT(0), 14 [GSI_SNOC_BYPASS_DIS] = BIT(1), 15 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), 16 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3), 17 /* Bit 4 reserved */ 18 [IPA_QMB_SELECT_CONS_EN] = BIT(5), 19 [IPA_QMB_SELECT_PROD_EN] = BIT(6), 20 [GSI_MULTI_INORDER_RD_DIS] = BIT(7), 21 [GSI_MULTI_INORDER_WR_DIS] = BIT(8), 22 [GEN_QMB_0_MULTI_INORDER_RD_DIS] = BIT(9), 23 [GEN_QMB_1_MULTI_INORDER_RD_DIS] = BIT(10), 24 [GEN_QMB_0_MULTI_INORDER_WR_DIS] = BIT(11), 25 [GEN_QMB_1_MULTI_INORDER_WR_DIS] = BIT(12), 26 [GEN_QMB_0_SNOC_CNOC_LOOP_PROT_DIS] = BIT(13), 27 [GSI_SNOC_CNOC_LOOP_PROT_DISABLE] = BIT(14), 28 [GSI_MULTI_AXI_MASTERS_DIS] = BIT(15), 29 [IPA_QMB_SELECT_GLOBAL_EN] = BIT(16), 30 [ATOMIC_FETCHER_ARB_LOCK_DIS] = GENMASK(20, 17), 31 [FULL_FLUSH_WAIT_RS_CLOSURE_EN] = BIT(21), 32 /* Bits 22-31 reserved */ 33}; 34 35REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); 36 37static const u32 reg_clkon_cfg_fmask[] = { 38 [CLKON_RX] = BIT(0), 39 [CLKON_PROC] = BIT(1), 40 [TX_WRAPPER] = BIT(2), 41 [CLKON_MISC] = BIT(3), 42 [RAM_ARB] = BIT(4), 43 [FTCH_HPS] = BIT(5), 44 [FTCH_DPS] = BIT(6), 45 [CLKON_HPS] = BIT(7), 46 [CLKON_DPS] = BIT(8), 47 [RX_HPS_CMDQS] = BIT(9), 48 [HPS_DPS_CMDQS] = BIT(10), 49 [DPS_TX_CMDQS] = BIT(11), 50 [RSRC_MNGR] = BIT(12), 51 [CTX_HANDLER] = BIT(13), 52 [ACK_MNGR] = BIT(14), 53 [D_DCPH] = BIT(15), 54 [H_DCPH] = BIT(16), 55 [CLKON_DCMP] = BIT(17), 56 [NTF_TX_CMDQS] = BIT(18), 57 [CLKON_TX_0] = BIT(19), 58 [CLKON_TX_1] = BIT(20), 59 [CLKON_FNR] = BIT(21), 60 [QSB2AXI_CMDQ_L] = BIT(22), 61 [AGGR_WRAPPER] = BIT(23), 62 [RAM_SLAVEWAY] = BIT(24), 63 [CLKON_QMB] = BIT(25), 64 [WEIGHT_ARB] = BIT(26), 65 [GSI_IF] = BIT(27), 66 [CLKON_GLOBAL] = BIT(28), 67 [GLOBAL_2X_CLK] = BIT(29), 68 [DPL_FIFO] = BIT(30), 69 [DRBIP] = BIT(31), 70}; 71 72REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); 73 74static const u32 reg_route_fmask[] = { 75 [ROUTE_DIS] = BIT(0), 76 [ROUTE_DEF_PIPE] = GENMASK(5, 1), 77 [ROUTE_DEF_HDR_TABLE] = BIT(6), 78 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7), 79 [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17), 80 /* Bits 22-23 reserved */ 81 [ROUTE_DEF_RETAIN_HDR] = BIT(24), 82 /* Bits 25-31 reserved */ 83}; 84 85REG_FIELDS(ROUTE, route, 0x00000048); 86 87static const u32 reg_shared_mem_size_fmask[] = { 88 [MEM_SIZE] = GENMASK(15, 0), 89 [MEM_BADDR] = GENMASK(31, 16), 90}; 91 92REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); 93 94static const u32 reg_qsb_max_writes_fmask[] = { 95 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), 96 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), 97 /* Bits 8-31 reserved */ 98}; 99 100REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); 101 102static const u32 reg_qsb_max_reads_fmask[] = { 103 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), 104 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), 105 /* Bits 8-15 reserved */ 106 [GEN_QMB_0_MAX_READS_BEATS] = GENMASK(23, 16), 107 [GEN_QMB_1_MAX_READS_BEATS] = GENMASK(31, 24), 108}; 109 110REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); 111 112static const u32 reg_filt_rout_hash_flush_fmask[] = { 113 [IPV6_ROUTER_HASH] = BIT(0), 114 /* Bits 1-3 reserved */ 115 [IPV6_FILTER_HASH] = BIT(4), 116 /* Bits 5-7 reserved */ 117 [IPV4_ROUTER_HASH] = BIT(8), 118 /* Bits 9-11 reserved */ 119 [IPV4_FILTER_HASH] = BIT(12), 120 /* Bits 13-31 reserved */ 121}; 122 123REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x000014c); 124 125/* Valid bits defined by ipa->available */ 126REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x000000b4, 0x0004); 127 128static const u32 reg_local_pkt_proc_cntxt_fmask[] = { 129 [IPA_BASE_ADDR] = GENMASK(17, 0), 130 /* Bits 18-31 reserved */ 131}; 132 133/* Offset must be a multiple of 8 */ 134REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); 135 136/* Valid bits defined by ipa->available */ 137REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004); 138 139static const u32 reg_ipa_tx_cfg_fmask[] = { 140 /* Bits 0-1 reserved */ 141 [PREFETCH_ALMOST_EMPTY_SIZE_TX0] = GENMASK(5, 2), 142 [DMAW_SCND_OUTSD_PRED_THRESHOLD] = GENMASK(9, 6), 143 [DMAW_SCND_OUTSD_PRED_EN] = BIT(10), 144 [DMAW_MAX_BEATS_256_DIS] = BIT(11), 145 [PA_MASK_EN] = BIT(12), 146 [PREFETCH_ALMOST_EMPTY_SIZE_TX1] = GENMASK(16, 13), 147 [DUAL_TX_ENABLE] = BIT(17), 148 [SSPND_PA_NO_START_STATE] = BIT(18), 149 /* Bits 19-31 reserved */ 150}; 151 152REG_FIELDS(IPA_TX_CFG, ipa_tx_cfg, 0x000001fc); 153 154static const u32 reg_flavor_0_fmask[] = { 155 [MAX_PIPES] = GENMASK(3, 0), 156 /* Bits 4-7 reserved */ 157 [MAX_CONS_PIPES] = GENMASK(12, 8), 158 /* Bits 13-15 reserved */ 159 [MAX_PROD_PIPES] = GENMASK(20, 16), 160 /* Bits 21-23 reserved */ 161 [PROD_LOWEST] = GENMASK(27, 24), 162 /* Bits 28-31 reserved */ 163}; 164 165REG_FIELDS(FLAVOR_0, flavor_0, 0x00000210); 166 167static const u32 reg_idle_indication_cfg_fmask[] = { 168 [ENTER_IDLE_DEBOUNCE_THRESH] = GENMASK(15, 0), 169 [CONST_NON_IDLE_ENABLE] = BIT(16), 170 /* Bits 17-31 reserved */ 171}; 172 173REG_FIELDS(IDLE_INDICATION_CFG, idle_indication_cfg, 0x00000240); 174 175static const u32 reg_qtime_timestamp_cfg_fmask[] = { 176 [DPL_TIMESTAMP_LSB] = GENMASK(4, 0), 177 /* Bits 5-6 reserved */ 178 [DPL_TIMESTAMP_SEL] = BIT(7), 179 [TAG_TIMESTAMP_LSB] = GENMASK(12, 8), 180 /* Bits 13-15 reserved */ 181 [NAT_TIMESTAMP_LSB] = GENMASK(20, 16), 182 /* Bits 21-31 reserved */ 183}; 184 185REG_FIELDS(QTIME_TIMESTAMP_CFG, qtime_timestamp_cfg, 0x0000024c); 186 187static const u32 reg_timers_xo_clk_div_cfg_fmask[] = { 188 [DIV_VALUE] = GENMASK(8, 0), 189 /* Bits 9-30 reserved */ 190 [DIV_ENABLE] = BIT(31), 191}; 192 193REG_FIELDS(TIMERS_XO_CLK_DIV_CFG, timers_xo_clk_div_cfg, 0x00000250); 194 195static const u32 reg_timers_pulse_gran_cfg_fmask[] = { 196 [PULSE_GRAN_0] = GENMASK(2, 0), 197 [PULSE_GRAN_1] = GENMASK(5, 3), 198 [PULSE_GRAN_2] = GENMASK(8, 6), 199}; 200 201REG_FIELDS(TIMERS_PULSE_GRAN_CFG, timers_pulse_gran_cfg, 0x00000254); 202 203static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = { 204 [X_MIN_LIM] = GENMASK(5, 0), 205 /* Bits 6-7 reserved */ 206 [X_MAX_LIM] = GENMASK(13, 8), 207 /* Bits 14-15 reserved */ 208 [Y_MIN_LIM] = GENMASK(21, 16), 209 /* Bits 22-23 reserved */ 210 [Y_MAX_LIM] = GENMASK(29, 24), 211 /* Bits 30-31 reserved */ 212}; 213 214REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, 215 0x00000400, 0x0020); 216 217static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = { 218 [X_MIN_LIM] = GENMASK(5, 0), 219 /* Bits 6-7 reserved */ 220 [X_MAX_LIM] = GENMASK(13, 8), 221 /* Bits 14-15 reserved */ 222 [Y_MIN_LIM] = GENMASK(21, 16), 223 /* Bits 22-23 reserved */ 224 [Y_MAX_LIM] = GENMASK(29, 24), 225 /* Bits 30-31 reserved */ 226}; 227 228REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, 229 0x00000404, 0x0020); 230 231static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { 232 [X_MIN_LIM] = GENMASK(5, 0), 233 /* Bits 6-7 reserved */ 234 [X_MAX_LIM] = GENMASK(13, 8), 235 /* Bits 14-15 reserved */ 236 [Y_MIN_LIM] = GENMASK(21, 16), 237 /* Bits 22-23 reserved */ 238 [Y_MAX_LIM] = GENMASK(29, 24), 239 /* Bits 30-31 reserved */ 240}; 241 242REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, 243 0x00000500, 0x0020); 244 245static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { 246 [X_MIN_LIM] = GENMASK(5, 0), 247 /* Bits 6-7 reserved */ 248 [X_MAX_LIM] = GENMASK(13, 8), 249 /* Bits 14-15 reserved */ 250 [Y_MIN_LIM] = GENMASK(21, 16), 251 /* Bits 22-23 reserved */ 252 [Y_MAX_LIM] = GENMASK(29, 24), 253 /* Bits 30-31 reserved */ 254}; 255 256REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, 257 0x00000504, 0x0020); 258 259static const u32 reg_endp_init_cfg_fmask[] = { 260 [FRAG_OFFLOAD_EN] = BIT(0), 261 [CS_OFFLOAD_EN] = GENMASK(2, 1), 262 [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), 263 /* Bit 7 reserved */ 264 [CS_GEN_QMB_MASTER_SEL] = BIT(8), 265 /* Bits 9-31 reserved */ 266}; 267 268REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); 269 270static const u32 reg_endp_init_nat_fmask[] = { 271 [NAT_EN] = GENMASK(1, 0), 272 /* Bits 2-31 reserved */ 273}; 274 275REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); 276 277static const u32 reg_endp_init_hdr_fmask[] = { 278 [HDR_LEN] = GENMASK(5, 0), 279 [HDR_OFST_METADATA_VALID] = BIT(6), 280 [HDR_OFST_METADATA] = GENMASK(12, 7), 281 [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13), 282 [HDR_OFST_PKT_SIZE_VALID] = BIT(19), 283 [HDR_OFST_PKT_SIZE] = GENMASK(25, 20), 284 [HDR_A5_MUX] = BIT(26), 285 [HDR_LEN_INC_DEAGG_HDR] = BIT(27), 286 [HDR_LEN_MSB] = GENMASK(29, 28), 287 [HDR_OFST_METADATA_MSB] = GENMASK(31, 30), 288}; 289 290REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); 291 292static const u32 reg_endp_init_hdr_ext_fmask[] = { 293 [HDR_ENDIANNESS] = BIT(0), 294 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), 295 [HDR_TOTAL_LEN_OR_PAD] = BIT(2), 296 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3), 297 [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4), 298 [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10), 299 /* Bits 14-15 reserved */ 300 [HDR_TOTAL_LEN_OR_PAD_OFFSET_MSB] = GENMASK(17, 16), 301 [HDR_OFST_PKT_SIZE_MSB] = GENMASK(19, 18), 302 [HDR_ADDITIONAL_CONST_LEN_MSB] = GENMASK(21, 20), 303 /* Bits 22-31 reserved */ 304}; 305 306REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); 307 308REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, 309 0x00000818, 0x0070); 310 311static const u32 reg_endp_init_mode_fmask[] = { 312 [ENDP_MODE] = GENMASK(2, 0), 313 [DCPH_ENABLE] = BIT(3), 314 [DEST_PIPE_INDEX] = GENMASK(8, 4), 315 /* Bits 9-11 reserved */ 316 [BYTE_THRESHOLD] = GENMASK(27, 12), 317 [PIPE_REPLICATION_EN] = BIT(28), 318 [PAD_EN] = BIT(29), 319 /* Bits 30-31 reserved */ 320}; 321 322REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); 323 324static const u32 reg_endp_init_aggr_fmask[] = { 325 [AGGR_EN] = GENMASK(1, 0), 326 [AGGR_TYPE] = GENMASK(4, 2), 327 [BYTE_LIMIT] = GENMASK(10, 5), 328 /* Bit 11 reserved */ 329 [TIME_LIMIT] = GENMASK(16, 12), 330 [PKT_LIMIT] = GENMASK(22, 17), 331 [SW_EOF_ACTIVE] = BIT(23), 332 [FORCE_CLOSE] = BIT(24), 333 /* Bit 25 reserved */ 334 [HARD_BYTE_LIMIT_EN] = BIT(26), 335 [AGGR_GRAN_SEL] = BIT(27), 336 /* Bits 28-31 reserved */ 337}; 338 339REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); 340 341static const u32 reg_endp_init_hol_block_en_fmask[] = { 342 [HOL_BLOCK_EN] = BIT(0), 343 /* Bits 1-31 reserved */ 344}; 345 346REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, 347 0x0000082c, 0x0070); 348 349static const u32 reg_endp_init_hol_block_timer_fmask[] = { 350 [TIMER_LIMIT] = GENMASK(4, 0), 351 /* Bits 5-7 reserved */ 352 [TIMER_GRAN_SEL] = BIT(8), 353 /* Bits 9-31 reserved */ 354}; 355 356REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, 357 0x00000830, 0x0070); 358 359static const u32 reg_endp_init_deaggr_fmask[] = { 360 [DEAGGR_HDR_LEN] = GENMASK(5, 0), 361 [SYSPIPE_ERR_DETECTION] = BIT(6), 362 [PACKET_OFFSET_VALID] = BIT(7), 363 [PACKET_OFFSET_LOCATION] = GENMASK(13, 8), 364 [IGNORE_MIN_PKT_ERR] = BIT(14), 365 /* Bit 15 reserved */ 366 [MAX_PACKET_LEN] = GENMASK(31, 16), 367}; 368 369REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); 370 371static const u32 reg_endp_init_rsrc_grp_fmask[] = { 372 [ENDP_RSRC_GRP] = BIT(0), 373 /* Bits 1-31 reserved */ 374}; 375 376REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070); 377 378static const u32 reg_endp_init_seq_fmask[] = { 379 [SEQ_TYPE] = GENMASK(7, 0), 380 /* Bits 8-31 reserved */ 381}; 382 383REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); 384 385static const u32 reg_endp_status_fmask[] = { 386 [STATUS_EN] = BIT(0), 387 [STATUS_ENDP] = GENMASK(5, 1), 388 /* Bits 6-8 reserved */ 389 [STATUS_PKT_SUPPRESS] = BIT(9), 390 /* Bits 10-31 reserved */ 391}; 392 393REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); 394 395static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = { 396 [FILTER_HASH_MSK_SRC_ID] = BIT(0), 397 [FILTER_HASH_MSK_SRC_IP] = BIT(1), 398 [FILTER_HASH_MSK_DST_IP] = BIT(2), 399 [FILTER_HASH_MSK_SRC_PORT] = BIT(3), 400 [FILTER_HASH_MSK_DST_PORT] = BIT(4), 401 [FILTER_HASH_MSK_PROTOCOL] = BIT(5), 402 [FILTER_HASH_MSK_METADATA] = BIT(6), 403 [FILTER_HASH_MSK_ALL] = GENMASK(6, 0), 404 /* Bits 7-15 reserved */ 405 [ROUTER_HASH_MSK_SRC_ID] = BIT(16), 406 [ROUTER_HASH_MSK_SRC_IP] = BIT(17), 407 [ROUTER_HASH_MSK_DST_IP] = BIT(18), 408 [ROUTER_HASH_MSK_SRC_PORT] = BIT(19), 409 [ROUTER_HASH_MSK_DST_PORT] = BIT(20), 410 [ROUTER_HASH_MSK_PROTOCOL] = BIT(21), 411 [ROUTER_HASH_MSK_METADATA] = BIT(22), 412 [ROUTER_HASH_MSK_ALL] = GENMASK(22, 16), 413 /* Bits 23-31 reserved */ 414}; 415 416REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, 417 0x0000085c, 0x0070); 418 419/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 420REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP); 421 422/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 423REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP); 424 425/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 426REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP); 427 428static const u32 reg_ipa_irq_uc_fmask[] = { 429 [UC_INTR] = BIT(0), 430 /* Bits 1-31 reserved */ 431}; 432 433REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP); 434 435/* Valid bits defined by ipa->available */ 436REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info, 437 0x00003030 + 0x1000 * GSI_EE_AP, 0x0004); 438 439/* Valid bits defined by ipa->available */ 440REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en, 441 0x00003034 + 0x1000 * GSI_EE_AP, 0x0004); 442 443/* Valid bits defined by ipa->available */ 444REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr, 445 0x00003038 + 0x1000 * GSI_EE_AP, 0x0004); 446 447static const struct reg *reg_array[] = { 448 [COMP_CFG] = ®_comp_cfg, 449 [CLKON_CFG] = ®_clkon_cfg, 450 [ROUTE] = ®_route, 451 [SHARED_MEM_SIZE] = ®_shared_mem_size, 452 [QSB_MAX_WRITES] = ®_qsb_max_writes, 453 [QSB_MAX_READS] = ®_qsb_max_reads, 454 [FILT_ROUT_HASH_FLUSH] = ®_filt_rout_hash_flush, 455 [STATE_AGGR_ACTIVE] = ®_state_aggr_active, 456 [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt, 457 [AGGR_FORCE_CLOSE] = ®_aggr_force_close, 458 [IPA_TX_CFG] = ®_ipa_tx_cfg, 459 [FLAVOR_0] = ®_flavor_0, 460 [IDLE_INDICATION_CFG] = ®_idle_indication_cfg, 461 [QTIME_TIMESTAMP_CFG] = ®_qtime_timestamp_cfg, 462 [TIMERS_XO_CLK_DIV_CFG] = ®_timers_xo_clk_div_cfg, 463 [TIMERS_PULSE_GRAN_CFG] = ®_timers_pulse_gran_cfg, 464 [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type, 465 [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type, 466 [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type, 467 [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type, 468 [ENDP_INIT_CFG] = ®_endp_init_cfg, 469 [ENDP_INIT_NAT] = ®_endp_init_nat, 470 [ENDP_INIT_HDR] = ®_endp_init_hdr, 471 [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext, 472 [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask, 473 [ENDP_INIT_MODE] = ®_endp_init_mode, 474 [ENDP_INIT_AGGR] = ®_endp_init_aggr, 475 [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en, 476 [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer, 477 [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr, 478 [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp, 479 [ENDP_INIT_SEQ] = ®_endp_init_seq, 480 [ENDP_STATUS] = ®_endp_status, 481 [ENDP_FILTER_ROUTER_HSH_CFG] = ®_endp_filter_router_hsh_cfg, 482 [IPA_IRQ_STTS] = ®_ipa_irq_stts, 483 [IPA_IRQ_EN] = ®_ipa_irq_en, 484 [IPA_IRQ_CLR] = ®_ipa_irq_clr, 485 [IPA_IRQ_UC] = ®_ipa_irq_uc, 486 [IRQ_SUSPEND_INFO] = ®_irq_suspend_info, 487 [IRQ_SUSPEND_EN] = ®_irq_suspend_en, 488 [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr, 489}; 490 491const struct regs ipa_regs_v4_7 = { 492 .reg_count = ARRAY_SIZE(reg_array), 493 .reg = reg_array, 494};
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