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ipa_reg-v3.1.c
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linux-6.19.14/drivers/net/ipa/reg/ipa_reg-v3.1.c
1// SPDX-License-Identifier: GPL-2.0 2 3/* Copyright (C) 2022-2024 Linaro Ltd. */ 4 5#include <linux/array_size.h> 6#include <linux/bits.h> 7#include <linux/types.h> 8 9#include "../ipa_reg.h" 10#include "../ipa_version.h" 11 12static const u32 reg_comp_cfg_fmask[] = { 13 [COMP_CFG_ENABLE] = BIT(0), 14 [GSI_SNOC_BYPASS_DIS] = BIT(1), 15 [GEN_QMB_0_SNOC_BYPASS_DIS] = BIT(2), 16 [GEN_QMB_1_SNOC_BYPASS_DIS] = BIT(3), 17 [IPA_DCMP_FAST_CLK_EN] = BIT(4), 18 /* Bits 5-31 reserved */ 19}; 20 21REG_FIELDS(COMP_CFG, comp_cfg, 0x0000003c); 22 23static const u32 reg_clkon_cfg_fmask[] = { 24 [CLKON_RX] = BIT(0), 25 [CLKON_PROC] = BIT(1), 26 [TX_WRAPPER] = BIT(2), 27 [CLKON_MISC] = BIT(3), 28 [RAM_ARB] = BIT(4), 29 [FTCH_HPS] = BIT(5), 30 [FTCH_DPS] = BIT(6), 31 [CLKON_HPS] = BIT(7), 32 [CLKON_DPS] = BIT(8), 33 [RX_HPS_CMDQS] = BIT(9), 34 [HPS_DPS_CMDQS] = BIT(10), 35 [DPS_TX_CMDQS] = BIT(11), 36 [RSRC_MNGR] = BIT(12), 37 [CTX_HANDLER] = BIT(13), 38 [ACK_MNGR] = BIT(14), 39 [D_DCPH] = BIT(15), 40 [H_DCPH] = BIT(16), 41 /* Bits 17-31 reserved */ 42}; 43 44REG_FIELDS(CLKON_CFG, clkon_cfg, 0x00000044); 45 46static const u32 reg_route_fmask[] = { 47 [ROUTE_DIS] = BIT(0), 48 [ROUTE_DEF_PIPE] = GENMASK(5, 1), 49 [ROUTE_DEF_HDR_TABLE] = BIT(6), 50 [ROUTE_DEF_HDR_OFST] = GENMASK(16, 7), 51 [ROUTE_FRAG_DEF_PIPE] = GENMASK(21, 17), 52 /* Bits 22-23 reserved */ 53 [ROUTE_DEF_RETAIN_HDR] = BIT(24), 54 /* Bits 25-31 reserved */ 55}; 56 57REG_FIELDS(ROUTE, route, 0x00000048); 58 59static const u32 reg_shared_mem_size_fmask[] = { 60 [MEM_SIZE] = GENMASK(15, 0), 61 [MEM_BADDR] = GENMASK(31, 16), 62}; 63 64REG_FIELDS(SHARED_MEM_SIZE, shared_mem_size, 0x00000054); 65 66static const u32 reg_qsb_max_writes_fmask[] = { 67 [GEN_QMB_0_MAX_WRITES] = GENMASK(3, 0), 68 [GEN_QMB_1_MAX_WRITES] = GENMASK(7, 4), 69 /* Bits 8-31 reserved */ 70}; 71 72REG_FIELDS(QSB_MAX_WRITES, qsb_max_writes, 0x00000074); 73 74static const u32 reg_qsb_max_reads_fmask[] = { 75 [GEN_QMB_0_MAX_READS] = GENMASK(3, 0), 76 [GEN_QMB_1_MAX_READS] = GENMASK(7, 4), 77}; 78 79REG_FIELDS(QSB_MAX_READS, qsb_max_reads, 0x00000078); 80 81static const u32 reg_filt_rout_hash_flush_fmask[] = { 82 [IPV6_ROUTER_HASH] = BIT(0), 83 /* Bits 1-3 reserved */ 84 [IPV6_FILTER_HASH] = BIT(4), 85 /* Bits 5-7 reserved */ 86 [IPV4_ROUTER_HASH] = BIT(8), 87 /* Bits 9-11 reserved */ 88 [IPV4_FILTER_HASH] = BIT(12), 89 /* Bits 13-31 reserved */ 90}; 91 92REG_FIELDS(FILT_ROUT_HASH_FLUSH, filt_rout_hash_flush, 0x0000090); 93 94/* Valid bits defined by ipa->available */ 95REG_STRIDE(STATE_AGGR_ACTIVE, state_aggr_active, 0x0000010c, 0x0004); 96 97REG(IPA_BCR, ipa_bcr, 0x000001d0); 98 99static const u32 reg_local_pkt_proc_cntxt_fmask[] = { 100 [IPA_BASE_ADDR] = GENMASK(16, 0), 101 /* Bits 17-31 reserved */ 102}; 103 104/* Offset must be a multiple of 8 */ 105REG_FIELDS(LOCAL_PKT_PROC_CNTXT, local_pkt_proc_cntxt, 0x000001e8); 106 107/* Valid bits defined by ipa->available */ 108REG_STRIDE(AGGR_FORCE_CLOSE, aggr_force_close, 0x000001ec, 0x0004); 109 110static const u32 reg_counter_cfg_fmask[] = { 111 [EOT_COAL_GRANULARITY] = GENMASK(3, 0), 112 [AGGR_GRANULARITY] = GENMASK(8, 4), 113 /* Bits 5-31 reserved */ 114}; 115 116REG_FIELDS(COUNTER_CFG, counter_cfg, 0x000001f0); 117 118static const u32 reg_src_rsrc_grp_01_rsrc_type_fmask[] = { 119 [X_MIN_LIM] = GENMASK(7, 0), 120 [X_MAX_LIM] = GENMASK(15, 8), 121 [Y_MIN_LIM] = GENMASK(23, 16), 122 [Y_MAX_LIM] = GENMASK(31, 24), 123}; 124 125REG_STRIDE_FIELDS(SRC_RSRC_GRP_01_RSRC_TYPE, src_rsrc_grp_01_rsrc_type, 126 0x00000400, 0x0020); 127 128static const u32 reg_src_rsrc_grp_23_rsrc_type_fmask[] = { 129 [X_MIN_LIM] = GENMASK(7, 0), 130 [X_MAX_LIM] = GENMASK(15, 8), 131 [Y_MIN_LIM] = GENMASK(23, 16), 132 [Y_MAX_LIM] = GENMASK(31, 24), 133}; 134 135REG_STRIDE_FIELDS(SRC_RSRC_GRP_23_RSRC_TYPE, src_rsrc_grp_23_rsrc_type, 136 0x00000404, 0x0020); 137 138static const u32 reg_src_rsrc_grp_45_rsrc_type_fmask[] = { 139 [X_MIN_LIM] = GENMASK(7, 0), 140 [X_MAX_LIM] = GENMASK(15, 8), 141 [Y_MIN_LIM] = GENMASK(23, 16), 142 [Y_MAX_LIM] = GENMASK(31, 24), 143}; 144 145REG_STRIDE_FIELDS(SRC_RSRC_GRP_45_RSRC_TYPE, src_rsrc_grp_45_rsrc_type, 146 0x00000408, 0x0020); 147 148static const u32 reg_src_rsrc_grp_67_rsrc_type_fmask[] = { 149 [X_MIN_LIM] = GENMASK(7, 0), 150 [X_MAX_LIM] = GENMASK(15, 8), 151 [Y_MIN_LIM] = GENMASK(23, 16), 152 [Y_MAX_LIM] = GENMASK(31, 24), 153}; 154 155REG_STRIDE_FIELDS(SRC_RSRC_GRP_67_RSRC_TYPE, src_rsrc_grp_67_rsrc_type, 156 0x0000040c, 0x0020); 157 158static const u32 reg_dst_rsrc_grp_01_rsrc_type_fmask[] = { 159 [X_MIN_LIM] = GENMASK(7, 0), 160 [X_MAX_LIM] = GENMASK(15, 8), 161 [Y_MIN_LIM] = GENMASK(23, 16), 162 [Y_MAX_LIM] = GENMASK(31, 24), 163}; 164 165REG_STRIDE_FIELDS(DST_RSRC_GRP_01_RSRC_TYPE, dst_rsrc_grp_01_rsrc_type, 166 0x00000500, 0x0020); 167 168static const u32 reg_dst_rsrc_grp_23_rsrc_type_fmask[] = { 169 [X_MIN_LIM] = GENMASK(7, 0), 170 [X_MAX_LIM] = GENMASK(15, 8), 171 [Y_MIN_LIM] = GENMASK(23, 16), 172 [Y_MAX_LIM] = GENMASK(31, 24), 173}; 174 175REG_STRIDE_FIELDS(DST_RSRC_GRP_23_RSRC_TYPE, dst_rsrc_grp_23_rsrc_type, 176 0x00000504, 0x0020); 177 178static const u32 reg_dst_rsrc_grp_45_rsrc_type_fmask[] = { 179 [X_MIN_LIM] = GENMASK(7, 0), 180 [X_MAX_LIM] = GENMASK(15, 8), 181 [Y_MIN_LIM] = GENMASK(23, 16), 182 [Y_MAX_LIM] = GENMASK(31, 24), 183}; 184 185REG_STRIDE_FIELDS(DST_RSRC_GRP_45_RSRC_TYPE, dst_rsrc_grp_45_rsrc_type, 186 0x00000508, 0x0020); 187 188static const u32 reg_dst_rsrc_grp_67_rsrc_type_fmask[] = { 189 [X_MIN_LIM] = GENMASK(7, 0), 190 [X_MAX_LIM] = GENMASK(15, 8), 191 [Y_MIN_LIM] = GENMASK(23, 16), 192 [Y_MAX_LIM] = GENMASK(31, 24), 193}; 194 195REG_STRIDE_FIELDS(DST_RSRC_GRP_67_RSRC_TYPE, dst_rsrc_grp_67_rsrc_type, 196 0x0000050c, 0x0020); 197 198static const u32 reg_endp_init_ctrl_fmask[] = { 199 [ENDP_SUSPEND] = BIT(0), 200 [ENDP_DELAY] = BIT(1), 201 /* Bits 2-31 reserved */ 202}; 203 204REG_STRIDE_FIELDS(ENDP_INIT_CTRL, endp_init_ctrl, 0x00000800, 0x0070); 205 206static const u32 reg_endp_init_cfg_fmask[] = { 207 [FRAG_OFFLOAD_EN] = BIT(0), 208 [CS_OFFLOAD_EN] = GENMASK(2, 1), 209 [CS_METADATA_HDR_OFFSET] = GENMASK(6, 3), 210 /* Bit 7 reserved */ 211 [CS_GEN_QMB_MASTER_SEL] = BIT(8), 212 /* Bits 9-31 reserved */ 213}; 214 215REG_STRIDE_FIELDS(ENDP_INIT_CFG, endp_init_cfg, 0x00000808, 0x0070); 216 217static const u32 reg_endp_init_nat_fmask[] = { 218 [NAT_EN] = GENMASK(1, 0), 219 /* Bits 2-31 reserved */ 220}; 221 222REG_STRIDE_FIELDS(ENDP_INIT_NAT, endp_init_nat, 0x0000080c, 0x0070); 223 224static const u32 reg_endp_init_hdr_fmask[] = { 225 [HDR_LEN] = GENMASK(5, 0), 226 [HDR_OFST_METADATA_VALID] = BIT(6), 227 [HDR_OFST_METADATA] = GENMASK(12, 7), 228 [HDR_ADDITIONAL_CONST_LEN] = GENMASK(18, 13), 229 [HDR_OFST_PKT_SIZE_VALID] = BIT(19), 230 [HDR_OFST_PKT_SIZE] = GENMASK(25, 20), 231 [HDR_A5_MUX] = BIT(26), 232 [HDR_LEN_INC_DEAGG_HDR] = BIT(27), 233 [HDR_METADATA_REG_VALID] = BIT(28), 234 /* Bits 29-31 reserved */ 235}; 236 237REG_STRIDE_FIELDS(ENDP_INIT_HDR, endp_init_hdr, 0x00000810, 0x0070); 238 239static const u32 reg_endp_init_hdr_ext_fmask[] = { 240 [HDR_ENDIANNESS] = BIT(0), 241 [HDR_TOTAL_LEN_OR_PAD_VALID] = BIT(1), 242 [HDR_TOTAL_LEN_OR_PAD] = BIT(2), 243 [HDR_PAYLOAD_LEN_INC_PADDING] = BIT(3), 244 [HDR_TOTAL_LEN_OR_PAD_OFFSET] = GENMASK(9, 4), 245 [HDR_PAD_TO_ALIGNMENT] = GENMASK(13, 10), 246 /* Bits 14-31 reserved */ 247}; 248 249REG_STRIDE_FIELDS(ENDP_INIT_HDR_EXT, endp_init_hdr_ext, 0x00000814, 0x0070); 250 251REG_STRIDE(ENDP_INIT_HDR_METADATA_MASK, endp_init_hdr_metadata_mask, 252 0x00000818, 0x0070); 253 254static const u32 reg_endp_init_mode_fmask[] = { 255 [ENDP_MODE] = GENMASK(2, 0), 256 /* Bit 3 reserved */ 257 [DEST_PIPE_INDEX] = GENMASK(8, 4), 258 /* Bits 9-11 reserved */ 259 [BYTE_THRESHOLD] = GENMASK(27, 12), 260 [PIPE_REPLICATION_EN] = BIT(28), 261 [PAD_EN] = BIT(29), 262 [HDR_FTCH_DISABLE] = BIT(30), 263 /* Bit 31 reserved */ 264}; 265 266REG_STRIDE_FIELDS(ENDP_INIT_MODE, endp_init_mode, 0x00000820, 0x0070); 267 268static const u32 reg_endp_init_aggr_fmask[] = { 269 [AGGR_EN] = GENMASK(1, 0), 270 [AGGR_TYPE] = GENMASK(4, 2), 271 [BYTE_LIMIT] = GENMASK(9, 5), 272 [TIME_LIMIT] = GENMASK(14, 10), 273 [PKT_LIMIT] = GENMASK(20, 15), 274 [SW_EOF_ACTIVE] = BIT(21), 275 [FORCE_CLOSE] = BIT(22), 276 /* Bit 23 reserved */ 277 [HARD_BYTE_LIMIT_EN] = BIT(24), 278 /* Bits 25-31 reserved */ 279}; 280 281REG_STRIDE_FIELDS(ENDP_INIT_AGGR, endp_init_aggr, 0x00000824, 0x0070); 282 283static const u32 reg_endp_init_hol_block_en_fmask[] = { 284 [HOL_BLOCK_EN] = BIT(0), 285 /* Bits 1-31 reserved */ 286}; 287 288REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_EN, endp_init_hol_block_en, 289 0x0000082c, 0x0070); 290 291/* Entire register is a tick count */ 292static const u32 reg_endp_init_hol_block_timer_fmask[] = { 293 [TIMER_BASE_VALUE] = GENMASK(31, 0), 294}; 295 296REG_STRIDE_FIELDS(ENDP_INIT_HOL_BLOCK_TIMER, endp_init_hol_block_timer, 297 0x00000830, 0x0070); 298 299static const u32 reg_endp_init_deaggr_fmask[] = { 300 [DEAGGR_HDR_LEN] = GENMASK(5, 0), 301 [SYSPIPE_ERR_DETECTION] = BIT(6), 302 [PACKET_OFFSET_VALID] = BIT(7), 303 [PACKET_OFFSET_LOCATION] = GENMASK(13, 8), 304 [IGNORE_MIN_PKT_ERR] = BIT(14), 305 /* Bit 15 reserved */ 306 [MAX_PACKET_LEN] = GENMASK(31, 16), 307}; 308 309REG_STRIDE_FIELDS(ENDP_INIT_DEAGGR, endp_init_deaggr, 0x00000834, 0x0070); 310 311static const u32 reg_endp_init_rsrc_grp_fmask[] = { 312 [ENDP_RSRC_GRP] = GENMASK(2, 0), 313 /* Bits 3-31 reserved */ 314}; 315 316REG_STRIDE_FIELDS(ENDP_INIT_RSRC_GRP, endp_init_rsrc_grp, 0x00000838, 0x0070); 317 318static const u32 reg_endp_init_seq_fmask[] = { 319 [SEQ_TYPE] = GENMASK(7, 0), 320 [SEQ_REP_TYPE] = GENMASK(15, 8), 321 /* Bits 16-31 reserved */ 322}; 323 324REG_STRIDE_FIELDS(ENDP_INIT_SEQ, endp_init_seq, 0x0000083c, 0x0070); 325 326static const u32 reg_endp_status_fmask[] = { 327 [STATUS_EN] = BIT(0), 328 [STATUS_ENDP] = GENMASK(5, 1), 329 /* Bits 6-7 reserved */ 330 [STATUS_LOCATION] = BIT(8), 331 /* Bits 9-31 reserved */ 332}; 333 334REG_STRIDE_FIELDS(ENDP_STATUS, endp_status, 0x00000840, 0x0070); 335 336static const u32 reg_endp_filter_router_hsh_cfg_fmask[] = { 337 [FILTER_HASH_MSK_SRC_ID] = BIT(0), 338 [FILTER_HASH_MSK_SRC_IP] = BIT(1), 339 [FILTER_HASH_MSK_DST_IP] = BIT(2), 340 [FILTER_HASH_MSK_SRC_PORT] = BIT(3), 341 [FILTER_HASH_MSK_DST_PORT] = BIT(4), 342 [FILTER_HASH_MSK_PROTOCOL] = BIT(5), 343 [FILTER_HASH_MSK_METADATA] = BIT(6), 344 [FILTER_HASH_MSK_ALL] = GENMASK(6, 0), 345 /* Bits 7-15 reserved */ 346 [ROUTER_HASH_MSK_SRC_ID] = BIT(16), 347 [ROUTER_HASH_MSK_SRC_IP] = BIT(17), 348 [ROUTER_HASH_MSK_DST_IP] = BIT(18), 349 [ROUTER_HASH_MSK_SRC_PORT] = BIT(19), 350 [ROUTER_HASH_MSK_DST_PORT] = BIT(20), 351 [ROUTER_HASH_MSK_PROTOCOL] = BIT(21), 352 [ROUTER_HASH_MSK_METADATA] = BIT(22), 353 [ROUTER_HASH_MSK_ALL] = GENMASK(22, 16), 354 /* Bits 23-31 reserved */ 355}; 356 357REG_STRIDE_FIELDS(ENDP_FILTER_ROUTER_HSH_CFG, endp_filter_router_hsh_cfg, 358 0x0000085c, 0x0070); 359 360/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 361REG(IPA_IRQ_STTS, ipa_irq_stts, 0x00003008 + 0x1000 * GSI_EE_AP); 362 363/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 364REG(IPA_IRQ_EN, ipa_irq_en, 0x0000300c + 0x1000 * GSI_EE_AP); 365 366/* Valid bits defined by enum ipa_irq_id; only used for GSI_EE_AP */ 367REG(IPA_IRQ_CLR, ipa_irq_clr, 0x00003010 + 0x1000 * GSI_EE_AP); 368 369static const u32 reg_ipa_irq_uc_fmask[] = { 370 [UC_INTR] = BIT(0), 371 /* Bits 1-31 reserved */ 372}; 373 374REG_FIELDS(IPA_IRQ_UC, ipa_irq_uc, 0x0000301c + 0x1000 * GSI_EE_AP); 375 376/* Valid bits defined by ipa->available */ 377REG_STRIDE(IRQ_SUSPEND_INFO, irq_suspend_info, 378 0x00003030 + 0x1000 * GSI_EE_AP, 0x0004); 379 380/* Valid bits defined by ipa->available */ 381REG_STRIDE(IRQ_SUSPEND_EN, irq_suspend_en, 382 0x00003034 + 0x1000 * GSI_EE_AP, 0x0004); 383 384/* Valid bits defined by ipa->available */ 385REG_STRIDE(IRQ_SUSPEND_CLR, irq_suspend_clr, 386 0x00003038 + 0x1000 * GSI_EE_AP, 0x0004); 387 388static const struct reg *reg_array[] = { 389 [COMP_CFG] = ®_comp_cfg, 390 [CLKON_CFG] = ®_clkon_cfg, 391 [ROUTE] = ®_route, 392 [SHARED_MEM_SIZE] = ®_shared_mem_size, 393 [QSB_MAX_WRITES] = ®_qsb_max_writes, 394 [QSB_MAX_READS] = ®_qsb_max_reads, 395 [FILT_ROUT_HASH_FLUSH] = ®_filt_rout_hash_flush, 396 [STATE_AGGR_ACTIVE] = ®_state_aggr_active, 397 [IPA_BCR] = ®_ipa_bcr, 398 [LOCAL_PKT_PROC_CNTXT] = ®_local_pkt_proc_cntxt, 399 [AGGR_FORCE_CLOSE] = ®_aggr_force_close, 400 [COUNTER_CFG] = ®_counter_cfg, 401 [SRC_RSRC_GRP_01_RSRC_TYPE] = ®_src_rsrc_grp_01_rsrc_type, 402 [SRC_RSRC_GRP_23_RSRC_TYPE] = ®_src_rsrc_grp_23_rsrc_type, 403 [SRC_RSRC_GRP_45_RSRC_TYPE] = ®_src_rsrc_grp_45_rsrc_type, 404 [SRC_RSRC_GRP_67_RSRC_TYPE] = ®_src_rsrc_grp_67_rsrc_type, 405 [DST_RSRC_GRP_01_RSRC_TYPE] = ®_dst_rsrc_grp_01_rsrc_type, 406 [DST_RSRC_GRP_23_RSRC_TYPE] = ®_dst_rsrc_grp_23_rsrc_type, 407 [DST_RSRC_GRP_45_RSRC_TYPE] = ®_dst_rsrc_grp_45_rsrc_type, 408 [DST_RSRC_GRP_67_RSRC_TYPE] = ®_dst_rsrc_grp_67_rsrc_type, 409 [ENDP_INIT_CTRL] = ®_endp_init_ctrl, 410 [ENDP_INIT_CFG] = ®_endp_init_cfg, 411 [ENDP_INIT_NAT] = ®_endp_init_nat, 412 [ENDP_INIT_HDR] = ®_endp_init_hdr, 413 [ENDP_INIT_HDR_EXT] = ®_endp_init_hdr_ext, 414 [ENDP_INIT_HDR_METADATA_MASK] = ®_endp_init_hdr_metadata_mask, 415 [ENDP_INIT_MODE] = ®_endp_init_mode, 416 [ENDP_INIT_AGGR] = ®_endp_init_aggr, 417 [ENDP_INIT_HOL_BLOCK_EN] = ®_endp_init_hol_block_en, 418 [ENDP_INIT_HOL_BLOCK_TIMER] = ®_endp_init_hol_block_timer, 419 [ENDP_INIT_DEAGGR] = ®_endp_init_deaggr, 420 [ENDP_INIT_RSRC_GRP] = ®_endp_init_rsrc_grp, 421 [ENDP_INIT_SEQ] = ®_endp_init_seq, 422 [ENDP_STATUS] = ®_endp_status, 423 [ENDP_FILTER_ROUTER_HSH_CFG] = ®_endp_filter_router_hsh_cfg, 424 [IPA_IRQ_STTS] = ®_ipa_irq_stts, 425 [IPA_IRQ_EN] = ®_ipa_irq_en, 426 [IPA_IRQ_CLR] = ®_ipa_irq_clr, 427 [IPA_IRQ_UC] = ®_ipa_irq_uc, 428 [IRQ_SUSPEND_INFO] = ®_irq_suspend_info, 429 [IRQ_SUSPEND_EN] = ®_irq_suspend_en, 430 [IRQ_SUSPEND_CLR] = ®_irq_suspend_clr, 431}; 432 433const struct regs ipa_regs_v3_1 = { 434 .reg_count = ARRAY_SIZE(reg_array), 435 .reg = reg_array, 436};
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