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gsi_reg-v5.0.c

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linux-6.19.14/drivers/net/ipa/reg/gsi_reg-v5.0.c C
  1// SPDX-License-Identifier: GPL-2.0
  2
  3/* Copyright (C) 2023-2024 Linaro Ltd. */
  4
  5#include <linux/array_size.h>
  6#include <linux/bits.h>
  7#include <linux/types.h>
  8
  9#include "../gsi_reg.h"
 10#include "../ipa_version.h"
 11#include "../reg.h"
 12
 13REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
 14    0x0000c01c + 0x1000 * GSI_EE_AP);
 15
 16REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
 17    0x0000c028 + 0x1000 * GSI_EE_AP);
 18
 19static const u32 reg_ch_c_cntxt_0_fmask[] = {
 20	[CHTYPE_PROTOCOL]				= GENMASK(6, 0),
 21	[CHTYPE_DIR]					= BIT(7),
 22	[CH_EE]						= GENMASK(11, 8),
 23	[CHID]						= GENMASK(19, 12),
 24	[CHSTATE]					= GENMASK(23, 20),
 25	[ELEMENT_SIZE]					= GENMASK(31, 24),
 26};
 27
 28REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
 29		  0x00014000 + 0x12000 * GSI_EE_AP, 0x80);
 30
 31static const u32 reg_ch_c_cntxt_1_fmask[] = {
 32	[CH_R_LENGTH]					= GENMASK(23, 0),
 33	[CH_ERINDEX]					= GENMASK(31, 24),
 34};
 35
 36REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
 37		  0x00014004 + 0x12000 * GSI_EE_AP, 0x80);
 38
 39REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x00014008 + 0x12000 * GSI_EE_AP, 0x80);
 40
 41REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001400c + 0x12000 * GSI_EE_AP, 0x80);
 42
 43static const u32 reg_ch_c_qos_fmask[] = {
 44	[WRR_WEIGHT]					= GENMASK(3, 0),
 45						/* Bits 4-7 reserved */
 46	[MAX_PREFETCH]					= BIT(8),
 47	[USE_DB_ENG]					= BIT(9),
 48	[PREFETCH_MODE]					= GENMASK(13, 10),
 49						/* Bits 14-15 reserved */
 50	[EMPTY_LVL_THRSHOLD]				= GENMASK(23, 16),
 51	[DB_IN_BYTES]					= BIT(24),
 52	[LOW_LATENCY_EN]				= BIT(25),
 53						/* Bits 26-31 reserved */
 54};
 55
 56REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x00014048 + 0x12000 * GSI_EE_AP, 0x80);
 57
 58REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
 59	   0x0001404c + 0x12000 * GSI_EE_AP, 0x80);
 60
 61REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
 62	   0x00014050 + 0x12000 * GSI_EE_AP, 0x80);
 63
 64REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
 65	   0x00014054 + 0x12000 * GSI_EE_AP, 0x80);
 66
 67REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
 68	   0x00014058 + 0x12000 * GSI_EE_AP, 0x80);
 69
 70static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
 71	[EV_CHTYPE]					= GENMASK(6, 0),
 72	[EV_INTYPE]					= BIT(7),
 73	[EV_EVCHID]					= GENMASK(15, 8),
 74	[EV_EE]						= GENMASK(19, 16),
 75	[EV_CHSTATE]					= GENMASK(23, 20),
 76	[EV_ELEMENT_SIZE]				= GENMASK(31, 24),
 77};
 78
 79REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
 80		  0x0001c000 + 0x12000 * GSI_EE_AP, 0x80);
 81
 82static const u32 reg_ev_ch_e_cntxt_1_fmask[] = {
 83	[R_LENGTH]					= GENMASK(23, 0),
 84};
 85
 86REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
 87		  0x0001c004 + 0x12000 * GSI_EE_AP, 0x80);
 88
 89REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
 90	   0x0001c008 + 0x12000 * GSI_EE_AP, 0x80);
 91
 92REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
 93	   0x0001c00c + 0x12000 * GSI_EE_AP, 0x80);
 94
 95REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
 96	   0x0001c010 + 0x12000 * GSI_EE_AP, 0x80);
 97
 98static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
 99	[EV_MODT]					= GENMASK(15, 0),
100	[EV_MODC]					= GENMASK(23, 16),
101	[EV_MOD_CNT]					= GENMASK(31, 24),
102};
103
104REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
105		  0x0001c020 + 0x12000 * GSI_EE_AP, 0x80);
106
107REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
108	   0x0001c024 + 0x12000 * GSI_EE_AP, 0x80);
109
110REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
111	   0x0001c028 + 0x12000 * GSI_EE_AP, 0x80);
112
113REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
114	   0x0001c02c + 0x12000 * GSI_EE_AP, 0x80);
115
116REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
117	   0x0001c030 + 0x12000 * GSI_EE_AP, 0x80);
118
119REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
120	   0x0001c034 + 0x12000 * GSI_EE_AP, 0x80);
121
122REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
123	   0x0001c048 + 0x12000 * GSI_EE_AP, 0x80);
124
125REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
126	   0x0001c04c + 0x12000 * GSI_EE_AP, 0x80);
127
128REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
129	   0x00024000 + 0x12000 * GSI_EE_AP, 0x08);
130
131REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
132	   0x00024800 + 0x12000 * GSI_EE_AP, 0x08);
133
134static const u32 reg_gsi_status_fmask[] = {
135	[ENABLED]					= BIT(0),
136						/* Bits 1-31 reserved */
137};
138
139REG_FIELDS(GSI_STATUS, gsi_status, 0x00025000 + 0x12000 * GSI_EE_AP);
140
141static const u32 reg_ch_cmd_fmask[] = {
142	[CH_CHID]					= GENMASK(7, 0),
143						/* Bits 8-23 reserved */
144	[CH_OPCODE]					= GENMASK(31, 24),
145};
146
147REG_FIELDS(CH_CMD, ch_cmd, 0x00025008 + 0x12000 * GSI_EE_AP);
148
149static const u32 reg_ev_ch_cmd_fmask[] = {
150	[EV_CHID]					= GENMASK(7, 0),
151						/* Bits 8-23 reserved */
152	[EV_OPCODE]					= GENMASK(31, 24),
153};
154
155REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x00025010 + 0x12000 * GSI_EE_AP);
156
157static const u32 reg_generic_cmd_fmask[] = {
158	[GENERIC_OPCODE]				= GENMASK(4, 0),
159	[GENERIC_CHID]					= GENMASK(12, 5),
160	[GENERIC_EE]					= GENMASK(16, 13),
161						/* Bits 17-23 reserved */
162	[GENERIC_PARAMS]				= GENMASK(31, 24),
163};
164
165REG_FIELDS(GENERIC_CMD, generic_cmd, 0x00025018 + 0x12000 * GSI_EE_AP);
166
167static const u32 reg_hw_param_2_fmask[] = {
168	[NUM_CH_PER_EE]					= GENMASK(7, 0),
169	[IRAM_SIZE]					= GENMASK(12, 8),
170	[GSI_CH_PEND_TRANSLATE]				= BIT(13),
171	[GSI_CH_FULL_LOGIC]				= BIT(14),
172	[GSI_USE_SDMA]					= BIT(15),
173	[GSI_SDMA_N_INT]				= GENMASK(18, 16),
174	[GSI_SDMA_MAX_BURST]				= GENMASK(26, 19),
175	[GSI_SDMA_N_IOVEC]				= GENMASK(29, 27),
176	[GSI_USE_RD_WR_ENG]				= BIT(30),
177	[GSI_USE_INTER_EE]				= BIT(31),
178};
179
180REG_FIELDS(HW_PARAM_2, hw_param_2, 0x00025040 + 0x12000 * GSI_EE_AP);
181
182static const u32 reg_hw_param_4_fmask[] = {
183	[EV_PER_EE]					= GENMASK(7, 0),
184	[IRAM_PROTOCOL_COUNT]				= GENMASK(15, 8),
185						/* Bits 16-31 reserved */
186};
187
188REG_FIELDS(HW_PARAM_4, hw_param_4, 0x00025050 + 0x12000 * GSI_EE_AP);
189
190REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x00025080 + 0x12000 * GSI_EE_AP);
191
192REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x00025088 + 0x12000 * GSI_EE_AP);
193
194REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x00025090 + 0x12000 * GSI_EE_AP);
195
196REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
197    0x00025094 + 0x12000 * GSI_EE_AP);
198
199REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
200    0x00025098 + 0x12000 * GSI_EE_AP);
201
202REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0002509c + 0x12000 * GSI_EE_AP);
203
204REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
205    0x000250a0 + 0x12000 * GSI_EE_AP);
206
207REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
208    0x000250a4 + 0x12000 * GSI_EE_AP);
209
210REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x000250a8 + 0x12000 * GSI_EE_AP);
211
212REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
213    0x000250ac + 0x12000 * GSI_EE_AP);
214
215REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
216    0x000250b0 + 0x12000 * GSI_EE_AP);
217
218REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x00025200 + 0x12000 * GSI_EE_AP);
219
220REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x00025204 + 0x12000 * GSI_EE_AP);
221
222REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x00025208 + 0x12000 * GSI_EE_AP);
223
224REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0002520c + 0x12000 * GSI_EE_AP);
225
226REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x00025210 + 0x12000 * GSI_EE_AP);
227
228REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x00025214 + 0x12000 * GSI_EE_AP);
229
230static const u32 reg_cntxt_intset_fmask[] = {
231	[INTYPE]					= BIT(0)
232						/* Bits 1-31 reserved */
233};
234
235REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x00025220 + 0x12000 * GSI_EE_AP);
236
237static const u32 reg_error_log_fmask[] = {
238	[ERR_ARG3]					= GENMASK(3, 0),
239	[ERR_ARG2]					= GENMASK(7, 4),
240	[ERR_ARG1]					= GENMASK(11, 8),
241	[ERR_CODE]					= GENMASK(15, 12),
242						/* Bits 16-18 reserved */
243	[ERR_VIRT_IDX]					= GENMASK(23, 19),
244	[ERR_TYPE]					= GENMASK(27, 24),
245	[ERR_EE]					= GENMASK(31, 28),
246};
247
248REG_FIELDS(ERROR_LOG, error_log, 0x00025240 + 0x12000 * GSI_EE_AP);
249
250REG(ERROR_LOG_CLR, error_log_clr, 0x00025244 + 0x12000 * GSI_EE_AP);
251
252static const u32 reg_cntxt_scratch_0_fmask[] = {
253	[INTER_EE_RESULT]				= GENMASK(2, 0),
254						/* Bits 3-4 reserved */
255	[GENERIC_EE_RESULT]				= GENMASK(7, 5),
256						/* Bits 8-31 reserved */
257};
258
259REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x00025400 + 0x12000 * GSI_EE_AP);
260
261static const struct reg *reg_array[] = {
262	[INTER_EE_SRC_CH_IRQ_MSK]	= &reg_inter_ee_src_ch_irq_msk,
263	[INTER_EE_SRC_EV_CH_IRQ_MSK]	= &reg_inter_ee_src_ev_ch_irq_msk,
264	[CH_C_CNTXT_0]			= &reg_ch_c_cntxt_0,
265	[CH_C_CNTXT_1]			= &reg_ch_c_cntxt_1,
266	[CH_C_CNTXT_2]			= &reg_ch_c_cntxt_2,
267	[CH_C_CNTXT_3]			= &reg_ch_c_cntxt_3,
268	[CH_C_QOS]			= &reg_ch_c_qos,
269	[CH_C_SCRATCH_0]		= &reg_ch_c_scratch_0,
270	[CH_C_SCRATCH_1]		= &reg_ch_c_scratch_1,
271	[CH_C_SCRATCH_2]		= &reg_ch_c_scratch_2,
272	[CH_C_SCRATCH_3]		= &reg_ch_c_scratch_3,
273	[EV_CH_E_CNTXT_0]		= &reg_ev_ch_e_cntxt_0,
274	[EV_CH_E_CNTXT_1]		= &reg_ev_ch_e_cntxt_1,
275	[EV_CH_E_CNTXT_2]		= &reg_ev_ch_e_cntxt_2,
276	[EV_CH_E_CNTXT_3]		= &reg_ev_ch_e_cntxt_3,
277	[EV_CH_E_CNTXT_4]		= &reg_ev_ch_e_cntxt_4,
278	[EV_CH_E_CNTXT_8]		= &reg_ev_ch_e_cntxt_8,
279	[EV_CH_E_CNTXT_9]		= &reg_ev_ch_e_cntxt_9,
280	[EV_CH_E_CNTXT_10]		= &reg_ev_ch_e_cntxt_10,
281	[EV_CH_E_CNTXT_11]		= &reg_ev_ch_e_cntxt_11,
282	[EV_CH_E_CNTXT_12]		= &reg_ev_ch_e_cntxt_12,
283	[EV_CH_E_CNTXT_13]		= &reg_ev_ch_e_cntxt_13,
284	[EV_CH_E_SCRATCH_0]		= &reg_ev_ch_e_scratch_0,
285	[EV_CH_E_SCRATCH_1]		= &reg_ev_ch_e_scratch_1,
286	[CH_C_DOORBELL_0]		= &reg_ch_c_doorbell_0,
287	[EV_CH_E_DOORBELL_0]		= &reg_ev_ch_e_doorbell_0,
288	[GSI_STATUS]			= &reg_gsi_status,
289	[CH_CMD]			= &reg_ch_cmd,
290	[EV_CH_CMD]			= &reg_ev_ch_cmd,
291	[GENERIC_CMD]			= &reg_generic_cmd,
292	[HW_PARAM_2]			= &reg_hw_param_2,
293	[HW_PARAM_4]			= &reg_hw_param_4,
294	[CNTXT_TYPE_IRQ]		= &reg_cntxt_type_irq,
295	[CNTXT_TYPE_IRQ_MSK]		= &reg_cntxt_type_irq_msk,
296	[CNTXT_SRC_CH_IRQ]		= &reg_cntxt_src_ch_irq,
297	[CNTXT_SRC_CH_IRQ_MSK]		= &reg_cntxt_src_ch_irq_msk,
298	[CNTXT_SRC_CH_IRQ_CLR]		= &reg_cntxt_src_ch_irq_clr,
299	[CNTXT_SRC_EV_CH_IRQ]		= &reg_cntxt_src_ev_ch_irq,
300	[CNTXT_SRC_EV_CH_IRQ_MSK]	= &reg_cntxt_src_ev_ch_irq_msk,
301	[CNTXT_SRC_EV_CH_IRQ_CLR]	= &reg_cntxt_src_ev_ch_irq_clr,
302	[CNTXT_SRC_IEOB_IRQ]		= &reg_cntxt_src_ieob_irq,
303	[CNTXT_SRC_IEOB_IRQ_MSK]	= &reg_cntxt_src_ieob_irq_msk,
304	[CNTXT_SRC_IEOB_IRQ_CLR]	= &reg_cntxt_src_ieob_irq_clr,
305	[CNTXT_GLOB_IRQ_STTS]		= &reg_cntxt_glob_irq_stts,
306	[CNTXT_GLOB_IRQ_EN]		= &reg_cntxt_glob_irq_en,
307	[CNTXT_GLOB_IRQ_CLR]		= &reg_cntxt_glob_irq_clr,
308	[CNTXT_GSI_IRQ_STTS]		= &reg_cntxt_gsi_irq_stts,
309	[CNTXT_GSI_IRQ_EN]		= &reg_cntxt_gsi_irq_en,
310	[CNTXT_GSI_IRQ_CLR]		= &reg_cntxt_gsi_irq_clr,
311	[CNTXT_INTSET]			= &reg_cntxt_intset,
312	[ERROR_LOG]			= &reg_error_log,
313	[ERROR_LOG_CLR]			= &reg_error_log_clr,
314	[CNTXT_SCRATCH_0]		= &reg_cntxt_scratch_0,
315};
316
317const struct regs gsi_regs_v5_0 = {
318	.reg_count	= ARRAY_SIZE(reg_array),
319	.reg		= reg_array,
320};
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