FILE
gsi_reg-v4.0.c

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linux-6.19.14/drivers/net/ipa/reg/gsi_reg-v4.0.c C
  1// SPDX-License-Identifier: GPL-2.0
  2
  3/* Copyright (C) 2023-2024 Linaro Ltd. */
  4
  5#include <linux/array_size.h>
  6#include <linux/bits.h>
  7#include <linux/types.h>
  8
  9#include "../gsi_reg.h"
 10#include "../ipa_version.h"
 11#include "../reg.h"
 12
 13REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
 14    0x0000c020 + 0x1000 * GSI_EE_AP);
 15
 16REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
 17    0x0000c024 + 0x1000 * GSI_EE_AP);
 18
 19static const u32 reg_ch_c_cntxt_0_fmask[] = {
 20	[CHTYPE_PROTOCOL]				= GENMASK(2, 0),
 21	[CHTYPE_DIR]					= BIT(3),
 22	[CH_EE]						= GENMASK(7, 4),
 23	[CHID]						= GENMASK(12, 8),
 24						/* Bit 13 reserved */
 25	[ERINDEX]					= GENMASK(18, 14),
 26						/* Bit 19 reserved */
 27	[CHSTATE]					= GENMASK(23, 20),
 28	[ELEMENT_SIZE]					= GENMASK(31, 24),
 29};
 30
 31REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
 32		  0x0001c000 + 0x4000 * GSI_EE_AP, 0x80);
 33
 34static const u32 reg_ch_c_cntxt_1_fmask[] = {
 35	[CH_R_LENGTH]					= GENMASK(15, 0),
 36						/* Bits 16-31 reserved */
 37};
 38
 39REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
 40		  0x0001c004 + 0x4000 * GSI_EE_AP, 0x80);
 41
 42REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80);
 43
 44REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80);
 45
 46static const u32 reg_ch_c_qos_fmask[] = {
 47	[WRR_WEIGHT]					= GENMASK(3, 0),
 48						/* Bits 4-7 reserved */
 49	[MAX_PREFETCH]					= BIT(8),
 50	[USE_DB_ENG]					= BIT(9),
 51	[USE_ESCAPE_BUF_ONLY]				= BIT(10),
 52						/* Bits 11-31 reserved */
 53};
 54
 55REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80);
 56
 57static const u32 reg_error_log_fmask[] = {
 58	[ERR_ARG3]					= GENMASK(3, 0),
 59	[ERR_ARG2]					= GENMASK(7, 4),
 60	[ERR_ARG1]					= GENMASK(11, 8),
 61	[ERR_CODE]					= GENMASK(15, 12),
 62						/* Bits 16-18 reserved */
 63	[ERR_VIRT_IDX]					= GENMASK(23, 19),
 64	[ERR_TYPE]					= GENMASK(27, 24),
 65	[ERR_EE]					= GENMASK(31, 28),
 66};
 67
 68REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
 69	   0x0001c060 + 0x4000 * GSI_EE_AP, 0x80);
 70
 71REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
 72	   0x0001c064 + 0x4000 * GSI_EE_AP, 0x80);
 73
 74REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
 75	   0x0001c068 + 0x4000 * GSI_EE_AP, 0x80);
 76
 77REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
 78	   0x0001c06c + 0x4000 * GSI_EE_AP, 0x80);
 79
 80static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
 81	[EV_CHTYPE]					= GENMASK(3, 0),
 82	[EV_EE]						= GENMASK(7, 4),
 83	[EV_EVCHID]					= GENMASK(15, 8),
 84	[EV_INTYPE]					= BIT(16),
 85						/* Bits 17-19 reserved */
 86	[EV_CHSTATE]					= GENMASK(23, 20),
 87	[EV_ELEMENT_SIZE]				= GENMASK(31, 24),
 88};
 89
 90REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
 91		  0x0001d000 + 0x4000 * GSI_EE_AP, 0x80);
 92
 93static const u32 reg_ev_ch_e_cntxt_1_fmask[] = {
 94	[R_LENGTH]					= GENMASK(15, 0),
 95};
 96
 97REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
 98		  0x0001d004 + 0x4000 * GSI_EE_AP, 0x80);
 99
100REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
101	   0x0001d008 + 0x4000 * GSI_EE_AP, 0x80);
102
103REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
104	   0x0001d00c + 0x4000 * GSI_EE_AP, 0x80);
105
106REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
107	   0x0001d010 + 0x4000 * GSI_EE_AP, 0x80);
108
109static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
110	[EV_MODT]					= GENMASK(15, 0),
111	[EV_MODC]					= GENMASK(23, 16),
112	[EV_MOD_CNT]					= GENMASK(31, 24),
113};
114
115REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
116		  0x0001d020 + 0x4000 * GSI_EE_AP, 0x80);
117
118REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
119	   0x0001d024 + 0x4000 * GSI_EE_AP, 0x80);
120
121REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
122	   0x0001d028 + 0x4000 * GSI_EE_AP, 0x80);
123
124REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
125	   0x0001d02c + 0x4000 * GSI_EE_AP, 0x80);
126
127REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
128	   0x0001d030 + 0x4000 * GSI_EE_AP, 0x80);
129
130REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
131	   0x0001d034 + 0x4000 * GSI_EE_AP, 0x80);
132
133REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
134	   0x0001d048 + 0x4000 * GSI_EE_AP, 0x80);
135
136REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
137	   0x0001d04c + 0x4000 * GSI_EE_AP, 0x80);
138
139REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
140	   0x0001e000 + 0x4000 * GSI_EE_AP, 0x08);
141
142REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
143	   0x0001e100 + 0x4000 * GSI_EE_AP, 0x08);
144
145static const u32 reg_gsi_status_fmask[] = {
146	[ENABLED]					= BIT(0),
147						/* Bits 1-31 reserved */
148};
149
150REG_FIELDS(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 * GSI_EE_AP);
151
152static const u32 reg_ch_cmd_fmask[] = {
153	[CH_CHID]					= GENMASK(7, 0),
154						/* Bits 8-23 reserved */
155	[CH_OPCODE]					= GENMASK(31, 24),
156};
157
158REG_FIELDS(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE_AP);
159
160static const u32 reg_ev_ch_cmd_fmask[] = {
161	[EV_CHID]					= GENMASK(7, 0),
162						/* Bits 8-23 reserved */
163	[EV_OPCODE]					= GENMASK(31, 24),
164};
165
166REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x0001f010 + 0x4000 * GSI_EE_AP);
167
168static const u32 reg_generic_cmd_fmask[] = {
169	[GENERIC_OPCODE]				= GENMASK(4, 0),
170	[GENERIC_CHID]					= GENMASK(9, 5),
171	[GENERIC_EE]					= GENMASK(13, 10),
172						/* Bits 14-31 reserved */
173};
174
175REG_FIELDS(GENERIC_CMD, generic_cmd, 0x0001f018 + 0x4000 * GSI_EE_AP);
176
177static const u32 reg_hw_param_2_fmask[] = {
178	[IRAM_SIZE]					= GENMASK(2, 0),
179	[NUM_CH_PER_EE]					= GENMASK(7, 3),
180	[NUM_EV_PER_EE]					= GENMASK(12, 8),
181	[GSI_CH_PEND_TRANSLATE]				= BIT(13),
182	[GSI_CH_FULL_LOGIC]				= BIT(14),
183	[GSI_USE_SDMA]					= BIT(15),
184	[GSI_SDMA_N_INT]				= GENMASK(18, 16),
185	[GSI_SDMA_MAX_BURST]				= GENMASK(26, 19),
186	[GSI_SDMA_N_IOVEC]				= GENMASK(29, 27),
187						/* Bits 30-31 reserved */
188};
189
190REG_FIELDS(HW_PARAM_2, hw_param_2, 0x0001f040 + 0x4000 * GSI_EE_AP);
191
192REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP);
193
194REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP);
195
196REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP);
197
198REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP);
199
200REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
201    0x0001f098 + 0x4000 * GSI_EE_AP);
202
203REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
204    0x0001f09c + 0x4000 * GSI_EE_AP);
205
206REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
207    0x0001f0a0 + 0x4000 * GSI_EE_AP);
208
209REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
210    0x0001f0a4 + 0x4000 * GSI_EE_AP);
211
212REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP);
213
214REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
215    0x0001f0b8 + 0x4000 * GSI_EE_AP);
216
217REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
218    0x0001f0c0 + 0x4000 * GSI_EE_AP);
219
220REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP);
221
222REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP);
223
224REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP);
225
226REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP);
227
228REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP);
229
230REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP);
231
232static const u32 reg_cntxt_intset_fmask[] = {
233	[INTYPE]					= BIT(0)
234						/* Bits 1-31 reserved */
235};
236
237REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP);
238
239REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP);
240
241REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP);
242
243static const u32 reg_cntxt_scratch_0_fmask[] = {
244	[INTER_EE_RESULT]				= GENMASK(2, 0),
245						/* Bits 3-4 reserved */
246	[GENERIC_EE_RESULT]				= GENMASK(7, 5),
247						/* Bits 8-31 reserved */
248};
249
250REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x0001f400 + 0x4000 * GSI_EE_AP);
251
252static const struct reg *reg_array[] = {
253	[INTER_EE_SRC_CH_IRQ_MSK]	= &reg_inter_ee_src_ch_irq_msk,
254	[INTER_EE_SRC_EV_CH_IRQ_MSK]	= &reg_inter_ee_src_ev_ch_irq_msk,
255	[CH_C_CNTXT_0]			= &reg_ch_c_cntxt_0,
256	[CH_C_CNTXT_1]			= &reg_ch_c_cntxt_1,
257	[CH_C_CNTXT_2]			= &reg_ch_c_cntxt_2,
258	[CH_C_CNTXT_3]			= &reg_ch_c_cntxt_3,
259	[CH_C_QOS]			= &reg_ch_c_qos,
260	[CH_C_SCRATCH_0]		= &reg_ch_c_scratch_0,
261	[CH_C_SCRATCH_1]		= &reg_ch_c_scratch_1,
262	[CH_C_SCRATCH_2]		= &reg_ch_c_scratch_2,
263	[CH_C_SCRATCH_3]		= &reg_ch_c_scratch_3,
264	[EV_CH_E_CNTXT_0]		= &reg_ev_ch_e_cntxt_0,
265	[EV_CH_E_CNTXT_1]		= &reg_ev_ch_e_cntxt_1,
266	[EV_CH_E_CNTXT_2]		= &reg_ev_ch_e_cntxt_2,
267	[EV_CH_E_CNTXT_3]		= &reg_ev_ch_e_cntxt_3,
268	[EV_CH_E_CNTXT_4]		= &reg_ev_ch_e_cntxt_4,
269	[EV_CH_E_CNTXT_8]		= &reg_ev_ch_e_cntxt_8,
270	[EV_CH_E_CNTXT_9]		= &reg_ev_ch_e_cntxt_9,
271	[EV_CH_E_CNTXT_10]		= &reg_ev_ch_e_cntxt_10,
272	[EV_CH_E_CNTXT_11]		= &reg_ev_ch_e_cntxt_11,
273	[EV_CH_E_CNTXT_12]		= &reg_ev_ch_e_cntxt_12,
274	[EV_CH_E_CNTXT_13]		= &reg_ev_ch_e_cntxt_13,
275	[EV_CH_E_SCRATCH_0]		= &reg_ev_ch_e_scratch_0,
276	[EV_CH_E_SCRATCH_1]		= &reg_ev_ch_e_scratch_1,
277	[CH_C_DOORBELL_0]		= &reg_ch_c_doorbell_0,
278	[EV_CH_E_DOORBELL_0]		= &reg_ev_ch_e_doorbell_0,
279	[GSI_STATUS]			= &reg_gsi_status,
280	[CH_CMD]			= &reg_ch_cmd,
281	[EV_CH_CMD]			= &reg_ev_ch_cmd,
282	[GENERIC_CMD]			= &reg_generic_cmd,
283	[HW_PARAM_2]			= &reg_hw_param_2,
284	[CNTXT_TYPE_IRQ]		= &reg_cntxt_type_irq,
285	[CNTXT_TYPE_IRQ_MSK]		= &reg_cntxt_type_irq_msk,
286	[CNTXT_SRC_CH_IRQ]		= &reg_cntxt_src_ch_irq,
287	[CNTXT_SRC_EV_CH_IRQ]		= &reg_cntxt_src_ev_ch_irq,
288	[CNTXT_SRC_CH_IRQ_MSK]		= &reg_cntxt_src_ch_irq_msk,
289	[CNTXT_SRC_EV_CH_IRQ_MSK]	= &reg_cntxt_src_ev_ch_irq_msk,
290	[CNTXT_SRC_CH_IRQ_CLR]		= &reg_cntxt_src_ch_irq_clr,
291	[CNTXT_SRC_EV_CH_IRQ_CLR]	= &reg_cntxt_src_ev_ch_irq_clr,
292	[CNTXT_SRC_IEOB_IRQ]		= &reg_cntxt_src_ieob_irq,
293	[CNTXT_SRC_IEOB_IRQ_MSK]	= &reg_cntxt_src_ieob_irq_msk,
294	[CNTXT_SRC_IEOB_IRQ_CLR]	= &reg_cntxt_src_ieob_irq_clr,
295	[CNTXT_GLOB_IRQ_STTS]		= &reg_cntxt_glob_irq_stts,
296	[CNTXT_GLOB_IRQ_EN]		= &reg_cntxt_glob_irq_en,
297	[CNTXT_GLOB_IRQ_CLR]		= &reg_cntxt_glob_irq_clr,
298	[CNTXT_GSI_IRQ_STTS]		= &reg_cntxt_gsi_irq_stts,
299	[CNTXT_GSI_IRQ_EN]		= &reg_cntxt_gsi_irq_en,
300	[CNTXT_GSI_IRQ_CLR]		= &reg_cntxt_gsi_irq_clr,
301	[CNTXT_INTSET]			= &reg_cntxt_intset,
302	[ERROR_LOG]			= &reg_error_log,
303	[ERROR_LOG_CLR]			= &reg_error_log_clr,
304	[CNTXT_SCRATCH_0]		= &reg_cntxt_scratch_0,
305};
306
307const struct regs gsi_regs_v4_0 = {
308	.reg_count	= ARRAY_SIZE(reg_array),
309	.reg		= reg_array,
310};
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