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gsi_reg-v3.5.1.c

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linux-6.19.14/drivers/net/ipa/reg/gsi_reg-v3.5.1.c C 
  1// SPDX-License-Identifier: GPL-2.0
  2
  3/* Copyright (C) 2023-2024 Linaro Ltd. */
  4
  5#include <linux/array_size.h>
  6#include <linux/bits.h>
  7#include <linux/types.h>
  8
  9#include "../gsi_reg.h"
 10#include "../ipa_version.h"
 11#include "../reg.h"
 12
 13REG(INTER_EE_SRC_CH_IRQ_MSK, inter_ee_src_ch_irq_msk,
 14    0x0000c020 + 0x1000 * GSI_EE_AP);
 15
 16REG(INTER_EE_SRC_EV_CH_IRQ_MSK, inter_ee_src_ev_ch_irq_msk,
 17    0x0000c024 + 0x1000 * GSI_EE_AP);
 18
 19static const u32 reg_ch_c_cntxt_0_fmask[] = {
 20	[CHTYPE_PROTOCOL]				= GENMASK(2, 0),
 21	[CHTYPE_DIR]					= BIT(3),
 22	[CH_EE]						= GENMASK(7, 4),
 23	[CHID]						= GENMASK(12, 8),
 24						/* Bit 13 reserved */
 25	[ERINDEX]					= GENMASK(18, 14),
 26						/* Bit 19 reserved */
 27	[CHSTATE]					= GENMASK(23, 20),
 28	[ELEMENT_SIZE]					= GENMASK(31, 24),
 29};
 30
 31REG_STRIDE_FIELDS(CH_C_CNTXT_0, ch_c_cntxt_0,
 32		  0x0001c000 + 0x4000 * GSI_EE_AP, 0x80);
 33
 34static const u32 reg_ch_c_cntxt_1_fmask[] = {
 35	[CH_R_LENGTH]					= GENMASK(15, 0),
 36						/* Bits 16-31 reserved */
 37};
 38
 39REG_STRIDE_FIELDS(CH_C_CNTXT_1, ch_c_cntxt_1,
 40		  0x0001c004 + 0x4000 * GSI_EE_AP, 0x80);
 41
 42REG_STRIDE(CH_C_CNTXT_2, ch_c_cntxt_2, 0x0001c008 + 0x4000 * GSI_EE_AP, 0x80);
 43
 44REG_STRIDE(CH_C_CNTXT_3, ch_c_cntxt_3, 0x0001c00c + 0x4000 * GSI_EE_AP, 0x80);
 45
 46static const u32 reg_ch_c_qos_fmask[] = {
 47	[WRR_WEIGHT]					= GENMASK(3, 0),
 48						/* Bits 4-7 reserved */
 49	[MAX_PREFETCH]					= BIT(8),
 50	[USE_DB_ENG]					= BIT(9),
 51						/* Bits 10-31 reserved */
 52};
 53
 54REG_STRIDE_FIELDS(CH_C_QOS, ch_c_qos, 0x0001c05c + 0x4000 * GSI_EE_AP, 0x80);
 55
 56static const u32 reg_error_log_fmask[] = {
 57	[ERR_ARG3]					= GENMASK(3, 0),
 58	[ERR_ARG2]					= GENMASK(7, 4),
 59	[ERR_ARG1]					= GENMASK(11, 8),
 60	[ERR_CODE]					= GENMASK(15, 12),
 61						/* Bits 16-18 reserved */
 62	[ERR_VIRT_IDX]					= GENMASK(23, 19),
 63	[ERR_TYPE]					= GENMASK(27, 24),
 64	[ERR_EE]					= GENMASK(31, 28),
 65};
 66
 67REG_STRIDE(CH_C_SCRATCH_0, ch_c_scratch_0,
 68	   0x0001c060 + 0x4000 * GSI_EE_AP, 0x80);
 69
 70REG_STRIDE(CH_C_SCRATCH_1, ch_c_scratch_1,
 71	   0x0001c064 + 0x4000 * GSI_EE_AP, 0x80);
 72
 73REG_STRIDE(CH_C_SCRATCH_2, ch_c_scratch_2,
 74	   0x0001c068 + 0x4000 * GSI_EE_AP, 0x80);
 75
 76REG_STRIDE(CH_C_SCRATCH_3, ch_c_scratch_3,
 77	   0x0001c06c + 0x4000 * GSI_EE_AP, 0x80);
 78
 79static const u32 reg_ev_ch_e_cntxt_0_fmask[] = {
 80	[EV_CHTYPE]					= GENMASK(3, 0),
 81	[EV_EE]						= GENMASK(7, 4),
 82	[EV_EVCHID]					= GENMASK(15, 8),
 83	[EV_INTYPE]					= BIT(16),
 84						/* Bits 17-19 reserved */
 85	[EV_CHSTATE]					= GENMASK(23, 20),
 86	[EV_ELEMENT_SIZE]				= GENMASK(31, 24),
 87};
 88
 89REG_STRIDE_FIELDS(EV_CH_E_CNTXT_0, ev_ch_e_cntxt_0,
 90		  0x0001d000 + 0x4000 * GSI_EE_AP, 0x80);
 91
 92static const u32 reg_ev_ch_e_cntxt_1_fmask[] = {
 93	[R_LENGTH]					= GENMASK(15, 0),
 94};
 95
 96REG_STRIDE_FIELDS(EV_CH_E_CNTXT_1, ev_ch_e_cntxt_1,
 97		  0x0001d004 + 0x4000 * GSI_EE_AP, 0x80);
 98
 99REG_STRIDE(EV_CH_E_CNTXT_2, ev_ch_e_cntxt_2,
100	   0x0001d008 + 0x4000 * GSI_EE_AP, 0x80);
101
102REG_STRIDE(EV_CH_E_CNTXT_3, ev_ch_e_cntxt_3,
103	   0x0001d00c + 0x4000 * GSI_EE_AP, 0x80);
104
105REG_STRIDE(EV_CH_E_CNTXT_4, ev_ch_e_cntxt_4,
106	   0x0001d010 + 0x4000 * GSI_EE_AP, 0x80);
107
108static const u32 reg_ev_ch_e_cntxt_8_fmask[] = {
109	[EV_MODT]					= GENMASK(15, 0),
110	[EV_MODC]					= GENMASK(23, 16),
111	[EV_MOD_CNT]					= GENMASK(31, 24),
112};
113
114REG_STRIDE_FIELDS(EV_CH_E_CNTXT_8, ev_ch_e_cntxt_8,
115		  0x0001d020 + 0x4000 * GSI_EE_AP, 0x80);
116
117REG_STRIDE(EV_CH_E_CNTXT_9, ev_ch_e_cntxt_9,
118	   0x0001d024 + 0x4000 * GSI_EE_AP, 0x80);
119
120REG_STRIDE(EV_CH_E_CNTXT_10, ev_ch_e_cntxt_10,
121	   0x0001d028 + 0x4000 * GSI_EE_AP, 0x80);
122
123REG_STRIDE(EV_CH_E_CNTXT_11, ev_ch_e_cntxt_11,
124	   0x0001d02c + 0x4000 * GSI_EE_AP, 0x80);
125
126REG_STRIDE(EV_CH_E_CNTXT_12, ev_ch_e_cntxt_12,
127	   0x0001d030 + 0x4000 * GSI_EE_AP, 0x80);
128
129REG_STRIDE(EV_CH_E_CNTXT_13, ev_ch_e_cntxt_13,
130	   0x0001d034 + 0x4000 * GSI_EE_AP, 0x80);
131
132REG_STRIDE(EV_CH_E_SCRATCH_0, ev_ch_e_scratch_0,
133	   0x0001d048 + 0x4000 * GSI_EE_AP, 0x80);
134
135REG_STRIDE(EV_CH_E_SCRATCH_1, ev_ch_e_scratch_1,
136	   0x0001d04c + 0x4000 * GSI_EE_AP, 0x80);
137
138REG_STRIDE(CH_C_DOORBELL_0, ch_c_doorbell_0,
139	   0x0001e000 + 0x4000 * GSI_EE_AP, 0x08);
140
141REG_STRIDE(EV_CH_E_DOORBELL_0, ev_ch_e_doorbell_0,
142	   0x0001e100 + 0x4000 * GSI_EE_AP, 0x08);
143
144static const u32 reg_gsi_status_fmask[] = {
145	[ENABLED]					= BIT(0),
146						/* Bits 1-31 reserved */
147};
148
149REG_FIELDS(GSI_STATUS, gsi_status, 0x0001f000 + 0x4000 * GSI_EE_AP);
150
151static const u32 reg_ch_cmd_fmask[] = {
152	[CH_CHID]					= GENMASK(7, 0),
153						/* Bits 8-23 reserved */
154	[CH_OPCODE]					= GENMASK(31, 24),
155};
156
157REG_FIELDS(CH_CMD, ch_cmd, 0x0001f008 + 0x4000 * GSI_EE_AP);
158
159static const u32 reg_ev_ch_cmd_fmask[] = {
160	[EV_CHID]					= GENMASK(7, 0),
161						/* Bits 8-23 reserved */
162	[EV_OPCODE]					= GENMASK(31, 24),
163};
164
165REG_FIELDS(EV_CH_CMD, ev_ch_cmd, 0x0001f010 + 0x4000 * GSI_EE_AP);
166
167static const u32 reg_generic_cmd_fmask[] = {
168	[GENERIC_OPCODE]				= GENMASK(4, 0),
169	[GENERIC_CHID]					= GENMASK(9, 5),
170	[GENERIC_EE]					= GENMASK(13, 10),
171						/* Bits 14-31 reserved */
172};
173
174REG_FIELDS(GENERIC_CMD, generic_cmd, 0x0001f018 + 0x4000 * GSI_EE_AP);
175
176static const u32 reg_hw_param_2_fmask[] = {
177	[IRAM_SIZE]					= GENMASK(2, 0),
178	[NUM_CH_PER_EE]					= GENMASK(7, 3),
179	[NUM_EV_PER_EE]					= GENMASK(12, 8),
180	[GSI_CH_PEND_TRANSLATE]				= BIT(13),
181	[GSI_CH_FULL_LOGIC]				= BIT(14),
182						/* Bits 15-31 reserved */
183};
184
185REG_FIELDS(HW_PARAM_2, hw_param_2, 0x0001f040 + 0x4000 * GSI_EE_AP);
186
187REG(CNTXT_TYPE_IRQ, cntxt_type_irq, 0x0001f080 + 0x4000 * GSI_EE_AP);
188
189REG(CNTXT_TYPE_IRQ_MSK, cntxt_type_irq_msk, 0x0001f088 + 0x4000 * GSI_EE_AP);
190
191REG(CNTXT_SRC_CH_IRQ, cntxt_src_ch_irq, 0x0001f090 + 0x4000 * GSI_EE_AP);
192
193REG(CNTXT_SRC_EV_CH_IRQ, cntxt_src_ev_ch_irq, 0x0001f094 + 0x4000 * GSI_EE_AP);
194
195REG(CNTXT_SRC_CH_IRQ_MSK, cntxt_src_ch_irq_msk,
196    0x0001f098 + 0x4000 * GSI_EE_AP);
197
198REG(CNTXT_SRC_EV_CH_IRQ_MSK, cntxt_src_ev_ch_irq_msk,
199    0x0001f09c + 0x4000 * GSI_EE_AP);
200
201REG(CNTXT_SRC_CH_IRQ_CLR, cntxt_src_ch_irq_clr,
202    0x0001f0a0 + 0x4000 * GSI_EE_AP);
203
204REG(CNTXT_SRC_EV_CH_IRQ_CLR, cntxt_src_ev_ch_irq_clr,
205    0x0001f0a4 + 0x4000 * GSI_EE_AP);
206
207REG(CNTXT_SRC_IEOB_IRQ, cntxt_src_ieob_irq, 0x0001f0b0 + 0x4000 * GSI_EE_AP);
208
209REG(CNTXT_SRC_IEOB_IRQ_MSK, cntxt_src_ieob_irq_msk,
210    0x0001f0b8 + 0x4000 * GSI_EE_AP);
211
212REG(CNTXT_SRC_IEOB_IRQ_CLR, cntxt_src_ieob_irq_clr,
213    0x0001f0c0 + 0x4000 * GSI_EE_AP);
214
215REG(CNTXT_GLOB_IRQ_STTS, cntxt_glob_irq_stts, 0x0001f100 + 0x4000 * GSI_EE_AP);
216
217REG(CNTXT_GLOB_IRQ_EN, cntxt_glob_irq_en, 0x0001f108 + 0x4000 * GSI_EE_AP);
218
219REG(CNTXT_GLOB_IRQ_CLR, cntxt_glob_irq_clr, 0x0001f110 + 0x4000 * GSI_EE_AP);
220
221REG(CNTXT_GSI_IRQ_STTS, cntxt_gsi_irq_stts, 0x0001f118 + 0x4000 * GSI_EE_AP);
222
223REG(CNTXT_GSI_IRQ_EN, cntxt_gsi_irq_en, 0x0001f120 + 0x4000 * GSI_EE_AP);
224
225REG(CNTXT_GSI_IRQ_CLR, cntxt_gsi_irq_clr, 0x0001f128 + 0x4000 * GSI_EE_AP);
226
227static const u32 reg_cntxt_intset_fmask[] = {
228	[INTYPE]					= BIT(0)
229						/* Bits 1-31 reserved */
230};
231
232REG_FIELDS(CNTXT_INTSET, cntxt_intset, 0x0001f180 + 0x4000 * GSI_EE_AP);
233
234REG_FIELDS(ERROR_LOG, error_log, 0x0001f200 + 0x4000 * GSI_EE_AP);
235
236REG(ERROR_LOG_CLR, error_log_clr, 0x0001f210 + 0x4000 * GSI_EE_AP);
237
238static const u32 reg_cntxt_scratch_0_fmask[] = {
239	[INTER_EE_RESULT]				= GENMASK(2, 0),
240						/* Bits 3-4 reserved */
241	[GENERIC_EE_RESULT]				= GENMASK(7, 5),
242						/* Bits 8-31 reserved */
243};
244
245REG_FIELDS(CNTXT_SCRATCH_0, cntxt_scratch_0, 0x0001f400 + 0x4000 * GSI_EE_AP);
246
247static const struct reg *reg_array[] = {
248	[INTER_EE_SRC_CH_IRQ_MSK]	= &reg_inter_ee_src_ch_irq_msk,
249	[INTER_EE_SRC_EV_CH_IRQ_MSK]	= &reg_inter_ee_src_ev_ch_irq_msk,
250	[CH_C_CNTXT_0]			= &reg_ch_c_cntxt_0,
251	[CH_C_CNTXT_1]			= &reg_ch_c_cntxt_1,
252	[CH_C_CNTXT_2]			= &reg_ch_c_cntxt_2,
253	[CH_C_CNTXT_3]			= &reg_ch_c_cntxt_3,
254	[CH_C_QOS]			= &reg_ch_c_qos,
255	[CH_C_SCRATCH_0]		= &reg_ch_c_scratch_0,
256	[CH_C_SCRATCH_1]		= &reg_ch_c_scratch_1,
257	[CH_C_SCRATCH_2]		= &reg_ch_c_scratch_2,
258	[CH_C_SCRATCH_3]		= &reg_ch_c_scratch_3,
259	[EV_CH_E_CNTXT_0]		= &reg_ev_ch_e_cntxt_0,
260	[EV_CH_E_CNTXT_1]		= &reg_ev_ch_e_cntxt_1,
261	[EV_CH_E_CNTXT_2]		= &reg_ev_ch_e_cntxt_2,
262	[EV_CH_E_CNTXT_3]		= &reg_ev_ch_e_cntxt_3,
263	[EV_CH_E_CNTXT_4]		= &reg_ev_ch_e_cntxt_4,
264	[EV_CH_E_CNTXT_8]		= &reg_ev_ch_e_cntxt_8,
265	[EV_CH_E_CNTXT_9]		= &reg_ev_ch_e_cntxt_9,
266	[EV_CH_E_CNTXT_10]		= &reg_ev_ch_e_cntxt_10,
267	[EV_CH_E_CNTXT_11]		= &reg_ev_ch_e_cntxt_11,
268	[EV_CH_E_CNTXT_12]		= &reg_ev_ch_e_cntxt_12,
269	[EV_CH_E_CNTXT_13]		= &reg_ev_ch_e_cntxt_13,
270	[EV_CH_E_SCRATCH_0]		= &reg_ev_ch_e_scratch_0,
271	[EV_CH_E_SCRATCH_1]		= &reg_ev_ch_e_scratch_1,
272	[CH_C_DOORBELL_0]		= &reg_ch_c_doorbell_0,
273	[EV_CH_E_DOORBELL_0]		= &reg_ev_ch_e_doorbell_0,
274	[GSI_STATUS]			= &reg_gsi_status,
275	[CH_CMD]			= &reg_ch_cmd,
276	[EV_CH_CMD]			= &reg_ev_ch_cmd,
277	[GENERIC_CMD]			= &reg_generic_cmd,
278	[HW_PARAM_2]			= &reg_hw_param_2,
279	[CNTXT_TYPE_IRQ]		= &reg_cntxt_type_irq,
280	[CNTXT_TYPE_IRQ_MSK]		= &reg_cntxt_type_irq_msk,
281	[CNTXT_SRC_CH_IRQ]		= &reg_cntxt_src_ch_irq,
282	[CNTXT_SRC_EV_CH_IRQ]		= &reg_cntxt_src_ev_ch_irq,
283	[CNTXT_SRC_CH_IRQ_MSK]		= &reg_cntxt_src_ch_irq_msk,
284	[CNTXT_SRC_EV_CH_IRQ_MSK]	= &reg_cntxt_src_ev_ch_irq_msk,
285	[CNTXT_SRC_CH_IRQ_CLR]		= &reg_cntxt_src_ch_irq_clr,
286	[CNTXT_SRC_EV_CH_IRQ_CLR]	= &reg_cntxt_src_ev_ch_irq_clr,
287	[CNTXT_SRC_IEOB_IRQ]		= &reg_cntxt_src_ieob_irq,
288	[CNTXT_SRC_IEOB_IRQ_MSK]	= &reg_cntxt_src_ieob_irq_msk,
289	[CNTXT_SRC_IEOB_IRQ_CLR]	= &reg_cntxt_src_ieob_irq_clr,
290	[CNTXT_GLOB_IRQ_STTS]		= &reg_cntxt_glob_irq_stts,
291	[CNTXT_GLOB_IRQ_EN]		= &reg_cntxt_glob_irq_en,
292	[CNTXT_GLOB_IRQ_CLR]		= &reg_cntxt_glob_irq_clr,
293	[CNTXT_GSI_IRQ_STTS]		= &reg_cntxt_gsi_irq_stts,
294	[CNTXT_GSI_IRQ_EN]		= &reg_cntxt_gsi_irq_en,
295	[CNTXT_GSI_IRQ_CLR]		= &reg_cntxt_gsi_irq_clr,
296	[CNTXT_INTSET]			= &reg_cntxt_intset,
297	[ERROR_LOG]			= &reg_error_log,
298	[ERROR_LOG_CLR]			= &reg_error_log_clr,
299	[CNTXT_SCRATCH_0]		= &reg_cntxt_scratch_0,
300};
301
302const struct regs gsi_regs_v3_5_1 = {
303	.reg_count	= ARRAY_SIZE(reg_array),
304	.reg		= reg_array,
305};
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