txgbe_phy.c

  1// SPDX-License-Identifier: GPL-2.0
  2/* Copyright (c) 2015 - 2023 Beijing WangXun Technology Co., Ltd. */
  3
  4#include <linux/gpio/machine.h>
  5#include <linux/gpio/driver.h>
  6#include <linux/gpio/property.h>
  7#include <linux/clk-provider.h>
  8#include <linux/clkdev.h>
  9#include <linux/i2c.h>
 10#include <linux/pci.h>
 11#include <linux/platform_device.h>
 12#include <linux/regmap.h>
 13#include <linux/pcs/pcs-xpcs.h>
 14#include <linux/phylink.h>
 15
 16#include "../libwx/wx_type.h"
 17#include "../libwx/wx_lib.h"
 18#include "../libwx/wx_ptp.h"
 19#include "../libwx/wx_sriov.h"
 20#include "../libwx/wx_mbx.h"
 21#include "../libwx/wx_hw.h"
 22#include "txgbe_type.h"
 23#include "txgbe_aml.h"
 24#include "txgbe_phy.h"
 25#include "txgbe_hw.h"
 26
 27static int txgbe_swnodes_register(struct txgbe *txgbe)
 28{
 29	struct txgbe_nodes *nodes = &txgbe->nodes;
 30	struct pci_dev *pdev = txgbe->wx->pdev;
 31	struct software_node *swnodes;
 32	u32 id;
 33
 34	id = pci_dev_id(pdev);
 35
 36	snprintf(nodes->gpio_name, sizeof(nodes->gpio_name), "txgbe_gpio-%x", id);
 37	snprintf(nodes->i2c_name, sizeof(nodes->i2c_name), "txgbe_i2c-%x", id);
 38	snprintf(nodes->sfp_name, sizeof(nodes->sfp_name), "txgbe_sfp-%x", id);
 39	snprintf(nodes->phylink_name, sizeof(nodes->phylink_name), "txgbe_phylink-%x", id);
 40
 41	swnodes = nodes->swnodes;
 42
 43	/* GPIO 0: tx fault
 44	 * GPIO 1: tx disable
 45	 * GPIO 2: sfp module absent
 46	 * GPIO 3: rx signal lost
 47	 * GPIO 4: rate select, 1G(0) 10G(1)
 48	 * GPIO 5: rate select, 1G(0) 10G(1)
 49	 */
 50	nodes->gpio_props[0] = PROPERTY_ENTRY_STRING("pinctrl-names", "default");
 51	swnodes[SWNODE_GPIO] = NODE_PROP(nodes->gpio_name, nodes->gpio_props);
 52	nodes->gpio0_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 0, GPIO_ACTIVE_HIGH);
 53	nodes->gpio1_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 1, GPIO_ACTIVE_HIGH);
 54	nodes->gpio2_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 2, GPIO_ACTIVE_LOW);
 55	nodes->gpio3_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 3, GPIO_ACTIVE_HIGH);
 56	nodes->gpio4_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 4, GPIO_ACTIVE_HIGH);
 57	nodes->gpio5_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_GPIO], 5, GPIO_ACTIVE_HIGH);
 58
 59	nodes->i2c_props[0] = PROPERTY_ENTRY_STRING("compatible", "snps,designware-i2c");
 60	nodes->i2c_props[1] = PROPERTY_ENTRY_BOOL("wx,i2c-snps-model");
 61	nodes->i2c_props[2] = PROPERTY_ENTRY_U32("clock-frequency", I2C_MAX_STANDARD_MODE_FREQ);
 62	swnodes[SWNODE_I2C] = NODE_PROP(nodes->i2c_name, nodes->i2c_props);
 63	nodes->i2c_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_I2C]);
 64
 65	nodes->sfp_props[0] = PROPERTY_ENTRY_STRING("compatible", "sff,sfp");
 66	nodes->sfp_props[1] = PROPERTY_ENTRY_REF_ARRAY("i2c-bus", nodes->i2c_ref);
 67	nodes->sfp_props[2] = PROPERTY_ENTRY_REF_ARRAY("tx-fault-gpios", nodes->gpio0_ref);
 68	nodes->sfp_props[3] = PROPERTY_ENTRY_REF_ARRAY("tx-disable-gpios", nodes->gpio1_ref);
 69	nodes->sfp_props[4] = PROPERTY_ENTRY_REF_ARRAY("mod-def0-gpios", nodes->gpio2_ref);
 70	nodes->sfp_props[5] = PROPERTY_ENTRY_REF_ARRAY("los-gpios", nodes->gpio3_ref);
 71	nodes->sfp_props[6] = PROPERTY_ENTRY_REF_ARRAY("rate-select1-gpios", nodes->gpio4_ref);
 72	nodes->sfp_props[7] = PROPERTY_ENTRY_REF_ARRAY("rate-select0-gpios", nodes->gpio5_ref);
 73	swnodes[SWNODE_SFP] = NODE_PROP(nodes->sfp_name, nodes->sfp_props);
 74	nodes->sfp_ref[0] = SOFTWARE_NODE_REFERENCE(&swnodes[SWNODE_SFP]);
 75
 76	nodes->phylink_props[0] = PROPERTY_ENTRY_STRING("managed", "in-band-status");
 77	nodes->phylink_props[1] = PROPERTY_ENTRY_REF_ARRAY("sfp", nodes->sfp_ref);
 78	swnodes[SWNODE_PHYLINK] = NODE_PROP(nodes->phylink_name, nodes->phylink_props);
 79
 80	nodes->group[SWNODE_GPIO] = &swnodes[SWNODE_GPIO];
 81	nodes->group[SWNODE_I2C] = &swnodes[SWNODE_I2C];
 82	nodes->group[SWNODE_SFP] = &swnodes[SWNODE_SFP];
 83	nodes->group[SWNODE_PHYLINK] = &swnodes[SWNODE_PHYLINK];
 84
 85	return software_node_register_node_group(nodes->group);
 86}
 87
 88static int txgbe_pcs_read(struct mii_bus *bus, int addr, int devnum, int regnum)
 89{
 90	struct wx *wx  = bus->priv;
 91	u32 offset, val;
 92
 93	if (addr)
 94		return -EOPNOTSUPP;
 95
 96	offset = devnum << 16 | regnum;
 97
 98	/* Set the LAN port indicator to IDA_ADDR */
 99	wr32(wx, TXGBE_XPCS_IDA_ADDR, offset);
100
101	/* Read the data from IDA_DATA register */
102	val = rd32(wx, TXGBE_XPCS_IDA_DATA);
103
104	return (u16)val;
105}
106
107static int txgbe_pcs_write(struct mii_bus *bus, int addr, int devnum, int regnum, u16 val)
108{
109	struct wx *wx = bus->priv;
110	u32 offset;
111
112	if (addr)
113		return -EOPNOTSUPP;
114
115	offset = devnum << 16 | regnum;
116
117	/* Set the LAN port indicator to IDA_ADDR */
118	wr32(wx, TXGBE_XPCS_IDA_ADDR, offset);
119
120	/* Write the data to IDA_DATA register */
121	wr32(wx, TXGBE_XPCS_IDA_DATA, val);
122
123	return 0;
124}
125
126static int txgbe_mdio_pcs_init(struct txgbe *txgbe)
127{
128	struct mii_bus *mii_bus;
129	struct phylink_pcs *pcs;
130	struct pci_dev *pdev;
131	struct wx *wx;
132	int ret = 0;
133
134	wx = txgbe->wx;
135	pdev = wx->pdev;
136
137	mii_bus = devm_mdiobus_alloc(&pdev->dev);
138	if (!mii_bus)
139		return -ENOMEM;
140
141	mii_bus->name = "txgbe_pcs_mdio_bus";
142	mii_bus->read_c45 = &txgbe_pcs_read;
143	mii_bus->write_c45 = &txgbe_pcs_write;
144	mii_bus->parent = &pdev->dev;
145	mii_bus->phy_mask = ~0;
146	mii_bus->priv = wx;
147	snprintf(mii_bus->id, MII_BUS_ID_SIZE, "txgbe_pcs-%x",
148		 pci_dev_id(pdev));
149
150	ret = devm_mdiobus_register(&pdev->dev, mii_bus);
151	if (ret)
152		return ret;
153
154	pcs = xpcs_create_pcs_mdiodev(mii_bus, 0);
155	if (IS_ERR(pcs))
156		return PTR_ERR(pcs);
157
158	txgbe->pcs = pcs;
159
160	return 0;
161}
162
163static struct phylink_pcs *txgbe_phylink_mac_select(struct phylink_config *config,
164						    phy_interface_t interface)
165{
166	struct wx *wx = phylink_to_wx(config);
167	struct txgbe *txgbe = wx->priv;
168
169	if (wx->media_type != wx_media_copper)
170		return txgbe->pcs;
171
172	return NULL;
173}
174
175static void txgbe_mac_config(struct phylink_config *config, unsigned int mode,
176			     const struct phylink_link_state *state)
177{
178}
179
180static void txgbe_mac_link_down(struct phylink_config *config,
181				unsigned int mode, phy_interface_t interface)
182{
183	struct wx *wx = phylink_to_wx(config);
184
185	wr32m(wx, WX_MAC_TX_CFG, WX_MAC_TX_CFG_TE, 0);
186
187	wx->speed = SPEED_UNKNOWN;
188	if (test_bit(WX_STATE_PTP_RUNNING, wx->state))
189		wx_ptp_reset_cyclecounter(wx);
190	/* ping all the active vfs to let them know we are going down */
191	wx_ping_all_vfs_with_link_status(wx, false);
192}
193
194static void txgbe_mac_link_up(struct phylink_config *config,
195			      struct phy_device *phy,
196			      unsigned int mode, phy_interface_t interface,
197			      int speed, int duplex,
198			      bool tx_pause, bool rx_pause)
199{
200	struct wx *wx = phylink_to_wx(config);
201	u32 txcfg, wdg;
202
203	wx_fc_enable(wx, tx_pause, rx_pause);
204
205	txcfg = rd32(wx, WX_MAC_TX_CFG);
206	txcfg &= ~WX_MAC_TX_CFG_SPEED_MASK;
207
208	switch (speed) {
209	case SPEED_10000:
210		txcfg |= WX_MAC_TX_CFG_SPEED_10G;
211		break;
212	case SPEED_1000:
213	case SPEED_100:
214	case SPEED_10:
215		txcfg |= WX_MAC_TX_CFG_SPEED_1G;
216		break;
217	default:
218		break;
219	}
220
221	wr32(wx, WX_MAC_TX_CFG, txcfg | WX_MAC_TX_CFG_TE);
222
223	/* Re configure MAC Rx */
224	wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE);
225	wr32(wx, WX_MAC_PKT_FLT, WX_MAC_PKT_FLT_PR);
226	wdg = rd32(wx, WX_MAC_WDG_TIMEOUT);
227	wr32(wx, WX_MAC_WDG_TIMEOUT, wdg);
228
229	wx->speed = speed;
230	wx->last_rx_ptp_check = jiffies;
231	if (test_bit(WX_STATE_PTP_RUNNING, wx->state))
232		wx_ptp_reset_cyclecounter(wx);
233	/* ping all the active vfs to let them know we are going up */
234	wx_ping_all_vfs_with_link_status(wx, true);
235}
236
237static int txgbe_mac_prepare(struct phylink_config *config, unsigned int mode,
238			     phy_interface_t interface)
239{
240	struct wx *wx = phylink_to_wx(config);
241
242	wr32m(wx, WX_MAC_TX_CFG, WX_MAC_TX_CFG_TE, 0);
243	wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, 0);
244
245	return txgbe_disable_sec_tx_path(wx);
246}
247
248static int txgbe_mac_finish(struct phylink_config *config, unsigned int mode,
249			    phy_interface_t interface)
250{
251	struct wx *wx = phylink_to_wx(config);
252
253	txgbe_enable_sec_tx_path(wx);
254	wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE);
255
256	return 0;
257}
258
259static const struct phylink_mac_ops txgbe_mac_ops = {
260	.mac_select_pcs = txgbe_phylink_mac_select,
261	.mac_prepare = txgbe_mac_prepare,
262	.mac_finish = txgbe_mac_finish,
263	.mac_config = txgbe_mac_config,
264	.mac_link_down = txgbe_mac_link_down,
265	.mac_link_up = txgbe_mac_link_up,
266};
267
268static int txgbe_phylink_init(struct txgbe *txgbe)
269{
270	struct fwnode_handle *fwnode = NULL;
271	struct phylink_config *config;
272	struct wx *wx = txgbe->wx;
273	phy_interface_t phy_mode;
274	struct phylink *phylink;
275
276	config = &wx->phylink_config;
277	config->dev = &wx->netdev->dev;
278	config->type = PHYLINK_NETDEV;
279	config->mac_capabilities = MAC_10000FD | MAC_1000FD | MAC_100FD |
280				   MAC_SYM_PAUSE | MAC_ASYM_PAUSE;
281
282	if (wx->media_type == wx_media_copper) {
283		phy_mode = PHY_INTERFACE_MODE_XAUI;
284		__set_bit(PHY_INTERFACE_MODE_XAUI, config->supported_interfaces);
285	} else {
286		phy_mode = PHY_INTERFACE_MODE_10GBASER;
287		fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_PHYLINK]);
288		__set_bit(PHY_INTERFACE_MODE_10GBASER, config->supported_interfaces);
289		__set_bit(PHY_INTERFACE_MODE_1000BASEX, config->supported_interfaces);
290		__set_bit(PHY_INTERFACE_MODE_SGMII, config->supported_interfaces);
291	}
292
293	phylink = phylink_create(config, fwnode, phy_mode, &txgbe_mac_ops);
294	if (IS_ERR(phylink))
295		return PTR_ERR(phylink);
296
297	if (wx->phydev) {
298		int ret;
299
300		ret = phylink_connect_phy(phylink, wx->phydev);
301		if (ret) {
302			phylink_destroy(phylink);
303			return ret;
304		}
305	}
306
307	wx->phylink = phylink;
308
309	return 0;
310}
311
312irqreturn_t txgbe_link_irq_handler(int irq, void *data)
313{
314	struct txgbe *txgbe = data;
315	struct wx *wx = txgbe->wx;
316	u32 status;
317	bool up;
318
319	status = rd32(wx, TXGBE_CFG_PORT_ST);
320	up = !!(status & TXGBE_CFG_PORT_ST_LINK_UP);
321
322	if (txgbe->pcs)
323		phylink_pcs_change(txgbe->pcs, up);
324	else
325		phylink_mac_change(wx->phylink, up);
326
327	return IRQ_HANDLED;
328}
329
330static int txgbe_gpio_get(struct gpio_chip *chip, unsigned int offset)
331{
332	struct wx *wx = gpiochip_get_data(chip);
333	int val;
334
335	val = rd32m(wx, WX_GPIO_EXT, BIT(offset));
336
337	return !!(val & BIT(offset));
338}
339
340static int txgbe_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
341{
342	struct wx *wx = gpiochip_get_data(chip);
343	u32 val;
344
345	val = rd32(wx, WX_GPIO_DDR);
346	if (BIT(offset) & val)
347		return GPIO_LINE_DIRECTION_OUT;
348
349	return GPIO_LINE_DIRECTION_IN;
350}
351
352static int txgbe_gpio_direction_in(struct gpio_chip *chip, unsigned int offset)
353{
354	struct wx *wx = gpiochip_get_data(chip);
355	unsigned long flags;
356
357	raw_spin_lock_irqsave(&wx->gpio_lock, flags);
358	wr32m(wx, WX_GPIO_DDR, BIT(offset), 0);
359	raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
360
361	return 0;
362}
363
364static int txgbe_gpio_direction_out(struct gpio_chip *chip, unsigned int offset,
365				    int val)
366{
367	struct wx *wx = gpiochip_get_data(chip);
368	unsigned long flags;
369	u32 set;
370
371	set = val ? BIT(offset) : 0;
372
373	raw_spin_lock_irqsave(&wx->gpio_lock, flags);
374	wr32m(wx, WX_GPIO_DR, BIT(offset), set);
375	wr32m(wx, WX_GPIO_DDR, BIT(offset), BIT(offset));
376	raw_spin_unlock_irqrestore(&wx->gpio_lock, flags);
377
378	return 0;
379}
380
381static int txgbe_gpio_init(struct txgbe *txgbe)
382{
383	struct gpio_chip *gc;
384	struct device *dev;
385	struct wx *wx;
386	int ret;
387
388	wx = txgbe->wx;
389	dev = &wx->pdev->dev;
390
391	raw_spin_lock_init(&wx->gpio_lock);
392
393	gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL);
394	if (!gc)
395		return -ENOMEM;
396
397	gc->label = devm_kasprintf(dev, GFP_KERNEL, "txgbe_gpio-%x",
398				   pci_dev_id(wx->pdev));
399	if (!gc->label)
400		return -ENOMEM;
401
402	gc->base = -1;
403	gc->ngpio = 6;
404	gc->owner = THIS_MODULE;
405	gc->parent = dev;
406	gc->fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_GPIO]);
407	gc->get = txgbe_gpio_get;
408	gc->get_direction = txgbe_gpio_get_direction;
409	gc->direction_input = txgbe_gpio_direction_in;
410	gc->direction_output = txgbe_gpio_direction_out;
411
412	ret = devm_gpiochip_add_data(dev, gc, wx);
413	if (ret)
414		return ret;
415
416	txgbe->gpio = gc;
417
418	return 0;
419}
420
421static int txgbe_clock_register(struct txgbe *txgbe)
422{
423	struct pci_dev *pdev = txgbe->wx->pdev;
424	struct clk_lookup *clock;
425	char clk_name[32];
426	struct clk *clk;
427
428	snprintf(clk_name, sizeof(clk_name), "i2c_designware.%d",
429		 pci_dev_id(pdev));
430
431	clk = clk_register_fixed_rate(NULL, clk_name, NULL, 0, 156250000);
432	if (IS_ERR(clk))
433		return PTR_ERR(clk);
434
435	clock = clkdev_create(clk, NULL, "%s", clk_name);
436	if (!clock) {
437		clk_unregister(clk);
438		return -ENOMEM;
439	}
440
441	txgbe->clk = clk;
442	txgbe->clock = clock;
443
444	return 0;
445}
446
447static int txgbe_i2c_read(void *context, unsigned int reg, unsigned int *val)
448{
449	struct wx *wx = context;
450
451	*val = rd32(wx, reg + TXGBE_I2C_BASE);
452
453	return 0;
454}
455
456static int txgbe_i2c_write(void *context, unsigned int reg, unsigned int val)
457{
458	struct wx *wx = context;
459
460	wr32(wx, reg + TXGBE_I2C_BASE, val);
461
462	return 0;
463}
464
465static const struct regmap_config i2c_regmap_config = {
466	.reg_bits = 32,
467	.val_bits = 32,
468	.reg_read = txgbe_i2c_read,
469	.reg_write = txgbe_i2c_write,
470	.fast_io = true,
471};
472
473static int txgbe_i2c_register(struct txgbe *txgbe)
474{
475	struct platform_device_info info = {};
476	struct platform_device *i2c_dev;
477	struct regmap *i2c_regmap;
478	struct pci_dev *pdev;
479	struct wx *wx;
480
481	wx = txgbe->wx;
482	pdev = wx->pdev;
483	i2c_regmap = devm_regmap_init(&pdev->dev, NULL, wx, &i2c_regmap_config);
484	if (IS_ERR(i2c_regmap)) {
485		wx_err(wx, "failed to init I2C regmap\n");
486		return PTR_ERR(i2c_regmap);
487	}
488
489	info.parent = &pdev->dev;
490	info.fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_I2C]);
491	info.name = "i2c_designware";
492	info.id = pci_dev_id(pdev);
493
494	info.res = &DEFINE_RES_IRQ(pdev->irq);
495	info.num_res = 1;
496	i2c_dev = platform_device_register_full(&info);
497	if (IS_ERR(i2c_dev))
498		return PTR_ERR(i2c_dev);
499
500	txgbe->i2c_dev = i2c_dev;
501
502	return 0;
503}
504
505static int txgbe_sfp_register(struct txgbe *txgbe)
506{
507	struct pci_dev *pdev = txgbe->wx->pdev;
508	struct platform_device_info info = {};
509	struct platform_device *sfp_dev;
510
511	info.parent = &pdev->dev;
512	info.fwnode = software_node_fwnode(txgbe->nodes.group[SWNODE_SFP]);
513	info.name = "sfp";
514	info.id = pci_dev_id(pdev);
515	sfp_dev = platform_device_register_full(&info);
516	if (IS_ERR(sfp_dev))
517		return PTR_ERR(sfp_dev);
518
519	txgbe->sfp_dev = sfp_dev;
520
521	return 0;
522}
523
524static int txgbe_ext_phy_init(struct txgbe *txgbe)
525{
526	struct phy_device *phydev;
527	struct mii_bus *mii_bus;
528	struct pci_dev *pdev;
529	struct wx *wx;
530	int ret = 0;
531
532	wx = txgbe->wx;
533	pdev = wx->pdev;
534
535	mii_bus = devm_mdiobus_alloc(&pdev->dev);
536	if (!mii_bus)
537		return -ENOMEM;
538
539	mii_bus->name = "txgbe_mii_bus";
540	mii_bus->read_c45 = &wx_phy_read_reg_mdi_c45;
541	mii_bus->write_c45 = &wx_phy_write_reg_mdi_c45;
542	mii_bus->parent = &pdev->dev;
543	mii_bus->phy_mask = GENMASK(31, 1);
544	mii_bus->priv = wx;
545	snprintf(mii_bus->id, MII_BUS_ID_SIZE, "txgbe-%x", pci_dev_id(pdev));
546
547	ret = devm_mdiobus_register(&pdev->dev, mii_bus);
548	if (ret) {
549		wx_err(wx, "failed to register MDIO bus: %d\n", ret);
550		return ret;
551	}
552
553	phydev = phy_find_first(mii_bus);
554	if (!phydev) {
555		wx_err(wx, "no PHY found\n");
556		return -ENODEV;
557	}
558
559	phy_attached_info(phydev);
560
561	wx->link = 0;
562	wx->speed = 0;
563	wx->duplex = 0;
564	wx->phydev = phydev;
565
566	ret = txgbe_phylink_init(txgbe);
567	if (ret) {
568		wx_err(wx, "failed to init phylink: %d\n", ret);
569		return ret;
570	}
571
572	return 0;
573}
574
575int txgbe_init_phy(struct txgbe *txgbe)
576{
577	struct wx *wx = txgbe->wx;
578	int ret;
579
580	switch (wx->mac.type) {
581	case wx_mac_aml40:
582	case wx_mac_aml:
583		return txgbe_phylink_init_aml(txgbe);
584	case wx_mac_sp:
585		if (wx->media_type == wx_media_copper)
586			return txgbe_ext_phy_init(txgbe);
587		break;
588	default:
589		break;
590	}
591
592	ret = txgbe_swnodes_register(txgbe);
593	if (ret) {
594		wx_err(wx, "failed to register software nodes\n");
595		return ret;
596	}
597
598	ret = txgbe_mdio_pcs_init(txgbe);
599	if (ret) {
600		wx_err(wx, "failed to init mdio pcs: %d\n", ret);
601		goto err_unregister_swnode;
602	}
603
604	ret = txgbe_phylink_init(txgbe);
605	if (ret) {
606		wx_err(wx, "failed to init phylink\n");
607		goto err_destroy_xpcs;
608	}
609
610	ret = txgbe_gpio_init(txgbe);
611	if (ret) {
612		wx_err(wx, "failed to init gpio\n");
613		goto err_destroy_phylink;
614	}
615
616	ret = txgbe_clock_register(txgbe);
617	if (ret) {
618		wx_err(wx, "failed to register clock: %d\n", ret);
619		goto err_destroy_phylink;
620	}
621
622	ret = txgbe_i2c_register(txgbe);
623	if (ret) {
624		wx_err(wx, "failed to init i2c interface: %d\n", ret);
625		goto err_unregister_clk;
626	}
627
628	ret = txgbe_sfp_register(txgbe);
629	if (ret) {
630		wx_err(wx, "failed to register sfp\n");
631		goto err_unregister_i2c;
632	}
633
634	return 0;
635
636err_unregister_i2c:
637	platform_device_unregister(txgbe->i2c_dev);
638err_unregister_clk:
639	clkdev_drop(txgbe->clock);
640	clk_unregister(txgbe->clk);
641err_destroy_phylink:
642	phylink_destroy(wx->phylink);
643err_destroy_xpcs:
644	xpcs_destroy_pcs(txgbe->pcs);
645err_unregister_swnode:
646	software_node_unregister_node_group(txgbe->nodes.group);
647
648	return ret;
649}
650
651void txgbe_remove_phy(struct txgbe *txgbe)
652{
653	switch (txgbe->wx->mac.type) {
654	case wx_mac_aml40:
655	case wx_mac_aml:
656		phylink_destroy(txgbe->wx->phylink);
657		return;
658	case wx_mac_sp:
659		if (txgbe->wx->media_type == wx_media_copper) {
660			phylink_disconnect_phy(txgbe->wx->phylink);
661			phylink_destroy(txgbe->wx->phylink);
662			return;
663		}
664		break;
665	default:
666		break;
667	}
668
669	platform_device_unregister(txgbe->sfp_dev);
670	platform_device_unregister(txgbe->i2c_dev);
671	clkdev_drop(txgbe->clock);
672	clk_unregister(txgbe->clk);
673	phylink_destroy(txgbe->wx->phylink);
674	xpcs_destroy_pcs(txgbe->pcs);
675	software_node_unregister_node_group(txgbe->nodes.group);
676}