ngbe_type.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Copyright (c) 2019 - 2022 Beijing WangXun Technology Co., Ltd. */
  3
  4#ifndef _NGBE_TYPE_H_
  5#define _NGBE_TYPE_H_
  6
  7#include <linux/types.h>
  8#include <linux/netdevice.h>
  9
 10/************ NGBE_register.h ************/
 11/* Device IDs */
 12#define NGBE_DEV_ID_EM_WX1860AL_W		0x0100
 13#define NGBE_DEV_ID_EM_WX1860A2			0x0101
 14#define NGBE_DEV_ID_EM_WX1860A2S		0x0102
 15#define NGBE_DEV_ID_EM_WX1860A4			0x0103
 16#define NGBE_DEV_ID_EM_WX1860A4S		0x0104
 17#define NGBE_DEV_ID_EM_WX1860AL2		0x0105
 18#define NGBE_DEV_ID_EM_WX1860AL2S		0x0106
 19#define NGBE_DEV_ID_EM_WX1860AL4		0x0107
 20#define NGBE_DEV_ID_EM_WX1860AL4S		0x0108
 21#define NGBE_DEV_ID_EM_WX1860LC			0x0109
 22#define NGBE_DEV_ID_EM_WX1860A1			0x010a
 23#define NGBE_DEV_ID_EM_WX1860A1L		0x010b
 24
 25/* Subsystem ID */
 26#define NGBE_SUBID_M88E1512_SFP			0x0003
 27#define NGBE_SUBID_OCP_CARD			0x0040
 28#define NGBE_SUBID_LY_M88E1512_SFP		0x0050
 29#define NGBE_SUBID_M88E1512_RJ45		0x0051
 30#define NGBE_SUBID_M88E1512_MIX			0x0052
 31#define NGBE_SUBID_YT8521S_SFP			0x0060
 32#define NGBE_SUBID_INTERNAL_YT8521S_SFP		0x0061
 33#define NGBE_SUBID_YT8521S_SFP_GPIO		0x0062
 34#define NGBE_SUBID_INTERNAL_YT8521S_SFP_GPIO	0x0064
 35#define NGBE_SUBID_LY_YT8521S_SFP		0x0070
 36#define NGBE_SUBID_RGMII_FPGA			0x0080
 37
 38#define NGBE_OEM_MASK				0x00FF
 39
 40#define NGBE_NCSI_SUP				0x8000
 41#define NGBE_NCSI_MASK				0x8000
 42#define NGBE_WOL_SUP				0x4000
 43#define NGBE_WOL_MASK				0x4000
 44
 45/**************** EM Registers ****************************/
 46/* chip control Registers */
 47#define NGBE_MIS_PRB_CTL			0x10010
 48/* FMGR Registers */
 49#define NGBE_SPI_ILDR_STATUS			0x10120
 50#define NGBE_SPI_ILDR_STATUS_PERST		BIT(0) /* PCIE_PERST is done */
 51#define NGBE_SPI_ILDR_STATUS_PWRRST		BIT(1) /* Power on reset is done */
 52
 53/* Checksum and EEPROM pointers */
 54#define NGBE_CALSUM_COMMAND			0xE9
 55#define NGBE_CALSUM_CAP_STATUS			0x10224
 56#define NGBE_EEPROM_VERSION_STORE_REG		0x1022C
 57#define NGBE_SAN_MAC_ADDR_PTR			0x18
 58#define NGBE_DEVICE_CAPS			0x1C
 59#define NGBE_EEPROM_VERSION_L			0x1D
 60#define NGBE_EEPROM_VERSION_H			0x1E
 61
 62/* GPIO Registers */
 63#define NGBE_GPIO_DR				0x14800
 64#define NGBE_GPIO_DDR				0x14804
 65/*GPIO bit */
 66#define NGBE_GPIO_DR_0				BIT(0) /* SDP0 Data Value */
 67#define NGBE_GPIO_DR_1				BIT(1) /* SDP1 Data Value */
 68#define NGBE_GPIO_DDR_0				BIT(0) /* SDP0 IO direction */
 69#define NGBE_GPIO_DDR_1				BIT(1) /* SDP1 IO direction */
 70
 71/* Extended Interrupt Enable Set */
 72#define NGBE_PX_MISC_IEN_DEV_RST		BIT(10)
 73#define NGBE_PX_MISC_IEN_TIMESYNC		BIT(11)
 74#define NGBE_PX_MISC_IEN_ETH_LK			BIT(18)
 75#define NGBE_PX_MISC_IEN_INT_ERR		BIT(20)
 76#define NGBE_PX_MISC_IC_VF_MBOX			BIT(23)
 77#define NGBE_PX_MISC_IEN_GPIO			BIT(26)
 78#define NGBE_PX_MISC_IEN_MASK ( \
 79				NGBE_PX_MISC_IEN_DEV_RST | \
 80				NGBE_PX_MISC_IEN_TIMESYNC | \
 81				NGBE_PX_MISC_IEN_ETH_LK | \
 82				NGBE_PX_MISC_IEN_INT_ERR | \
 83				NGBE_PX_MISC_IC_VF_MBOX | \
 84				NGBE_PX_MISC_IEN_GPIO)
 85
 86/* Extended Interrupt Cause Read */
 87#define NGBE_PX_MISC_IC_TIMESYNC		BIT(11) /* time sync */
 88
 89#define NGBE_INTR_ALL				0x1FF
 90#define NGBE_INTR_MISC(A)			BIT((A)->msix_entry->entry)
 91
 92#define NGBE_PHY_CONFIG(reg_offset)		(0x14000 + ((reg_offset) * 4))
 93#define NGBE_CFG_LAN_SPEED			0x14440
 94#define NGBE_CFG_PORT_ST			0x14404
 95
 96/* Wake up registers */
 97#define NGBE_PSR_WKUP_CTL			0x15B80
 98/* Wake Up Filter Control Bit */
 99#define NGBE_PSR_WKUP_CTL_LNKC			BIT(0) /* Link Status Change Wakeup Enable*/
100#define NGBE_PSR_WKUP_CTL_MAG			BIT(1) /* Magic Packet Wakeup Enable */
101#define NGBE_PSR_WKUP_CTL_EX			BIT(2) /* Directed Exact Wakeup Enable */
102#define NGBE_PSR_WKUP_CTL_MC			BIT(3) /* Directed Multicast Wakeup Enable*/
103#define NGBE_PSR_WKUP_CTL_BC			BIT(4) /* Broadcast Wakeup Enable */
104#define NGBE_PSR_WKUP_CTL_ARP			BIT(5) /* ARP Request Packet Wakeup Enable*/
105#define NGBE_PSR_WKUP_CTL_IPV4			BIT(6) /* Directed IPv4 Pkt Wakeup Enable */
106#define NGBE_PSR_WKUP_CTL_IPV6			BIT(7) /* Directed IPv6 Pkt Wakeup Enable */
107
108#define NGBE_FW_EEPROM_CHECKSUM_CMD		0xE9
109#define NGBE_FW_NVM_DATA_OFFSET			3
110#define NGBE_FW_CMD_DEFAULT_CHECKSUM		0xFF /* checksum always 0xFF */
111#define NGBE_FW_CMD_ST_PASS			0x80658383
112#define NGBE_FW_CMD_ST_FAIL			0x70657376
113
114#define NGBE_MAX_FDIR_INDICES			7
115#define NGBE_MAX_RSS_INDICES			8
116
117#define NGBE_MAX_RX_QUEUES			(NGBE_MAX_FDIR_INDICES + 1)
118#define NGBE_MAX_TX_QUEUES			(NGBE_MAX_FDIR_INDICES + 1)
119
120#define NGBE_ETH_LENGTH_OF_ADDRESS		6
121#define NGBE_MAX_MSIX_VECTORS			0x09
122#define NGBE_RAR_ENTRIES			32
123#define NGBE_RX_PB_SIZE				42
124#define NGBE_MC_TBL_SIZE			128
125#define NGBE_SP_VFT_TBL_SIZE			128
126#define NGBE_TDB_PB_SZ				(20 * 1024) /* 160KB Packet Buffer */
127
128/* TX/RX descriptor defines */
129#define NGBE_DEFAULT_TXD			512 /* default ring size */
130#define NGBE_DEFAULT_TX_WORK			256
131#define NGBE_MAX_TXD				8192
132#define NGBE_MIN_TXD				128
133
134#define NGBE_DEFAULT_RXD			512 /* default ring size */
135#define NGBE_DEFAULT_RX_WORK			256
136#define NGBE_MAX_RXD				8192
137#define NGBE_MIN_RXD				128
138
139#define NGBE_MAX_VFS_DRV_LIMIT			7
140extern char ngbe_driver_name[];
141
142void ngbe_down(struct wx *wx);
143void ngbe_up(struct wx *wx);
144int ngbe_setup_tc(struct net_device *dev, u8 tc);
145
146#endif /* _NGBE_TYPE_H_ */