wx_vf.h

  1/* SPDX-License-Identifier: GPL-2.0 */
  2/* Copyright (c) 2015 - 2025 Beijing WangXun Technology Co., Ltd. */
  3
  4#ifndef _WX_VF_H_
  5#define _WX_VF_H_
  6
  7/* Control registers */
  8#define WX_VF_MAX_RING_NUMS      8
  9#define WX_VX_PF_BME             0x4B8
 10#define WX_VF_BME_ENABLE         BIT(0)
 11#define WX_VXSTATUS              0x4
 12#define WX_VXCTRL                0x8
 13#define WX_VXCTRL_RST            BIT(0)
 14
 15#define WX_VXMRQC                0x78
 16#define WX_VXMRQC_PSR_L4HDR      BIT(0)
 17#define WX_VXMRQC_PSR_L3HDR      BIT(1)
 18#define WX_VXMRQC_PSR_L2HDR      BIT(2)
 19#define WX_VXMRQC_PSR_TUNHDR     BIT(3)
 20#define WX_VXMRQC_PSR_TUNMAC     BIT(4)
 21#define WX_VXMRQC_PSR_MASK       GENMASK(5, 1)
 22#define WX_VXMRQC_PSR(f)         FIELD_PREP(GENMASK(5, 1), f)
 23#define WX_VXMRQC_RSS_HASH(f)    FIELD_PREP(GENMASK(15, 13), f)
 24#define WX_VXMRQC_RSS_MASK       GENMASK(31, 16)
 25#define WX_VXMRQC_RSS(f)         FIELD_PREP(GENMASK(31, 16), f)
 26#define WX_VXMRQC_RSS_ALG_IPV4_TCP   BIT(0)
 27#define WX_VXMRQC_RSS_ALG_IPV4       BIT(1)
 28#define WX_VXMRQC_RSS_ALG_IPV6       BIT(4)
 29#define WX_VXMRQC_RSS_ALG_IPV6_TCP   BIT(5)
 30#define WX_VXMRQC_RSS_EN             BIT(8)
 31
 32#define WX_VXRSSRK(i)            (0x80 + ((i) * 4)) /* i=[0,9] */
 33#define WX_VXRETA(i)             (0xC0 + ((i) * 4)) /* i=[0,15] */
 34
 35/* Interrupt registers */
 36#define WX_VXICR                 0x100
 37#define WX_VXIMS                 0x108
 38#define WX_VXIMC                 0x10C
 39#define WX_VF_IRQ_CLEAR_MASK     7
 40#define WX_VF_MAX_TX_QUEUES      4
 41#define WX_VF_MAX_RX_QUEUES      4
 42
 43#define WX_VXITR(i)              (0x200 + (4 * (i))) /* i=[0,1] */
 44#define WX_VXITR_MASK            GENMASK(8, 0)
 45#define WX_VXITR_CNT_WDIS        BIT(31)
 46#define WX_VXIVAR_MISC           0x260
 47#define WX_VXIVAR(i)             (0x240 + (4 * (i))) /* i=[0,3] */
 48
 49#define wx_conf_size(v, mwidth, uwidth) ({ \
 50	typeof(v) _v = (v); \
 51	(_v == 2 << (mwidth) ? 0 : _v >> (uwidth)); \
 52})
 53#define wx_buf_len(v)            wx_conf_size(v, 13, 7)
 54#define wx_hdr_sz(v)             wx_conf_size(v, 10, 6)
 55#define wx_buf_sz(v)             wx_conf_size(v, 14, 10)
 56#define wx_pkt_thresh(v)         wx_conf_size(v, 4, 0)
 57
 58#define WX_RX_HDR_SIZE           256
 59#define WX_RX_BUF_SIZE           2048
 60
 61#define WX_RXBUFFER_2048         (2048)
 62#define WX_RXBUFFER_3072         3072
 63
 64/* Receive Path */
 65#define WX_VXRDBAL(r)            (0x1000 + (0x40 * (r)))
 66#define WX_VXRDBAH(r)            (0x1004 + (0x40 * (r)))
 67#define WX_VXRDT(r)              (0x1008 + (0x40 * (r)))
 68#define WX_VXRDH(r)              (0x100C + (0x40 * (r)))
 69#define WX_VXRXDCTL(r)           (0x1010 + (0x40 * (r)))
 70#define WX_VXRXDCTL_ENABLE       BIT(0)
 71#define WX_VXRXDCTL_BUFLEN_MASK  GENMASK(6, 1)
 72#define WX_VXRXDCTL_BUFLEN(f)    FIELD_PREP(GENMASK(6, 1), f)
 73#define WX_VXRXDCTL_BUFSZ_MASK   GENMASK(11, 8)
 74#define WX_VXRXDCTL_BUFSZ(f)     FIELD_PREP(GENMASK(11, 8), f)
 75#define WX_VXRXDCTL_HDRSZ_MASK   GENMASK(15, 12)
 76#define WX_VXRXDCTL_HDRSZ(f)     FIELD_PREP(GENMASK(15, 12), f)
 77#define WX_VXRXDCTL_DESC_MERGE   BIT(19)
 78#define WX_VXRXDCTL_RSCMAX_MASK  GENMASK(24, 23)
 79#define WX_VXRXDCTL_RSCMAX(f)    FIELD_PREP(GENMASK(24, 23), f)
 80#define WX_VXRXDCTL_RSCEN        BIT(29)
 81#define WX_VXRXDCTL_DROP         BIT(30)
 82#define WX_VXRXDCTL_VLAN         BIT(31)
 83
 84/* Transimit Path */
 85#define WX_VXTDBAL(r)            (0x3000 + (0x40 * (r)))
 86#define WX_VXTDBAH(r)            (0x3004 + (0x40 * (r)))
 87#define WX_VXTDT(r)              (0x3008 + (0x40 * (r)))
 88#define WX_VXTDH(r)              (0x300C + (0x40 * (r)))
 89#define WX_VXTXDCTL(r)           (0x3010 + (0x40 * (r)))
 90#define WX_VXTXDCTL_ENABLE       BIT(0)
 91#define WX_VXTXDCTL_BUFLEN(f)    FIELD_PREP(GENMASK(6, 1), f)
 92#define WX_VXTXDCTL_PTHRESH(f)   FIELD_PREP(GENMASK(11, 8), f)
 93#define WX_VXTXDCTL_WTHRESH(f)   FIELD_PREP(GENMASK(22, 16), f)
 94#define WX_VXTXDCTL_FLUSH        BIT(26)
 95#define WX_VXTXDCTL_HEAD_WB      BIT(27)
 96#define WX_VXTXD_HEAD_ADDRL(r)   (0x3028 + (0x40 * (r)))
 97#define WX_VXTXD_HEAD_ADDRH(r)   (0x302C + (0x40 * (r)))
 98
 99#define WX_PFLINK_STATUS(g)      FIELD_GET(BIT(0), g)
100#define WX_PFLINK_SPEED(g)       FIELD_GET(GENMASK(31, 1), g)
101#define WX_VXSTATUS_SPEED(g)     FIELD_GET(GENMASK(4, 1), g)
102
103struct wx_link_reg_fields {
104	u32 mac_type;
105	u32 bit0_f;
106	u32 bit1_f;
107	u32 bit2_f;
108	u32 bit3_f;
109	u32 bit4_f;
110};
111
112void wx_init_hw_vf(struct wx *wx);
113int wx_reset_hw_vf(struct wx *wx);
114void wx_get_mac_addr_vf(struct wx *wx, u8 *mac_addr);
115void wx_stop_adapter_vf(struct wx *wx);
116int wx_get_fw_version_vf(struct wx *wx);
117int wx_set_rar_vf(struct wx *wx, u32 index, u8 *addr, u32 enable_addr);
118int wx_update_mc_addr_list_vf(struct wx *wx, struct net_device *netdev);
119int wx_set_uc_addr_vf(struct wx *wx, u32 index, u8 *addr);
120int wx_rlpml_set_vf(struct wx *wx, u16 max_size);
121int wx_negotiate_api_version(struct wx *wx, int api);
122int wx_get_queues_vf(struct wx *wx, u32 *num_tcs, u32 *default_tc);
123int wx_update_xcast_mode_vf(struct wx *wx, int xcast_mode);
124int wx_get_link_state_vf(struct wx *wx, u16 *link_state);
125int wx_set_vfta_vf(struct wx *wx, u32 vlan, u32 vind, bool vlan_on,
126		   bool vlvf_bypass);
127int wx_check_mac_link_vf(struct wx *wx);
128
129#endif /* _WX_VF_H_ */