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wx_hw.c
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linux-6.19.14/drivers/net/ethernet/wangxun/libwx/wx_hw.c
1// SPDX-License-Identifier: GPL-2.0 2/* Copyright (c) 2015 - 2022 Beijing WangXun Technology Co., Ltd. */ 3 4#include <linux/etherdevice.h> 5#include <linux/netdevice.h> 6#include <linux/if_ether.h> 7#include <linux/if_vlan.h> 8#include <linux/iopoll.h> 9#include <linux/pci.h> 10 11#include "wx_type.h" 12#include "wx_lib.h" 13#include "wx_sriov.h" 14#include "wx_vf.h" 15#include "wx_hw.h" 16 17static int wx_phy_read_reg_mdi(struct mii_bus *bus, int phy_addr, int devnum, int regnum) 18{ 19 struct wx *wx = bus->priv; 20 u32 command, val; 21 int ret; 22 23 /* setup and write the address cycle command */ 24 command = WX_MSCA_RA(regnum) | 25 WX_MSCA_PA(phy_addr) | 26 WX_MSCA_DA(devnum); 27 wr32(wx, WX_MSCA, command); 28 29 command = WX_MSCC_CMD(WX_MSCA_CMD_READ) | WX_MSCC_BUSY; 30 if (wx->mac.type == wx_mac_em) 31 command |= WX_MDIO_CLK(6); 32 wr32(wx, WX_MSCC, command); 33 34 /* wait to complete */ 35 ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000, 36 100000, false, wx, WX_MSCC); 37 if (ret) { 38 wx_err(wx, "Mdio read c22 command did not complete.\n"); 39 return ret; 40 } 41 42 return (u16)rd32(wx, WX_MSCC); 43} 44 45static int wx_phy_write_reg_mdi(struct mii_bus *bus, int phy_addr, 46 int devnum, int regnum, u16 value) 47{ 48 struct wx *wx = bus->priv; 49 u32 command, val; 50 int ret; 51 52 /* setup and write the address cycle command */ 53 command = WX_MSCA_RA(regnum) | 54 WX_MSCA_PA(phy_addr) | 55 WX_MSCA_DA(devnum); 56 wr32(wx, WX_MSCA, command); 57 58 command = value | WX_MSCC_CMD(WX_MSCA_CMD_WRITE) | WX_MSCC_BUSY; 59 if (wx->mac.type == wx_mac_em) 60 command |= WX_MDIO_CLK(6); 61 wr32(wx, WX_MSCC, command); 62 63 /* wait to complete */ 64 ret = read_poll_timeout(rd32, val, !(val & WX_MSCC_BUSY), 1000, 65 100000, false, wx, WX_MSCC); 66 if (ret) 67 wx_err(wx, "Mdio write c22 command did not complete.\n"); 68 69 return ret; 70} 71 72int wx_phy_read_reg_mdi_c22(struct mii_bus *bus, int phy_addr, int regnum) 73{ 74 struct wx *wx = bus->priv; 75 76 wr32(wx, WX_MDIO_CLAUSE_SELECT, 0xF); 77 return wx_phy_read_reg_mdi(bus, phy_addr, 0, regnum); 78} 79EXPORT_SYMBOL(wx_phy_read_reg_mdi_c22); 80 81int wx_phy_write_reg_mdi_c22(struct mii_bus *bus, int phy_addr, int regnum, u16 value) 82{ 83 struct wx *wx = bus->priv; 84 85 wr32(wx, WX_MDIO_CLAUSE_SELECT, 0xF); 86 return wx_phy_write_reg_mdi(bus, phy_addr, 0, regnum, value); 87} 88EXPORT_SYMBOL(wx_phy_write_reg_mdi_c22); 89 90int wx_phy_read_reg_mdi_c45(struct mii_bus *bus, int phy_addr, int devnum, int regnum) 91{ 92 struct wx *wx = bus->priv; 93 94 wr32(wx, WX_MDIO_CLAUSE_SELECT, 0); 95 return wx_phy_read_reg_mdi(bus, phy_addr, devnum, regnum); 96} 97EXPORT_SYMBOL(wx_phy_read_reg_mdi_c45); 98 99int wx_phy_write_reg_mdi_c45(struct mii_bus *bus, int phy_addr, 100 int devnum, int regnum, u16 value) 101{ 102 struct wx *wx = bus->priv; 103 104 wr32(wx, WX_MDIO_CLAUSE_SELECT, 0); 105 return wx_phy_write_reg_mdi(bus, phy_addr, devnum, regnum, value); 106} 107EXPORT_SYMBOL(wx_phy_write_reg_mdi_c45); 108 109static void wx_intr_disable(struct wx *wx, u64 qmask) 110{ 111 u32 mask; 112 113 mask = (qmask & U32_MAX); 114 if (mask) 115 wr32(wx, WX_PX_IMS(0), mask); 116 117 if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) { 118 mask = (qmask >> 32); 119 if (mask) 120 wr32(wx, WX_PX_IMS(1), mask); 121 } 122} 123 124void wx_intr_enable(struct wx *wx, u64 qmask) 125{ 126 u32 mask; 127 128 if (wx->pdev->is_virtfn) { 129 wr32(wx, WX_VXIMC, qmask); 130 return; 131 } 132 133 mask = (qmask & U32_MAX); 134 if (mask) 135 wr32(wx, WX_PX_IMC(0), mask); 136 137 if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) { 138 mask = (qmask >> 32); 139 if (mask) 140 wr32(wx, WX_PX_IMC(1), mask); 141 } 142} 143EXPORT_SYMBOL(wx_intr_enable); 144 145/** 146 * wx_irq_disable - Mask off interrupt generation on the NIC 147 * @wx: board private structure 148 **/ 149void wx_irq_disable(struct wx *wx) 150{ 151 struct pci_dev *pdev = wx->pdev; 152 153 wr32(wx, WX_PX_MISC_IEN, 0); 154 wx_intr_disable(wx, WX_INTR_ALL); 155 156 if (pdev->msix_enabled) { 157 int vector; 158 159 for (vector = 0; vector < wx->num_q_vectors; vector++) 160 synchronize_irq(wx->msix_q_entries[vector].vector); 161 162 synchronize_irq(wx->msix_entry->vector); 163 } else { 164 synchronize_irq(pdev->irq); 165 } 166} 167EXPORT_SYMBOL(wx_irq_disable); 168 169/* cmd_addr is used for some special command: 170 * 1. to be sector address, when implemented erase sector command 171 * 2. to be flash address when implemented read, write flash address 172 */ 173static int wx_fmgr_cmd_op(struct wx *wx, u32 cmd, u32 cmd_addr) 174{ 175 u32 cmd_val = 0, val = 0; 176 177 cmd_val = WX_SPI_CMD_CMD(cmd) | 178 WX_SPI_CMD_CLK(WX_SPI_CLK_DIV) | 179 cmd_addr; 180 wr32(wx, WX_SPI_CMD, cmd_val); 181 182 return read_poll_timeout(rd32, val, (val & 0x1), 10, 100000, 183 false, wx, WX_SPI_STATUS); 184} 185 186static int wx_flash_read_dword(struct wx *wx, u32 addr, u32 *data) 187{ 188 int ret = 0; 189 190 ret = wx_fmgr_cmd_op(wx, WX_SPI_CMD_READ_DWORD, addr); 191 if (ret < 0) 192 return ret; 193 194 *data = rd32(wx, WX_SPI_DATA); 195 196 return ret; 197} 198 199int wx_check_flash_load(struct wx *hw, u32 check_bit) 200{ 201 u32 reg = 0; 202 int err = 0; 203 204 /* if there's flash existing */ 205 if (!(rd32(hw, WX_SPI_STATUS) & 206 WX_SPI_STATUS_FLASH_BYPASS)) { 207 /* wait hw load flash done */ 208 err = read_poll_timeout(rd32, reg, !(reg & check_bit), 20000, 2000000, 209 false, hw, WX_SPI_ILDR_STATUS); 210 if (err < 0) 211 wx_err(hw, "Check flash load timeout.\n"); 212 } 213 214 return err; 215} 216EXPORT_SYMBOL(wx_check_flash_load); 217 218void wx_control_hw(struct wx *wx, bool drv) 219{ 220 /* True : Let firmware know the driver has taken over 221 * False : Let firmware take over control of hw 222 */ 223 wr32m(wx, WX_CFG_PORT_CTL, WX_CFG_PORT_CTL_DRV_LOAD, 224 drv ? WX_CFG_PORT_CTL_DRV_LOAD : 0); 225} 226EXPORT_SYMBOL(wx_control_hw); 227 228/** 229 * wx_mng_present - returns 0 when management capability is present 230 * @wx: pointer to hardware structure 231 */ 232int wx_mng_present(struct wx *wx) 233{ 234 u32 fwsm; 235 236 fwsm = rd32(wx, WX_MIS_ST); 237 if (fwsm & WX_MIS_ST_MNG_INIT_DN) 238 return 0; 239 else 240 return -EACCES; 241} 242EXPORT_SYMBOL(wx_mng_present); 243 244/* Software lock to be held while software semaphore is being accessed. */ 245static DEFINE_MUTEX(wx_sw_sync_lock); 246 247/** 248 * wx_release_sw_sync - Release SW semaphore 249 * @wx: pointer to hardware structure 250 * @mask: Mask to specify which semaphore to release 251 * 252 * Releases the SW semaphore for the specified 253 * function (CSR, PHY0, PHY1, EEPROM, Flash) 254 **/ 255static void wx_release_sw_sync(struct wx *wx, u32 mask) 256{ 257 mutex_lock(&wx_sw_sync_lock); 258 wr32m(wx, WX_MNG_SWFW_SYNC, mask, 0); 259 mutex_unlock(&wx_sw_sync_lock); 260} 261 262/** 263 * wx_acquire_sw_sync - Acquire SW semaphore 264 * @wx: pointer to hardware structure 265 * @mask: Mask to specify which semaphore to acquire 266 * 267 * Acquires the SW semaphore for the specified 268 * function (CSR, PHY0, PHY1, EEPROM, Flash) 269 **/ 270static int wx_acquire_sw_sync(struct wx *wx, u32 mask) 271{ 272 u32 sem = 0; 273 int ret = 0; 274 275 mutex_lock(&wx_sw_sync_lock); 276 ret = read_poll_timeout(rd32, sem, !(sem & mask), 277 5000, 2000000, false, wx, WX_MNG_SWFW_SYNC); 278 if (!ret) { 279 sem |= mask; 280 wr32(wx, WX_MNG_SWFW_SYNC, sem); 281 } else { 282 wx_err(wx, "SW Semaphore not granted: 0x%x.\n", sem); 283 } 284 mutex_unlock(&wx_sw_sync_lock); 285 286 return ret; 287} 288 289static int wx_host_interface_command_s(struct wx *wx, u32 *buffer, 290 u32 length, u32 timeout, bool return_data) 291{ 292 u32 hdr_size = sizeof(struct wx_hic_hdr); 293 u32 hicr, i, bi, buf[64] = {}; 294 int status = 0; 295 u32 dword_len; 296 u16 buf_len; 297 298 status = wx_acquire_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_MB); 299 if (status != 0) 300 return status; 301 302 dword_len = length >> 2; 303 304 /* The device driver writes the relevant command block 305 * into the ram area. 306 */ 307 for (i = 0; i < dword_len; i++) { 308 wr32a(wx, WX_MNG_MBOX, i, (__force u32)cpu_to_le32(buffer[i])); 309 /* write flush */ 310 buf[i] = rd32a(wx, WX_MNG_MBOX, i); 311 } 312 /* Setting this bit tells the ARC that a new command is pending. */ 313 wr32m(wx, WX_MNG_MBOX_CTL, 314 WX_MNG_MBOX_CTL_SWRDY, WX_MNG_MBOX_CTL_SWRDY); 315 316 status = read_poll_timeout(rd32, hicr, hicr & WX_MNG_MBOX_CTL_FWRDY, 1000, 317 timeout * 1000, false, wx, WX_MNG_MBOX_CTL); 318 319 buf[0] = rd32(wx, WX_MNG_MBOX); 320 if ((buf[0] & 0xff0000) >> 16 == 0x80) { 321 wx_err(wx, "Unknown FW command: 0x%x\n", buffer[0] & 0xff); 322 status = -EINVAL; 323 goto rel_out; 324 } 325 326 /* Check command completion */ 327 if (status) { 328 wx_err(wx, "Command has failed with no status valid.\n"); 329 wx_dbg(wx, "write value:\n"); 330 for (i = 0; i < dword_len; i++) 331 wx_dbg(wx, "%x ", buffer[i]); 332 wx_dbg(wx, "read value:\n"); 333 for (i = 0; i < dword_len; i++) 334 wx_dbg(wx, "%x ", buf[i]); 335 wx_dbg(wx, "\ncheck: %x %x\n", buffer[0] & 0xff, ~buf[0] >> 24); 336 337 goto rel_out; 338 } 339 340 if (!return_data) 341 goto rel_out; 342 343 /* Calculate length in DWORDs */ 344 dword_len = hdr_size >> 2; 345 346 /* first pull in the header so we know the buffer length */ 347 for (bi = 0; bi < dword_len; bi++) { 348 buffer[bi] = rd32a(wx, WX_MNG_MBOX, bi); 349 le32_to_cpus(&buffer[bi]); 350 } 351 352 /* If there is any thing in data position pull it in */ 353 buf_len = ((struct wx_hic_hdr *)buffer)->buf_len; 354 if (buf_len == 0) 355 goto rel_out; 356 357 if (length < buf_len + hdr_size) { 358 wx_err(wx, "Buffer not large enough for reply message.\n"); 359 status = -EFAULT; 360 goto rel_out; 361 } 362 363 /* Calculate length in DWORDs, add 3 for odd lengths */ 364 dword_len = (buf_len + 3) >> 2; 365 366 /* Pull in the rest of the buffer (bi is where we left off) */ 367 for (; bi <= dword_len; bi++) { 368 buffer[bi] = rd32a(wx, WX_MNG_MBOX, bi); 369 le32_to_cpus(&buffer[bi]); 370 } 371 372rel_out: 373 wx_release_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_MB); 374 return status; 375} 376 377static bool wx_poll_fw_reply(struct wx *wx, u32 *buffer, u8 send_cmd) 378{ 379 u32 dword_len = sizeof(struct wx_hic_hdr) >> 2; 380 struct wx_hic_hdr *recv_hdr; 381 u32 i; 382 383 /* read hdr */ 384 for (i = 0; i < dword_len; i++) { 385 buffer[i] = rd32a(wx, WX_FW2SW_MBOX, i); 386 le32_to_cpus(&buffer[i]); 387 } 388 389 /* check hdr */ 390 recv_hdr = (struct wx_hic_hdr *)buffer; 391 if (recv_hdr->cmd == send_cmd && 392 recv_hdr->index == wx->swfw_index) 393 return true; 394 395 return false; 396} 397 398static int wx_host_interface_command_r(struct wx *wx, u32 *buffer, 399 u32 length, u32 timeout, bool return_data) 400{ 401 struct wx_hic_hdr *hdr = (struct wx_hic_hdr *)buffer; 402 u32 hdr_size = sizeof(struct wx_hic_hdr); 403 bool busy, reply; 404 u32 dword_len; 405 u16 buf_len; 406 int err = 0; 407 u8 send_cmd; 408 u32 i; 409 410 /* wait to get lock */ 411 might_sleep(); 412 err = read_poll_timeout(test_and_set_bit, busy, !busy, 1000, timeout * 1000, 413 false, WX_STATE_SWFW_BUSY, wx->state); 414 if (err) 415 return err; 416 417 /* index to unique seq id for each mbox message */ 418 hdr->index = wx->swfw_index; 419 send_cmd = hdr->cmd; 420 421 dword_len = length >> 2; 422 /* write data to SW-FW mbox array */ 423 for (i = 0; i < dword_len; i++) { 424 wr32a(wx, WX_SW2FW_MBOX, i, (__force u32)cpu_to_le32(buffer[i])); 425 /* write flush */ 426 rd32a(wx, WX_SW2FW_MBOX, i); 427 } 428 429 /* generate interrupt to notify FW */ 430 wr32m(wx, WX_SW2FW_MBOX_CMD, WX_SW2FW_MBOX_CMD_VLD, 0); 431 wr32m(wx, WX_SW2FW_MBOX_CMD, WX_SW2FW_MBOX_CMD_VLD, WX_SW2FW_MBOX_CMD_VLD); 432 433 /* polling reply from FW */ 434 err = read_poll_timeout(wx_poll_fw_reply, reply, reply, 2000, 435 timeout * 1000, true, wx, buffer, send_cmd); 436 if (err) { 437 wx_err(wx, "Polling from FW messages timeout, cmd: 0x%x, index: %d\n", 438 send_cmd, wx->swfw_index); 439 goto rel_out; 440 } 441 442 if (hdr->cmd_or_resp.ret_status == 0x80) { 443 wx_err(wx, "Unknown FW command: 0x%x\n", send_cmd); 444 err = -EINVAL; 445 goto rel_out; 446 } 447 448 /* expect no reply from FW then return */ 449 if (!return_data) 450 goto rel_out; 451 452 /* If there is any thing in data position pull it in */ 453 buf_len = hdr->buf_len; 454 if (buf_len == 0) 455 goto rel_out; 456 457 if (length < buf_len + hdr_size) { 458 wx_err(wx, "Buffer not large enough for reply message.\n"); 459 err = -EFAULT; 460 goto rel_out; 461 } 462 463 /* Calculate length in DWORDs, add 3 for odd lengths */ 464 dword_len = (buf_len + 3) >> 2; 465 for (i = hdr_size >> 2; i <= dword_len; i++) { 466 buffer[i] = rd32a(wx, WX_FW2SW_MBOX, i); 467 le32_to_cpus(&buffer[i]); 468 } 469 470rel_out: 471 /* index++, index replace wx_hic_hdr.checksum */ 472 if (wx->swfw_index == WX_HIC_HDR_INDEX_MAX) 473 wx->swfw_index = 0; 474 else 475 wx->swfw_index++; 476 477 clear_bit(WX_STATE_SWFW_BUSY, wx->state); 478 return err; 479} 480 481/** 482 * wx_host_interface_command - Issue command to manageability block 483 * @wx: pointer to the HW structure 484 * @buffer: contains the command to write and where the return status will 485 * be placed 486 * @length: length of buffer, must be multiple of 4 bytes 487 * @timeout: time in ms to wait for command completion 488 * @return_data: read and return data from the buffer (true) or not (false) 489 * Needed because FW structures are big endian and decoding of 490 * these fields can be 8 bit or 16 bit based on command. Decoding 491 * is not easily understood without making a table of commands. 492 * So we will leave this up to the caller to read back the data 493 * in these cases. 494 **/ 495int wx_host_interface_command(struct wx *wx, u32 *buffer, 496 u32 length, u32 timeout, bool return_data) 497{ 498 if (length == 0 || length > WX_HI_MAX_BLOCK_BYTE_LENGTH) { 499 wx_err(wx, "Buffer length failure buffersize=%d.\n", length); 500 return -EINVAL; 501 } 502 503 /* Calculate length in DWORDs. We must be DWORD aligned */ 504 if ((length % (sizeof(u32))) != 0) { 505 wx_err(wx, "Buffer length failure, not aligned to dword"); 506 return -EINVAL; 507 } 508 509 if (test_bit(WX_FLAG_SWFW_RING, wx->flags)) 510 return wx_host_interface_command_r(wx, buffer, length, 511 timeout, return_data); 512 513 return wx_host_interface_command_s(wx, buffer, length, timeout, return_data); 514} 515EXPORT_SYMBOL(wx_host_interface_command); 516 517int wx_set_pps(struct wx *wx, bool enable, u64 nsec, u64 cycles) 518{ 519 struct wx_hic_set_pps pps_cmd; 520 521 pps_cmd.hdr.cmd = FW_PPS_SET_CMD; 522 pps_cmd.hdr.buf_len = FW_PPS_SET_LEN; 523 pps_cmd.hdr.cmd_or_resp.cmd_resv = FW_CEM_CMD_RESERVED; 524 pps_cmd.lan_id = wx->bus.func; 525 pps_cmd.enable = (u8)enable; 526 pps_cmd.nsec = nsec; 527 pps_cmd.cycles = cycles; 528 pps_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 529 530 return wx_host_interface_command(wx, (u32 *)&pps_cmd, 531 sizeof(pps_cmd), 532 WX_HI_COMMAND_TIMEOUT, 533 false); 534} 535 536/** 537 * wx_read_ee_hostif_data - Read EEPROM word using a host interface cmd 538 * assuming that the semaphore is already obtained. 539 * @wx: pointer to hardware structure 540 * @offset: offset of word in the EEPROM to read 541 * @data: word read from the EEPROM 542 * 543 * Reads a 16 bit word from the EEPROM using the hostif. 544 **/ 545static int wx_read_ee_hostif_data(struct wx *wx, u16 offset, u16 *data) 546{ 547 struct wx_hic_read_shadow_ram buffer; 548 int status; 549 550 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 551 buffer.hdr.req.buf_lenh = 0; 552 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 553 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 554 555 /* convert offset from words to bytes */ 556 buffer.address = (__force u32)cpu_to_be32(offset * 2); 557 /* one word */ 558 buffer.length = (__force u16)cpu_to_be16(sizeof(u16)); 559 560 status = wx_host_interface_command(wx, (u32 *)&buffer, sizeof(buffer), 561 WX_HI_COMMAND_TIMEOUT, false); 562 563 if (status != 0) 564 return status; 565 566 if (!test_bit(WX_FLAG_SWFW_RING, wx->flags)) 567 *data = (u16)rd32a(wx, WX_MNG_MBOX, FW_NVM_DATA_OFFSET); 568 else 569 *data = (u16)rd32a(wx, WX_FW2SW_MBOX, FW_NVM_DATA_OFFSET); 570 571 return status; 572} 573 574/** 575 * wx_read_ee_hostif - Read EEPROM word using a host interface cmd 576 * @wx: pointer to hardware structure 577 * @offset: offset of word in the EEPROM to read 578 * @data: word read from the EEPROM 579 * 580 * Reads a 16 bit word from the EEPROM using the hostif. 581 **/ 582int wx_read_ee_hostif(struct wx *wx, u16 offset, u16 *data) 583{ 584 int status = 0; 585 586 status = wx_acquire_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH); 587 if (status == 0) { 588 status = wx_read_ee_hostif_data(wx, offset, data); 589 wx_release_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH); 590 } 591 592 return status; 593} 594EXPORT_SYMBOL(wx_read_ee_hostif); 595 596/** 597 * wx_read_ee_hostif_buffer- Read EEPROM word(s) using hostif 598 * @wx: pointer to hardware structure 599 * @offset: offset of word in the EEPROM to read 600 * @words: number of words 601 * @data: word(s) read from the EEPROM 602 * 603 * Reads a 16 bit word(s) from the EEPROM using the hostif. 604 **/ 605int wx_read_ee_hostif_buffer(struct wx *wx, 606 u16 offset, u16 words, u16 *data) 607{ 608 struct wx_hic_read_shadow_ram buffer; 609 u32 current_word = 0; 610 u16 words_to_read; 611 u32 value = 0; 612 int status; 613 u32 mbox; 614 u32 i; 615 616 /* Take semaphore for the entire operation. */ 617 status = wx_acquire_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH); 618 if (status != 0) 619 return status; 620 621 while (words) { 622 if (words > FW_MAX_READ_BUFFER_SIZE / 2) 623 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 624 else 625 words_to_read = words; 626 627 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 628 buffer.hdr.req.buf_lenh = 0; 629 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 630 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 631 632 /* convert offset from words to bytes */ 633 buffer.address = (__force u32)cpu_to_be32((offset + current_word) * 2); 634 buffer.length = (__force u16)cpu_to_be16(words_to_read * 2); 635 636 status = wx_host_interface_command(wx, (u32 *)&buffer, 637 sizeof(buffer), 638 WX_HI_COMMAND_TIMEOUT, 639 false); 640 641 if (status != 0) { 642 wx_err(wx, "Host interface command failed\n"); 643 goto out; 644 } 645 646 if (!test_bit(WX_FLAG_SWFW_RING, wx->flags)) 647 mbox = WX_MNG_MBOX; 648 else 649 mbox = WX_FW2SW_MBOX; 650 for (i = 0; i < words_to_read; i++) { 651 u32 reg = mbox + (FW_NVM_DATA_OFFSET << 2) + 2 * i; 652 653 value = rd32(wx, reg); 654 data[current_word] = (u16)(value & 0xffff); 655 current_word++; 656 i++; 657 if (i < words_to_read) { 658 value >>= 16; 659 data[current_word] = (u16)(value & 0xffff); 660 current_word++; 661 } 662 } 663 words -= words_to_read; 664 } 665 666out: 667 wx_release_sw_sync(wx, WX_MNG_SWFW_SYNC_SW_FLASH); 668 return status; 669} 670EXPORT_SYMBOL(wx_read_ee_hostif_buffer); 671 672/** 673 * wx_init_eeprom_params - Initialize EEPROM params 674 * @wx: pointer to hardware structure 675 * 676 * Initializes the EEPROM parameters wx_eeprom_info within the 677 * wx_hw struct in order to set up EEPROM access. 678 **/ 679void wx_init_eeprom_params(struct wx *wx) 680{ 681 struct wx_eeprom_info *eeprom = &wx->eeprom; 682 u16 eeprom_size; 683 u16 data = 0x80; 684 685 if (eeprom->type == wx_eeprom_uninitialized) { 686 eeprom->semaphore_delay = 10; 687 eeprom->type = wx_eeprom_none; 688 689 if (!(rd32(wx, WX_SPI_STATUS) & 690 WX_SPI_STATUS_FLASH_BYPASS)) { 691 eeprom->type = wx_flash; 692 693 eeprom_size = 4096; 694 eeprom->word_size = eeprom_size >> 1; 695 696 wx_dbg(wx, "Eeprom params: type = %d, size = %d\n", 697 eeprom->type, eeprom->word_size); 698 } 699 } 700 701 switch (wx->mac.type) { 702 case wx_mac_sp: 703 case wx_mac_aml: 704 case wx_mac_aml40: 705 if (wx_read_ee_hostif(wx, WX_SW_REGION_PTR, &data)) { 706 wx_err(wx, "NVM Read Error\n"); 707 return; 708 } 709 data = data >> 1; 710 break; 711 default: 712 break; 713 } 714 715 eeprom->sw_region_offset = data; 716} 717EXPORT_SYMBOL(wx_init_eeprom_params); 718 719/** 720 * wx_get_mac_addr - Generic get MAC address 721 * @wx: pointer to hardware structure 722 * @mac_addr: Adapter MAC address 723 * 724 * Reads the adapter's MAC address from first Receive Address Register (RAR0) 725 * A reset of the adapter must be performed prior to calling this function 726 * in order for the MAC address to have been loaded from the EEPROM into RAR0 727 **/ 728void wx_get_mac_addr(struct wx *wx, u8 *mac_addr) 729{ 730 u32 rar_high; 731 u32 rar_low; 732 u16 i; 733 734 wr32(wx, WX_PSR_MAC_SWC_IDX, 0); 735 rar_high = rd32(wx, WX_PSR_MAC_SWC_AD_H); 736 rar_low = rd32(wx, WX_PSR_MAC_SWC_AD_L); 737 738 for (i = 0; i < 2; i++) 739 mac_addr[i] = (u8)(rar_high >> (1 - i) * 8); 740 741 for (i = 0; i < 4; i++) 742 mac_addr[i + 2] = (u8)(rar_low >> (3 - i) * 8); 743} 744EXPORT_SYMBOL(wx_get_mac_addr); 745 746/** 747 * wx_set_rar - Set Rx address register 748 * @wx: pointer to hardware structure 749 * @index: Receive address register to write 750 * @addr: Address to put into receive address register 751 * @pools: VMDq "set" or "pool" index 752 * @enable_addr: set flag that address is active 753 * 754 * Puts an ethernet address into a receive address register. 755 **/ 756static int wx_set_rar(struct wx *wx, u32 index, u8 *addr, u64 pools, 757 u32 enable_addr) 758{ 759 u32 rar_entries = wx->mac.num_rar_entries; 760 u32 rar_low, rar_high; 761 762 /* Make sure we are using a valid rar index range */ 763 if (index >= rar_entries) { 764 wx_err(wx, "RAR index %d is out of range.\n", index); 765 return -EINVAL; 766 } 767 768 /* select the MAC address */ 769 wr32(wx, WX_PSR_MAC_SWC_IDX, index); 770 771 /* setup VMDq pool mapping */ 772 wr32(wx, WX_PSR_MAC_SWC_VM_L, pools & 0xFFFFFFFF); 773 774 if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) 775 wr32(wx, WX_PSR_MAC_SWC_VM_H, pools >> 32); 776 777 /* HW expects these in little endian so we reverse the byte 778 * order from network order (big endian) to little endian 779 * 780 * Some parts put the VMDq setting in the extra RAH bits, 781 * so save everything except the lower 16 bits that hold part 782 * of the address and the address valid bit. 783 */ 784 rar_low = ((u32)addr[5] | 785 ((u32)addr[4] << 8) | 786 ((u32)addr[3] << 16) | 787 ((u32)addr[2] << 24)); 788 rar_high = ((u32)addr[1] | 789 ((u32)addr[0] << 8)); 790 if (enable_addr != 0) 791 rar_high |= WX_PSR_MAC_SWC_AD_H_AV; 792 793 wr32(wx, WX_PSR_MAC_SWC_AD_L, rar_low); 794 wr32m(wx, WX_PSR_MAC_SWC_AD_H, 795 (WX_PSR_MAC_SWC_AD_H_AD(U16_MAX) | 796 WX_PSR_MAC_SWC_AD_H_ADTYPE(1) | 797 WX_PSR_MAC_SWC_AD_H_AV), 798 rar_high); 799 800 return 0; 801} 802 803/** 804 * wx_clear_rar - Remove Rx address register 805 * @wx: pointer to hardware structure 806 * @index: Receive address register to write 807 * 808 * Clears an ethernet address from a receive address register. 809 **/ 810static int wx_clear_rar(struct wx *wx, u32 index) 811{ 812 u32 rar_entries = wx->mac.num_rar_entries; 813 814 /* Make sure we are using a valid rar index range */ 815 if (index >= rar_entries) { 816 wx_err(wx, "RAR index %d is out of range.\n", index); 817 return -EINVAL; 818 } 819 820 /* Some parts put the VMDq setting in the extra RAH bits, 821 * so save everything except the lower 16 bits that hold part 822 * of the address and the address valid bit. 823 */ 824 wr32(wx, WX_PSR_MAC_SWC_IDX, index); 825 826 wr32(wx, WX_PSR_MAC_SWC_VM_L, 0); 827 wr32(wx, WX_PSR_MAC_SWC_VM_H, 0); 828 829 wr32(wx, WX_PSR_MAC_SWC_AD_L, 0); 830 wr32m(wx, WX_PSR_MAC_SWC_AD_H, 831 (WX_PSR_MAC_SWC_AD_H_AD(U16_MAX) | 832 WX_PSR_MAC_SWC_AD_H_ADTYPE(1) | 833 WX_PSR_MAC_SWC_AD_H_AV), 834 0); 835 836 return 0; 837} 838 839/** 840 * wx_clear_vmdq - Disassociate a VMDq pool index from a rx address 841 * @wx: pointer to hardware struct 842 * @rar: receive address register index to disassociate 843 * @vmdq: VMDq pool index to remove from the rar 844 **/ 845static int wx_clear_vmdq(struct wx *wx, u32 rar, u32 __maybe_unused vmdq) 846{ 847 u32 rar_entries = wx->mac.num_rar_entries; 848 u32 mpsar_lo, mpsar_hi; 849 850 /* Make sure we are using a valid rar index range */ 851 if (rar >= rar_entries) { 852 wx_err(wx, "RAR index %d is out of range.\n", rar); 853 return -EINVAL; 854 } 855 856 wr32(wx, WX_PSR_MAC_SWC_IDX, rar); 857 mpsar_lo = rd32(wx, WX_PSR_MAC_SWC_VM_L); 858 mpsar_hi = rd32(wx, WX_PSR_MAC_SWC_VM_H); 859 860 if (!mpsar_lo && !mpsar_hi) 861 return 0; 862 863 /* was that the last pool using this rar? */ 864 if (mpsar_lo == 0 && mpsar_hi == 0 && rar != 0) 865 wx_clear_rar(wx, rar); 866 867 return 0; 868} 869 870/** 871 * wx_init_uta_tables - Initialize the Unicast Table Array 872 * @wx: pointer to hardware structure 873 **/ 874static void wx_init_uta_tables(struct wx *wx) 875{ 876 int i; 877 878 wx_dbg(wx, " Clearing UTA\n"); 879 880 for (i = 0; i < 128; i++) 881 wr32(wx, WX_PSR_UC_TBL(i), 0); 882} 883 884/** 885 * wx_init_rx_addrs - Initializes receive address filters. 886 * @wx: pointer to hardware structure 887 * 888 * Places the MAC address in receive address register 0 and clears the rest 889 * of the receive address registers. Clears the multicast table. Assumes 890 * the receiver is in reset when the routine is called. 891 **/ 892void wx_init_rx_addrs(struct wx *wx) 893{ 894 u32 rar_entries = wx->mac.num_rar_entries; 895 u32 psrctl; 896 int i; 897 898 /* If the current mac address is valid, assume it is a software override 899 * to the permanent address. 900 * Otherwise, use the permanent address from the eeprom. 901 */ 902 if (!is_valid_ether_addr(wx->mac.addr)) { 903 /* Get the MAC address from the RAR0 for later reference */ 904 wx_get_mac_addr(wx, wx->mac.addr); 905 wx_dbg(wx, "Keeping Current RAR0 Addr = %pM\n", wx->mac.addr); 906 } else { 907 /* Setup the receive address. */ 908 wx_dbg(wx, "Overriding MAC Address in RAR[0]\n"); 909 wx_dbg(wx, "New MAC Addr = %pM\n", wx->mac.addr); 910 911 wx_set_rar(wx, 0, wx->mac.addr, 0, WX_PSR_MAC_SWC_AD_H_AV); 912 913 if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) { 914 /* clear VMDq pool/queue selection for RAR 0 */ 915 wx_clear_vmdq(wx, 0, WX_CLEAR_VMDQ_ALL); 916 } 917 } 918 919 /* Zero out the other receive addresses. */ 920 wx_dbg(wx, "Clearing RAR[1-%d]\n", rar_entries - 1); 921 for (i = 1; i < rar_entries; i++) { 922 wr32(wx, WX_PSR_MAC_SWC_IDX, i); 923 wr32(wx, WX_PSR_MAC_SWC_AD_L, 0); 924 wr32(wx, WX_PSR_MAC_SWC_AD_H, 0); 925 } 926 927 /* Clear the MTA */ 928 wx->addr_ctrl.mta_in_use = 0; 929 psrctl = rd32(wx, WX_PSR_CTL); 930 psrctl &= ~(WX_PSR_CTL_MO | WX_PSR_CTL_MFE); 931 psrctl |= wx->mac.mc_filter_type << WX_PSR_CTL_MO_SHIFT; 932 wr32(wx, WX_PSR_CTL, psrctl); 933 wx_dbg(wx, " Clearing MTA\n"); 934 for (i = 0; i < wx->mac.mcft_size; i++) 935 wr32(wx, WX_PSR_MC_TBL(i), 0); 936 937 wx_init_uta_tables(wx); 938} 939EXPORT_SYMBOL(wx_init_rx_addrs); 940 941static void wx_sync_mac_table(struct wx *wx) 942{ 943 int i; 944 945 for (i = 0; i < wx->mac.num_rar_entries; i++) { 946 if (wx->mac_table[i].state & WX_MAC_STATE_MODIFIED) { 947 if (wx->mac_table[i].state & WX_MAC_STATE_IN_USE) { 948 wx_set_rar(wx, i, 949 wx->mac_table[i].addr, 950 wx->mac_table[i].pools, 951 WX_PSR_MAC_SWC_AD_H_AV); 952 } else { 953 wx_clear_rar(wx, i); 954 } 955 wx->mac_table[i].state &= ~(WX_MAC_STATE_MODIFIED); 956 } 957 } 958} 959 960static void wx_full_sync_mac_table(struct wx *wx) 961{ 962 int i; 963 964 for (i = 0; i < wx->mac.num_rar_entries; i++) { 965 if (wx->mac_table[i].state & WX_MAC_STATE_IN_USE) { 966 wx_set_rar(wx, i, 967 wx->mac_table[i].addr, 968 wx->mac_table[i].pools, 969 WX_PSR_MAC_SWC_AD_H_AV); 970 } else { 971 wx_clear_rar(wx, i); 972 } 973 wx->mac_table[i].state &= ~(WX_MAC_STATE_MODIFIED); 974 } 975} 976 977/* this function destroys the first RAR entry */ 978void wx_mac_set_default_filter(struct wx *wx, u8 *addr) 979{ 980 memcpy(&wx->mac_table[0].addr, addr, ETH_ALEN); 981 wx->mac_table[0].pools = BIT(VMDQ_P(0)); 982 wx->mac_table[0].state = (WX_MAC_STATE_DEFAULT | WX_MAC_STATE_IN_USE); 983 wx_set_rar(wx, 0, wx->mac_table[0].addr, 984 wx->mac_table[0].pools, 985 WX_PSR_MAC_SWC_AD_H_AV); 986} 987EXPORT_SYMBOL(wx_mac_set_default_filter); 988 989void wx_flush_sw_mac_table(struct wx *wx) 990{ 991 u32 i; 992 993 for (i = 0; i < wx->mac.num_rar_entries; i++) { 994 if (!(wx->mac_table[i].state & WX_MAC_STATE_IN_USE)) 995 continue; 996 997 wx->mac_table[i].state |= WX_MAC_STATE_MODIFIED; 998 wx->mac_table[i].state &= ~WX_MAC_STATE_IN_USE; 999 memset(wx->mac_table[i].addr, 0, ETH_ALEN); 1000 wx->mac_table[i].pools = 0; 1001 } 1002 wx_sync_mac_table(wx); 1003} 1004EXPORT_SYMBOL(wx_flush_sw_mac_table); 1005 1006int wx_add_mac_filter(struct wx *wx, u8 *addr, u16 pool) 1007{ 1008 u32 i; 1009 1010 if (is_zero_ether_addr(addr)) 1011 return -EINVAL; 1012 1013 for (i = 0; i < wx->mac.num_rar_entries; i++) { 1014 if (wx->mac_table[i].state & WX_MAC_STATE_IN_USE) { 1015 if (ether_addr_equal(addr, wx->mac_table[i].addr)) { 1016 if (wx->mac_table[i].pools != (1ULL << pool)) { 1017 memcpy(wx->mac_table[i].addr, addr, ETH_ALEN); 1018 wx->mac_table[i].pools |= (1ULL << pool); 1019 wx_sync_mac_table(wx); 1020 return i; 1021 } 1022 } 1023 } 1024 1025 if (wx->mac_table[i].state & WX_MAC_STATE_IN_USE) 1026 continue; 1027 wx->mac_table[i].state |= (WX_MAC_STATE_MODIFIED | 1028 WX_MAC_STATE_IN_USE); 1029 memcpy(wx->mac_table[i].addr, addr, ETH_ALEN); 1030 wx->mac_table[i].pools |= (1ULL << pool); 1031 wx_sync_mac_table(wx); 1032 return i; 1033 } 1034 return -ENOMEM; 1035} 1036 1037int wx_del_mac_filter(struct wx *wx, u8 *addr, u16 pool) 1038{ 1039 u32 i; 1040 1041 if (is_zero_ether_addr(addr)) 1042 return -EINVAL; 1043 1044 /* search table for addr, if found, set to 0 and sync */ 1045 for (i = 0; i < wx->mac.num_rar_entries; i++) { 1046 if (!ether_addr_equal(addr, wx->mac_table[i].addr)) 1047 continue; 1048 1049 wx->mac_table[i].state |= WX_MAC_STATE_MODIFIED; 1050 wx->mac_table[i].pools &= ~(1ULL << pool); 1051 if (!wx->mac_table[i].pools) { 1052 wx->mac_table[i].state &= ~WX_MAC_STATE_IN_USE; 1053 memset(wx->mac_table[i].addr, 0, ETH_ALEN); 1054 } 1055 wx_sync_mac_table(wx); 1056 return 0; 1057 } 1058 return -ENOMEM; 1059} 1060 1061static int wx_available_rars(struct wx *wx) 1062{ 1063 u32 i, count = 0; 1064 1065 for (i = 0; i < wx->mac.num_rar_entries; i++) { 1066 if (wx->mac_table[i].state == 0) 1067 count++; 1068 } 1069 1070 return count; 1071} 1072 1073/** 1074 * wx_write_uc_addr_list - write unicast addresses to RAR table 1075 * @netdev: network interface device structure 1076 * @pool: index for mac table 1077 * 1078 * Writes unicast address list to the RAR table. 1079 * Returns: -ENOMEM on failure/insufficient address space 1080 * 0 on no addresses written 1081 * X on writing X addresses to the RAR table 1082 **/ 1083static int wx_write_uc_addr_list(struct net_device *netdev, int pool) 1084{ 1085 struct wx *wx = netdev_priv(netdev); 1086 int count = 0; 1087 1088 /* return ENOMEM indicating insufficient memory for addresses */ 1089 if (netdev_uc_count(netdev) > wx_available_rars(wx)) 1090 return -ENOMEM; 1091 1092 if (!netdev_uc_empty(netdev)) { 1093 struct netdev_hw_addr *ha; 1094 1095 netdev_for_each_uc_addr(ha, netdev) { 1096 wx_del_mac_filter(wx, ha->addr, pool); 1097 wx_add_mac_filter(wx, ha->addr, pool); 1098 count++; 1099 } 1100 } 1101 return count; 1102} 1103 1104/** 1105 * wx_mta_vector - Determines bit-vector in multicast table to set 1106 * @wx: pointer to private structure 1107 * @mc_addr: the multicast address 1108 * 1109 * Extracts the 12 bits, from a multicast address, to determine which 1110 * bit-vector to set in the multicast table. The hardware uses 12 bits, from 1111 * incoming rx multicast addresses, to determine the bit-vector to check in 1112 * the MTA. Which of the 4 combination, of 12-bits, the hardware uses is set 1113 * by the MO field of the MCSTCTRL. The MO field is set during initialization 1114 * to mc_filter_type. 1115 **/ 1116u32 wx_mta_vector(struct wx *wx, u8 *mc_addr) 1117{ 1118 u32 vector = 0; 1119 1120 switch (wx->mac.mc_filter_type) { 1121 case 0: /* use bits [47:36] of the address */ 1122 vector = ((mc_addr[4] >> 4) | (((u16)mc_addr[5]) << 4)); 1123 break; 1124 case 1: /* use bits [46:35] of the address */ 1125 vector = ((mc_addr[4] >> 3) | (((u16)mc_addr[5]) << 5)); 1126 break; 1127 case 2: /* use bits [45:34] of the address */ 1128 vector = ((mc_addr[4] >> 2) | (((u16)mc_addr[5]) << 6)); 1129 break; 1130 case 3: /* use bits [43:32] of the address */ 1131 vector = ((mc_addr[4]) | (((u16)mc_addr[5]) << 8)); 1132 break; 1133 default: /* Invalid mc_filter_type */ 1134 wx_err(wx, "MC filter type param set incorrectly\n"); 1135 break; 1136 } 1137 1138 /* vector can only be 12-bits or boundary will be exceeded */ 1139 vector &= 0xFFF; 1140 return vector; 1141} 1142 1143/** 1144 * wx_set_mta - Set bit-vector in multicast table 1145 * @wx: pointer to private structure 1146 * @mc_addr: Multicast address 1147 * 1148 * Sets the bit-vector in the multicast table. 1149 **/ 1150static void wx_set_mta(struct wx *wx, u8 *mc_addr) 1151{ 1152 u32 vector, vector_bit, vector_reg; 1153 1154 wx->addr_ctrl.mta_in_use++; 1155 1156 vector = wx_mta_vector(wx, mc_addr); 1157 wx_dbg(wx, " bit-vector = 0x%03X\n", vector); 1158 1159 /* The MTA is a register array of 128 32-bit registers. It is treated 1160 * like an array of 4096 bits. We want to set bit 1161 * BitArray[vector_value]. So we figure out what register the bit is 1162 * in, read it, OR in the new bit, then write back the new value. The 1163 * register is determined by the upper 7 bits of the vector value and 1164 * the bit within that register are determined by the lower 5 bits of 1165 * the value. 1166 */ 1167 vector_reg = (vector >> 5) & 0x7F; 1168 vector_bit = vector & 0x1F; 1169 wx->mac.mta_shadow[vector_reg] |= (1 << vector_bit); 1170} 1171 1172/** 1173 * wx_update_mc_addr_list - Updates MAC list of multicast addresses 1174 * @wx: pointer to private structure 1175 * @netdev: pointer to net device structure 1176 * 1177 * The given list replaces any existing list. Clears the MC addrs from receive 1178 * address registers and the multicast table. Uses unused receive address 1179 * registers for the first multicast addresses, and hashes the rest into the 1180 * multicast table. 1181 **/ 1182static void wx_update_mc_addr_list(struct wx *wx, struct net_device *netdev) 1183{ 1184 struct netdev_hw_addr *ha; 1185 u32 i, psrctl; 1186 1187 /* Set the new number of MC addresses that we are being requested to 1188 * use. 1189 */ 1190 wx->addr_ctrl.num_mc_addrs = netdev_mc_count(netdev); 1191 wx->addr_ctrl.mta_in_use = 0; 1192 1193 /* Clear mta_shadow */ 1194 wx_dbg(wx, " Clearing MTA\n"); 1195 memset(&wx->mac.mta_shadow, 0, sizeof(wx->mac.mta_shadow)); 1196 1197 /* Update mta_shadow */ 1198 netdev_for_each_mc_addr(ha, netdev) { 1199 wx_dbg(wx, " Adding the multicast addresses:\n"); 1200 wx_set_mta(wx, ha->addr); 1201 } 1202 1203 /* Enable mta */ 1204 for (i = 0; i < wx->mac.mcft_size; i++) 1205 wr32a(wx, WX_PSR_MC_TBL(0), i, 1206 wx->mac.mta_shadow[i]); 1207 1208 if (wx->addr_ctrl.mta_in_use > 0) { 1209 psrctl = rd32(wx, WX_PSR_CTL); 1210 psrctl &= ~(WX_PSR_CTL_MO | WX_PSR_CTL_MFE); 1211 psrctl |= WX_PSR_CTL_MFE | 1212 (wx->mac.mc_filter_type << WX_PSR_CTL_MO_SHIFT); 1213 wr32(wx, WX_PSR_CTL, psrctl); 1214 } 1215 1216 wx_dbg(wx, "Update mc addr list Complete\n"); 1217} 1218 1219static void wx_restore_vf_multicasts(struct wx *wx) 1220{ 1221 u32 i, j, vector_bit, vector_reg; 1222 struct vf_data_storage *vfinfo; 1223 1224 for (i = 0; i < wx->num_vfs; i++) { 1225 u32 vmolr = rd32(wx, WX_PSR_VM_L2CTL(i)); 1226 1227 vfinfo = &wx->vfinfo[i]; 1228 for (j = 0; j < vfinfo->num_vf_mc_hashes; j++) { 1229 wx->addr_ctrl.mta_in_use++; 1230 vector_reg = WX_PSR_MC_TBL_REG(vfinfo->vf_mc_hashes[j]); 1231 vector_bit = WX_PSR_MC_TBL_BIT(vfinfo->vf_mc_hashes[j]); 1232 wr32m(wx, WX_PSR_MC_TBL(vector_reg), 1233 BIT(vector_bit), BIT(vector_bit)); 1234 /* errata 5: maintain a copy of the reg table conf */ 1235 wx->mac.mta_shadow[vector_reg] |= BIT(vector_bit); 1236 } 1237 if (vfinfo->num_vf_mc_hashes) 1238 vmolr |= WX_PSR_VM_L2CTL_ROMPE; 1239 else 1240 vmolr &= ~WX_PSR_VM_L2CTL_ROMPE; 1241 wr32(wx, WX_PSR_VM_L2CTL(i), vmolr); 1242 } 1243 1244 /* Restore any VF macvlans */ 1245 wx_full_sync_mac_table(wx); 1246} 1247 1248/** 1249 * wx_write_mc_addr_list - write multicast addresses to MTA 1250 * @netdev: network interface device structure 1251 * 1252 * Writes multicast address list to the MTA hash table. 1253 * Returns: 0 on no addresses written 1254 * X on writing X addresses to MTA 1255 **/ 1256static int wx_write_mc_addr_list(struct net_device *netdev) 1257{ 1258 struct wx *wx = netdev_priv(netdev); 1259 1260 if (!netif_running(netdev)) 1261 return 0; 1262 1263 wx_update_mc_addr_list(wx, netdev); 1264 1265 if (test_bit(WX_FLAG_SRIOV_ENABLED, wx->flags)) 1266 wx_restore_vf_multicasts(wx); 1267 1268 return netdev_mc_count(netdev); 1269} 1270 1271/** 1272 * wx_set_mac - Change the Ethernet Address of the NIC 1273 * @netdev: network interface device structure 1274 * @p: pointer to an address structure 1275 * 1276 * Returns 0 on success, negative on failure 1277 **/ 1278int wx_set_mac(struct net_device *netdev, void *p) 1279{ 1280 struct wx *wx = netdev_priv(netdev); 1281 struct sockaddr *addr = p; 1282 int retval; 1283 1284 retval = eth_prepare_mac_addr_change(netdev, addr); 1285 if (retval) 1286 return retval; 1287 1288 wx_del_mac_filter(wx, wx->mac.addr, VMDQ_P(0)); 1289 eth_hw_addr_set(netdev, addr->sa_data); 1290 memcpy(wx->mac.addr, addr->sa_data, netdev->addr_len); 1291 1292 wx_mac_set_default_filter(wx, wx->mac.addr); 1293 1294 return 0; 1295} 1296EXPORT_SYMBOL(wx_set_mac); 1297 1298void wx_disable_rx(struct wx *wx) 1299{ 1300 u32 pfdtxgswc; 1301 u32 rxctrl; 1302 1303 rxctrl = rd32(wx, WX_RDB_PB_CTL); 1304 if (rxctrl & WX_RDB_PB_CTL_RXEN) { 1305 pfdtxgswc = rd32(wx, WX_PSR_CTL); 1306 if (pfdtxgswc & WX_PSR_CTL_SW_EN) { 1307 pfdtxgswc &= ~WX_PSR_CTL_SW_EN; 1308 wr32(wx, WX_PSR_CTL, pfdtxgswc); 1309 wx->mac.set_lben = true; 1310 } else { 1311 wx->mac.set_lben = false; 1312 } 1313 rxctrl &= ~WX_RDB_PB_CTL_RXEN; 1314 wr32(wx, WX_RDB_PB_CTL, rxctrl); 1315 1316 if (!(((wx->subsystem_device_id & WX_NCSI_MASK) == WX_NCSI_SUP) || 1317 ((wx->subsystem_device_id & WX_WOL_MASK) == WX_WOL_SUP))) { 1318 /* disable mac receiver */ 1319 wr32m(wx, WX_MAC_RX_CFG, 1320 WX_MAC_RX_CFG_RE, 0); 1321 } 1322 } 1323} 1324EXPORT_SYMBOL(wx_disable_rx); 1325 1326static void wx_enable_rx(struct wx *wx) 1327{ 1328 u32 psrctl; 1329 1330 /* enable mac receiver */ 1331 wr32m(wx, WX_MAC_RX_CFG, 1332 WX_MAC_RX_CFG_RE, WX_MAC_RX_CFG_RE); 1333 1334 wr32m(wx, WX_RDB_PB_CTL, 1335 WX_RDB_PB_CTL_RXEN, WX_RDB_PB_CTL_RXEN); 1336 1337 if (wx->mac.set_lben) { 1338 psrctl = rd32(wx, WX_PSR_CTL); 1339 psrctl |= WX_PSR_CTL_SW_EN; 1340 wr32(wx, WX_PSR_CTL, psrctl); 1341 wx->mac.set_lben = false; 1342 } 1343} 1344 1345/** 1346 * wx_set_rxpba - Initialize Rx packet buffer 1347 * @wx: pointer to private structure 1348 **/ 1349static void wx_set_rxpba(struct wx *wx) 1350{ 1351 u32 rxpktsize, txpktsize, txpbthresh; 1352 u32 pbsize = wx->mac.rx_pb_size; 1353 1354 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags)) { 1355 if (test_bit(WX_FLAG_FDIR_HASH, wx->flags) || 1356 test_bit(WX_FLAG_FDIR_PERFECT, wx->flags)) 1357 pbsize -= 64; /* Default 64KB */ 1358 } 1359 1360 rxpktsize = pbsize << WX_RDB_PB_SZ_SHIFT; 1361 wr32(wx, WX_RDB_PB_SZ(0), rxpktsize); 1362 1363 /* Only support an equally distributed Tx packet buffer strategy. */ 1364 txpktsize = wx->mac.tx_pb_size; 1365 txpbthresh = (txpktsize / 1024) - WX_TXPKT_SIZE_MAX; 1366 wr32(wx, WX_TDB_PB_SZ(0), txpktsize); 1367 wr32(wx, WX_TDM_PB_THRE(0), txpbthresh); 1368} 1369 1370#define WX_ETH_FRAMING 20 1371 1372/** 1373 * wx_hpbthresh - calculate high water mark for flow control 1374 * 1375 * @wx: board private structure to calculate for 1376 **/ 1377static int wx_hpbthresh(struct wx *wx) 1378{ 1379 struct net_device *dev = wx->netdev; 1380 int link, tc, kb, marker; 1381 u32 dv_id, rx_pba; 1382 1383 /* Calculate max LAN frame size */ 1384 link = dev->mtu + ETH_HLEN + ETH_FCS_LEN + WX_ETH_FRAMING; 1385 tc = link; 1386 1387 /* Calculate delay value for device */ 1388 dv_id = WX_DV(link, tc); 1389 1390 /* Loopback switch introduces additional latency */ 1391 if (test_bit(WX_FLAG_SRIOV_ENABLED, wx->flags)) 1392 dv_id += WX_B2BT(tc); 1393 1394 /* Delay value is calculated in bit times convert to KB */ 1395 kb = WX_BT2KB(dv_id); 1396 rx_pba = rd32(wx, WX_RDB_PB_SZ(0)) >> WX_RDB_PB_SZ_SHIFT; 1397 1398 marker = rx_pba - kb; 1399 1400 /* It is possible that the packet buffer is not large enough 1401 * to provide required headroom. In this case throw an error 1402 * to user and a do the best we can. 1403 */ 1404 if (marker < 0) { 1405 dev_warn(&wx->pdev->dev, 1406 "Packet Buffer can not provide enough headroom to support flow control. Decrease MTU or number of traffic classes\n"); 1407 marker = tc + 1; 1408 } 1409 1410 return marker; 1411} 1412 1413/** 1414 * wx_lpbthresh - calculate low water mark for flow control 1415 * 1416 * @wx: board private structure to calculate for 1417 **/ 1418static int wx_lpbthresh(struct wx *wx) 1419{ 1420 struct net_device *dev = wx->netdev; 1421 u32 dv_id; 1422 int tc; 1423 1424 /* Calculate max LAN frame size */ 1425 tc = dev->mtu + ETH_HLEN + ETH_FCS_LEN; 1426 1427 /* Calculate delay value for device */ 1428 dv_id = WX_LOW_DV(tc); 1429 1430 /* Delay value is calculated in bit times convert to KB */ 1431 return WX_BT2KB(dv_id); 1432} 1433 1434/** 1435 * wx_pbthresh_setup - calculate and setup high low water marks 1436 * 1437 * @wx: board private structure to calculate for 1438 **/ 1439static void wx_pbthresh_setup(struct wx *wx) 1440{ 1441 wx->fc.high_water = wx_hpbthresh(wx); 1442 wx->fc.low_water = wx_lpbthresh(wx); 1443 1444 /* Low water marks must not be larger than high water marks */ 1445 if (wx->fc.low_water > wx->fc.high_water) 1446 wx->fc.low_water = 0; 1447} 1448 1449static void wx_set_ethertype_anti_spoofing(struct wx *wx, bool enable, int vf) 1450{ 1451 u32 pfvfspoof, reg_offset, vf_shift; 1452 1453 vf_shift = WX_VF_IND_SHIFT(vf); 1454 reg_offset = WX_VF_REG_OFFSET(vf); 1455 1456 pfvfspoof = rd32(wx, WX_TDM_ETYPE_AS(reg_offset)); 1457 if (enable) 1458 pfvfspoof |= BIT(vf_shift); 1459 else 1460 pfvfspoof &= ~BIT(vf_shift); 1461 wr32(wx, WX_TDM_ETYPE_AS(reg_offset), pfvfspoof); 1462} 1463 1464int wx_set_vf_spoofchk(struct net_device *netdev, int vf, bool setting) 1465{ 1466 u32 index = WX_VF_REG_OFFSET(vf), vf_bit = WX_VF_IND_SHIFT(vf); 1467 struct wx *wx = netdev_priv(netdev); 1468 u32 regval; 1469 1470 if (vf >= wx->num_vfs) 1471 return -EINVAL; 1472 1473 wx->vfinfo[vf].spoofchk_enabled = setting; 1474 1475 regval = (setting << vf_bit); 1476 wr32m(wx, WX_TDM_MAC_AS(index), regval | BIT(vf_bit), regval); 1477 1478 if (wx->vfinfo[vf].vlan_count) 1479 wr32m(wx, WX_TDM_VLAN_AS(index), regval | BIT(vf_bit), regval); 1480 1481 return 0; 1482} 1483 1484static void wx_configure_virtualization(struct wx *wx) 1485{ 1486 u16 pool = wx->num_rx_pools; 1487 u32 reg_offset, vf_shift; 1488 u32 i; 1489 1490 if (!test_bit(WX_FLAG_SRIOV_ENABLED, wx->flags)) 1491 return; 1492 1493 wr32m(wx, WX_PSR_VM_CTL, 1494 WX_PSR_VM_CTL_POOL_MASK | WX_PSR_VM_CTL_REPLEN, 1495 FIELD_PREP(WX_PSR_VM_CTL_POOL_MASK, VMDQ_P(0)) | 1496 WX_PSR_VM_CTL_REPLEN); 1497 while (pool--) 1498 wr32m(wx, WX_PSR_VM_L2CTL(pool), 1499 WX_PSR_VM_L2CTL_AUPE, WX_PSR_VM_L2CTL_AUPE); 1500 1501 if (!test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) { 1502 vf_shift = BIT(VMDQ_P(0)); 1503 /* Enable only the PF pools for Tx/Rx */ 1504 wr32(wx, WX_RDM_VF_RE(0), vf_shift); 1505 wr32(wx, WX_TDM_VF_TE(0), vf_shift); 1506 } else { 1507 vf_shift = WX_VF_IND_SHIFT(VMDQ_P(0)); 1508 reg_offset = WX_VF_REG_OFFSET(VMDQ_P(0)); 1509 1510 /* Enable only the PF pools for Tx/Rx */ 1511 wr32(wx, WX_RDM_VF_RE(reg_offset), GENMASK(31, vf_shift)); 1512 wr32(wx, WX_RDM_VF_RE(reg_offset ^ 1), reg_offset - 1); 1513 wr32(wx, WX_TDM_VF_TE(reg_offset), GENMASK(31, vf_shift)); 1514 wr32(wx, WX_TDM_VF_TE(reg_offset ^ 1), reg_offset - 1); 1515 } 1516 1517 /* clear VLAN promisc flag so VFTA will be updated if necessary */ 1518 clear_bit(WX_FLAG_VLAN_PROMISC, wx->flags); 1519 1520 for (i = 0; i < wx->num_vfs; i++) { 1521 if (!wx->vfinfo[i].spoofchk_enabled) 1522 wx_set_vf_spoofchk(wx->netdev, i, false); 1523 /* enable ethertype anti spoofing if hw supports it */ 1524 wx_set_ethertype_anti_spoofing(wx, true, i); 1525 } 1526} 1527 1528static void wx_configure_port(struct wx *wx) 1529{ 1530 u32 value, i; 1531 1532 if (!test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) { 1533 value = (wx->num_vfs == 0) ? 1534 WX_CFG_PORT_CTL_NUM_VT_NONE : 1535 WX_CFG_PORT_CTL_NUM_VT_8; 1536 } else { 1537 if (test_bit(WX_FLAG_VMDQ_ENABLED, wx->flags)) { 1538 if (wx->ring_feature[RING_F_RSS].indices == 4) 1539 value = WX_CFG_PORT_CTL_NUM_VT_32; 1540 else 1541 value = WX_CFG_PORT_CTL_NUM_VT_64; 1542 } else { 1543 value = 0; 1544 } 1545 } 1546 1547 value |= WX_CFG_PORT_CTL_D_VLAN | WX_CFG_PORT_CTL_QINQ; 1548 wr32m(wx, WX_CFG_PORT_CTL, 1549 WX_CFG_PORT_CTL_NUM_VT_MASK | 1550 WX_CFG_PORT_CTL_D_VLAN | 1551 WX_CFG_PORT_CTL_QINQ, 1552 value); 1553 1554 wr32(wx, WX_CFG_TAG_TPID(0), 1555 ETH_P_8021Q | ETH_P_8021AD << 16); 1556 wx->tpid[0] = ETH_P_8021Q; 1557 wx->tpid[1] = ETH_P_8021AD; 1558 for (i = 1; i < 4; i++) 1559 wr32(wx, WX_CFG_TAG_TPID(i), 1560 ETH_P_8021Q | ETH_P_8021Q << 16); 1561 for (i = 2; i < 8; i++) 1562 wx->tpid[i] = ETH_P_8021Q; 1563} 1564 1565/** 1566 * wx_disable_sec_rx_path - Stops the receive data path 1567 * @wx: pointer to private structure 1568 * 1569 * Stops the receive data path and waits for the HW to internally empty 1570 * the Rx security block 1571 **/ 1572int wx_disable_sec_rx_path(struct wx *wx) 1573{ 1574 u32 secrx; 1575 1576 wr32m(wx, WX_RSC_CTL, 1577 WX_RSC_CTL_RX_DIS, WX_RSC_CTL_RX_DIS); 1578 1579 return read_poll_timeout(rd32, secrx, secrx & WX_RSC_ST_RSEC_RDY, 1580 1000, 40000, false, wx, WX_RSC_ST); 1581} 1582EXPORT_SYMBOL(wx_disable_sec_rx_path); 1583 1584/** 1585 * wx_enable_sec_rx_path - Enables the receive data path 1586 * @wx: pointer to private structure 1587 * 1588 * Enables the receive data path. 1589 **/ 1590void wx_enable_sec_rx_path(struct wx *wx) 1591{ 1592 wr32m(wx, WX_RSC_CTL, WX_RSC_CTL_RX_DIS, 0); 1593 WX_WRITE_FLUSH(wx); 1594} 1595EXPORT_SYMBOL(wx_enable_sec_rx_path); 1596 1597static void wx_vlan_strip_control(struct wx *wx, bool enable) 1598{ 1599 int i, j; 1600 1601 for (i = 0; i < wx->num_rx_queues; i++) { 1602 struct wx_ring *ring = wx->rx_ring[i]; 1603 1604 j = ring->reg_idx; 1605 wr32m(wx, WX_PX_RR_CFG(j), WX_PX_RR_CFG_VLAN, 1606 enable ? WX_PX_RR_CFG_VLAN : 0); 1607 } 1608} 1609 1610static void wx_vlan_promisc_enable(struct wx *wx) 1611{ 1612 u32 vlnctrl, i, vind, bits, reg_idx; 1613 1614 vlnctrl = rd32(wx, WX_PSR_VLAN_CTL); 1615 if (test_bit(WX_FLAG_VMDQ_ENABLED, wx->flags)) { 1616 /* we need to keep the VLAN filter on in SRIOV */ 1617 vlnctrl |= WX_PSR_VLAN_CTL_VFE; 1618 wr32(wx, WX_PSR_VLAN_CTL, vlnctrl); 1619 } else { 1620 vlnctrl &= ~WX_PSR_VLAN_CTL_VFE; 1621 wr32(wx, WX_PSR_VLAN_CTL, vlnctrl); 1622 return; 1623 } 1624 /* We are already in VLAN promisc, nothing to do */ 1625 if (test_bit(WX_FLAG_VLAN_PROMISC, wx->flags)) 1626 return; 1627 /* Set flag so we don't redo unnecessary work */ 1628 set_bit(WX_FLAG_VLAN_PROMISC, wx->flags); 1629 /* Add PF to all active pools */ 1630 for (i = WX_PSR_VLAN_SWC_ENTRIES; --i;) { 1631 wr32(wx, WX_PSR_VLAN_SWC_IDX, i); 1632 vind = WX_VF_IND_SHIFT(VMDQ_P(0)); 1633 reg_idx = WX_VF_REG_OFFSET(VMDQ_P(0)); 1634 bits = rd32(wx, WX_PSR_VLAN_SWC_VM(reg_idx)); 1635 bits |= BIT(vind); 1636 wr32(wx, WX_PSR_VLAN_SWC_VM(reg_idx), bits); 1637 } 1638 /* Set all bits in the VLAN filter table array */ 1639 for (i = 0; i < wx->mac.vft_size; i++) 1640 wr32(wx, WX_PSR_VLAN_TBL(i), U32_MAX); 1641} 1642 1643static void wx_scrub_vfta(struct wx *wx) 1644{ 1645 u32 i, vid, bits, vfta, vind, vlvf, reg_idx; 1646 1647 for (i = WX_PSR_VLAN_SWC_ENTRIES; --i;) { 1648 wr32(wx, WX_PSR_VLAN_SWC_IDX, i); 1649 vlvf = rd32(wx, WX_PSR_VLAN_SWC_IDX); 1650 /* pull VLAN ID from VLVF */ 1651 vid = vlvf & ~WX_PSR_VLAN_SWC_VIEN; 1652 if (vlvf & WX_PSR_VLAN_SWC_VIEN) { 1653 /* if PF is part of this then continue */ 1654 if (test_bit(vid, wx->active_vlans)) 1655 continue; 1656 } 1657 /* remove PF from the pool */ 1658 vind = WX_VF_IND_SHIFT(VMDQ_P(0)); 1659 reg_idx = WX_VF_REG_OFFSET(VMDQ_P(0)); 1660 bits = rd32(wx, WX_PSR_VLAN_SWC_VM(reg_idx)); 1661 bits &= ~BIT(vind); 1662 wr32(wx, WX_PSR_VLAN_SWC_VM(reg_idx), bits); 1663 } 1664 /* extract values from vft_shadow and write back to VFTA */ 1665 for (i = 0; i < wx->mac.vft_size; i++) { 1666 vfta = wx->mac.vft_shadow[i]; 1667 wr32(wx, WX_PSR_VLAN_TBL(i), vfta); 1668 } 1669} 1670 1671static void wx_vlan_promisc_disable(struct wx *wx) 1672{ 1673 u32 vlnctrl; 1674 1675 /* configure vlan filtering */ 1676 vlnctrl = rd32(wx, WX_PSR_VLAN_CTL); 1677 vlnctrl |= WX_PSR_VLAN_CTL_VFE; 1678 wr32(wx, WX_PSR_VLAN_CTL, vlnctrl); 1679 /* We are not in VLAN promisc, nothing to do */ 1680 if (!test_bit(WX_FLAG_VLAN_PROMISC, wx->flags)) 1681 return; 1682 /* Set flag so we don't redo unnecessary work */ 1683 clear_bit(WX_FLAG_VLAN_PROMISC, wx->flags); 1684 wx_scrub_vfta(wx); 1685} 1686 1687void wx_set_rx_mode(struct net_device *netdev) 1688{ 1689 struct wx *wx = netdev_priv(netdev); 1690 netdev_features_t features; 1691 u32 fctrl, vmolr, vlnctrl; 1692 int count; 1693 1694 features = netdev->features; 1695 1696 /* Check for Promiscuous and All Multicast modes */ 1697 fctrl = rd32(wx, WX_PSR_CTL); 1698 fctrl &= ~(WX_PSR_CTL_UPE | WX_PSR_CTL_MPE); 1699 vmolr = rd32(wx, WX_PSR_VM_L2CTL(VMDQ_P(0))); 1700 vmolr &= ~(WX_PSR_VM_L2CTL_UPE | 1701 WX_PSR_VM_L2CTL_MPE | 1702 WX_PSR_VM_L2CTL_ROPE | 1703 WX_PSR_VM_L2CTL_ROMPE); 1704 vlnctrl = rd32(wx, WX_PSR_VLAN_CTL); 1705 vlnctrl &= ~(WX_PSR_VLAN_CTL_VFE | WX_PSR_VLAN_CTL_CFIEN); 1706 1707 /* set all bits that we expect to always be set */ 1708 fctrl |= WX_PSR_CTL_BAM | WX_PSR_CTL_MFE; 1709 vmolr |= WX_PSR_VM_L2CTL_BAM | 1710 WX_PSR_VM_L2CTL_AUPE | 1711 WX_PSR_VM_L2CTL_VACC; 1712 vlnctrl |= WX_PSR_VLAN_CTL_VFE; 1713 1714 wx->addr_ctrl.user_set_promisc = false; 1715 if (netdev->flags & IFF_PROMISC) { 1716 wx->addr_ctrl.user_set_promisc = true; 1717 fctrl |= WX_PSR_CTL_UPE | WX_PSR_CTL_MPE; 1718 /* pf don't want packets routing to vf, so clear UPE */ 1719 vmolr |= WX_PSR_VM_L2CTL_MPE; 1720 if (test_bit(WX_FLAG_VMDQ_ENABLED, wx->flags) && 1721 test_bit(WX_FLAG_SRIOV_ENABLED, wx->flags)) 1722 vlnctrl |= WX_PSR_VLAN_CTL_VFE; 1723 features &= ~NETIF_F_HW_VLAN_CTAG_FILTER; 1724 } 1725 1726 if (netdev->flags & IFF_ALLMULTI) { 1727 fctrl |= WX_PSR_CTL_MPE; 1728 vmolr |= WX_PSR_VM_L2CTL_MPE; 1729 } 1730 1731 if (netdev->features & NETIF_F_RXALL) { 1732 vmolr |= (WX_PSR_VM_L2CTL_UPE | WX_PSR_VM_L2CTL_MPE); 1733 vlnctrl &= ~WX_PSR_VLAN_CTL_VFE; 1734 /* receive bad packets */ 1735 wr32m(wx, WX_RSC_CTL, 1736 WX_RSC_CTL_SAVE_MAC_ERR, 1737 WX_RSC_CTL_SAVE_MAC_ERR); 1738 } else { 1739 vmolr |= WX_PSR_VM_L2CTL_ROPE | WX_PSR_VM_L2CTL_ROMPE; 1740 } 1741 1742 /* Write addresses to available RAR registers, if there is not 1743 * sufficient space to store all the addresses then enable 1744 * unicast promiscuous mode 1745 */ 1746 count = wx_write_uc_addr_list(netdev, VMDQ_P(0)); 1747 if (count < 0) { 1748 vmolr &= ~WX_PSR_VM_L2CTL_ROPE; 1749 vmolr |= WX_PSR_VM_L2CTL_UPE; 1750 } 1751 1752 /* Write addresses to the MTA, if the attempt fails 1753 * then we should just turn on promiscuous mode so 1754 * that we can at least receive multicast traffic 1755 */ 1756 count = wx_write_mc_addr_list(netdev); 1757 if (count < 0) { 1758 vmolr &= ~WX_PSR_VM_L2CTL_ROMPE; 1759 vmolr |= WX_PSR_VM_L2CTL_MPE; 1760 } 1761 1762 wr32(wx, WX_PSR_VLAN_CTL, vlnctrl); 1763 wr32(wx, WX_PSR_CTL, fctrl); 1764 wr32(wx, WX_PSR_VM_L2CTL(VMDQ_P(0)), vmolr); 1765 1766 if ((features & NETIF_F_HW_VLAN_CTAG_RX) && 1767 (features & NETIF_F_HW_VLAN_STAG_RX)) 1768 wx_vlan_strip_control(wx, true); 1769 else 1770 wx_vlan_strip_control(wx, false); 1771 1772 if (features & NETIF_F_HW_VLAN_CTAG_FILTER) 1773 wx_vlan_promisc_disable(wx); 1774 else 1775 wx_vlan_promisc_enable(wx); 1776} 1777EXPORT_SYMBOL(wx_set_rx_mode); 1778 1779static void wx_set_rx_buffer_len(struct wx *wx) 1780{ 1781 struct net_device *netdev = wx->netdev; 1782 struct wx_ring *rx_ring; 1783 u32 mhadd, max_frame; 1784 int i; 1785 1786 max_frame = netdev->mtu + ETH_HLEN + ETH_FCS_LEN + VLAN_HLEN; 1787 /* adjust max frame to be at least the size of a standard frame */ 1788 if (max_frame < (ETH_FRAME_LEN + ETH_FCS_LEN)) 1789 max_frame = (ETH_FRAME_LEN + ETH_FCS_LEN); 1790 1791 mhadd = rd32(wx, WX_PSR_MAX_SZ); 1792 if (max_frame != mhadd) 1793 wr32(wx, WX_PSR_MAX_SZ, max_frame); 1794 1795 /* 1796 * Setup the HW Rx Head and Tail Descriptor Pointers and 1797 * the Base and Length of the Rx Descriptor Ring 1798 */ 1799 for (i = 0; i < wx->num_rx_queues; i++) { 1800 rx_ring = wx->rx_ring[i]; 1801 rx_ring->rx_buf_len = WX_RXBUFFER_2K; 1802#if (PAGE_SIZE < 8192) 1803 if (test_bit(WX_FLAG_RSC_ENABLED, wx->flags)) 1804 rx_ring->rx_buf_len = WX_RXBUFFER_3K; 1805#endif 1806 } 1807} 1808 1809/** 1810 * wx_change_mtu - Change the Maximum Transfer Unit 1811 * @netdev: network interface device structure 1812 * @new_mtu: new value for maximum frame size 1813 * 1814 * Returns 0 on success, negative on failure 1815 **/ 1816int wx_change_mtu(struct net_device *netdev, int new_mtu) 1817{ 1818 struct wx *wx = netdev_priv(netdev); 1819 1820 WRITE_ONCE(netdev->mtu, new_mtu); 1821 wx_set_rx_buffer_len(wx); 1822 1823 return 0; 1824} 1825EXPORT_SYMBOL(wx_change_mtu); 1826 1827/* Disable the specified rx queue */ 1828void wx_disable_rx_queue(struct wx *wx, struct wx_ring *ring) 1829{ 1830 u8 reg_idx = ring->reg_idx; 1831 u32 rxdctl; 1832 int ret; 1833 1834 /* write value back with RRCFG.EN bit cleared */ 1835 wr32m(wx, WX_PX_RR_CFG(reg_idx), 1836 WX_PX_RR_CFG_RR_EN, 0); 1837 1838 /* the hardware may take up to 100us to really disable the rx queue */ 1839 ret = read_poll_timeout(rd32, rxdctl, !(rxdctl & WX_PX_RR_CFG_RR_EN), 1840 10, 100, true, wx, WX_PX_RR_CFG(reg_idx)); 1841 1842 if (ret == -ETIMEDOUT) { 1843 /* Just for information */ 1844 wx_err(wx, 1845 "RRCFG.EN on Rx queue %d not cleared within the polling period\n", 1846 reg_idx); 1847 } 1848} 1849EXPORT_SYMBOL(wx_disable_rx_queue); 1850 1851void wx_enable_rx_queue(struct wx *wx, struct wx_ring *ring) 1852{ 1853 u8 reg_idx = ring->reg_idx; 1854 u32 rxdctl; 1855 int ret; 1856 1857 ret = read_poll_timeout(rd32, rxdctl, rxdctl & WX_PX_RR_CFG_RR_EN, 1858 1000, 10000, true, wx, WX_PX_RR_CFG(reg_idx)); 1859 1860 if (ret == -ETIMEDOUT) { 1861 /* Just for information */ 1862 wx_err(wx, 1863 "RRCFG.EN on Rx queue %d not set within the polling period\n", 1864 reg_idx); 1865 } 1866} 1867EXPORT_SYMBOL(wx_enable_rx_queue); 1868 1869static void wx_configure_srrctl(struct wx *wx, 1870 struct wx_ring *rx_ring) 1871{ 1872 u16 reg_idx = rx_ring->reg_idx; 1873 u32 srrctl; 1874 1875 srrctl = rd32(wx, WX_PX_RR_CFG(reg_idx)); 1876 srrctl &= ~(WX_PX_RR_CFG_RR_HDR_SZ | 1877 WX_PX_RR_CFG_RR_BUF_SZ | 1878 WX_PX_RR_CFG_SPLIT_MODE); 1879 /* configure header buffer length, needed for RSC */ 1880 srrctl |= WX_RXBUFFER_256 << WX_PX_RR_CFG_BHDRSIZE_SHIFT; 1881 1882 /* configure the packet buffer length */ 1883 srrctl |= rx_ring->rx_buf_len >> WX_PX_RR_CFG_BSIZEPKT_SHIFT; 1884 1885 wr32(wx, WX_PX_RR_CFG(reg_idx), srrctl); 1886} 1887 1888static void wx_configure_rscctl(struct wx *wx, 1889 struct wx_ring *ring) 1890{ 1891 u8 reg_idx = ring->reg_idx; 1892 u32 rscctrl; 1893 1894 if (!test_bit(WX_FLAG_RSC_ENABLED, wx->flags)) 1895 return; 1896 1897 rscctrl = rd32(wx, WX_PX_RR_CFG(reg_idx)); 1898 rscctrl |= WX_PX_RR_CFG_RSC; 1899 rscctrl |= WX_PX_RR_CFG_MAX_RSCBUF_16; 1900 1901 wr32(wx, WX_PX_RR_CFG(reg_idx), rscctrl); 1902} 1903 1904static void wx_configure_tx_ring(struct wx *wx, 1905 struct wx_ring *ring) 1906{ 1907 u32 txdctl = WX_PX_TR_CFG_ENABLE; 1908 u8 reg_idx = ring->reg_idx; 1909 u64 tdba = ring->dma; 1910 int ret; 1911 1912 /* disable queue to avoid issues while updating state */ 1913 wr32(wx, WX_PX_TR_CFG(reg_idx), WX_PX_TR_CFG_SWFLSH); 1914 WX_WRITE_FLUSH(wx); 1915 1916 wr32(wx, WX_PX_TR_BAL(reg_idx), tdba & DMA_BIT_MASK(32)); 1917 wr32(wx, WX_PX_TR_BAH(reg_idx), upper_32_bits(tdba)); 1918 1919 /* reset head and tail pointers */ 1920 wr32(wx, WX_PX_TR_RP(reg_idx), 0); 1921 wr32(wx, WX_PX_TR_WP(reg_idx), 0); 1922 ring->tail = wx->hw_addr + WX_PX_TR_WP(reg_idx); 1923 1924 if (ring->count < WX_MAX_TXD) 1925 txdctl |= ring->count / 128 << WX_PX_TR_CFG_TR_SIZE_SHIFT; 1926 txdctl |= 0x20 << WX_PX_TR_CFG_WTHRESH_SHIFT; 1927 1928 ring->atr_count = 0; 1929 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags) && 1930 test_bit(WX_FLAG_FDIR_HASH, wx->flags)) 1931 ring->atr_sample_rate = wx->atr_sample_rate; 1932 else 1933 ring->atr_sample_rate = 0; 1934 1935 /* reinitialize tx_buffer_info */ 1936 memset(ring->tx_buffer_info, 0, 1937 sizeof(struct wx_tx_buffer) * ring->count); 1938 1939 if (ring->headwb_mem) { 1940 wr32(wx, WX_PX_TR_HEAD_ADDRL(reg_idx), 1941 ring->headwb_dma & DMA_BIT_MASK(32)); 1942 wr32(wx, WX_PX_TR_HEAD_ADDRH(reg_idx), 1943 upper_32_bits(ring->headwb_dma)); 1944 1945 txdctl |= WX_PX_TR_CFG_HEAD_WB; 1946 } 1947 1948 /* enable queue */ 1949 wr32(wx, WX_PX_TR_CFG(reg_idx), txdctl); 1950 1951 /* poll to verify queue is enabled */ 1952 ret = read_poll_timeout(rd32, txdctl, txdctl & WX_PX_TR_CFG_ENABLE, 1953 1000, 10000, true, wx, WX_PX_TR_CFG(reg_idx)); 1954 if (ret == -ETIMEDOUT) 1955 wx_err(wx, "Could not enable Tx Queue %d\n", reg_idx); 1956} 1957 1958static void wx_configure_rx_ring(struct wx *wx, 1959 struct wx_ring *ring) 1960{ 1961 u16 reg_idx = ring->reg_idx; 1962 u64 rdba = ring->dma; 1963 u32 rxdctl; 1964 1965 /* disable queue to avoid issues while updating state */ 1966 rxdctl = rd32(wx, WX_PX_RR_CFG(reg_idx)); 1967 wx_disable_rx_queue(wx, ring); 1968 1969 wr32(wx, WX_PX_RR_BAL(reg_idx), rdba & DMA_BIT_MASK(32)); 1970 wr32(wx, WX_PX_RR_BAH(reg_idx), upper_32_bits(rdba)); 1971 1972 if (ring->count == WX_MAX_RXD) 1973 rxdctl |= 0 << WX_PX_RR_CFG_RR_SIZE_SHIFT; 1974 else 1975 rxdctl |= (ring->count / 128) << WX_PX_RR_CFG_RR_SIZE_SHIFT; 1976 1977 rxdctl |= 0x1 << WX_PX_RR_CFG_RR_THER_SHIFT; 1978 1979 if (test_bit(WX_FLAG_RX_MERGE_ENABLED, wx->flags)) 1980 rxdctl |= WX_PX_RR_CFG_DESC_MERGE; 1981 1982 wr32(wx, WX_PX_RR_CFG(reg_idx), rxdctl); 1983 1984 /* reset head and tail pointers */ 1985 wr32(wx, WX_PX_RR_RP(reg_idx), 0); 1986 wr32(wx, WX_PX_RR_WP(reg_idx), 0); 1987 ring->tail = wx->hw_addr + WX_PX_RR_WP(reg_idx); 1988 1989 wx_configure_srrctl(wx, ring); 1990 wx_configure_rscctl(wx, ring); 1991 1992 /* initialize rx_buffer_info */ 1993 memset(ring->rx_buffer_info, 0, 1994 sizeof(struct wx_rx_buffer) * ring->count); 1995 1996 /* reset ntu and ntc to place SW in sync with hardware */ 1997 ring->next_to_clean = 0; 1998 ring->next_to_use = 0; 1999 2000 /* enable receive descriptor ring */ 2001 wr32m(wx, WX_PX_RR_CFG(reg_idx), 2002 WX_PX_RR_CFG_RR_EN, WX_PX_RR_CFG_RR_EN); 2003 2004 wx_enable_rx_queue(wx, ring); 2005 wx_alloc_rx_buffers(ring, wx_desc_unused(ring)); 2006} 2007 2008/** 2009 * wx_configure_tx - Configure Transmit Unit after Reset 2010 * @wx: pointer to private structure 2011 * 2012 * Configure the Tx unit of the MAC after a reset. 2013 **/ 2014static void wx_configure_tx(struct wx *wx) 2015{ 2016 u32 i; 2017 2018 /* TDM_CTL.TE must be before Tx queues are enabled */ 2019 wr32m(wx, WX_TDM_CTL, 2020 WX_TDM_CTL_TE, WX_TDM_CTL_TE); 2021 2022 /* Setup the HW Tx Head and Tail descriptor pointers */ 2023 for (i = 0; i < wx->num_tx_queues; i++) 2024 wx_configure_tx_ring(wx, wx->tx_ring[i]); 2025 2026 wr32m(wx, WX_TSC_BUF_AE, WX_TSC_BUF_AE_THR, 0x10); 2027 2028 if (wx->mac.type == wx_mac_em) 2029 wr32m(wx, WX_TSC_CTL, WX_TSC_CTL_TX_DIS | WX_TSC_CTL_TSEC_DIS, 0x1); 2030 2031 /* enable mac transmitter */ 2032 wr32m(wx, WX_MAC_TX_CFG, 2033 WX_MAC_TX_CFG_TE, WX_MAC_TX_CFG_TE); 2034} 2035 2036static void wx_restore_vlan(struct wx *wx) 2037{ 2038 u16 vid = 1; 2039 2040 wx_vlan_rx_add_vid(wx->netdev, htons(ETH_P_8021Q), 0); 2041 2042 for_each_set_bit_from(vid, wx->active_vlans, VLAN_N_VID) 2043 wx_vlan_rx_add_vid(wx->netdev, htons(ETH_P_8021Q), vid); 2044} 2045 2046u32 wx_rss_indir_tbl_entries(struct wx *wx) 2047{ 2048 if (test_bit(WX_FLAG_SRIOV_ENABLED, wx->flags)) 2049 return 64; 2050 else 2051 return 128; 2052} 2053 2054void wx_store_reta(struct wx *wx) 2055{ 2056 u32 reta_entries = wx_rss_indir_tbl_entries(wx); 2057 u8 *indir_tbl = wx->rss_indir_tbl; 2058 u32 reta = 0; 2059 u32 i; 2060 2061 /* Fill out the redirection table as follows: 2062 * - 8 bit wide entries containing 4 bit RSS index 2063 */ 2064 for (i = 0; i < reta_entries; i++) { 2065 reta |= indir_tbl[i] << (i & 0x3) * 8; 2066 if ((i & 3) == 3) { 2067 if (test_bit(WX_FLAG_SRIOV_ENABLED, wx->flags) && 2068 test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) 2069 wr32(wx, WX_RDB_VMRSSTBL(i >> 2, wx->num_vfs), reta); 2070 else 2071 wr32(wx, WX_RDB_RSSTBL(i >> 2), reta); 2072 reta = 0; 2073 } 2074 } 2075} 2076 2077void wx_store_rsskey(struct wx *wx) 2078{ 2079 u32 key_size = WX_RSS_KEY_SIZE / 4; 2080 u32 i; 2081 2082 if (test_bit(WX_FLAG_SRIOV_ENABLED, wx->flags) && 2083 test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) { 2084 for (i = 0; i < key_size; i++) 2085 wr32(wx, WX_RDB_VMRSSRK(i, wx->num_vfs), 2086 wx->rss_key[i]); 2087 } else { 2088 for (i = 0; i < key_size; i++) 2089 wr32(wx, WX_RDB_RSSRK(i), wx->rss_key[i]); 2090 } 2091} 2092 2093static void wx_setup_reta(struct wx *wx) 2094{ 2095 /* Fill out hash function seeds */ 2096 wx_store_rsskey(wx); 2097 2098 /* Fill out redirection table */ 2099 if (!netif_is_rxfh_configured(wx->netdev)) { 2100 u16 rss_i = wx->ring_feature[RING_F_RSS].indices; 2101 u32 reta_entries = wx_rss_indir_tbl_entries(wx); 2102 u32 i, j; 2103 2104 memset(wx->rss_indir_tbl, 0, sizeof(wx->rss_indir_tbl)); 2105 2106 if (test_bit(WX_FLAG_SRIOV_ENABLED, wx->flags)) { 2107 if (test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) 2108 rss_i = rss_i < 2 ? 2 : rss_i; 2109 else 2110 rss_i = 1; 2111 } 2112 2113 for (i = 0, j = 0; i < reta_entries; i++, j++) { 2114 if (j == rss_i) 2115 j = 0; 2116 2117 wx->rss_indir_tbl[i] = j; 2118 } 2119 } 2120 2121 wx_store_reta(wx); 2122} 2123 2124void wx_config_rss_field(struct wx *wx) 2125{ 2126 u32 rss_field; 2127 2128 if (test_bit(WX_FLAG_SRIOV_ENABLED, wx->flags) && 2129 test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) { 2130 rss_field = rd32(wx, WX_RDB_PL_CFG(wx->num_vfs)); 2131 rss_field &= ~WX_RDB_PL_CFG_RSS_MASK; 2132 rss_field |= FIELD_PREP(WX_RDB_PL_CFG_RSS_MASK, wx->rss_flags); 2133 wr32(wx, WX_RDB_PL_CFG(wx->num_vfs), rss_field); 2134 2135 /* Enable global RSS and multiple RSS to make the RSS 2136 * field of each pool take effect. 2137 */ 2138 wr32m(wx, WX_RDB_RA_CTL, 2139 WX_RDB_RA_CTL_MULTI_RSS | WX_RDB_RA_CTL_RSS_EN, 2140 WX_RDB_RA_CTL_MULTI_RSS | WX_RDB_RA_CTL_RSS_EN); 2141 } else { 2142 rss_field = rd32(wx, WX_RDB_RA_CTL); 2143 rss_field &= ~WX_RDB_RA_CTL_RSS_MASK; 2144 rss_field |= FIELD_PREP(WX_RDB_RA_CTL_RSS_MASK, wx->rss_flags); 2145 wr32(wx, WX_RDB_RA_CTL, rss_field); 2146 } 2147} 2148 2149void wx_enable_rss(struct wx *wx, bool enable) 2150{ 2151 if (test_bit(WX_FLAG_SRIOV_ENABLED, wx->flags) && 2152 test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) { 2153 if (enable) 2154 wr32m(wx, WX_RDB_PL_CFG(wx->num_vfs), 2155 WX_RDB_PL_CFG_RSS_EN, WX_RDB_PL_CFG_RSS_EN); 2156 else 2157 wr32m(wx, WX_RDB_PL_CFG(wx->num_vfs), 2158 WX_RDB_PL_CFG_RSS_EN, 0); 2159 } else { 2160 if (enable) 2161 wr32m(wx, WX_RDB_RA_CTL, WX_RDB_RA_CTL_RSS_EN, 2162 WX_RDB_RA_CTL_RSS_EN); 2163 else 2164 wr32m(wx, WX_RDB_RA_CTL, WX_RDB_RA_CTL_RSS_EN, 0); 2165 } 2166} 2167 2168#define WX_RDB_RSS_PL_2 FIELD_PREP(GENMASK(31, 29), 1) 2169#define WX_RDB_RSS_PL_4 FIELD_PREP(GENMASK(31, 29), 2) 2170static void wx_setup_psrtype(struct wx *wx) 2171{ 2172 int rss_i = wx->ring_feature[RING_F_RSS].indices; 2173 u32 psrtype; 2174 int pool; 2175 2176 psrtype = WX_RDB_PL_CFG_L4HDR | 2177 WX_RDB_PL_CFG_L3HDR | 2178 WX_RDB_PL_CFG_L2HDR | 2179 WX_RDB_PL_CFG_TUN_OUTL2HDR | 2180 WX_RDB_PL_CFG_TUN_TUNHDR; 2181 2182 if (!test_bit(WX_FLAG_MULTI_64_FUNC, wx->flags)) { 2183 for_each_set_bit(pool, &wx->fwd_bitmask, 8) 2184 wr32(wx, WX_RDB_PL_CFG(VMDQ_P(pool)), psrtype); 2185 } else { 2186 if (rss_i > 3) 2187 psrtype |= WX_RDB_RSS_PL_4; 2188 else if (rss_i > 1) 2189 psrtype |= WX_RDB_RSS_PL_2; 2190 2191 for_each_set_bit(pool, &wx->fwd_bitmask, 32) 2192 wr32(wx, WX_RDB_PL_CFG(VMDQ_P(pool)), psrtype); 2193 } 2194} 2195 2196static void wx_setup_mrqc(struct wx *wx) 2197{ 2198 /* Disable indicating checksum in descriptor, enables RSS hash */ 2199 wr32m(wx, WX_PSR_CTL, WX_PSR_CTL_PCSD, WX_PSR_CTL_PCSD); 2200 2201 wx_config_rss_field(wx); 2202 wx_enable_rss(wx, wx->rss_enabled); 2203 wx_setup_reta(wx); 2204} 2205 2206/** 2207 * wx_configure_rx - Configure Receive Unit after Reset 2208 * @wx: pointer to private structure 2209 * 2210 * Configure the Rx unit of the MAC after a reset. 2211 **/ 2212void wx_configure_rx(struct wx *wx) 2213{ 2214 int ret; 2215 u32 i; 2216 2217 wx_disable_rx(wx); 2218 wx_setup_psrtype(wx); 2219 2220 /* enable hw crc stripping */ 2221 wr32m(wx, WX_RSC_CTL, WX_RSC_CTL_CRC_STRIP, WX_RSC_CTL_CRC_STRIP); 2222 2223 if (test_bit(WX_FLAG_RSC_CAPABLE, wx->flags)) { 2224 u32 psrctl; 2225 2226 /* RSC Setup */ 2227 psrctl = rd32(wx, WX_PSR_CTL); 2228 psrctl |= WX_PSR_CTL_RSC_ACK; /* Disable RSC for ACK packets */ 2229 psrctl &= ~WX_PSR_CTL_RSC_DIS; 2230 if (!test_bit(WX_FLAG_RSC_ENABLED, wx->flags)) 2231 psrctl |= WX_PSR_CTL_RSC_DIS; 2232 wr32(wx, WX_PSR_CTL, psrctl); 2233 } 2234 2235 wx_setup_mrqc(wx); 2236 2237 /* set_rx_buffer_len must be called before ring initialization */ 2238 wx_set_rx_buffer_len(wx); 2239 2240 if (test_bit(WX_FLAG_RX_MERGE_ENABLED, wx->flags)) { 2241 wr32(wx, WX_RDM_DCACHE_CTL, WX_RDM_DCACHE_CTL_EN); 2242 wr32m(wx, WX_RDM_RSC_CTL, 2243 WX_RDM_RSC_CTL_FREE_CTL | WX_RDM_RSC_CTL_FREE_CNT_DIS, 2244 WX_RDM_RSC_CTL_FREE_CTL); 2245 } 2246 /* Setup the HW Rx Head and Tail Descriptor Pointers and 2247 * the Base and Length of the Rx Descriptor Ring 2248 */ 2249 for (i = 0; i < wx->num_rx_queues; i++) 2250 wx_configure_rx_ring(wx, wx->rx_ring[i]); 2251 2252 /* Enable all receives, disable security engine prior to block traffic */ 2253 ret = wx_disable_sec_rx_path(wx); 2254 if (ret < 0) 2255 wx_err(wx, "The register status is abnormal, please check device."); 2256 2257 wx_enable_rx(wx); 2258 wx_enable_sec_rx_path(wx); 2259} 2260EXPORT_SYMBOL(wx_configure_rx); 2261 2262static void wx_configure_isb(struct wx *wx) 2263{ 2264 /* set ISB Address */ 2265 wr32(wx, WX_PX_ISB_ADDR_L, wx->isb_dma & DMA_BIT_MASK(32)); 2266 if (IS_ENABLED(CONFIG_ARCH_DMA_ADDR_T_64BIT)) 2267 wr32(wx, WX_PX_ISB_ADDR_H, upper_32_bits(wx->isb_dma)); 2268} 2269 2270void wx_configure(struct wx *wx) 2271{ 2272 wx_set_rxpba(wx); 2273 wx_pbthresh_setup(wx); 2274 wx_configure_virtualization(wx); 2275 wx_configure_port(wx); 2276 2277 wx_set_rx_mode(wx->netdev); 2278 wx_restore_vlan(wx); 2279 2280 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags)) 2281 wx->configure_fdir(wx); 2282 2283 wx_configure_tx(wx); 2284 wx_configure_rx(wx); 2285 wx_configure_isb(wx); 2286} 2287EXPORT_SYMBOL(wx_configure); 2288 2289/** 2290 * wx_disable_pcie_master - Disable PCI-express master access 2291 * @wx: pointer to hardware structure 2292 * 2293 * Disables PCI-Express master access and verifies there are no pending 2294 * requests. 2295 **/ 2296int wx_disable_pcie_master(struct wx *wx) 2297{ 2298 int status = 0; 2299 u32 val; 2300 2301 /* Always set this bit to ensure any future transactions are blocked */ 2302 pci_clear_master(wx->pdev); 2303 2304 /* Exit if master requests are blocked */ 2305 if (!(rd32(wx, WX_PX_TRANSACTION_PENDING))) 2306 return 0; 2307 2308 /* Poll for master request bit to clear */ 2309 status = read_poll_timeout(rd32, val, !val, 100, WX_PCI_MASTER_DISABLE_TIMEOUT, 2310 false, wx, WX_PX_TRANSACTION_PENDING); 2311 if (status < 0) 2312 wx_err(wx, "PCIe transaction pending bit did not clear.\n"); 2313 2314 return status; 2315} 2316EXPORT_SYMBOL(wx_disable_pcie_master); 2317 2318/** 2319 * wx_stop_adapter - Generic stop Tx/Rx units 2320 * @wx: pointer to hardware structure 2321 * 2322 * Sets the adapter_stopped flag within wx_hw struct. Clears interrupts, 2323 * disables transmit and receive units. The adapter_stopped flag is used by 2324 * the shared code and drivers to determine if the adapter is in a stopped 2325 * state and should not touch the hardware. 2326 **/ 2327int wx_stop_adapter(struct wx *wx) 2328{ 2329 u16 i; 2330 2331 /* Set the adapter_stopped flag so other driver functions stop touching 2332 * the hardware 2333 */ 2334 wx->adapter_stopped = true; 2335 2336 /* Disable the receive unit */ 2337 wx_disable_rx(wx); 2338 2339 /* Set interrupt mask to stop interrupts from being generated */ 2340 wx_intr_disable(wx, WX_INTR_ALL); 2341 2342 /* Clear any pending interrupts, flush previous writes */ 2343 wr32(wx, WX_PX_MISC_IC, 0xffffffff); 2344 wr32(wx, WX_BME_CTL, 0x3); 2345 2346 /* Disable the transmit unit. Each queue must be disabled. */ 2347 for (i = 0; i < wx->mac.max_tx_queues; i++) { 2348 wr32m(wx, WX_PX_TR_CFG(i), 2349 WX_PX_TR_CFG_SWFLSH | WX_PX_TR_CFG_ENABLE, 2350 WX_PX_TR_CFG_SWFLSH); 2351 } 2352 2353 /* Disable the receive unit by stopping each queue */ 2354 for (i = 0; i < wx->mac.max_rx_queues; i++) { 2355 wr32m(wx, WX_PX_RR_CFG(i), 2356 WX_PX_RR_CFG_RR_EN, 0); 2357 } 2358 2359 /* flush all queues disables */ 2360 WX_WRITE_FLUSH(wx); 2361 2362 /* Prevent the PCI-E bus from hanging by disabling PCI-E master 2363 * access and verify no pending requests 2364 */ 2365 return wx_disable_pcie_master(wx); 2366} 2367EXPORT_SYMBOL(wx_stop_adapter); 2368 2369void wx_reset_mac(struct wx *wx) 2370{ 2371 /* receive packets that size > 2048 */ 2372 wr32m(wx, WX_MAC_RX_CFG, WX_MAC_RX_CFG_JE, WX_MAC_RX_CFG_JE); 2373 2374 /* clear counters on read */ 2375 wr32m(wx, WX_MMC_CONTROL, 2376 WX_MMC_CONTROL_RSTONRD, WX_MMC_CONTROL_RSTONRD); 2377 2378 wr32m(wx, WX_MAC_RX_FLOW_CTRL, 2379 WX_MAC_RX_FLOW_CTRL_RFE, WX_MAC_RX_FLOW_CTRL_RFE); 2380 2381 wr32(wx, WX_MAC_PKT_FLT, WX_MAC_PKT_FLT_PR); 2382} 2383EXPORT_SYMBOL(wx_reset_mac); 2384 2385void wx_reset_misc(struct wx *wx) 2386{ 2387 int i; 2388 2389 wx_reset_mac(wx); 2390 2391 wr32m(wx, WX_MIS_RST_ST, 2392 WX_MIS_RST_ST_RST_INIT, 0x1E00); 2393 2394 /* errata 4: initialize mng flex tbl and wakeup flex tbl*/ 2395 wr32(wx, WX_PSR_MNG_FLEX_SEL, 0); 2396 for (i = 0; i < 16; i++) { 2397 wr32(wx, WX_PSR_MNG_FLEX_DW_L(i), 0); 2398 wr32(wx, WX_PSR_MNG_FLEX_DW_H(i), 0); 2399 wr32(wx, WX_PSR_MNG_FLEX_MSK(i), 0); 2400 } 2401 wr32(wx, WX_PSR_LAN_FLEX_SEL, 0); 2402 for (i = 0; i < 16; i++) { 2403 wr32(wx, WX_PSR_LAN_FLEX_DW_L(i), 0); 2404 wr32(wx, WX_PSR_LAN_FLEX_DW_H(i), 0); 2405 wr32(wx, WX_PSR_LAN_FLEX_MSK(i), 0); 2406 } 2407 2408 /* set pause frame dst mac addr */ 2409 wr32(wx, WX_RDB_PFCMACDAL, 0xC2000001); 2410 wr32(wx, WX_RDB_PFCMACDAH, 0x0180); 2411} 2412EXPORT_SYMBOL(wx_reset_misc); 2413 2414/** 2415 * wx_get_pcie_msix_counts - Gets MSI-X vector count 2416 * @wx: pointer to hardware structure 2417 * @msix_count: number of MSI interrupts that can be obtained 2418 * @max_msix_count: number of MSI interrupts that mac need 2419 * 2420 * Read PCIe configuration space, and get the MSI-X vector count from 2421 * the capabilities table. 2422 **/ 2423int wx_get_pcie_msix_counts(struct wx *wx, u16 *msix_count, u16 max_msix_count) 2424{ 2425 struct pci_dev *pdev = wx->pdev; 2426 struct device *dev = &pdev->dev; 2427 int pos; 2428 2429 *msix_count = 1; 2430 pos = pci_find_capability(pdev, PCI_CAP_ID_MSIX); 2431 if (!pos) { 2432 dev_err(dev, "Unable to find MSI-X Capabilities\n"); 2433 return -EINVAL; 2434 } 2435 pci_read_config_word(pdev, 2436 pos + PCI_MSIX_FLAGS, 2437 msix_count); 2438 *msix_count &= WX_PCIE_MSIX_TBL_SZ_MASK; 2439 /* MSI-X count is zero-based in HW */ 2440 *msix_count += 1; 2441 2442 if (*msix_count > max_msix_count) 2443 *msix_count = max_msix_count; 2444 2445 return 0; 2446} 2447EXPORT_SYMBOL(wx_get_pcie_msix_counts); 2448 2449/** 2450 * wx_init_rss_key - Initialize wx RSS key 2451 * @wx: device handle 2452 * 2453 * Allocates and initializes the RSS key if it is not allocated. 2454 **/ 2455static int wx_init_rss_key(struct wx *wx) 2456{ 2457 u32 *rss_key; 2458 2459 if (!wx->rss_key) { 2460 rss_key = kzalloc(WX_RSS_KEY_SIZE, GFP_KERNEL); 2461 if (unlikely(!rss_key)) 2462 return -ENOMEM; 2463 2464 netdev_rss_key_fill(rss_key, WX_RSS_KEY_SIZE); 2465 wx->rss_key = rss_key; 2466 } 2467 2468 return 0; 2469} 2470 2471int wx_sw_init(struct wx *wx) 2472{ 2473 struct pci_dev *pdev = wx->pdev; 2474 u32 ssid = 0; 2475 int err = 0; 2476 2477 wx->vendor_id = pdev->vendor; 2478 wx->device_id = pdev->device; 2479 wx->revision_id = pdev->revision; 2480 wx->oem_svid = pdev->subsystem_vendor; 2481 wx->oem_ssid = pdev->subsystem_device; 2482 wx->bus.device = PCI_SLOT(pdev->devfn); 2483 wx->bus.func = FIELD_GET(WX_CFG_PORT_ST_LANID, 2484 rd32(wx, WX_CFG_PORT_ST)); 2485 2486 if (wx->oem_svid == PCI_VENDOR_ID_WANGXUN || 2487 pdev->is_virtfn) { 2488 wx->subsystem_vendor_id = pdev->subsystem_vendor; 2489 wx->subsystem_device_id = pdev->subsystem_device; 2490 } else { 2491 err = wx_flash_read_dword(wx, 0xfffdc, &ssid); 2492 if (err < 0) { 2493 wx_err(wx, "read of internal subsystem device id failed\n"); 2494 return err; 2495 } 2496 2497 wx->subsystem_device_id = swab16((u16)ssid); 2498 } 2499 2500 err = wx_init_rss_key(wx); 2501 if (err < 0) { 2502 wx_err(wx, "rss key allocation failed\n"); 2503 return err; 2504 } 2505 wx->rss_flags = WX_RSS_FIELD_IPV4 | WX_RSS_FIELD_IPV4_TCP | 2506 WX_RSS_FIELD_IPV6 | WX_RSS_FIELD_IPV6_TCP; 2507 2508 wx->mac_table = kcalloc(wx->mac.num_rar_entries, 2509 sizeof(struct wx_mac_addr), 2510 GFP_KERNEL); 2511 if (!wx->mac_table) { 2512 wx_err(wx, "mac_table allocation failed\n"); 2513 kfree(wx->rss_key); 2514 return -ENOMEM; 2515 } 2516 2517 bitmap_zero(wx->state, WX_STATE_NBITS); 2518 bitmap_zero(wx->flags, WX_PF_FLAGS_NBITS); 2519 wx->misc_irq_domain = false; 2520 2521 return 0; 2522} 2523EXPORT_SYMBOL(wx_sw_init); 2524 2525/** 2526 * wx_find_vlvf_slot - find the vlanid or the first empty slot 2527 * @wx: pointer to hardware structure 2528 * @vlan: VLAN id to write to VLAN filter 2529 * 2530 * return the VLVF index where this VLAN id should be placed 2531 * 2532 **/ 2533static int wx_find_vlvf_slot(struct wx *wx, u32 vlan) 2534{ 2535 u32 bits = 0, first_empty_slot = 0; 2536 int regindex; 2537 2538 /* short cut the special case */ 2539 if (vlan == 0) 2540 return 0; 2541 2542 /* Search for the vlan id in the VLVF entries. Save off the first empty 2543 * slot found along the way 2544 */ 2545 for (regindex = 1; regindex < WX_PSR_VLAN_SWC_ENTRIES; regindex++) { 2546 wr32(wx, WX_PSR_VLAN_SWC_IDX, regindex); 2547 bits = rd32(wx, WX_PSR_VLAN_SWC); 2548 if (!bits && !(first_empty_slot)) 2549 first_empty_slot = regindex; 2550 else if ((bits & 0x0FFF) == vlan) 2551 break; 2552 } 2553 2554 if (regindex >= WX_PSR_VLAN_SWC_ENTRIES) { 2555 if (first_empty_slot) 2556 regindex = first_empty_slot; 2557 else 2558 regindex = -ENOMEM; 2559 } 2560 2561 return regindex; 2562} 2563 2564/** 2565 * wx_set_vlvf - Set VLAN Pool Filter 2566 * @wx: pointer to hardware structure 2567 * @vlan: VLAN id to write to VLAN filter 2568 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 2569 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 2570 * @vfta_changed: pointer to boolean flag which indicates whether VFTA 2571 * should be changed 2572 * 2573 * Turn on/off specified bit in VLVF table. 2574 **/ 2575static int wx_set_vlvf(struct wx *wx, u32 vlan, u32 vind, bool vlan_on, 2576 bool *vfta_changed) 2577{ 2578 int vlvf_index; 2579 u32 vt, bits; 2580 2581 /* If VT Mode is set 2582 * Either vlan_on 2583 * make sure the vlan is in VLVF 2584 * set the vind bit in the matching VLVFB 2585 * Or !vlan_on 2586 * clear the pool bit and possibly the vind 2587 */ 2588 vt = rd32(wx, WX_CFG_PORT_CTL); 2589 if (!(vt & WX_CFG_PORT_CTL_NUM_VT_MASK)) 2590 return 0; 2591 2592 vlvf_index = wx_find_vlvf_slot(wx, vlan); 2593 if (vlvf_index < 0) 2594 return vlvf_index; 2595 2596 wr32(wx, WX_PSR_VLAN_SWC_IDX, vlvf_index); 2597 if (vlan_on) { 2598 /* set the pool bit */ 2599 if (vind < 32) { 2600 bits = rd32(wx, WX_PSR_VLAN_SWC_VM_L); 2601 bits |= (1 << vind); 2602 wr32(wx, WX_PSR_VLAN_SWC_VM_L, bits); 2603 } else { 2604 bits = rd32(wx, WX_PSR_VLAN_SWC_VM_H); 2605 bits |= (1 << (vind - 32)); 2606 wr32(wx, WX_PSR_VLAN_SWC_VM_H, bits); 2607 } 2608 } else { 2609 /* clear the pool bit */ 2610 if (vind < 32) { 2611 bits = rd32(wx, WX_PSR_VLAN_SWC_VM_L); 2612 bits &= ~(1 << vind); 2613 wr32(wx, WX_PSR_VLAN_SWC_VM_L, bits); 2614 bits |= rd32(wx, WX_PSR_VLAN_SWC_VM_H); 2615 } else { 2616 bits = rd32(wx, WX_PSR_VLAN_SWC_VM_H); 2617 bits &= ~(1 << (vind - 32)); 2618 wr32(wx, WX_PSR_VLAN_SWC_VM_H, bits); 2619 bits |= rd32(wx, WX_PSR_VLAN_SWC_VM_L); 2620 } 2621 } 2622 2623 if (bits) { 2624 wr32(wx, WX_PSR_VLAN_SWC, (WX_PSR_VLAN_SWC_VIEN | vlan)); 2625 if (!vlan_on && vfta_changed) 2626 *vfta_changed = false; 2627 } else { 2628 wr32(wx, WX_PSR_VLAN_SWC, 0); 2629 } 2630 2631 return 0; 2632} 2633 2634/** 2635 * wx_set_vfta - Set VLAN filter table 2636 * @wx: pointer to hardware structure 2637 * @vlan: VLAN id to write to VLAN filter 2638 * @vind: VMDq output index that maps queue to VLAN id in VFVFB 2639 * @vlan_on: boolean flag to turn on/off VLAN in VFVF 2640 * 2641 * Turn on/off specified VLAN in the VLAN filter table. 2642 **/ 2643int wx_set_vfta(struct wx *wx, u32 vlan, u32 vind, bool vlan_on) 2644{ 2645 u32 bitindex, vfta, targetbit; 2646 bool vfta_changed = false; 2647 int regindex, ret; 2648 2649 /* this is a 2 part operation - first the VFTA, then the 2650 * VLVF and VLVFB if VT Mode is set 2651 * We don't write the VFTA until we know the VLVF part succeeded. 2652 */ 2653 2654 /* Part 1 2655 * The VFTA is a bitstring made up of 128 32-bit registers 2656 * that enable the particular VLAN id, much like the MTA: 2657 * bits[11-5]: which register 2658 * bits[4-0]: which bit in the register 2659 */ 2660 regindex = (vlan >> 5) & 0x7F; 2661 bitindex = vlan & 0x1F; 2662 targetbit = (1 << bitindex); 2663 /* errata 5 */ 2664 vfta = wx->mac.vft_shadow[regindex]; 2665 if (vlan_on) { 2666 if (!(vfta & targetbit)) { 2667 vfta |= targetbit; 2668 vfta_changed = true; 2669 } 2670 } else { 2671 if ((vfta & targetbit)) { 2672 vfta &= ~targetbit; 2673 vfta_changed = true; 2674 } 2675 } 2676 /* Part 2 2677 * Call wx_set_vlvf to set VLVFB and VLVF 2678 */ 2679 ret = wx_set_vlvf(wx, vlan, vind, vlan_on, &vfta_changed); 2680 if (ret != 0) 2681 return ret; 2682 2683 if (vfta_changed) 2684 wr32(wx, WX_PSR_VLAN_TBL(regindex), vfta); 2685 wx->mac.vft_shadow[regindex] = vfta; 2686 2687 return 0; 2688} 2689 2690/** 2691 * wx_clear_vfta - Clear VLAN filter table 2692 * @wx: pointer to hardware structure 2693 * 2694 * Clears the VLAN filer table, and the VMDq index associated with the filter 2695 **/ 2696static void wx_clear_vfta(struct wx *wx) 2697{ 2698 u32 offset; 2699 2700 for (offset = 0; offset < wx->mac.vft_size; offset++) { 2701 wr32(wx, WX_PSR_VLAN_TBL(offset), 0); 2702 wx->mac.vft_shadow[offset] = 0; 2703 } 2704 2705 for (offset = 0; offset < WX_PSR_VLAN_SWC_ENTRIES; offset++) { 2706 wr32(wx, WX_PSR_VLAN_SWC_IDX, offset); 2707 wr32(wx, WX_PSR_VLAN_SWC, 0); 2708 wr32(wx, WX_PSR_VLAN_SWC_VM_L, 0); 2709 wr32(wx, WX_PSR_VLAN_SWC_VM_H, 0); 2710 } 2711} 2712 2713int wx_vlan_rx_add_vid(struct net_device *netdev, 2714 __be16 proto, u16 vid) 2715{ 2716 struct wx *wx = netdev_priv(netdev); 2717 2718 /* add VID to filter table */ 2719 wx_set_vfta(wx, vid, VMDQ_P(0), true); 2720 set_bit(vid, wx->active_vlans); 2721 2722 return 0; 2723} 2724EXPORT_SYMBOL(wx_vlan_rx_add_vid); 2725 2726int wx_vlan_rx_kill_vid(struct net_device *netdev, __be16 proto, u16 vid) 2727{ 2728 struct wx *wx = netdev_priv(netdev); 2729 2730 /* remove VID from filter table */ 2731 if (vid) 2732 wx_set_vfta(wx, vid, VMDQ_P(0), false); 2733 clear_bit(vid, wx->active_vlans); 2734 2735 return 0; 2736} 2737EXPORT_SYMBOL(wx_vlan_rx_kill_vid); 2738 2739static void wx_enable_rx_drop(struct wx *wx, struct wx_ring *ring) 2740{ 2741 u16 reg_idx = ring->reg_idx; 2742 u32 srrctl; 2743 2744 srrctl = rd32(wx, WX_PX_RR_CFG(reg_idx)); 2745 srrctl |= WX_PX_RR_CFG_DROP_EN; 2746 2747 wr32(wx, WX_PX_RR_CFG(reg_idx), srrctl); 2748} 2749 2750static void wx_disable_rx_drop(struct wx *wx, struct wx_ring *ring) 2751{ 2752 u16 reg_idx = ring->reg_idx; 2753 u32 srrctl; 2754 2755 srrctl = rd32(wx, WX_PX_RR_CFG(reg_idx)); 2756 srrctl &= ~WX_PX_RR_CFG_DROP_EN; 2757 2758 wr32(wx, WX_PX_RR_CFG(reg_idx), srrctl); 2759} 2760 2761int wx_fc_enable(struct wx *wx, bool tx_pause, bool rx_pause) 2762{ 2763 u16 pause_time = WX_DEFAULT_FCPAUSE; 2764 u32 mflcn_reg, fccfg_reg, reg; 2765 u32 fcrtl, fcrth; 2766 int i; 2767 2768 /* Low water mark of zero causes XOFF floods */ 2769 if (tx_pause && wx->fc.high_water) { 2770 if (!wx->fc.low_water || wx->fc.low_water >= wx->fc.high_water) { 2771 wx_err(wx, "Invalid water mark configuration\n"); 2772 return -EINVAL; 2773 } 2774 } 2775 2776 /* Disable any previous flow control settings */ 2777 mflcn_reg = rd32(wx, WX_MAC_RX_FLOW_CTRL); 2778 mflcn_reg &= ~WX_MAC_RX_FLOW_CTRL_RFE; 2779 2780 fccfg_reg = rd32(wx, WX_RDB_RFCC); 2781 fccfg_reg &= ~WX_RDB_RFCC_RFCE_802_3X; 2782 2783 if (rx_pause) 2784 mflcn_reg |= WX_MAC_RX_FLOW_CTRL_RFE; 2785 if (tx_pause) 2786 fccfg_reg |= WX_RDB_RFCC_RFCE_802_3X; 2787 2788 /* Set 802.3x based flow control settings. */ 2789 wr32(wx, WX_MAC_RX_FLOW_CTRL, mflcn_reg); 2790 wr32(wx, WX_RDB_RFCC, fccfg_reg); 2791 2792 /* Set up and enable Rx high/low water mark thresholds, enable XON. */ 2793 if (tx_pause && wx->fc.high_water) { 2794 fcrtl = (wx->fc.low_water << 10) | WX_RDB_RFCL_XONE; 2795 wr32(wx, WX_RDB_RFCL, fcrtl); 2796 fcrth = (wx->fc.high_water << 10) | WX_RDB_RFCH_XOFFE; 2797 } else { 2798 wr32(wx, WX_RDB_RFCL, 0); 2799 /* In order to prevent Tx hangs when the internal Tx 2800 * switch is enabled we must set the high water mark 2801 * to the Rx packet buffer size - 24KB. This allows 2802 * the Tx switch to function even under heavy Rx 2803 * workloads. 2804 */ 2805 fcrth = rd32(wx, WX_RDB_PB_SZ(0)) - 24576; 2806 } 2807 2808 wr32(wx, WX_RDB_RFCH, fcrth); 2809 2810 /* Configure pause time */ 2811 reg = pause_time * 0x00010001; 2812 wr32(wx, WX_RDB_RFCV, reg); 2813 2814 /* Configure flow control refresh threshold value */ 2815 wr32(wx, WX_RDB_RFCRT, pause_time / 2); 2816 2817 /* We should set the drop enable bit if: 2818 * Number of Rx queues > 1 and flow control is disabled 2819 * 2820 * This allows us to avoid head of line blocking for security 2821 * and performance reasons. 2822 */ 2823 if (wx->num_rx_queues > 1 && !tx_pause) { 2824 for (i = 0; i < wx->num_rx_queues; i++) 2825 wx_enable_rx_drop(wx, wx->rx_ring[i]); 2826 } else { 2827 for (i = 0; i < wx->num_rx_queues; i++) 2828 wx_disable_rx_drop(wx, wx->rx_ring[i]); 2829 } 2830 2831 return 0; 2832} 2833EXPORT_SYMBOL(wx_fc_enable); 2834 2835/** 2836 * wx_update_stats - Update the board statistics counters. 2837 * @wx: board private structure 2838 **/ 2839void wx_update_stats(struct wx *wx) 2840{ 2841 struct wx_hw_stats *hwstats = &wx->stats; 2842 2843 u64 non_eop_descs = 0, alloc_rx_buff_failed = 0; 2844 u64 hw_csum_rx_good = 0, hw_csum_rx_error = 0; 2845 u64 restart_queue = 0, tx_busy = 0; 2846 u32 i; 2847 2848 /* gather some stats to the wx struct that are per queue */ 2849 for (i = 0; i < wx->num_rx_queues; i++) { 2850 struct wx_ring *rx_ring = wx->rx_ring[i]; 2851 2852 non_eop_descs += rx_ring->rx_stats.non_eop_descs; 2853 alloc_rx_buff_failed += rx_ring->rx_stats.alloc_rx_buff_failed; 2854 hw_csum_rx_good += rx_ring->rx_stats.csum_good_cnt; 2855 hw_csum_rx_error += rx_ring->rx_stats.csum_err; 2856 } 2857 wx->non_eop_descs = non_eop_descs; 2858 wx->alloc_rx_buff_failed = alloc_rx_buff_failed; 2859 wx->hw_csum_rx_error = hw_csum_rx_error; 2860 wx->hw_csum_rx_good = hw_csum_rx_good; 2861 2862 if (test_bit(WX_FLAG_RSC_ENABLED, wx->flags)) { 2863 u64 rsc_count = 0; 2864 u64 rsc_flush = 0; 2865 2866 for (i = 0; i < wx->num_rx_queues; i++) { 2867 rsc_count += wx->rx_ring[i]->rx_stats.rsc_count; 2868 rsc_flush += wx->rx_ring[i]->rx_stats.rsc_flush; 2869 } 2870 wx->rsc_count = rsc_count; 2871 wx->rsc_flush = rsc_flush; 2872 } 2873 2874 for (i = 0; i < wx->num_tx_queues; i++) { 2875 struct wx_ring *tx_ring = wx->tx_ring[i]; 2876 2877 restart_queue += tx_ring->tx_stats.restart_queue; 2878 tx_busy += tx_ring->tx_stats.tx_busy; 2879 } 2880 wx->restart_queue = restart_queue; 2881 wx->tx_busy = tx_busy; 2882 2883 hwstats->gprc += rd32(wx, WX_RDM_PKT_CNT); 2884 hwstats->gptc += rd32(wx, WX_TDM_PKT_CNT); 2885 hwstats->gorc += rd64(wx, WX_RDM_BYTE_CNT_LSB); 2886 hwstats->gotc += rd64(wx, WX_TDM_BYTE_CNT_LSB); 2887 hwstats->tpr += rd64(wx, WX_RX_FRAME_CNT_GOOD_BAD_L); 2888 hwstats->tpt += rd64(wx, WX_TX_FRAME_CNT_GOOD_BAD_L); 2889 hwstats->crcerrs += rd64(wx, WX_RX_CRC_ERROR_FRAMES_L); 2890 hwstats->rlec += rd64(wx, WX_RX_LEN_ERROR_FRAMES_L); 2891 hwstats->bprc += rd64(wx, WX_RX_BC_FRAMES_GOOD_L); 2892 hwstats->bptc += rd64(wx, WX_TX_BC_FRAMES_GOOD_L); 2893 hwstats->mprc += rd64(wx, WX_RX_MC_FRAMES_GOOD_L); 2894 hwstats->mptc += rd64(wx, WX_TX_MC_FRAMES_GOOD_L); 2895 hwstats->roc += rd32(wx, WX_RX_OVERSIZE_FRAMES_GOOD); 2896 hwstats->ruc += rd32(wx, WX_RX_UNDERSIZE_FRAMES_GOOD); 2897 hwstats->lxonoffrxc += rd32(wx, WX_MAC_LXONOFFRXC); 2898 hwstats->lxontxc += rd32(wx, WX_RDB_LXONTXC); 2899 hwstats->lxofftxc += rd32(wx, WX_RDB_LXOFFTXC); 2900 hwstats->o2bgptc += rd32(wx, WX_TDM_OS2BMC_CNT); 2901 hwstats->b2ospc += rd32(wx, WX_MNG_BMC2OS_CNT); 2902 hwstats->o2bspc += rd32(wx, WX_MNG_OS2BMC_CNT); 2903 hwstats->b2ogprc += rd32(wx, WX_RDM_BMC2OS_CNT); 2904 hwstats->rdmdrop += rd32(wx, WX_RDM_DRP_PKT); 2905 2906 if (test_bit(WX_FLAG_FDIR_CAPABLE, wx->flags)) { 2907 hwstats->fdirmatch += rd32(wx, WX_RDB_FDIR_MATCH); 2908 hwstats->fdirmiss += rd32(wx, WX_RDB_FDIR_MISS); 2909 } 2910 2911 /* qmprc is not cleared on read, manual reset it */ 2912 hwstats->qmprc = 0; 2913 for (i = wx->num_vfs * wx->num_rx_queues_per_pool; 2914 i < wx->mac.max_rx_queues; i++) 2915 hwstats->qmprc += rd32(wx, WX_PX_MPRC(i)); 2916} 2917EXPORT_SYMBOL(wx_update_stats); 2918 2919/** 2920 * wx_clear_hw_cntrs - Generic clear hardware counters 2921 * @wx: board private structure 2922 * 2923 * Clears all hardware statistics counters by reading them from the hardware 2924 * Statistics counters are clear on read. 2925 **/ 2926void wx_clear_hw_cntrs(struct wx *wx) 2927{ 2928 u16 i = 0; 2929 2930 for (i = 0; i < wx->mac.max_rx_queues; i++) 2931 wr32(wx, WX_PX_MPRC(i), 0); 2932 2933 rd32(wx, WX_RDM_PKT_CNT); 2934 rd32(wx, WX_TDM_PKT_CNT); 2935 rd64(wx, WX_RDM_BYTE_CNT_LSB); 2936 rd32(wx, WX_TDM_BYTE_CNT_LSB); 2937 rd32(wx, WX_RDM_DRP_PKT); 2938 rd32(wx, WX_RX_UNDERSIZE_FRAMES_GOOD); 2939 rd32(wx, WX_RX_OVERSIZE_FRAMES_GOOD); 2940 rd64(wx, WX_RX_FRAME_CNT_GOOD_BAD_L); 2941 rd64(wx, WX_TX_FRAME_CNT_GOOD_BAD_L); 2942 rd64(wx, WX_RX_MC_FRAMES_GOOD_L); 2943 rd64(wx, WX_TX_MC_FRAMES_GOOD_L); 2944 rd64(wx, WX_RX_BC_FRAMES_GOOD_L); 2945 rd64(wx, WX_TX_BC_FRAMES_GOOD_L); 2946 rd64(wx, WX_RX_CRC_ERROR_FRAMES_L); 2947 rd64(wx, WX_RX_LEN_ERROR_FRAMES_L); 2948 rd32(wx, WX_RDB_LXONTXC); 2949 rd32(wx, WX_RDB_LXOFFTXC); 2950 rd32(wx, WX_MAC_LXONOFFRXC); 2951} 2952EXPORT_SYMBOL(wx_clear_hw_cntrs); 2953 2954/** 2955 * wx_start_hw - Prepare hardware for Tx/Rx 2956 * @wx: pointer to hardware structure 2957 * 2958 * Starts the hardware using the generic start_hw function 2959 * and the generation start_hw function. 2960 * Then performs revision-specific operations, if any. 2961 **/ 2962void wx_start_hw(struct wx *wx) 2963{ 2964 int i; 2965 2966 /* Clear the VLAN filter table */ 2967 wx_clear_vfta(wx); 2968 WX_WRITE_FLUSH(wx); 2969 /* Clear the rate limiters */ 2970 for (i = 0; i < wx->mac.max_tx_queues; i++) { 2971 wr32(wx, WX_TDM_RP_IDX, i); 2972 wr32(wx, WX_TDM_RP_RATE, 0); 2973 } 2974} 2975EXPORT_SYMBOL(wx_start_hw); 2976 2977MODULE_LICENSE("GPL");
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