FILE
via-rhine.c
File preview with syntax highlighting.
linux-6.19.14/drivers/net/ethernet/via/via-rhine.c
1/* via-rhine.c: A Linux Ethernet device driver for VIA Rhine family chips. */ 2/* 3 Written 1998-2001 by Donald Becker. 4 5 Current Maintainer: Kevin Brace <kevinbrace@bracecomputerlab.com> 6 7 This software may be used and distributed according to the terms of 8 the GNU General Public License (GPL), incorporated herein by reference. 9 Drivers based on or derived from this code fall under the GPL and must 10 retain the authorship, copyright and license notice. This file is not 11 a complete program and may only be used when the entire operating 12 system is licensed under the GPL. 13 14 This driver is designed for the VIA VT86C100A Rhine-I. 15 It also works with the Rhine-II (6102) and Rhine-III (6105/6105L/6105LOM 16 and management NIC 6105M). 17 18 The author may be reached as becker@scyld.com, or C/O 19 Scyld Computing Corporation 20 410 Severn Ave., Suite 210 21 Annapolis MD 21403 22 23 24 This driver contains some changes from the original Donald Becker 25 version. He may or may not be interested in bug reports on this 26 code. You can find his versions at: 27 http://www.scyld.com/network/via-rhine.html 28 [link no longer provides useful info -jgarzik] 29 30*/ 31 32#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt 33 34#define DRV_NAME "via-rhine" 35 36#include <linux/types.h> 37 38/* A few user-configurable values. 39 These may be modified when a driver module is loaded. */ 40static int debug = 0; 41#define RHINE_MSG_DEFAULT \ 42 (0x0000) 43 44/* Set the copy breakpoint for the copy-only-tiny-frames scheme. 45 Setting to > 1518 effectively disables this feature. */ 46#if defined(__alpha__) || defined(__arm__) || defined(__hppa__) || \ 47 defined(CONFIG_SPARC) || defined(__ia64__) || \ 48 defined(__sh__) || defined(__mips__) 49static int rx_copybreak = 1518; 50#else 51static int rx_copybreak; 52#endif 53 54/* Work-around for broken BIOSes: they are unable to get the chip back out of 55 power state D3 so PXE booting fails. bootparam(7): via-rhine.avoid_D3=1 */ 56static bool avoid_D3; 57 58/* 59 * In case you are looking for 'options[]' or 'full_duplex[]', they 60 * are gone. Use ethtool(8) instead. 61 */ 62 63/* Maximum number of multicast addresses to filter (vs. rx-all-multicast). 64 The Rhine has a 64 element 8390-like hash table. */ 65static const int multicast_filter_limit = 32; 66 67 68/* Operational parameters that are set at compile time. */ 69 70/* Keep the ring sizes a power of two for compile efficiency. 71 * The compiler will convert <unsigned>'%'<2^N> into a bit mask. 72 * Making the Tx ring too large decreases the effectiveness of channel 73 * bonding and packet priority. 74 * With BQL support, we can increase TX ring safely. 75 * There are no ill effects from too-large receive rings. 76 */ 77#define TX_RING_SIZE 64 78#define TX_QUEUE_LEN (TX_RING_SIZE - 6) /* Limit ring entries actually used. */ 79#define RX_RING_SIZE 64 80 81/* Operational parameters that usually are not changed. */ 82 83/* Time in jiffies before concluding the transmitter is hung. */ 84#define TX_TIMEOUT (2*HZ) 85 86#define PKT_BUF_SZ 1536 /* Size of each temporary Rx buffer.*/ 87 88#include <linux/module.h> 89#include <linux/moduleparam.h> 90#include <linux/kernel.h> 91#include <linux/string.h> 92#include <linux/timer.h> 93#include <linux/errno.h> 94#include <linux/ioport.h> 95#include <linux/interrupt.h> 96#include <linux/pci.h> 97#include <linux/of.h> 98#include <linux/of_irq.h> 99#include <linux/platform_device.h> 100#include <linux/dma-mapping.h> 101#include <linux/netdevice.h> 102#include <linux/etherdevice.h> 103#include <linux/skbuff.h> 104#include <linux/init.h> 105#include <linux/delay.h> 106#include <linux/mii.h> 107#include <linux/ethtool.h> 108#include <linux/crc32.h> 109#include <linux/if_vlan.h> 110#include <linux/bitops.h> 111#include <linux/workqueue.h> 112#include <asm/processor.h> /* Processor type for cache alignment. */ 113#include <asm/io.h> 114#include <asm/irq.h> 115#include <linux/uaccess.h> 116#include <linux/dmi.h> 117 118MODULE_AUTHOR("Donald Becker <becker@scyld.com>"); 119MODULE_DESCRIPTION("VIA Rhine PCI Fast Ethernet driver"); 120MODULE_LICENSE("GPL"); 121 122module_param(debug, int, 0); 123module_param(rx_copybreak, int, 0); 124module_param(avoid_D3, bool, 0); 125MODULE_PARM_DESC(debug, "VIA Rhine debug message flags"); 126MODULE_PARM_DESC(rx_copybreak, "VIA Rhine copy breakpoint for copy-only-tiny-frames"); 127MODULE_PARM_DESC(avoid_D3, "Avoid power state D3 (work-around for broken BIOSes)"); 128 129#define MCAM_SIZE 32 130#define VCAM_SIZE 32 131 132/* 133 Theory of Operation 134 135I. Board Compatibility 136 137This driver is designed for the VIA 86c100A Rhine-II PCI Fast Ethernet 138controller. 139 140II. Board-specific settings 141 142Boards with this chip are functional only in a bus-master PCI slot. 143 144Many operational settings are loaded from the EEPROM to the Config word at 145offset 0x78. For most of these settings, this driver assumes that they are 146correct. 147If this driver is compiled to use PCI memory space operations the EEPROM 148must be configured to enable memory ops. 149 150III. Driver operation 151 152IIIa. Ring buffers 153 154This driver uses two statically allocated fixed-size descriptor lists 155formed into rings by a branch from the final descriptor to the beginning of 156the list. The ring sizes are set at compile time by RX/TX_RING_SIZE. 157 158IIIb/c. Transmit/Receive Structure 159 160This driver attempts to use a zero-copy receive and transmit scheme. 161 162Alas, all data buffers are required to start on a 32 bit boundary, so 163the driver must often copy transmit packets into bounce buffers. 164 165The driver allocates full frame size skbuffs for the Rx ring buffers at 166open() time and passes the skb->data field to the chip as receive data 167buffers. When an incoming frame is less than RX_COPYBREAK bytes long, 168a fresh skbuff is allocated and the frame is copied to the new skbuff. 169When the incoming frame is larger, the skbuff is passed directly up the 170protocol stack. Buffers consumed this way are replaced by newly allocated 171skbuffs in the last phase of rhine_rx(). 172 173The RX_COPYBREAK value is chosen to trade-off the memory wasted by 174using a full-sized skbuff for small frames vs. the copying costs of larger 175frames. New boards are typically used in generously configured machines 176and the underfilled buffers have negligible impact compared to the benefit of 177a single allocation size, so the default value of zero results in never 178copying packets. When copying is done, the cost is usually mitigated by using 179a combined copy/checksum routine. Copying also preloads the cache, which is 180most useful with small frames. 181 182Since the VIA chips are only able to transfer data to buffers on 32 bit 183boundaries, the IP header at offset 14 in an ethernet frame isn't 184longword aligned for further processing. Copying these unaligned buffers 185has the beneficial effect of 16-byte aligning the IP header. 186 187IIId. Synchronization 188 189The driver runs as two independent, single-threaded flows of control. One 190is the send-packet routine, which enforces single-threaded use by the 191netdev_priv(dev)->lock spinlock. The other thread is the interrupt handler, 192which is single threaded by the hardware and interrupt handling software. 193 194The send packet thread has partial control over the Tx ring. It locks the 195netdev_priv(dev)->lock whenever it's queuing a Tx packet. If the next slot in 196the ring is not available it stops the transmit queue by 197calling netif_stop_queue. 198 199The interrupt handler has exclusive control over the Rx ring and records stats 200from the Tx ring. After reaping the stats, it marks the Tx queue entry as 201empty by incrementing the dirty_tx mark. If at least half of the entries in 202the Rx ring are available the transmit queue is woken up if it was stopped. 203 204IV. Notes 205 206IVb. References 207 208Preliminary VT86C100A manual from http://www.via.com.tw/ 209http://www.scyld.com/expert/100mbps.html 210http://www.scyld.com/expert/NWay.html 211ftp://ftp.via.com.tw/public/lan/Products/NIC/VT86C100A/Datasheet/VT86C100A03.pdf 212ftp://ftp.via.com.tw/public/lan/Products/NIC/VT6102/Datasheet/VT6102_021.PDF 213 214 215IVc. Errata 216 217The VT86C100A manual is not reliable information. 218The 3043 chip does not handle unaligned transmit or receive buffers, resulting 219in significant performance degradation for bounce buffer copies on transmit 220and unaligned IP headers on receive. 221The chip does not pad to minimum transmit length. 222 223*/ 224 225 226/* This table drives the PCI probe routines. It's mostly boilerplate in all 227 of the drivers, and will likely be provided by some future kernel. 228 Note the matching code -- the first table entry matchs all 56** cards but 229 second only the 1234 card. 230*/ 231 232enum rhine_revs { 233 VT86C100A = 0x00, 234 VTunknown0 = 0x20, 235 VT6102 = 0x40, 236 VT8231 = 0x50, /* Integrated MAC */ 237 VT8233 = 0x60, /* Integrated MAC */ 238 VT8235 = 0x74, /* Integrated MAC */ 239 VT8237 = 0x78, /* Integrated MAC */ 240 VT8251 = 0x7C, /* Integrated MAC */ 241 VT6105 = 0x80, 242 VT6105_B0 = 0x83, 243 VT6105L = 0x8A, 244 VT6107 = 0x8C, 245 VTunknown2 = 0x8E, 246 VT6105M = 0x90, /* Management adapter */ 247}; 248 249enum rhine_quirks { 250 rqWOL = 0x0001, /* Wake-On-LAN support */ 251 rqForceReset = 0x0002, 252 rq6patterns = 0x0040, /* 6 instead of 4 patterns for WOL */ 253 rqStatusWBRace = 0x0080, /* Tx Status Writeback Error possible */ 254 rqRhineI = 0x0100, /* See comment below */ 255 rqIntPHY = 0x0200, /* Integrated PHY */ 256 rqMgmt = 0x0400, /* Management adapter */ 257 rqNeedEnMMIO = 0x0800, /* Whether the core needs to be 258 * switched from PIO mode to MMIO 259 * (only applies to PCI) 260 */ 261}; 262/* 263 * rqRhineI: VT86C100A (aka Rhine-I) uses different bits to enable 264 * MMIO as well as for the collision counter and the Tx FIFO underflow 265 * indicator. In addition, Tx and Rx buffers need to 4 byte aligned. 266 */ 267 268/* Beware of PCI posted writes */ 269#define IOSYNC do { ioread8(ioaddr + StationAddr); } while (0) 270 271static const struct pci_device_id rhine_pci_tbl[] = { 272 { 0x1106, 0x3043, PCI_ANY_ID, PCI_ANY_ID, }, /* VT86C100A */ 273 { 0x1106, 0x3065, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6102 */ 274 { 0x1106, 0x3106, PCI_ANY_ID, PCI_ANY_ID, }, /* 6105{,L,LOM} */ 275 { 0x1106, 0x3053, PCI_ANY_ID, PCI_ANY_ID, }, /* VT6105M */ 276 { } /* terminate list */ 277}; 278MODULE_DEVICE_TABLE(pci, rhine_pci_tbl); 279 280/* OpenFirmware identifiers for platform-bus devices 281 * The .data field is currently only used to store quirks 282 */ 283static u32 vt8500_quirks = rqWOL | rqForceReset | rq6patterns; 284static const struct of_device_id rhine_of_tbl[] = { 285 { .compatible = "via,vt8500-rhine", .data = &vt8500_quirks }, 286 { } /* terminate list */ 287}; 288MODULE_DEVICE_TABLE(of, rhine_of_tbl); 289 290/* Offsets to the device registers. */ 291enum register_offsets { 292 StationAddr=0x00, RxConfig=0x06, TxConfig=0x07, ChipCmd=0x08, 293 ChipCmd1=0x09, TQWake=0x0A, 294 IntrStatus=0x0C, IntrEnable=0x0E, 295 MulticastFilter0=0x10, MulticastFilter1=0x14, 296 RxRingPtr=0x18, TxRingPtr=0x1C, GFIFOTest=0x54, 297 MIIPhyAddr=0x6C, MIIStatus=0x6D, PCIBusConfig=0x6E, PCIBusConfig1=0x6F, 298 MIICmd=0x70, MIIRegAddr=0x71, MIIData=0x72, MACRegEEcsr=0x74, 299 ConfigA=0x78, ConfigB=0x79, ConfigC=0x7A, ConfigD=0x7B, 300 RxMissed=0x7C, RxCRCErrs=0x7E, MiscCmd=0x81, 301 StickyHW=0x83, IntrStatus2=0x84, 302 CamMask=0x88, CamCon=0x92, CamAddr=0x93, 303 WOLcrSet=0xA0, PwcfgSet=0xA1, WOLcgSet=0xA3, WOLcrClr=0xA4, 304 WOLcrClr1=0xA6, WOLcgClr=0xA7, 305 PwrcsrSet=0xA8, PwrcsrSet1=0xA9, PwrcsrClr=0xAC, PwrcsrClr1=0xAD, 306}; 307 308/* Bits in ConfigD */ 309enum backoff_bits { 310 BackOptional=0x01, BackModify=0x02, 311 BackCaptureEffect=0x04, BackRandom=0x08 312}; 313 314/* Bits in the TxConfig (TCR) register */ 315enum tcr_bits { 316 TCR_PQEN=0x01, 317 TCR_LB0=0x02, /* loopback[0] */ 318 TCR_LB1=0x04, /* loopback[1] */ 319 TCR_OFSET=0x08, 320 TCR_RTGOPT=0x10, 321 TCR_RTFT0=0x20, 322 TCR_RTFT1=0x40, 323 TCR_RTSF=0x80, 324}; 325 326/* Bits in the CamCon (CAMC) register */ 327enum camcon_bits { 328 CAMC_CAMEN=0x01, 329 CAMC_VCAMSL=0x02, 330 CAMC_CAMWR=0x04, 331 CAMC_CAMRD=0x08, 332}; 333 334/* Bits in the PCIBusConfig1 (BCR1) register */ 335enum bcr1_bits { 336 BCR1_POT0=0x01, 337 BCR1_POT1=0x02, 338 BCR1_POT2=0x04, 339 BCR1_CTFT0=0x08, 340 BCR1_CTFT1=0x10, 341 BCR1_CTSF=0x20, 342 BCR1_TXQNOBK=0x40, /* for VT6105 */ 343 BCR1_VIDFR=0x80, /* for VT6105 */ 344 BCR1_MED0=0x40, /* for VT6102 */ 345 BCR1_MED1=0x80, /* for VT6102 */ 346}; 347 348/* Registers we check that mmio and reg are the same. */ 349static const int mmio_verify_registers[] = { 350 RxConfig, TxConfig, IntrEnable, ConfigA, ConfigB, ConfigC, ConfigD, 351 0 352}; 353 354/* Bits in the interrupt status/mask registers. */ 355enum intr_status_bits { 356 IntrRxDone = 0x0001, 357 IntrTxDone = 0x0002, 358 IntrRxErr = 0x0004, 359 IntrTxError = 0x0008, 360 IntrRxEmpty = 0x0020, 361 IntrPCIErr = 0x0040, 362 IntrStatsMax = 0x0080, 363 IntrRxEarly = 0x0100, 364 IntrTxUnderrun = 0x0210, 365 IntrRxOverflow = 0x0400, 366 IntrRxDropped = 0x0800, 367 IntrRxNoBuf = 0x1000, 368 IntrTxAborted = 0x2000, 369 IntrLinkChange = 0x4000, 370 IntrRxWakeUp = 0x8000, 371 IntrTxDescRace = 0x080000, /* mapped from IntrStatus2 */ 372 IntrNormalSummary = IntrRxDone | IntrTxDone, 373 IntrTxErrSummary = IntrTxDescRace | IntrTxAborted | IntrTxError | 374 IntrTxUnderrun, 375}; 376 377/* Bits in WOLcrSet/WOLcrClr and PwrcsrSet/PwrcsrClr */ 378enum wol_bits { 379 WOLucast = 0x10, 380 WOLmagic = 0x20, 381 WOLbmcast = 0x30, 382 WOLlnkon = 0x40, 383 WOLlnkoff = 0x80, 384}; 385 386/* The Rx and Tx buffer descriptors. */ 387struct rx_desc { 388 __le32 rx_status; 389 __le32 desc_length; /* Chain flag, Buffer/frame length */ 390 __le32 addr; 391 __le32 next_desc; 392}; 393struct tx_desc { 394 __le32 tx_status; 395 __le32 desc_length; /* Chain flag, Tx Config, Frame length */ 396 __le32 addr; 397 __le32 next_desc; 398}; 399 400/* Initial value for tx_desc.desc_length, Buffer size goes to bits 0-10 */ 401#define TXDESC 0x00e08000 402 403enum rx_status_bits { 404 RxOK=0x8000, RxWholePkt=0x0300, RxErr=0x008F 405}; 406 407/* Bits in *_desc.*_status */ 408enum desc_status_bits { 409 DescOwn=0x80000000 410}; 411 412/* Bits in *_desc.*_length */ 413enum desc_length_bits { 414 DescTag=0x00010000 415}; 416 417/* Bits in ChipCmd. */ 418enum chip_cmd_bits { 419 CmdInit=0x01, CmdStart=0x02, CmdStop=0x04, CmdRxOn=0x08, 420 CmdTxOn=0x10, Cmd1TxDemand=0x20, CmdRxDemand=0x40, 421 Cmd1EarlyRx=0x01, Cmd1EarlyTx=0x02, Cmd1FDuplex=0x04, 422 Cmd1NoTxPoll=0x08, Cmd1Reset=0x80, 423}; 424 425struct rhine_stats { 426 u64 packets; 427 u64 bytes; 428 struct u64_stats_sync syncp; 429}; 430 431struct rhine_private { 432 /* Bit mask for configured VLAN ids */ 433 unsigned long active_vlans[BITS_TO_LONGS(VLAN_N_VID)]; 434 435 /* Descriptor rings */ 436 struct rx_desc *rx_ring; 437 struct tx_desc *tx_ring; 438 dma_addr_t rx_ring_dma; 439 dma_addr_t tx_ring_dma; 440 441 /* The addresses of receive-in-place skbuffs. */ 442 struct sk_buff *rx_skbuff[RX_RING_SIZE]; 443 dma_addr_t rx_skbuff_dma[RX_RING_SIZE]; 444 445 /* The saved address of a sent-in-place packet/buffer, for later free(). */ 446 struct sk_buff *tx_skbuff[TX_RING_SIZE]; 447 dma_addr_t tx_skbuff_dma[TX_RING_SIZE]; 448 449 /* Tx bounce buffers (Rhine-I only) */ 450 unsigned char *tx_buf[TX_RING_SIZE]; 451 unsigned char *tx_bufs; 452 dma_addr_t tx_bufs_dma; 453 454 int irq; 455 long pioaddr; 456 struct net_device *dev; 457 struct napi_struct napi; 458 spinlock_t lock; 459 struct mutex task_lock; 460 bool task_enable; 461 struct work_struct slow_event_task; 462 struct work_struct reset_task; 463 464 u32 msg_enable; 465 466 /* Frequently used values: keep some adjacent for cache effect. */ 467 u32 quirks; 468 unsigned int cur_rx; 469 unsigned int cur_tx, dirty_tx; 470 unsigned int rx_buf_sz; /* Based on MTU+slack. */ 471 struct rhine_stats rx_stats; 472 struct rhine_stats tx_stats; 473 u8 wolopts; 474 475 u8 tx_thresh, rx_thresh; 476 477 struct mii_if_info mii_if; 478 void __iomem *base; 479}; 480 481#define BYTE_REG_BITS_ON(x, p) do { iowrite8((ioread8((p))|(x)), (p)); } while (0) 482#define WORD_REG_BITS_ON(x, p) do { iowrite16((ioread16((p))|(x)), (p)); } while (0) 483#define DWORD_REG_BITS_ON(x, p) do { iowrite32((ioread32((p))|(x)), (p)); } while (0) 484 485#define BYTE_REG_BITS_IS_ON(x, p) (ioread8((p)) & (x)) 486#define WORD_REG_BITS_IS_ON(x, p) (ioread16((p)) & (x)) 487#define DWORD_REG_BITS_IS_ON(x, p) (ioread32((p)) & (x)) 488 489#define BYTE_REG_BITS_OFF(x, p) do { iowrite8(ioread8((p)) & (~(x)), (p)); } while (0) 490#define WORD_REG_BITS_OFF(x, p) do { iowrite16(ioread16((p)) & (~(x)), (p)); } while (0) 491#define DWORD_REG_BITS_OFF(x, p) do { iowrite32(ioread32((p)) & (~(x)), (p)); } while (0) 492 493#define BYTE_REG_BITS_SET(x, m, p) do { iowrite8((ioread8((p)) & (~(m)))|(x), (p)); } while (0) 494#define WORD_REG_BITS_SET(x, m, p) do { iowrite16((ioread16((p)) & (~(m)))|(x), (p)); } while (0) 495#define DWORD_REG_BITS_SET(x, m, p) do { iowrite32((ioread32((p)) & (~(m)))|(x), (p)); } while (0) 496 497 498static int mdio_read(struct net_device *dev, int phy_id, int location); 499static void mdio_write(struct net_device *dev, int phy_id, int location, int value); 500static int rhine_open(struct net_device *dev); 501static void rhine_reset_task(struct work_struct *work); 502static void rhine_slow_event_task(struct work_struct *work); 503static void rhine_tx_timeout(struct net_device *dev, unsigned int txqueue); 504static netdev_tx_t rhine_start_tx(struct sk_buff *skb, 505 struct net_device *dev); 506static irqreturn_t rhine_interrupt(int irq, void *dev_instance); 507static void rhine_tx(struct net_device *dev); 508static int rhine_rx(struct net_device *dev, int limit); 509static void rhine_set_rx_mode(struct net_device *dev); 510static void rhine_get_stats64(struct net_device *dev, 511 struct rtnl_link_stats64 *stats); 512static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd); 513static const struct ethtool_ops netdev_ethtool_ops; 514static int rhine_close(struct net_device *dev); 515static int rhine_vlan_rx_add_vid(struct net_device *dev, 516 __be16 proto, u16 vid); 517static int rhine_vlan_rx_kill_vid(struct net_device *dev, 518 __be16 proto, u16 vid); 519static void rhine_restart_tx(struct net_device *dev); 520 521static void rhine_wait_bit(struct rhine_private *rp, u8 reg, u8 mask, bool low) 522{ 523 void __iomem *ioaddr = rp->base; 524 int i; 525 526 for (i = 0; i < 1024; i++) { 527 bool has_mask_bits = !!(ioread8(ioaddr + reg) & mask); 528 529 if (low ^ has_mask_bits) 530 break; 531 udelay(10); 532 } 533 if (i > 64) { 534 netif_dbg(rp, hw, rp->dev, "%s bit wait (%02x/%02x) cycle " 535 "count: %04d\n", low ? "low" : "high", reg, mask, i); 536 } 537} 538 539static void rhine_wait_bit_high(struct rhine_private *rp, u8 reg, u8 mask) 540{ 541 rhine_wait_bit(rp, reg, mask, false); 542} 543 544static void rhine_wait_bit_low(struct rhine_private *rp, u8 reg, u8 mask) 545{ 546 rhine_wait_bit(rp, reg, mask, true); 547} 548 549static u32 rhine_get_events(struct rhine_private *rp) 550{ 551 void __iomem *ioaddr = rp->base; 552 u32 intr_status; 553 554 intr_status = ioread16(ioaddr + IntrStatus); 555 /* On Rhine-II, Bit 3 indicates Tx descriptor write-back race. */ 556 if (rp->quirks & rqStatusWBRace) 557 intr_status |= ioread8(ioaddr + IntrStatus2) << 16; 558 return intr_status; 559} 560 561static void rhine_ack_events(struct rhine_private *rp, u32 mask) 562{ 563 void __iomem *ioaddr = rp->base; 564 565 if (rp->quirks & rqStatusWBRace) 566 iowrite8(mask >> 16, ioaddr + IntrStatus2); 567 iowrite16(mask, ioaddr + IntrStatus); 568} 569 570/* 571 * Get power related registers into sane state. 572 * Notify user about past WOL event. 573 */ 574static void rhine_power_init(struct net_device *dev) 575{ 576 struct rhine_private *rp = netdev_priv(dev); 577 void __iomem *ioaddr = rp->base; 578 u16 wolstat; 579 580 if (rp->quirks & rqWOL) { 581 /* Make sure chip is in power state D0 */ 582 iowrite8(ioread8(ioaddr + StickyHW) & 0xFC, ioaddr + StickyHW); 583 584 /* Disable "force PME-enable" */ 585 iowrite8(0x80, ioaddr + WOLcgClr); 586 587 /* Clear power-event config bits (WOL) */ 588 iowrite8(0xFF, ioaddr + WOLcrClr); 589 /* More recent cards can manage two additional patterns */ 590 if (rp->quirks & rq6patterns) 591 iowrite8(0x03, ioaddr + WOLcrClr1); 592 593 /* Save power-event status bits */ 594 wolstat = ioread8(ioaddr + PwrcsrSet); 595 if (rp->quirks & rq6patterns) 596 wolstat |= (ioread8(ioaddr + PwrcsrSet1) & 0x03) << 8; 597 598 /* Clear power-event status bits */ 599 iowrite8(0xFF, ioaddr + PwrcsrClr); 600 if (rp->quirks & rq6patterns) 601 iowrite8(0x03, ioaddr + PwrcsrClr1); 602 603 if (wolstat) { 604 char *reason; 605 switch (wolstat) { 606 case WOLmagic: 607 reason = "Magic packet"; 608 break; 609 case WOLlnkon: 610 reason = "Link went up"; 611 break; 612 case WOLlnkoff: 613 reason = "Link went down"; 614 break; 615 case WOLucast: 616 reason = "Unicast packet"; 617 break; 618 case WOLbmcast: 619 reason = "Multicast/broadcast packet"; 620 break; 621 default: 622 reason = "Unknown"; 623 } 624 netdev_info(dev, "Woke system up. Reason: %s\n", 625 reason); 626 } 627 } 628} 629 630static void rhine_chip_reset(struct net_device *dev) 631{ 632 struct rhine_private *rp = netdev_priv(dev); 633 void __iomem *ioaddr = rp->base; 634 u8 cmd1; 635 636 iowrite8(Cmd1Reset, ioaddr + ChipCmd1); 637 IOSYNC; 638 639 if (ioread8(ioaddr + ChipCmd1) & Cmd1Reset) { 640 netdev_info(dev, "Reset not complete yet. Trying harder.\n"); 641 642 /* Force reset */ 643 if (rp->quirks & rqForceReset) 644 iowrite8(0x40, ioaddr + MiscCmd); 645 646 /* Reset can take somewhat longer (rare) */ 647 rhine_wait_bit_low(rp, ChipCmd1, Cmd1Reset); 648 } 649 650 cmd1 = ioread8(ioaddr + ChipCmd1); 651 netif_info(rp, hw, dev, "Reset %s\n", (cmd1 & Cmd1Reset) ? 652 "failed" : "succeeded"); 653} 654 655static void enable_mmio(long pioaddr, u32 quirks) 656{ 657 int n; 658 659 if (quirks & rqNeedEnMMIO) { 660 if (quirks & rqRhineI) { 661 /* More recent docs say that this bit is reserved */ 662 n = inb(pioaddr + ConfigA) | 0x20; 663 outb(n, pioaddr + ConfigA); 664 } else { 665 n = inb(pioaddr + ConfigD) | 0x80; 666 outb(n, pioaddr + ConfigD); 667 } 668 } 669} 670 671static inline int verify_mmio(struct device *hwdev, 672 long pioaddr, 673 void __iomem *ioaddr, 674 u32 quirks) 675{ 676 if (quirks & rqNeedEnMMIO) { 677 int i = 0; 678 679 /* Check that selected MMIO registers match the PIO ones */ 680 while (mmio_verify_registers[i]) { 681 int reg = mmio_verify_registers[i++]; 682 unsigned char a = inb(pioaddr+reg); 683 unsigned char b = readb(ioaddr+reg); 684 685 if (a != b) { 686 dev_err(hwdev, 687 "MMIO do not match PIO [%02x] (%02x != %02x)\n", 688 reg, a, b); 689 return -EIO; 690 } 691 } 692 } 693 return 0; 694} 695 696/* 697 * Loads bytes 0x00-0x05, 0x6E-0x6F, 0x78-0x7B from EEPROM 698 * (plus 0x6C for Rhine-I/II) 699 */ 700static void rhine_reload_eeprom(long pioaddr, struct net_device *dev) 701{ 702 struct rhine_private *rp = netdev_priv(dev); 703 void __iomem *ioaddr = rp->base; 704 int i; 705 706 outb(0x20, pioaddr + MACRegEEcsr); 707 for (i = 0; i < 1024; i++) { 708 if (!(inb(pioaddr + MACRegEEcsr) & 0x20)) 709 break; 710 } 711 if (i > 512) 712 pr_info("%4d cycles used @ %s:%d\n", i, __func__, __LINE__); 713 714 /* 715 * Reloading from EEPROM overwrites ConfigA-D, so we must re-enable 716 * MMIO. If reloading EEPROM was done first this could be avoided, but 717 * it is not known if that still works with the "win98-reboot" problem. 718 */ 719 enable_mmio(pioaddr, rp->quirks); 720 721 /* Turn off EEPROM-controlled wake-up (magic packet) */ 722 if (rp->quirks & rqWOL) 723 iowrite8(ioread8(ioaddr + ConfigA) & 0xFC, ioaddr + ConfigA); 724 725} 726 727#ifdef CONFIG_NET_POLL_CONTROLLER 728static void rhine_poll(struct net_device *dev) 729{ 730 struct rhine_private *rp = netdev_priv(dev); 731 const int irq = rp->irq; 732 733 disable_irq(irq); 734 rhine_interrupt(irq, dev); 735 enable_irq(irq); 736} 737#endif 738 739static void rhine_kick_tx_threshold(struct rhine_private *rp) 740{ 741 if (rp->tx_thresh < 0xe0) { 742 void __iomem *ioaddr = rp->base; 743 744 rp->tx_thresh += 0x20; 745 BYTE_REG_BITS_SET(rp->tx_thresh, 0x80, ioaddr + TxConfig); 746 } 747} 748 749static void rhine_tx_err(struct rhine_private *rp, u32 status) 750{ 751 struct net_device *dev = rp->dev; 752 753 if (status & IntrTxAborted) { 754 netif_info(rp, tx_err, dev, 755 "Abort %08x, frame dropped\n", status); 756 } 757 758 if (status & IntrTxUnderrun) { 759 rhine_kick_tx_threshold(rp); 760 netif_info(rp, tx_err ,dev, "Transmitter underrun, " 761 "Tx threshold now %02x\n", rp->tx_thresh); 762 } 763 764 if (status & IntrTxDescRace) 765 netif_info(rp, tx_err, dev, "Tx descriptor write-back race\n"); 766 767 if ((status & IntrTxError) && 768 (status & (IntrTxAborted | IntrTxUnderrun | IntrTxDescRace)) == 0) { 769 rhine_kick_tx_threshold(rp); 770 netif_info(rp, tx_err, dev, "Unspecified error. " 771 "Tx threshold now %02x\n", rp->tx_thresh); 772 } 773 774 rhine_restart_tx(dev); 775} 776 777static void rhine_update_rx_crc_and_missed_errord(struct rhine_private *rp) 778{ 779 void __iomem *ioaddr = rp->base; 780 struct net_device_stats *stats = &rp->dev->stats; 781 782 stats->rx_crc_errors += ioread16(ioaddr + RxCRCErrs); 783 stats->rx_missed_errors += ioread16(ioaddr + RxMissed); 784 785 /* 786 * Clears the "tally counters" for CRC errors and missed frames(?). 787 * It has been reported that some chips need a write of 0 to clear 788 * these, for others the counters are set to 1 when written to and 789 * instead cleared when read. So we clear them both ways ... 790 */ 791 iowrite32(0, ioaddr + RxMissed); 792 ioread16(ioaddr + RxCRCErrs); 793 ioread16(ioaddr + RxMissed); 794} 795 796#define RHINE_EVENT_NAPI_RX (IntrRxDone | \ 797 IntrRxErr | \ 798 IntrRxEmpty | \ 799 IntrRxOverflow | \ 800 IntrRxDropped | \ 801 IntrRxNoBuf | \ 802 IntrRxWakeUp) 803 804#define RHINE_EVENT_NAPI_TX_ERR (IntrTxError | \ 805 IntrTxAborted | \ 806 IntrTxUnderrun | \ 807 IntrTxDescRace) 808#define RHINE_EVENT_NAPI_TX (IntrTxDone | RHINE_EVENT_NAPI_TX_ERR) 809 810#define RHINE_EVENT_NAPI (RHINE_EVENT_NAPI_RX | \ 811 RHINE_EVENT_NAPI_TX | \ 812 IntrStatsMax) 813#define RHINE_EVENT_SLOW (IntrPCIErr | IntrLinkChange) 814#define RHINE_EVENT (RHINE_EVENT_NAPI | RHINE_EVENT_SLOW) 815 816static int rhine_napipoll(struct napi_struct *napi, int budget) 817{ 818 struct rhine_private *rp = container_of(napi, struct rhine_private, napi); 819 struct net_device *dev = rp->dev; 820 void __iomem *ioaddr = rp->base; 821 u16 enable_mask = RHINE_EVENT & 0xffff; 822 int work_done = 0; 823 u32 status; 824 825 status = rhine_get_events(rp); 826 rhine_ack_events(rp, status & ~RHINE_EVENT_SLOW); 827 828 if (status & RHINE_EVENT_NAPI_RX) 829 work_done += rhine_rx(dev, budget); 830 831 if (status & RHINE_EVENT_NAPI_TX) { 832 if (status & RHINE_EVENT_NAPI_TX_ERR) { 833 /* Avoid scavenging before Tx engine turned off */ 834 rhine_wait_bit_low(rp, ChipCmd, CmdTxOn); 835 if (ioread8(ioaddr + ChipCmd) & CmdTxOn) 836 netif_warn(rp, tx_err, dev, "Tx still on\n"); 837 } 838 839 rhine_tx(dev); 840 841 if (status & RHINE_EVENT_NAPI_TX_ERR) 842 rhine_tx_err(rp, status); 843 } 844 845 if (status & IntrStatsMax) { 846 spin_lock(&rp->lock); 847 rhine_update_rx_crc_and_missed_errord(rp); 848 spin_unlock(&rp->lock); 849 } 850 851 if (status & RHINE_EVENT_SLOW) { 852 enable_mask &= ~RHINE_EVENT_SLOW; 853 schedule_work(&rp->slow_event_task); 854 } 855 856 if (work_done < budget) { 857 napi_complete_done(napi, work_done); 858 iowrite16(enable_mask, ioaddr + IntrEnable); 859 } 860 return work_done; 861} 862 863static void rhine_hw_init(struct net_device *dev, long pioaddr) 864{ 865 struct rhine_private *rp = netdev_priv(dev); 866 867 /* Reset the chip to erase previous misconfiguration. */ 868 rhine_chip_reset(dev); 869 870 /* Rhine-I needs extra time to recuperate before EEPROM reload */ 871 if (rp->quirks & rqRhineI) 872 msleep(5); 873 874 /* Reload EEPROM controlled bytes cleared by soft reset */ 875 if (dev_is_pci(dev->dev.parent)) 876 rhine_reload_eeprom(pioaddr, dev); 877} 878 879static const struct net_device_ops rhine_netdev_ops = { 880 .ndo_open = rhine_open, 881 .ndo_stop = rhine_close, 882 .ndo_start_xmit = rhine_start_tx, 883 .ndo_get_stats64 = rhine_get_stats64, 884 .ndo_set_rx_mode = rhine_set_rx_mode, 885 .ndo_validate_addr = eth_validate_addr, 886 .ndo_set_mac_address = eth_mac_addr, 887 .ndo_eth_ioctl = netdev_ioctl, 888 .ndo_tx_timeout = rhine_tx_timeout, 889 .ndo_vlan_rx_add_vid = rhine_vlan_rx_add_vid, 890 .ndo_vlan_rx_kill_vid = rhine_vlan_rx_kill_vid, 891#ifdef CONFIG_NET_POLL_CONTROLLER 892 .ndo_poll_controller = rhine_poll, 893#endif 894}; 895 896static int rhine_init_one_common(struct device *hwdev, u32 quirks, 897 long pioaddr, void __iomem *ioaddr, int irq) 898{ 899 struct net_device *dev; 900 struct rhine_private *rp; 901 int i, rc, phy_id; 902 u8 addr[ETH_ALEN]; 903 const char *name; 904 905 /* this should always be supported */ 906 rc = dma_set_mask(hwdev, DMA_BIT_MASK(32)); 907 if (rc) { 908 dev_err(hwdev, "32-bit DMA addresses not supported by the card!?\n"); 909 goto err_out; 910 } 911 912 dev = alloc_etherdev(sizeof(struct rhine_private)); 913 if (!dev) { 914 rc = -ENOMEM; 915 goto err_out; 916 } 917 SET_NETDEV_DEV(dev, hwdev); 918 919 rp = netdev_priv(dev); 920 rp->dev = dev; 921 rp->quirks = quirks; 922 rp->pioaddr = pioaddr; 923 rp->base = ioaddr; 924 rp->irq = irq; 925 rp->msg_enable = netif_msg_init(debug, RHINE_MSG_DEFAULT); 926 927 phy_id = rp->quirks & rqIntPHY ? 1 : 0; 928 929 u64_stats_init(&rp->tx_stats.syncp); 930 u64_stats_init(&rp->rx_stats.syncp); 931 932 /* Get chip registers into a sane state */ 933 rhine_power_init(dev); 934 rhine_hw_init(dev, pioaddr); 935 936 for (i = 0; i < 6; i++) 937 addr[i] = ioread8(ioaddr + StationAddr + i); 938 eth_hw_addr_set(dev, addr); 939 940 if (!is_valid_ether_addr(dev->dev_addr)) { 941 /* Report it and use a random ethernet address instead */ 942 netdev_err(dev, "Invalid MAC address: %pM\n", dev->dev_addr); 943 eth_hw_addr_random(dev); 944 netdev_info(dev, "Using random MAC address: %pM\n", 945 dev->dev_addr); 946 } 947 948 /* For Rhine-I/II, phy_id is loaded from EEPROM */ 949 if (!phy_id) 950 phy_id = ioread8(ioaddr + 0x6C); 951 952 spin_lock_init(&rp->lock); 953 mutex_init(&rp->task_lock); 954 INIT_WORK(&rp->reset_task, rhine_reset_task); 955 INIT_WORK(&rp->slow_event_task, rhine_slow_event_task); 956 957 rp->mii_if.dev = dev; 958 rp->mii_if.mdio_read = mdio_read; 959 rp->mii_if.mdio_write = mdio_write; 960 rp->mii_if.phy_id_mask = 0x1f; 961 rp->mii_if.reg_num_mask = 0x1f; 962 963 /* The chip-specific entries in the device structure. */ 964 dev->netdev_ops = &rhine_netdev_ops; 965 dev->ethtool_ops = &netdev_ethtool_ops; 966 dev->watchdog_timeo = TX_TIMEOUT; 967 968 netif_napi_add(dev, &rp->napi, rhine_napipoll); 969 970 if (rp->quirks & rqRhineI) 971 dev->features |= NETIF_F_SG|NETIF_F_HW_CSUM; 972 973 if (rp->quirks & rqMgmt) 974 dev->features |= NETIF_F_HW_VLAN_CTAG_TX | 975 NETIF_F_HW_VLAN_CTAG_RX | 976 NETIF_F_HW_VLAN_CTAG_FILTER; 977 978 /* dev->name not defined before register_netdev()! */ 979 rc = register_netdev(dev); 980 if (rc) 981 goto err_out_free_netdev; 982 983 if (rp->quirks & rqRhineI) 984 name = "Rhine"; 985 else if (rp->quirks & rqStatusWBRace) 986 name = "Rhine II"; 987 else if (rp->quirks & rqMgmt) 988 name = "Rhine III (Management Adapter)"; 989 else 990 name = "Rhine III"; 991 992 netdev_info(dev, "VIA %s at %p, %pM, IRQ %d\n", 993 name, ioaddr, dev->dev_addr, rp->irq); 994 995 dev_set_drvdata(hwdev, dev); 996 997 { 998 u16 mii_cmd; 999 int mii_status = mdio_read(dev, phy_id, 1); 1000 mii_cmd = mdio_read(dev, phy_id, MII_BMCR) & ~BMCR_ISOLATE; 1001 mdio_write(dev, phy_id, MII_BMCR, mii_cmd); 1002 if (mii_status != 0xffff && mii_status != 0x0000) { 1003 rp->mii_if.advertising = mdio_read(dev, phy_id, 4); 1004 netdev_info(dev, 1005 "MII PHY found at address %d, status 0x%04x advertising %04x Link %04x\n", 1006 phy_id, 1007 mii_status, rp->mii_if.advertising, 1008 mdio_read(dev, phy_id, 5)); 1009 1010 /* set IFF_RUNNING */ 1011 if (mii_status & BMSR_LSTATUS) 1012 netif_carrier_on(dev); 1013 else 1014 netif_carrier_off(dev); 1015 1016 } 1017 } 1018 rp->mii_if.phy_id = phy_id; 1019 if (avoid_D3) 1020 netif_info(rp, probe, dev, "No D3 power state at shutdown\n"); 1021 1022 return 0; 1023 1024err_out_free_netdev: 1025 free_netdev(dev); 1026err_out: 1027 return rc; 1028} 1029 1030static int rhine_init_one_pci(struct pci_dev *pdev, 1031 const struct pci_device_id *ent) 1032{ 1033 struct device *hwdev = &pdev->dev; 1034 int rc; 1035 long pioaddr, memaddr; 1036 void __iomem *ioaddr; 1037 int io_size = pdev->revision < VTunknown0 ? 128 : 256; 1038 1039/* This driver was written to use PCI memory space. Some early versions 1040 * of the Rhine may only work correctly with I/O space accesses. 1041 * TODO: determine for which revisions this is true and assign the flag 1042 * in code as opposed to this Kconfig option (???) 1043 */ 1044#ifdef CONFIG_VIA_RHINE_MMIO 1045 u32 quirks = rqNeedEnMMIO; 1046#else 1047 u32 quirks = 0; 1048#endif 1049 1050 rc = pci_enable_device(pdev); 1051 if (rc) 1052 goto err_out; 1053 1054 if (pdev->revision < VTunknown0) { 1055 quirks |= rqRhineI; 1056 } else if (pdev->revision >= VT6102) { 1057 quirks |= rqWOL | rqForceReset; 1058 if (pdev->revision < VT6105) { 1059 quirks |= rqStatusWBRace; 1060 } else { 1061 quirks |= rqIntPHY; 1062 if (pdev->revision >= VT6105_B0) 1063 quirks |= rq6patterns; 1064 if (pdev->revision >= VT6105M) 1065 quirks |= rqMgmt; 1066 } 1067 } 1068 1069 /* sanity check */ 1070 if ((pci_resource_len(pdev, 0) < io_size) || 1071 (pci_resource_len(pdev, 1) < io_size)) { 1072 rc = -EIO; 1073 dev_err(hwdev, "Insufficient PCI resources, aborting\n"); 1074 goto err_out_pci_disable; 1075 } 1076 1077 pioaddr = pci_resource_start(pdev, 0); 1078 memaddr = pci_resource_start(pdev, 1); 1079 1080 pci_set_master(pdev); 1081 1082 rc = pci_request_regions(pdev, DRV_NAME); 1083 if (rc) 1084 goto err_out_pci_disable; 1085 1086 ioaddr = pci_iomap(pdev, (quirks & rqNeedEnMMIO ? 1 : 0), io_size); 1087 if (!ioaddr) { 1088 rc = -EIO; 1089 dev_err(hwdev, 1090 "ioremap failed for device %s, region 0x%X @ 0x%lX\n", 1091 dev_name(hwdev), io_size, memaddr); 1092 goto err_out_free_res; 1093 } 1094 1095 enable_mmio(pioaddr, quirks); 1096 1097 rc = verify_mmio(hwdev, pioaddr, ioaddr, quirks); 1098 if (rc) 1099 goto err_out_unmap; 1100 1101 rc = rhine_init_one_common(&pdev->dev, quirks, 1102 pioaddr, ioaddr, pdev->irq); 1103 if (!rc) 1104 return 0; 1105 1106err_out_unmap: 1107 pci_iounmap(pdev, ioaddr); 1108err_out_free_res: 1109 pci_release_regions(pdev); 1110err_out_pci_disable: 1111 pci_disable_device(pdev); 1112err_out: 1113 return rc; 1114} 1115 1116static int rhine_init_one_platform(struct platform_device *pdev) 1117{ 1118 const u32 *quirks; 1119 int irq; 1120 void __iomem *ioaddr; 1121 1122 quirks = of_device_get_match_data(&pdev->dev); 1123 if (!quirks) 1124 return -EINVAL; 1125 1126 ioaddr = devm_platform_ioremap_resource(pdev, 0); 1127 if (IS_ERR(ioaddr)) 1128 return PTR_ERR(ioaddr); 1129 1130 irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 1131 if (!irq) 1132 return -EINVAL; 1133 1134 return rhine_init_one_common(&pdev->dev, *quirks, 1135 (long)ioaddr, ioaddr, irq); 1136} 1137 1138static int alloc_ring(struct net_device* dev) 1139{ 1140 struct rhine_private *rp = netdev_priv(dev); 1141 struct device *hwdev = dev->dev.parent; 1142 void *ring; 1143 dma_addr_t ring_dma; 1144 1145 ring = dma_alloc_coherent(hwdev, 1146 RX_RING_SIZE * sizeof(struct rx_desc) + 1147 TX_RING_SIZE * sizeof(struct tx_desc), 1148 &ring_dma, 1149 GFP_ATOMIC); 1150 if (!ring) { 1151 netdev_err(dev, "Could not allocate DMA memory\n"); 1152 return -ENOMEM; 1153 } 1154 if (rp->quirks & rqRhineI) { 1155 rp->tx_bufs = dma_alloc_coherent(hwdev, 1156 PKT_BUF_SZ * TX_RING_SIZE, 1157 &rp->tx_bufs_dma, 1158 GFP_ATOMIC); 1159 if (rp->tx_bufs == NULL) { 1160 dma_free_coherent(hwdev, 1161 RX_RING_SIZE * sizeof(struct rx_desc) + 1162 TX_RING_SIZE * sizeof(struct tx_desc), 1163 ring, ring_dma); 1164 return -ENOMEM; 1165 } 1166 } 1167 1168 rp->rx_ring = ring; 1169 rp->tx_ring = ring + RX_RING_SIZE * sizeof(struct rx_desc); 1170 rp->rx_ring_dma = ring_dma; 1171 rp->tx_ring_dma = ring_dma + RX_RING_SIZE * sizeof(struct rx_desc); 1172 1173 return 0; 1174} 1175 1176static void free_ring(struct net_device* dev) 1177{ 1178 struct rhine_private *rp = netdev_priv(dev); 1179 struct device *hwdev = dev->dev.parent; 1180 1181 dma_free_coherent(hwdev, 1182 RX_RING_SIZE * sizeof(struct rx_desc) + 1183 TX_RING_SIZE * sizeof(struct tx_desc), 1184 rp->rx_ring, rp->rx_ring_dma); 1185 rp->tx_ring = NULL; 1186 1187 if (rp->tx_bufs) 1188 dma_free_coherent(hwdev, PKT_BUF_SZ * TX_RING_SIZE, 1189 rp->tx_bufs, rp->tx_bufs_dma); 1190 1191 rp->tx_bufs = NULL; 1192 1193} 1194 1195struct rhine_skb_dma { 1196 struct sk_buff *skb; 1197 dma_addr_t dma; 1198}; 1199 1200static inline int rhine_skb_dma_init(struct net_device *dev, 1201 struct rhine_skb_dma *sd) 1202{ 1203 struct rhine_private *rp = netdev_priv(dev); 1204 struct device *hwdev = dev->dev.parent; 1205 const int size = rp->rx_buf_sz; 1206 1207 sd->skb = netdev_alloc_skb(dev, size); 1208 if (!sd->skb) 1209 return -ENOMEM; 1210 1211 sd->dma = dma_map_single(hwdev, sd->skb->data, size, DMA_FROM_DEVICE); 1212 if (unlikely(dma_mapping_error(hwdev, sd->dma))) { 1213 netif_err(rp, drv, dev, "Rx DMA mapping failure\n"); 1214 dev_kfree_skb_any(sd->skb); 1215 return -EIO; 1216 } 1217 1218 return 0; 1219} 1220 1221static void rhine_reset_rbufs(struct rhine_private *rp) 1222{ 1223 int i; 1224 1225 rp->cur_rx = 0; 1226 1227 for (i = 0; i < RX_RING_SIZE; i++) 1228 rp->rx_ring[i].rx_status = cpu_to_le32(DescOwn); 1229} 1230 1231static inline void rhine_skb_dma_nic_store(struct rhine_private *rp, 1232 struct rhine_skb_dma *sd, int entry) 1233{ 1234 rp->rx_skbuff_dma[entry] = sd->dma; 1235 rp->rx_skbuff[entry] = sd->skb; 1236 1237 rp->rx_ring[entry].addr = cpu_to_le32(sd->dma); 1238 dma_wmb(); 1239} 1240 1241static void free_rbufs(struct net_device* dev); 1242 1243static int alloc_rbufs(struct net_device *dev) 1244{ 1245 struct rhine_private *rp = netdev_priv(dev); 1246 dma_addr_t next; 1247 int rc, i; 1248 1249 rp->rx_buf_sz = (dev->mtu <= 1500 ? PKT_BUF_SZ : dev->mtu + 32); 1250 next = rp->rx_ring_dma; 1251 1252 /* Init the ring entries */ 1253 for (i = 0; i < RX_RING_SIZE; i++) { 1254 rp->rx_ring[i].rx_status = 0; 1255 rp->rx_ring[i].desc_length = cpu_to_le32(rp->rx_buf_sz); 1256 next += sizeof(struct rx_desc); 1257 rp->rx_ring[i].next_desc = cpu_to_le32(next); 1258 rp->rx_skbuff[i] = NULL; 1259 } 1260 /* Mark the last entry as wrapping the ring. */ 1261 rp->rx_ring[i-1].next_desc = cpu_to_le32(rp->rx_ring_dma); 1262 1263 /* Fill in the Rx buffers. Handle allocation failure gracefully. */ 1264 for (i = 0; i < RX_RING_SIZE; i++) { 1265 struct rhine_skb_dma sd; 1266 1267 rc = rhine_skb_dma_init(dev, &sd); 1268 if (rc < 0) { 1269 free_rbufs(dev); 1270 goto out; 1271 } 1272 1273 rhine_skb_dma_nic_store(rp, &sd, i); 1274 } 1275 1276 rhine_reset_rbufs(rp); 1277out: 1278 return rc; 1279} 1280 1281static void free_rbufs(struct net_device* dev) 1282{ 1283 struct rhine_private *rp = netdev_priv(dev); 1284 struct device *hwdev = dev->dev.parent; 1285 int i; 1286 1287 /* Free all the skbuffs in the Rx queue. */ 1288 for (i = 0; i < RX_RING_SIZE; i++) { 1289 rp->rx_ring[i].rx_status = 0; 1290 rp->rx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */ 1291 if (rp->rx_skbuff[i]) { 1292 dma_unmap_single(hwdev, 1293 rp->rx_skbuff_dma[i], 1294 rp->rx_buf_sz, DMA_FROM_DEVICE); 1295 dev_kfree_skb(rp->rx_skbuff[i]); 1296 } 1297 rp->rx_skbuff[i] = NULL; 1298 } 1299} 1300 1301static void alloc_tbufs(struct net_device* dev) 1302{ 1303 struct rhine_private *rp = netdev_priv(dev); 1304 dma_addr_t next; 1305 int i; 1306 1307 rp->dirty_tx = rp->cur_tx = 0; 1308 next = rp->tx_ring_dma; 1309 for (i = 0; i < TX_RING_SIZE; i++) { 1310 rp->tx_skbuff[i] = NULL; 1311 rp->tx_ring[i].tx_status = 0; 1312 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC); 1313 next += sizeof(struct tx_desc); 1314 rp->tx_ring[i].next_desc = cpu_to_le32(next); 1315 if (rp->quirks & rqRhineI) 1316 rp->tx_buf[i] = &rp->tx_bufs[i * PKT_BUF_SZ]; 1317 } 1318 rp->tx_ring[i-1].next_desc = cpu_to_le32(rp->tx_ring_dma); 1319 1320 netdev_reset_queue(dev); 1321} 1322 1323static void free_tbufs(struct net_device* dev) 1324{ 1325 struct rhine_private *rp = netdev_priv(dev); 1326 struct device *hwdev = dev->dev.parent; 1327 int i; 1328 1329 for (i = 0; i < TX_RING_SIZE; i++) { 1330 rp->tx_ring[i].tx_status = 0; 1331 rp->tx_ring[i].desc_length = cpu_to_le32(TXDESC); 1332 rp->tx_ring[i].addr = cpu_to_le32(0xBADF00D0); /* An invalid address. */ 1333 if (rp->tx_skbuff[i]) { 1334 if (rp->tx_skbuff_dma[i]) { 1335 dma_unmap_single(hwdev, 1336 rp->tx_skbuff_dma[i], 1337 rp->tx_skbuff[i]->len, 1338 DMA_TO_DEVICE); 1339 } 1340 dev_kfree_skb(rp->tx_skbuff[i]); 1341 } 1342 rp->tx_skbuff[i] = NULL; 1343 rp->tx_buf[i] = NULL; 1344 } 1345} 1346 1347static void rhine_check_media(struct net_device *dev, unsigned int init_media) 1348{ 1349 struct rhine_private *rp = netdev_priv(dev); 1350 void __iomem *ioaddr = rp->base; 1351 1352 if (!rp->mii_if.force_media) 1353 mii_check_media(&rp->mii_if, netif_msg_link(rp), init_media); 1354 1355 if (rp->mii_if.full_duplex) 1356 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1FDuplex, 1357 ioaddr + ChipCmd1); 1358 else 1359 iowrite8(ioread8(ioaddr + ChipCmd1) & ~Cmd1FDuplex, 1360 ioaddr + ChipCmd1); 1361 1362 netif_info(rp, link, dev, "force_media %d, carrier %d\n", 1363 rp->mii_if.force_media, netif_carrier_ok(dev)); 1364} 1365 1366/* Called after status of force_media possibly changed */ 1367static void rhine_set_carrier(struct mii_if_info *mii) 1368{ 1369 struct net_device *dev = mii->dev; 1370 struct rhine_private *rp = netdev_priv(dev); 1371 1372 if (mii->force_media) { 1373 /* autoneg is off: Link is always assumed to be up */ 1374 if (!netif_carrier_ok(dev)) 1375 netif_carrier_on(dev); 1376 } 1377 1378 rhine_check_media(dev, 0); 1379 1380 netif_info(rp, link, dev, "force_media %d, carrier %d\n", 1381 mii->force_media, netif_carrier_ok(dev)); 1382} 1383 1384/** 1385 * rhine_set_cam - set CAM multicast filters 1386 * @ioaddr: register block of this Rhine 1387 * @idx: multicast CAM index [0..MCAM_SIZE-1] 1388 * @addr: multicast address (6 bytes) 1389 * 1390 * Load addresses into multicast filters. 1391 */ 1392static void rhine_set_cam(void __iomem *ioaddr, int idx, u8 *addr) 1393{ 1394 int i; 1395 1396 iowrite8(CAMC_CAMEN, ioaddr + CamCon); 1397 wmb(); 1398 1399 /* Paranoid -- idx out of range should never happen */ 1400 idx &= (MCAM_SIZE - 1); 1401 1402 iowrite8((u8) idx, ioaddr + CamAddr); 1403 1404 for (i = 0; i < 6; i++, addr++) 1405 iowrite8(*addr, ioaddr + MulticastFilter0 + i); 1406 udelay(10); 1407 wmb(); 1408 1409 iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon); 1410 udelay(10); 1411 1412 iowrite8(0, ioaddr + CamCon); 1413} 1414 1415/** 1416 * rhine_set_vlan_cam - set CAM VLAN filters 1417 * @ioaddr: register block of this Rhine 1418 * @idx: VLAN CAM index [0..VCAM_SIZE-1] 1419 * @addr: VLAN ID (2 bytes) 1420 * 1421 * Load addresses into VLAN filters. 1422 */ 1423static void rhine_set_vlan_cam(void __iomem *ioaddr, int idx, u8 *addr) 1424{ 1425 iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon); 1426 wmb(); 1427 1428 /* Paranoid -- idx out of range should never happen */ 1429 idx &= (VCAM_SIZE - 1); 1430 1431 iowrite8((u8) idx, ioaddr + CamAddr); 1432 1433 iowrite16(*((u16 *) addr), ioaddr + MulticastFilter0 + 6); 1434 udelay(10); 1435 wmb(); 1436 1437 iowrite8(CAMC_CAMWR | CAMC_CAMEN, ioaddr + CamCon); 1438 udelay(10); 1439 1440 iowrite8(0, ioaddr + CamCon); 1441} 1442 1443/** 1444 * rhine_set_cam_mask - set multicast CAM mask 1445 * @ioaddr: register block of this Rhine 1446 * @mask: multicast CAM mask 1447 * 1448 * Mask sets multicast filters active/inactive. 1449 */ 1450static void rhine_set_cam_mask(void __iomem *ioaddr, u32 mask) 1451{ 1452 iowrite8(CAMC_CAMEN, ioaddr + CamCon); 1453 wmb(); 1454 1455 /* write mask */ 1456 iowrite32(mask, ioaddr + CamMask); 1457 1458 /* disable CAMEN */ 1459 iowrite8(0, ioaddr + CamCon); 1460} 1461 1462/** 1463 * rhine_set_vlan_cam_mask - set VLAN CAM mask 1464 * @ioaddr: register block of this Rhine 1465 * @mask: VLAN CAM mask 1466 * 1467 * Mask sets VLAN filters active/inactive. 1468 */ 1469static void rhine_set_vlan_cam_mask(void __iomem *ioaddr, u32 mask) 1470{ 1471 iowrite8(CAMC_CAMEN | CAMC_VCAMSL, ioaddr + CamCon); 1472 wmb(); 1473 1474 /* write mask */ 1475 iowrite32(mask, ioaddr + CamMask); 1476 1477 /* disable CAMEN */ 1478 iowrite8(0, ioaddr + CamCon); 1479} 1480 1481/** 1482 * rhine_init_cam_filter - initialize CAM filters 1483 * @dev: network device 1484 * 1485 * Initialize (disable) hardware VLAN and multicast support on this 1486 * Rhine. 1487 */ 1488static void rhine_init_cam_filter(struct net_device *dev) 1489{ 1490 struct rhine_private *rp = netdev_priv(dev); 1491 void __iomem *ioaddr = rp->base; 1492 1493 /* Disable all CAMs */ 1494 rhine_set_vlan_cam_mask(ioaddr, 0); 1495 rhine_set_cam_mask(ioaddr, 0); 1496 1497 /* disable hardware VLAN support */ 1498 BYTE_REG_BITS_ON(TCR_PQEN, ioaddr + TxConfig); 1499 BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1); 1500} 1501 1502/** 1503 * rhine_update_vcam - update VLAN CAM filters 1504 * @dev: rhine_private data of this Rhine 1505 * 1506 * Update VLAN CAM filters to match configuration change. 1507 */ 1508static void rhine_update_vcam(struct net_device *dev) 1509{ 1510 struct rhine_private *rp = netdev_priv(dev); 1511 void __iomem *ioaddr = rp->base; 1512 u16 vid; 1513 u32 vCAMmask = 0; /* 32 vCAMs (6105M and better) */ 1514 unsigned int i = 0; 1515 1516 for_each_set_bit(vid, rp->active_vlans, VLAN_N_VID) { 1517 rhine_set_vlan_cam(ioaddr, i, (u8 *)&vid); 1518 vCAMmask |= 1 << i; 1519 if (++i >= VCAM_SIZE) 1520 break; 1521 } 1522 rhine_set_vlan_cam_mask(ioaddr, vCAMmask); 1523} 1524 1525static int rhine_vlan_rx_add_vid(struct net_device *dev, __be16 proto, u16 vid) 1526{ 1527 struct rhine_private *rp = netdev_priv(dev); 1528 1529 spin_lock_bh(&rp->lock); 1530 set_bit(vid, rp->active_vlans); 1531 rhine_update_vcam(dev); 1532 spin_unlock_bh(&rp->lock); 1533 return 0; 1534} 1535 1536static int rhine_vlan_rx_kill_vid(struct net_device *dev, __be16 proto, u16 vid) 1537{ 1538 struct rhine_private *rp = netdev_priv(dev); 1539 1540 spin_lock_bh(&rp->lock); 1541 clear_bit(vid, rp->active_vlans); 1542 rhine_update_vcam(dev); 1543 spin_unlock_bh(&rp->lock); 1544 return 0; 1545} 1546 1547static void init_registers(struct net_device *dev) 1548{ 1549 struct rhine_private *rp = netdev_priv(dev); 1550 void __iomem *ioaddr = rp->base; 1551 int i; 1552 1553 for (i = 0; i < 6; i++) 1554 iowrite8(dev->dev_addr[i], ioaddr + StationAddr + i); 1555 1556 /* Initialize other registers. */ 1557 iowrite16(0x0006, ioaddr + PCIBusConfig); /* Tune configuration??? */ 1558 /* Configure initial FIFO thresholds. */ 1559 iowrite8(0x20, ioaddr + TxConfig); 1560 rp->tx_thresh = 0x20; 1561 rp->rx_thresh = 0x60; /* Written in rhine_set_rx_mode(). */ 1562 1563 iowrite32(rp->rx_ring_dma, ioaddr + RxRingPtr); 1564 iowrite32(rp->tx_ring_dma, ioaddr + TxRingPtr); 1565 1566 rhine_set_rx_mode(dev); 1567 1568 if (rp->quirks & rqMgmt) 1569 rhine_init_cam_filter(dev); 1570 1571 napi_enable_locked(&rp->napi); 1572 1573 iowrite16(RHINE_EVENT & 0xffff, ioaddr + IntrEnable); 1574 1575 iowrite16(CmdStart | CmdTxOn | CmdRxOn | (Cmd1NoTxPoll << 8), 1576 ioaddr + ChipCmd); 1577 rhine_check_media(dev, 1); 1578} 1579 1580/* Enable MII link status auto-polling (required for IntrLinkChange) */ 1581static void rhine_enable_linkmon(struct rhine_private *rp) 1582{ 1583 void __iomem *ioaddr = rp->base; 1584 1585 iowrite8(0, ioaddr + MIICmd); 1586 iowrite8(MII_BMSR, ioaddr + MIIRegAddr); 1587 iowrite8(0x80, ioaddr + MIICmd); 1588 1589 rhine_wait_bit_high(rp, MIIRegAddr, 0x20); 1590 1591 iowrite8(MII_BMSR | 0x40, ioaddr + MIIRegAddr); 1592} 1593 1594/* Disable MII link status auto-polling (required for MDIO access) */ 1595static void rhine_disable_linkmon(struct rhine_private *rp) 1596{ 1597 void __iomem *ioaddr = rp->base; 1598 1599 iowrite8(0, ioaddr + MIICmd); 1600 1601 if (rp->quirks & rqRhineI) { 1602 iowrite8(0x01, ioaddr + MIIRegAddr); // MII_BMSR 1603 1604 /* Can be called from ISR. Evil. */ 1605 mdelay(1); 1606 1607 /* 0x80 must be set immediately before turning it off */ 1608 iowrite8(0x80, ioaddr + MIICmd); 1609 1610 rhine_wait_bit_high(rp, MIIRegAddr, 0x20); 1611 1612 /* Heh. Now clear 0x80 again. */ 1613 iowrite8(0, ioaddr + MIICmd); 1614 } 1615 else 1616 rhine_wait_bit_high(rp, MIIRegAddr, 0x80); 1617} 1618 1619/* Read and write over the MII Management Data I/O (MDIO) interface. */ 1620 1621static int mdio_read(struct net_device *dev, int phy_id, int regnum) 1622{ 1623 struct rhine_private *rp = netdev_priv(dev); 1624 void __iomem *ioaddr = rp->base; 1625 int result; 1626 1627 rhine_disable_linkmon(rp); 1628 1629 /* rhine_disable_linkmon already cleared MIICmd */ 1630 iowrite8(phy_id, ioaddr + MIIPhyAddr); 1631 iowrite8(regnum, ioaddr + MIIRegAddr); 1632 iowrite8(0x40, ioaddr + MIICmd); /* Trigger read */ 1633 rhine_wait_bit_low(rp, MIICmd, 0x40); 1634 result = ioread16(ioaddr + MIIData); 1635 1636 rhine_enable_linkmon(rp); 1637 return result; 1638} 1639 1640static void mdio_write(struct net_device *dev, int phy_id, int regnum, int value) 1641{ 1642 struct rhine_private *rp = netdev_priv(dev); 1643 void __iomem *ioaddr = rp->base; 1644 1645 rhine_disable_linkmon(rp); 1646 1647 /* rhine_disable_linkmon already cleared MIICmd */ 1648 iowrite8(phy_id, ioaddr + MIIPhyAddr); 1649 iowrite8(regnum, ioaddr + MIIRegAddr); 1650 iowrite16(value, ioaddr + MIIData); 1651 iowrite8(0x20, ioaddr + MIICmd); /* Trigger write */ 1652 rhine_wait_bit_low(rp, MIICmd, 0x20); 1653 1654 rhine_enable_linkmon(rp); 1655} 1656 1657static void rhine_task_disable(struct rhine_private *rp) 1658{ 1659 mutex_lock(&rp->task_lock); 1660 rp->task_enable = false; 1661 mutex_unlock(&rp->task_lock); 1662 1663 cancel_work_sync(&rp->slow_event_task); 1664 cancel_work_sync(&rp->reset_task); 1665} 1666 1667static void rhine_task_enable(struct rhine_private *rp) 1668{ 1669 mutex_lock(&rp->task_lock); 1670 rp->task_enable = true; 1671 mutex_unlock(&rp->task_lock); 1672} 1673 1674static int rhine_open(struct net_device *dev) 1675{ 1676 struct rhine_private *rp = netdev_priv(dev); 1677 void __iomem *ioaddr = rp->base; 1678 int rc; 1679 1680 rc = request_irq(rp->irq, rhine_interrupt, IRQF_SHARED, dev->name, dev); 1681 if (rc) 1682 goto out; 1683 1684 netif_dbg(rp, ifup, dev, "%s() irq %d\n", __func__, rp->irq); 1685 1686 rc = alloc_ring(dev); 1687 if (rc < 0) 1688 goto out_free_irq; 1689 1690 rc = alloc_rbufs(dev); 1691 if (rc < 0) 1692 goto out_free_ring; 1693 1694 alloc_tbufs(dev); 1695 enable_mmio(rp->pioaddr, rp->quirks); 1696 rhine_power_init(dev); 1697 rhine_chip_reset(dev); 1698 rhine_task_enable(rp); 1699 1700 netdev_lock(dev); 1701 init_registers(dev); 1702 netdev_unlock(dev); 1703 1704 netif_dbg(rp, ifup, dev, "%s() Done - status %04x MII status: %04x\n", 1705 __func__, ioread16(ioaddr + ChipCmd), 1706 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR)); 1707 1708 netif_start_queue(dev); 1709 1710out: 1711 return rc; 1712 1713out_free_ring: 1714 free_ring(dev); 1715out_free_irq: 1716 free_irq(rp->irq, dev); 1717 goto out; 1718} 1719 1720static void rhine_reset_task(struct work_struct *work) 1721{ 1722 struct rhine_private *rp = container_of(work, struct rhine_private, 1723 reset_task); 1724 struct net_device *dev = rp->dev; 1725 1726 mutex_lock(&rp->task_lock); 1727 1728 if (!rp->task_enable) 1729 goto out_unlock; 1730 1731 napi_disable(&rp->napi); 1732 netif_tx_disable(dev); 1733 1734 netdev_lock(dev); 1735 spin_lock_bh(&rp->lock); 1736 1737 /* clear all descriptors */ 1738 free_tbufs(dev); 1739 alloc_tbufs(dev); 1740 1741 rhine_reset_rbufs(rp); 1742 1743 /* Reinitialize the hardware. */ 1744 rhine_chip_reset(dev); 1745 init_registers(dev); 1746 1747 spin_unlock_bh(&rp->lock); 1748 netdev_unlock(dev); 1749 1750 netif_trans_update(dev); /* prevent tx timeout */ 1751 dev->stats.tx_errors++; 1752 netif_wake_queue(dev); 1753 1754out_unlock: 1755 mutex_unlock(&rp->task_lock); 1756} 1757 1758static void rhine_tx_timeout(struct net_device *dev, unsigned int txqueue) 1759{ 1760 struct rhine_private *rp = netdev_priv(dev); 1761 void __iomem *ioaddr = rp->base; 1762 1763 netdev_warn(dev, "Transmit timed out, status %04x, PHY status %04x, resetting...\n", 1764 ioread16(ioaddr + IntrStatus), 1765 mdio_read(dev, rp->mii_if.phy_id, MII_BMSR)); 1766 1767 schedule_work(&rp->reset_task); 1768} 1769 1770static inline bool rhine_tx_queue_full(struct rhine_private *rp) 1771{ 1772 return (rp->cur_tx - rp->dirty_tx) >= TX_QUEUE_LEN; 1773} 1774 1775static netdev_tx_t rhine_start_tx(struct sk_buff *skb, 1776 struct net_device *dev) 1777{ 1778 struct rhine_private *rp = netdev_priv(dev); 1779 struct device *hwdev = dev->dev.parent; 1780 void __iomem *ioaddr = rp->base; 1781 unsigned entry; 1782 1783 /* Caution: the write order is important here, set the field 1784 with the "ownership" bits last. */ 1785 1786 /* Calculate the next Tx descriptor entry. */ 1787 entry = rp->cur_tx % TX_RING_SIZE; 1788 1789 if (skb_padto(skb, ETH_ZLEN)) 1790 return NETDEV_TX_OK; 1791 1792 rp->tx_skbuff[entry] = skb; 1793 1794 if ((rp->quirks & rqRhineI) && 1795 (((unsigned long)skb->data & 3) || skb_shinfo(skb)->nr_frags != 0 || skb->ip_summed == CHECKSUM_PARTIAL)) { 1796 /* Must use alignment buffer. */ 1797 if (skb->len > PKT_BUF_SZ) { 1798 /* packet too long, drop it */ 1799 dev_kfree_skb_any(skb); 1800 rp->tx_skbuff[entry] = NULL; 1801 dev->stats.tx_dropped++; 1802 return NETDEV_TX_OK; 1803 } 1804 1805 /* Padding is not copied and so must be redone. */ 1806 skb_copy_and_csum_dev(skb, rp->tx_buf[entry]); 1807 if (skb->len < ETH_ZLEN) 1808 memset(rp->tx_buf[entry] + skb->len, 0, 1809 ETH_ZLEN - skb->len); 1810 rp->tx_skbuff_dma[entry] = 0; 1811 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_bufs_dma + 1812 (rp->tx_buf[entry] - 1813 rp->tx_bufs)); 1814 } else { 1815 rp->tx_skbuff_dma[entry] = 1816 dma_map_single(hwdev, skb->data, skb->len, 1817 DMA_TO_DEVICE); 1818 if (dma_mapping_error(hwdev, rp->tx_skbuff_dma[entry])) { 1819 dev_kfree_skb_any(skb); 1820 rp->tx_skbuff_dma[entry] = 0; 1821 dev->stats.tx_dropped++; 1822 return NETDEV_TX_OK; 1823 } 1824 rp->tx_ring[entry].addr = cpu_to_le32(rp->tx_skbuff_dma[entry]); 1825 } 1826 1827 rp->tx_ring[entry].desc_length = 1828 cpu_to_le32(TXDESC | (skb->len >= ETH_ZLEN ? skb->len : ETH_ZLEN)); 1829 1830 if (unlikely(skb_vlan_tag_present(skb))) { 1831 u16 vid_pcp = skb_vlan_tag_get(skb); 1832 1833 /* drop CFI/DEI bit, register needs VID and PCP */ 1834 vid_pcp = (vid_pcp & VLAN_VID_MASK) | 1835 ((vid_pcp & VLAN_PRIO_MASK) >> 1); 1836 rp->tx_ring[entry].tx_status = cpu_to_le32((vid_pcp) << 16); 1837 /* request tagging */ 1838 rp->tx_ring[entry].desc_length |= cpu_to_le32(0x020000); 1839 } 1840 else 1841 rp->tx_ring[entry].tx_status = 0; 1842 1843 netdev_sent_queue(dev, skb->len); 1844 /* lock eth irq */ 1845 dma_wmb(); 1846 rp->tx_ring[entry].tx_status |= cpu_to_le32(DescOwn); 1847 wmb(); 1848 1849 rp->cur_tx++; 1850 /* 1851 * Nobody wants cur_tx write to rot for ages after the NIC will have 1852 * seen the transmit request, especially as the transmit completion 1853 * handler could miss it. 1854 */ 1855 smp_wmb(); 1856 1857 /* Non-x86 Todo: explicitly flush cache lines here. */ 1858 1859 if (skb_vlan_tag_present(skb)) 1860 /* Tx queues are bits 7-0 (first Tx queue: bit 7) */ 1861 BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake); 1862 1863 /* Wake the potentially-idle transmit channel */ 1864 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand, 1865 ioaddr + ChipCmd1); 1866 IOSYNC; 1867 1868 /* dirty_tx may be pessimistically out-of-sync. See rhine_tx. */ 1869 if (rhine_tx_queue_full(rp)) { 1870 netif_stop_queue(dev); 1871 smp_rmb(); 1872 /* Rejuvenate. */ 1873 if (!rhine_tx_queue_full(rp)) 1874 netif_wake_queue(dev); 1875 } 1876 1877 netif_dbg(rp, tx_queued, dev, "Transmit frame #%d queued in slot %d\n", 1878 rp->cur_tx - 1, entry); 1879 1880 return NETDEV_TX_OK; 1881} 1882 1883static void rhine_irq_disable(struct rhine_private *rp) 1884{ 1885 iowrite16(0x0000, rp->base + IntrEnable); 1886} 1887 1888/* The interrupt handler does all of the Rx thread work and cleans up 1889 after the Tx thread. */ 1890static irqreturn_t rhine_interrupt(int irq, void *dev_instance) 1891{ 1892 struct net_device *dev = dev_instance; 1893 struct rhine_private *rp = netdev_priv(dev); 1894 u32 status; 1895 int handled = 0; 1896 1897 status = rhine_get_events(rp); 1898 1899 netif_dbg(rp, intr, dev, "Interrupt, status %08x\n", status); 1900 1901 if (status & RHINE_EVENT) { 1902 handled = 1; 1903 1904 rhine_irq_disable(rp); 1905 napi_schedule(&rp->napi); 1906 } 1907 1908 if (status & ~(IntrLinkChange | IntrStatsMax | RHINE_EVENT_NAPI)) { 1909 netif_err(rp, intr, dev, "Something Wicked happened! %08x\n", 1910 status); 1911 } 1912 1913 return IRQ_RETVAL(handled); 1914} 1915 1916/* This routine is logically part of the interrupt handler, but isolated 1917 for clarity. */ 1918static void rhine_tx(struct net_device *dev) 1919{ 1920 struct rhine_private *rp = netdev_priv(dev); 1921 struct device *hwdev = dev->dev.parent; 1922 unsigned int pkts_compl = 0, bytes_compl = 0; 1923 unsigned int dirty_tx = rp->dirty_tx; 1924 unsigned int cur_tx; 1925 struct sk_buff *skb; 1926 1927 /* 1928 * The race with rhine_start_tx does not matter here as long as the 1929 * driver enforces a value of cur_tx that was relevant when the 1930 * packet was scheduled to the network chipset. 1931 * Executive summary: smp_rmb() balances smp_wmb() in rhine_start_tx. 1932 */ 1933 smp_rmb(); 1934 cur_tx = rp->cur_tx; 1935 /* find and cleanup dirty tx descriptors */ 1936 while (dirty_tx != cur_tx) { 1937 unsigned int entry = dirty_tx % TX_RING_SIZE; 1938 u32 txstatus = le32_to_cpu(rp->tx_ring[entry].tx_status); 1939 1940 netif_dbg(rp, tx_done, dev, "Tx scavenge %d status %08x\n", 1941 entry, txstatus); 1942 if (txstatus & DescOwn) 1943 break; 1944 skb = rp->tx_skbuff[entry]; 1945 if (txstatus & 0x8000) { 1946 netif_dbg(rp, tx_done, dev, 1947 "Transmit error, Tx status %08x\n", txstatus); 1948 dev->stats.tx_errors++; 1949 if (txstatus & 0x0400) 1950 dev->stats.tx_carrier_errors++; 1951 if (txstatus & 0x0200) 1952 dev->stats.tx_window_errors++; 1953 if (txstatus & 0x0100) 1954 dev->stats.tx_aborted_errors++; 1955 if (txstatus & 0x0080) 1956 dev->stats.tx_heartbeat_errors++; 1957 if (((rp->quirks & rqRhineI) && txstatus & 0x0002) || 1958 (txstatus & 0x0800) || (txstatus & 0x1000)) { 1959 dev->stats.tx_fifo_errors++; 1960 rp->tx_ring[entry].tx_status = cpu_to_le32(DescOwn); 1961 break; /* Keep the skb - we try again */ 1962 } 1963 /* Transmitter restarted in 'abnormal' handler. */ 1964 } else { 1965 if (rp->quirks & rqRhineI) 1966 dev->stats.collisions += (txstatus >> 3) & 0x0F; 1967 else 1968 dev->stats.collisions += txstatus & 0x0F; 1969 netif_dbg(rp, tx_done, dev, "collisions: %1.1x:%1.1x\n", 1970 (txstatus >> 3) & 0xF, txstatus & 0xF); 1971 1972 u64_stats_update_begin(&rp->tx_stats.syncp); 1973 rp->tx_stats.bytes += skb->len; 1974 rp->tx_stats.packets++; 1975 u64_stats_update_end(&rp->tx_stats.syncp); 1976 } 1977 /* Free the original skb. */ 1978 if (rp->tx_skbuff_dma[entry]) { 1979 dma_unmap_single(hwdev, 1980 rp->tx_skbuff_dma[entry], 1981 skb->len, 1982 DMA_TO_DEVICE); 1983 } 1984 bytes_compl += skb->len; 1985 pkts_compl++; 1986 dev_consume_skb_any(skb); 1987 rp->tx_skbuff[entry] = NULL; 1988 dirty_tx++; 1989 } 1990 1991 rp->dirty_tx = dirty_tx; 1992 /* Pity we can't rely on the nearby BQL completion implicit barrier. */ 1993 smp_wmb(); 1994 1995 netdev_completed_queue(dev, pkts_compl, bytes_compl); 1996 1997 /* cur_tx may be optimistically out-of-sync. See rhine_start_tx. */ 1998 if (!rhine_tx_queue_full(rp) && netif_queue_stopped(dev)) { 1999 netif_wake_queue(dev); 2000 smp_rmb(); 2001 /* Rejuvenate. */ 2002 if (rhine_tx_queue_full(rp)) 2003 netif_stop_queue(dev); 2004 } 2005} 2006 2007/** 2008 * rhine_get_vlan_tci - extract TCI from Rx data buffer 2009 * @skb: pointer to sk_buff 2010 * @data_size: used data area of the buffer including CRC 2011 * 2012 * If hardware VLAN tag extraction is enabled and the chip indicates a 802.1Q 2013 * packet, the extracted 802.1Q header (2 bytes TPID + 2 bytes TCI) is 4-byte 2014 * aligned following the CRC. 2015 */ 2016static inline u16 rhine_get_vlan_tci(struct sk_buff *skb, int data_size) 2017{ 2018 u8 *trailer = (u8 *)skb->data + ((data_size + 3) & ~3) + 2; 2019 return be16_to_cpup((__be16 *)trailer); 2020} 2021 2022static inline void rhine_rx_vlan_tag(struct sk_buff *skb, struct rx_desc *desc, 2023 int data_size) 2024{ 2025 dma_rmb(); 2026 if (unlikely(desc->desc_length & cpu_to_le32(DescTag))) { 2027 u16 vlan_tci; 2028 2029 vlan_tci = rhine_get_vlan_tci(skb, data_size); 2030 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), vlan_tci); 2031 } 2032} 2033 2034/* Process up to limit frames from receive ring */ 2035static int rhine_rx(struct net_device *dev, int limit) 2036{ 2037 struct rhine_private *rp = netdev_priv(dev); 2038 struct device *hwdev = dev->dev.parent; 2039 int entry = rp->cur_rx % RX_RING_SIZE; 2040 int count; 2041 2042 netif_dbg(rp, rx_status, dev, "%s(), entry %d status %08x\n", __func__, 2043 entry, le32_to_cpu(rp->rx_ring[entry].rx_status)); 2044 2045 /* If EOP is set on the next entry, it's a new packet. Send it up. */ 2046 for (count = 0; count < limit; ++count) { 2047 struct rx_desc *desc = rp->rx_ring + entry; 2048 u32 desc_status = le32_to_cpu(desc->rx_status); 2049 int data_size = desc_status >> 16; 2050 2051 if (desc_status & DescOwn) 2052 break; 2053 2054 netif_dbg(rp, rx_status, dev, "%s() status %08x\n", __func__, 2055 desc_status); 2056 2057 if ((desc_status & (RxWholePkt | RxErr)) != RxWholePkt) { 2058 if ((desc_status & RxWholePkt) != RxWholePkt) { 2059 netdev_warn(dev, 2060 "Oversized Ethernet frame spanned multiple buffers, " 2061 "entry %#x length %d status %08x!\n", 2062 entry, data_size, 2063 desc_status); 2064 dev->stats.rx_length_errors++; 2065 } else if (desc_status & RxErr) { 2066 /* There was a error. */ 2067 netif_dbg(rp, rx_err, dev, 2068 "%s() Rx error %08x\n", __func__, 2069 desc_status); 2070 dev->stats.rx_errors++; 2071 if (desc_status & 0x0030) 2072 dev->stats.rx_length_errors++; 2073 if (desc_status & 0x0048) 2074 dev->stats.rx_fifo_errors++; 2075 if (desc_status & 0x0004) 2076 dev->stats.rx_frame_errors++; 2077 if (desc_status & 0x0002) { 2078 /* this can also be updated outside the interrupt handler */ 2079 spin_lock(&rp->lock); 2080 dev->stats.rx_crc_errors++; 2081 spin_unlock(&rp->lock); 2082 } 2083 } 2084 } else { 2085 /* Length should omit the CRC */ 2086 int pkt_len = data_size - 4; 2087 struct sk_buff *skb; 2088 2089 /* Check if the packet is long enough to accept without 2090 copying to a minimally-sized skbuff. */ 2091 if (pkt_len < rx_copybreak) { 2092 skb = netdev_alloc_skb_ip_align(dev, pkt_len); 2093 if (unlikely(!skb)) 2094 goto drop; 2095 2096 dma_sync_single_for_cpu(hwdev, 2097 rp->rx_skbuff_dma[entry], 2098 rp->rx_buf_sz, 2099 DMA_FROM_DEVICE); 2100 2101 skb_copy_to_linear_data(skb, 2102 rp->rx_skbuff[entry]->data, 2103 pkt_len); 2104 2105 dma_sync_single_for_device(hwdev, 2106 rp->rx_skbuff_dma[entry], 2107 rp->rx_buf_sz, 2108 DMA_FROM_DEVICE); 2109 } else { 2110 struct rhine_skb_dma sd; 2111 2112 if (unlikely(rhine_skb_dma_init(dev, &sd) < 0)) 2113 goto drop; 2114 2115 skb = rp->rx_skbuff[entry]; 2116 2117 dma_unmap_single(hwdev, 2118 rp->rx_skbuff_dma[entry], 2119 rp->rx_buf_sz, 2120 DMA_FROM_DEVICE); 2121 rhine_skb_dma_nic_store(rp, &sd, entry); 2122 } 2123 2124 skb_put(skb, pkt_len); 2125 2126 rhine_rx_vlan_tag(skb, desc, data_size); 2127 2128 skb->protocol = eth_type_trans(skb, dev); 2129 2130 netif_receive_skb(skb); 2131 2132 u64_stats_update_begin(&rp->rx_stats.syncp); 2133 rp->rx_stats.bytes += pkt_len; 2134 rp->rx_stats.packets++; 2135 u64_stats_update_end(&rp->rx_stats.syncp); 2136 } 2137give_descriptor_to_nic: 2138 desc->rx_status = cpu_to_le32(DescOwn); 2139 entry = (++rp->cur_rx) % RX_RING_SIZE; 2140 } 2141 2142 return count; 2143 2144drop: 2145 dev->stats.rx_dropped++; 2146 goto give_descriptor_to_nic; 2147} 2148 2149static void rhine_restart_tx(struct net_device *dev) { 2150 struct rhine_private *rp = netdev_priv(dev); 2151 void __iomem *ioaddr = rp->base; 2152 int entry = rp->dirty_tx % TX_RING_SIZE; 2153 u32 intr_status; 2154 2155 /* 2156 * If new errors occurred, we need to sort them out before doing Tx. 2157 * In that case the ISR will be back here RSN anyway. 2158 */ 2159 intr_status = rhine_get_events(rp); 2160 2161 if ((intr_status & IntrTxErrSummary) == 0) { 2162 2163 /* We know better than the chip where it should continue. */ 2164 iowrite32(rp->tx_ring_dma + entry * sizeof(struct tx_desc), 2165 ioaddr + TxRingPtr); 2166 2167 iowrite8(ioread8(ioaddr + ChipCmd) | CmdTxOn, 2168 ioaddr + ChipCmd); 2169 2170 if (rp->tx_ring[entry].desc_length & cpu_to_le32(0x020000)) 2171 /* Tx queues are bits 7-0 (first Tx queue: bit 7) */ 2172 BYTE_REG_BITS_ON(1 << 7, ioaddr + TQWake); 2173 2174 iowrite8(ioread8(ioaddr + ChipCmd1) | Cmd1TxDemand, 2175 ioaddr + ChipCmd1); 2176 IOSYNC; 2177 } 2178 else { 2179 /* This should never happen */ 2180 netif_warn(rp, tx_err, dev, "another error occurred %08x\n", 2181 intr_status); 2182 } 2183 2184} 2185 2186static void rhine_slow_event_task(struct work_struct *work) 2187{ 2188 struct rhine_private *rp = 2189 container_of(work, struct rhine_private, slow_event_task); 2190 struct net_device *dev = rp->dev; 2191 u32 intr_status; 2192 2193 mutex_lock(&rp->task_lock); 2194 2195 if (!rp->task_enable) 2196 goto out_unlock; 2197 2198 intr_status = rhine_get_events(rp); 2199 rhine_ack_events(rp, intr_status & RHINE_EVENT_SLOW); 2200 2201 if (intr_status & IntrLinkChange) 2202 rhine_check_media(dev, 0); 2203 2204 if (intr_status & IntrPCIErr) 2205 netif_warn(rp, hw, dev, "PCI error\n"); 2206 2207 iowrite16(RHINE_EVENT & 0xffff, rp->base + IntrEnable); 2208 2209out_unlock: 2210 mutex_unlock(&rp->task_lock); 2211} 2212 2213static void 2214rhine_get_stats64(struct net_device *dev, struct rtnl_link_stats64 *stats) 2215{ 2216 struct rhine_private *rp = netdev_priv(dev); 2217 unsigned int start; 2218 2219 spin_lock_bh(&rp->lock); 2220 rhine_update_rx_crc_and_missed_errord(rp); 2221 spin_unlock_bh(&rp->lock); 2222 2223 netdev_stats_to_stats64(stats, &dev->stats); 2224 2225 do { 2226 start = u64_stats_fetch_begin(&rp->rx_stats.syncp); 2227 stats->rx_packets = rp->rx_stats.packets; 2228 stats->rx_bytes = rp->rx_stats.bytes; 2229 } while (u64_stats_fetch_retry(&rp->rx_stats.syncp, start)); 2230 2231 do { 2232 start = u64_stats_fetch_begin(&rp->tx_stats.syncp); 2233 stats->tx_packets = rp->tx_stats.packets; 2234 stats->tx_bytes = rp->tx_stats.bytes; 2235 } while (u64_stats_fetch_retry(&rp->tx_stats.syncp, start)); 2236} 2237 2238static void rhine_set_rx_mode(struct net_device *dev) 2239{ 2240 struct rhine_private *rp = netdev_priv(dev); 2241 void __iomem *ioaddr = rp->base; 2242 u32 mc_filter[2]; /* Multicast hash filter */ 2243 u8 rx_mode = 0x0C; /* Note: 0x02=accept runt, 0x01=accept errs */ 2244 struct netdev_hw_addr *ha; 2245 2246 if (dev->flags & IFF_PROMISC) { /* Set promiscuous. */ 2247 rx_mode = 0x1C; 2248 iowrite32(0xffffffff, ioaddr + MulticastFilter0); 2249 iowrite32(0xffffffff, ioaddr + MulticastFilter1); 2250 } else if ((netdev_mc_count(dev) > multicast_filter_limit) || 2251 (dev->flags & IFF_ALLMULTI)) { 2252 /* Too many to match, or accept all multicasts. */ 2253 iowrite32(0xffffffff, ioaddr + MulticastFilter0); 2254 iowrite32(0xffffffff, ioaddr + MulticastFilter1); 2255 } else if (rp->quirks & rqMgmt) { 2256 int i = 0; 2257 u32 mCAMmask = 0; /* 32 mCAMs (6105M and better) */ 2258 netdev_for_each_mc_addr(ha, dev) { 2259 if (i == MCAM_SIZE) 2260 break; 2261 rhine_set_cam(ioaddr, i, ha->addr); 2262 mCAMmask |= 1 << i; 2263 i++; 2264 } 2265 rhine_set_cam_mask(ioaddr, mCAMmask); 2266 } else { 2267 memset(mc_filter, 0, sizeof(mc_filter)); 2268 netdev_for_each_mc_addr(ha, dev) { 2269 int bit_nr = ether_crc(ETH_ALEN, ha->addr) >> 26; 2270 2271 mc_filter[bit_nr >> 5] |= 1 << (bit_nr & 31); 2272 } 2273 iowrite32(mc_filter[0], ioaddr + MulticastFilter0); 2274 iowrite32(mc_filter[1], ioaddr + MulticastFilter1); 2275 } 2276 /* enable/disable VLAN receive filtering */ 2277 if (rp->quirks & rqMgmt) { 2278 if (dev->flags & IFF_PROMISC) 2279 BYTE_REG_BITS_OFF(BCR1_VIDFR, ioaddr + PCIBusConfig1); 2280 else 2281 BYTE_REG_BITS_ON(BCR1_VIDFR, ioaddr + PCIBusConfig1); 2282 } 2283 BYTE_REG_BITS_ON(rx_mode, ioaddr + RxConfig); 2284} 2285 2286static void netdev_get_drvinfo(struct net_device *dev, struct ethtool_drvinfo *info) 2287{ 2288 struct device *hwdev = dev->dev.parent; 2289 2290 strscpy(info->driver, DRV_NAME, sizeof(info->driver)); 2291 strscpy(info->bus_info, dev_name(hwdev), sizeof(info->bus_info)); 2292} 2293 2294static int netdev_get_link_ksettings(struct net_device *dev, 2295 struct ethtool_link_ksettings *cmd) 2296{ 2297 struct rhine_private *rp = netdev_priv(dev); 2298 2299 mutex_lock(&rp->task_lock); 2300 mii_ethtool_get_link_ksettings(&rp->mii_if, cmd); 2301 mutex_unlock(&rp->task_lock); 2302 2303 return 0; 2304} 2305 2306static int netdev_set_link_ksettings(struct net_device *dev, 2307 const struct ethtool_link_ksettings *cmd) 2308{ 2309 struct rhine_private *rp = netdev_priv(dev); 2310 int rc; 2311 2312 mutex_lock(&rp->task_lock); 2313 rc = mii_ethtool_set_link_ksettings(&rp->mii_if, cmd); 2314 rhine_set_carrier(&rp->mii_if); 2315 mutex_unlock(&rp->task_lock); 2316 2317 return rc; 2318} 2319 2320static int netdev_nway_reset(struct net_device *dev) 2321{ 2322 struct rhine_private *rp = netdev_priv(dev); 2323 2324 return mii_nway_restart(&rp->mii_if); 2325} 2326 2327static u32 netdev_get_link(struct net_device *dev) 2328{ 2329 struct rhine_private *rp = netdev_priv(dev); 2330 2331 return mii_link_ok(&rp->mii_if); 2332} 2333 2334static u32 netdev_get_msglevel(struct net_device *dev) 2335{ 2336 struct rhine_private *rp = netdev_priv(dev); 2337 2338 return rp->msg_enable; 2339} 2340 2341static void netdev_set_msglevel(struct net_device *dev, u32 value) 2342{ 2343 struct rhine_private *rp = netdev_priv(dev); 2344 2345 rp->msg_enable = value; 2346} 2347 2348static void rhine_get_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2349{ 2350 struct rhine_private *rp = netdev_priv(dev); 2351 2352 if (!(rp->quirks & rqWOL)) 2353 return; 2354 2355 spin_lock_irq(&rp->lock); 2356 wol->supported = WAKE_PHY | WAKE_MAGIC | 2357 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */ 2358 wol->wolopts = rp->wolopts; 2359 spin_unlock_irq(&rp->lock); 2360} 2361 2362static int rhine_set_wol(struct net_device *dev, struct ethtool_wolinfo *wol) 2363{ 2364 struct rhine_private *rp = netdev_priv(dev); 2365 u32 support = WAKE_PHY | WAKE_MAGIC | 2366 WAKE_UCAST | WAKE_MCAST | WAKE_BCAST; /* Untested */ 2367 2368 if (!(rp->quirks & rqWOL)) 2369 return -EINVAL; 2370 2371 if (wol->wolopts & ~support) 2372 return -EINVAL; 2373 2374 spin_lock_irq(&rp->lock); 2375 rp->wolopts = wol->wolopts; 2376 spin_unlock_irq(&rp->lock); 2377 2378 return 0; 2379} 2380 2381static const struct ethtool_ops netdev_ethtool_ops = { 2382 .get_drvinfo = netdev_get_drvinfo, 2383 .nway_reset = netdev_nway_reset, 2384 .get_link = netdev_get_link, 2385 .get_msglevel = netdev_get_msglevel, 2386 .set_msglevel = netdev_set_msglevel, 2387 .get_wol = rhine_get_wol, 2388 .set_wol = rhine_set_wol, 2389 .get_link_ksettings = netdev_get_link_ksettings, 2390 .set_link_ksettings = netdev_set_link_ksettings, 2391}; 2392 2393static int netdev_ioctl(struct net_device *dev, struct ifreq *rq, int cmd) 2394{ 2395 struct rhine_private *rp = netdev_priv(dev); 2396 int rc; 2397 2398 if (!netif_running(dev)) 2399 return -EINVAL; 2400 2401 mutex_lock(&rp->task_lock); 2402 rc = generic_mii_ioctl(&rp->mii_if, if_mii(rq), cmd, NULL); 2403 rhine_set_carrier(&rp->mii_if); 2404 mutex_unlock(&rp->task_lock); 2405 2406 return rc; 2407} 2408 2409static int rhine_close(struct net_device *dev) 2410{ 2411 struct rhine_private *rp = netdev_priv(dev); 2412 void __iomem *ioaddr = rp->base; 2413 2414 rhine_task_disable(rp); 2415 napi_disable(&rp->napi); 2416 netif_stop_queue(dev); 2417 2418 netif_dbg(rp, ifdown, dev, "Shutting down ethercard, status was %04x\n", 2419 ioread16(ioaddr + ChipCmd)); 2420 2421 /* Switch to loopback mode to avoid hardware races. */ 2422 iowrite8(rp->tx_thresh | 0x02, ioaddr + TxConfig); 2423 2424 rhine_irq_disable(rp); 2425 2426 /* Stop the chip's Tx and Rx processes. */ 2427 iowrite16(CmdStop, ioaddr + ChipCmd); 2428 2429 free_irq(rp->irq, dev); 2430 free_rbufs(dev); 2431 free_tbufs(dev); 2432 free_ring(dev); 2433 2434 return 0; 2435} 2436 2437 2438static void rhine_remove_one_pci(struct pci_dev *pdev) 2439{ 2440 struct net_device *dev = pci_get_drvdata(pdev); 2441 struct rhine_private *rp = netdev_priv(dev); 2442 2443 unregister_netdev(dev); 2444 2445 pci_iounmap(pdev, rp->base); 2446 pci_release_regions(pdev); 2447 2448 free_netdev(dev); 2449 pci_disable_device(pdev); 2450} 2451 2452static void rhine_remove_one_platform(struct platform_device *pdev) 2453{ 2454 struct net_device *dev = platform_get_drvdata(pdev); 2455 struct rhine_private *rp = netdev_priv(dev); 2456 2457 unregister_netdev(dev); 2458 2459 iounmap(rp->base); 2460 2461 free_netdev(dev); 2462} 2463 2464static void rhine_shutdown_pci(struct pci_dev *pdev) 2465{ 2466 struct net_device *dev = pci_get_drvdata(pdev); 2467 struct rhine_private *rp = netdev_priv(dev); 2468 void __iomem *ioaddr = rp->base; 2469 2470 if (!(rp->quirks & rqWOL)) 2471 return; /* Nothing to do for non-WOL adapters */ 2472 2473 rhine_power_init(dev); 2474 2475 /* Make sure we use pattern 0, 1 and not 4, 5 */ 2476 if (rp->quirks & rq6patterns) 2477 iowrite8(0x04, ioaddr + WOLcgClr); 2478 2479 spin_lock(&rp->lock); 2480 2481 if (rp->wolopts & WAKE_MAGIC) { 2482 iowrite8(WOLmagic, ioaddr + WOLcrSet); 2483 /* 2484 * Turn EEPROM-controlled wake-up back on -- some hardware may 2485 * not cooperate otherwise. 2486 */ 2487 iowrite8(ioread8(ioaddr + ConfigA) | 0x03, ioaddr + ConfigA); 2488 } 2489 2490 if (rp->wolopts & (WAKE_BCAST|WAKE_MCAST)) 2491 iowrite8(WOLbmcast, ioaddr + WOLcgSet); 2492 2493 if (rp->wolopts & WAKE_PHY) 2494 iowrite8(WOLlnkon | WOLlnkoff, ioaddr + WOLcrSet); 2495 2496 if (rp->wolopts & WAKE_UCAST) 2497 iowrite8(WOLucast, ioaddr + WOLcrSet); 2498 2499 if (rp->wolopts) { 2500 /* Enable legacy WOL (for old motherboards) */ 2501 iowrite8(0x01, ioaddr + PwcfgSet); 2502 iowrite8(ioread8(ioaddr + StickyHW) | 0x04, ioaddr + StickyHW); 2503 } 2504 2505 spin_unlock(&rp->lock); 2506 2507 if (system_state == SYSTEM_POWER_OFF && !avoid_D3) { 2508 iowrite8(ioread8(ioaddr + StickyHW) | 0x03, ioaddr + StickyHW); 2509 2510 pci_wake_from_d3(pdev, true); 2511 pci_set_power_state(pdev, PCI_D3hot); 2512 } 2513} 2514 2515#ifdef CONFIG_PM_SLEEP 2516static int rhine_suspend(struct device *device) 2517{ 2518 struct net_device *dev = dev_get_drvdata(device); 2519 struct rhine_private *rp = netdev_priv(dev); 2520 2521 if (!netif_running(dev)) 2522 return 0; 2523 2524 rhine_task_disable(rp); 2525 rhine_irq_disable(rp); 2526 napi_disable(&rp->napi); 2527 2528 netif_device_detach(dev); 2529 2530 if (dev_is_pci(device)) 2531 rhine_shutdown_pci(to_pci_dev(device)); 2532 2533 return 0; 2534} 2535 2536static int rhine_resume(struct device *device) 2537{ 2538 struct net_device *dev = dev_get_drvdata(device); 2539 struct rhine_private *rp = netdev_priv(dev); 2540 2541 if (!netif_running(dev)) 2542 return 0; 2543 2544 enable_mmio(rp->pioaddr, rp->quirks); 2545 rhine_power_init(dev); 2546 free_tbufs(dev); 2547 alloc_tbufs(dev); 2548 rhine_reset_rbufs(rp); 2549 rhine_task_enable(rp); 2550 2551 netdev_lock(dev); 2552 spin_lock_bh(&rp->lock); 2553 init_registers(dev); 2554 spin_unlock_bh(&rp->lock); 2555 netdev_unlock(dev); 2556 2557 netif_device_attach(dev); 2558 2559 return 0; 2560} 2561 2562static SIMPLE_DEV_PM_OPS(rhine_pm_ops, rhine_suspend, rhine_resume); 2563#define RHINE_PM_OPS (&rhine_pm_ops) 2564 2565#else 2566 2567#define RHINE_PM_OPS NULL 2568 2569#endif /* !CONFIG_PM_SLEEP */ 2570 2571static struct pci_driver rhine_driver_pci = { 2572 .name = DRV_NAME, 2573 .id_table = rhine_pci_tbl, 2574 .probe = rhine_init_one_pci, 2575 .remove = rhine_remove_one_pci, 2576 .shutdown = rhine_shutdown_pci, 2577 .driver.pm = RHINE_PM_OPS, 2578}; 2579 2580static struct platform_driver rhine_driver_platform = { 2581 .probe = rhine_init_one_platform, 2582 .remove = rhine_remove_one_platform, 2583 .driver = { 2584 .name = DRV_NAME, 2585 .of_match_table = rhine_of_tbl, 2586 .pm = RHINE_PM_OPS, 2587 } 2588}; 2589 2590static const struct dmi_system_id rhine_dmi_table[] __initconst = { 2591 { 2592 .ident = "EPIA-M", 2593 .matches = { 2594 DMI_MATCH(DMI_BIOS_VENDOR, "Award Software International, Inc."), 2595 DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"), 2596 }, 2597 }, 2598 { 2599 .ident = "KV7", 2600 .matches = { 2601 DMI_MATCH(DMI_BIOS_VENDOR, "Phoenix Technologies, LTD"), 2602 DMI_MATCH(DMI_BIOS_VERSION, "6.00 PG"), 2603 }, 2604 }, 2605 { NULL } 2606}; 2607 2608static int __init rhine_init(void) 2609{ 2610 int ret_pci, ret_platform; 2611 2612/* when a module, this is printed whether or not devices are found in probe */ 2613 if (dmi_check_system(rhine_dmi_table)) { 2614 /* these BIOSes fail at PXE boot if chip is in D3 */ 2615 avoid_D3 = true; 2616 pr_warn("Broken BIOS detected, avoid_D3 enabled\n"); 2617 } 2618 else if (avoid_D3) 2619 pr_info("avoid_D3 set\n"); 2620 2621 ret_pci = pci_register_driver(&rhine_driver_pci); 2622 ret_platform = platform_driver_register(&rhine_driver_platform); 2623 if ((ret_pci < 0) && (ret_platform < 0)) 2624 return ret_pci; 2625 2626 return 0; 2627} 2628 2629 2630static void __exit rhine_cleanup(void) 2631{ 2632 platform_driver_unregister(&rhine_driver_platform); 2633 pci_unregister_driver(&rhine_driver_pci); 2634} 2635 2636 2637module_init(rhine_init); 2638module_exit(rhine_cleanup);
~/
Read-only file preview.